424 lines
17 KiB
C++
424 lines
17 KiB
C++
/*
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* Copyright (C) Switch-OC-Suite
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*
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* Copyright (c) 2023 hanai3Bi
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*
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* Copyright (c) Souldbminer and Horizon OC Contributors
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "../oc_common.hpp"
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#include "pcv_common.hpp"
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namespace ams::ldr::oc::pcv
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{
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namespace mariko {
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constexpr cvb_entry_t CpuCvbTableDefault[] = {
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// CPUB01_CVB_TABLE
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{204000, {721589, -12695, 27}, {}},
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{306000, {747134, -14195, 27}, {}},
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{408000, {776324, -15705, 27}, {}},
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{510000, {809160, -17205, 27}, {}},
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{612000, {845641, -18715, 27}, {}},
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{714000, {885768, -20215, 27}, {}},
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{816000, {929540, -21725, 27}, {}},
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{918000, {976958, -23225, 27}, {}},
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{1020000, {1028021, -24725, 27}, {1120000}},
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{1122000, {1082730, -26235, 27}, {1120000}},
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{1224000, {1141084, -27735, 27}, {1120000}},
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{1326000, {1203084, -29245, 27}, {1120000}},
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{1428000, {1268729, -30745, 27}, {1120000}},
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{1581000, {1374032, -33005, 27}, {1120000}},
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{1683000, {1448791, -34505, 27}, {1120000}},
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{1785000, {1527196, -36015, 27}, {1120000}},
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{1887000, {1609246, -37515, 27}, {1120000}},
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{1963500, {1675751, -38635, 27}, {1120000}},
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{},
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};
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constexpr int gpuVmax = 750;
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constexpr int gpuVmin = 610;
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constexpr u16 CpuMinVolts[] = {800, 637, 620, 610};
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constexpr u32 CpuClkOfficial = 1963'500;
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constexpr u32 CpuVoltOfficial = 1120;
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constexpr cvb_entry_t GpuCvbTableDefault[] = {
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// GPUB01_NA_CVB_TABLE
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{76800, {}, {
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610000,
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}},
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{153600, {}, {
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610000,
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}},
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{230400, {}, {
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610000,
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}},
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{307200, {}, {
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610000,
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}},
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{384000, {}, {
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610000,
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}},
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{460800, {}, {
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610000,
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}},
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{537600, {}, {801688, -10900, -163, 298, -10599, 162}},
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{614400, {}, {824214, -5743, -452, 238, -6325, 81}},
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{691200, {}, {848830, -3903, -552, 119, -4030, -2}},
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{768000, {}, {891575, -4409, -584, 0, -2849, 39}},
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{844800, {}, {940071, -5367, -602, -60, -63, -93}},
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{921600, {}, {986765, -6637, -614, -179, 1905, -13}},
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{998400, {}, {1098475, -13529, -497, -179, 3626, 9}},
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{1075200, {}, {1163644, -12688, -648, 0, 1077, 40}},
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{1152000, {}, {1204812, -9908, -830, 0, 1469, 110}},
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{1228800, {}, {1277303, -11675, -859, 0, 3722, 313}},
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{1267200, {}, {1335531, -12567, -867, 0, 3681, 559}},
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{},
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};
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constexpr u32 GpuClkPllMax = 1300'000'000;
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constexpr u32 GpuClkPllLimit = 2'600'000;
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constexpr u32 CpuVminOfficial = 620;
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/* GPU Max Clock asm Pattern:
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*
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* MOV W11, #0x1000 MOV (wide immediate) 0x1000 0xB (11)
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* sf | opc | | hw | imm16 | Rd
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* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
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* 0 | 1 0 | 1 0 0 1 0 1| 0 0| 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 |0 1 0 1 1
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*
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* MOVK W11, #0xE, LSL#16 <shift>16 0xE 0xB (11)
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* sf | opc | | hw | imm16 | Rd
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* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
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* 0 | 1 1 | 1 0 0 1 0 1| 0 1| 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 |0 1 0 1 1
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*/
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inline constexpr u32 asm_pattern[] = {0x52820000, 0x72A001C0};
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inline auto asm_compare_no_rd = [](u32 ins1, u32 ins2)
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{ return ((ins1 ^ ins2) >> 5) == 0; };
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inline auto asm_get_rd = [](u32 ins)
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{ return ins & ((1 << 5) - 1); };
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inline auto asm_set_rd = [](u32 ins, u8 rd)
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{ return (ins & 0xFFFFFFE0) | (rd & 0x1F); };
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inline auto asm_set_imm16 = [](u32 ins, u16 imm)
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{ return (ins & 0xFFE0001F) | ((imm & 0xFFFF) << 5); };
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inline bool GpuMaxClockPatternFn(u32 *ptr32) {
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return asm_compare_no_rd(*ptr32, asm_pattern[0]);
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}
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constexpr emc_dvb_dvfs_table_t EmcDvbTableDefault[] = {
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{204000, {
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637,
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637,
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637,
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}},
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{408000, {
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637,
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637,
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637,
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}},
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{800000, {
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637,
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637,
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637,
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}},
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{1065600, {
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637,
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637,
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637,
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}},
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{1331200, {
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650,
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637,
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637,
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}},
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{1600000, {
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675,
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650,
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637,
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}},
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};
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constexpr u32 EmcClkOSAlt = 1331'200;
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constexpr u32 EmcClkPllmLimit = 2133'000'000;
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constexpr u32 EmcVddqDefault = 600'000;
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constexpr u32 MemVdd2Default = 1100'000;
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constexpr u32 MTC_TABLE_REV = 3;
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void Patch(uintptr_t mapped_nso, size_t nso_size);
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}
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namespace erista {
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constexpr cvb_entry_t CpuCvbTableDefault[] = {
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// CPU_PLL_CVB_TABLE_ODN
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{204000, {721094}, {}},
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{306000, {754040}, {}},
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{408000, {786986}, {}},
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{510000, {819932}, {}},
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{612000, {852878}, {}},
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{714000, {885824}, {}},
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{816000, {918770}, {}},
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{918000, {951716}, {}},
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{1020000, {984662}, {-2875621, 358099, -8585}},
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{1122000, {1017608}, {-52225, 104159, -2816}},
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{1224000, {1050554}, {1076868, 8356, -727}},
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{1326000, {1083500}, {2208191, -84659, 1240}},
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{1428000, {1116446}, {2519460, -105063, 1611}},
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{1581000, {1130000}, {2889664, -122173, 1834}},
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{1683000, {1168000}, {5100873, -279186, 4747}},
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{1785000, {1227500}, {5100873, -279186, 4747}},
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{},
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};
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constexpr int gpuVmin = 810;
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constexpr u32 CpuVoltOfficial = 1235;
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constexpr u32 CpuVoltL4T = 1235'000;
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constexpr u16 CpuMinVolts[] = {950, 850, 825, 810};
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inline bool CpuMaxVoltPatternFn(u32 *ptr32) {
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u32 val = *ptr32;
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return (val == 1132 || val == 1170 || val == 1227);
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}
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constexpr u32 GpuClkPllLimit = 921'600'000;
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/* GPU Max Clock asm Pattern:
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*
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* MOV W11, #0x1000 MOV (wide immediate) 0x1000 0xB (11)
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* sf | opc | | hw | imm16 | Rd
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* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
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* 0 | 1 0 | 1 0 0 1 0 1| 0 0| 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 |0 1 0 1 1
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*
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* MOVK W11, #0xE, LSL#16 <shift>16 0xE 0xB (11)
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* sf | opc | | hw | imm16 | Rd
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* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
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* 0 | 1 1 | 1 0 0 1 0 1| 0 1| 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 |0 1 0 1 1
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*/
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inline constexpr u32 asm_pattern[] = {0x52820000, 0x72A001C0};
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inline auto asm_compare_no_rd = [](u32 ins1, u32 ins2)
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{ return ((ins1 ^ ins2) >> 5) == 0; };
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inline auto asm_get_rd = [](u32 ins)
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{ return ins & ((1 << 5) - 1); };
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inline auto asm_set_rd = [](u32 ins, u8 rd)
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{ return (ins & 0xFFFFFFE0) | (rd & 0x1F); };
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inline auto asm_set_imm16 = [](u32 ins, u16 imm)
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{ return (ins & 0xFFE0001F) | ((imm & 0xFFFF) << 5); };
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inline bool GpuMaxClockPatternFn(u32 *ptr32) {
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return asm_compare_no_rd(*ptr32, asm_pattern[0]);
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}
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constexpr cvb_entry_t GpuCvbTableDefault[] = {
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// NA_FREQ_CVB_TABLE
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{76800, {}, {814294, 8144, -940, 808, -21583, 226}},
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{153600, {}, {856185, 8144, -940, 808, -21583, 226}},
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{230400, {}, {898077, 8144, -940, 808, -21583, 226}},
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{307200, {}, {939968, 8144, -940, 808, -21583, 226}},
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{384000, {}, {981860, 8144, -940, 808, -21583, 226}},
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{460800, {}, {1023751, 8144, -940, 808, -21583, 226}},
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{537600, {}, {1065642, 8144, -940, 808, -21583, 226}},
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{614400, {}, {1107534, 8144, -940, 808, -21583, 226}},
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{691200, {}, {1149425, 8144, -940, 808, -21583, 226}},
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{768000, {}, {1191317, 8144, -940, 808, -21583, 226}},
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{844800, {}, {1233208, 8144, -940, 808, -21583, 226}},
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{921600, {}, {1275100, 8144, -940, 808, -21583, 226}},
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{},
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};
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constexpr u32 MemVoltHOS = 1125'000;
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constexpr u32 EmcClkPllmLimit = 1866'000'000;
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constexpr u32 MTC_TABLE_REV = 7;
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void Patch(uintptr_t mapped_nso, size_t nso_size);
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}
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template <bool isMariko>
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Result CpuFreqCvbTable(u32 *ptr) {
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cvb_entry_t *default_table = isMariko ? (cvb_entry_t *)(&mariko::CpuCvbTableDefault) : (cvb_entry_t *)(&erista::CpuCvbTableDefault);
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cvb_entry_t *customize_table = nullptr; // impossible to reach, there will always be a way to set a pointer
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if (isMariko) {
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if (C.marikoCpuUV) {
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customize_table = const_cast<cvb_entry_t *>(C.marikoCpuDvfsTableSLT);
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} else {
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customize_table = const_cast<cvb_entry_t *>(C.marikoCpuDvfsTable);
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}
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} else {
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customize_table = const_cast<cvb_entry_t *>(C.eristaCpuDvfsTable);
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}
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u32 cpu_max_volt = isMariko ? C.marikoCpuMaxVolt : C.eristaCpuMaxVolt;
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u32 cpu_freq_threshold = 1020'000;
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if (isMariko) {
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cpu_freq_threshold = C.marikoCpuUV ? 2193'000 : 2091'000;
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} else {
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cpu_freq_threshold = cpu_max_volt >= 1300 ? 1887'000 : 1428'000;
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}
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size_t default_entry_count = GetDvfsTableEntryCount(default_table);
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size_t default_table_size = default_entry_count * sizeof(cvb_entry_t);
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size_t customize_entry_count = GetDvfsTableEntryCount(customize_table);
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size_t customize_table_size = customize_entry_count * sizeof(cvb_entry_t);
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// Validate existing table
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cvb_entry_t *table_free = reinterpret_cast<cvb_entry_t *>(ptr) + 1;
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void *cpu_cvb_table_head = reinterpret_cast<u8 *>(table_free) - default_table_size;
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bool validated = std::memcmp(cpu_cvb_table_head, default_table, default_table_size) == 0;
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R_UNLESS(validated, ldr::ResultInvalidCpuDvfs());
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std::memcpy(cpu_cvb_table_head, static_cast<void *>(customize_table), customize_table_size);
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// Patch CPU max volt
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if (cpu_max_volt) {
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cvb_entry_t *entry = static_cast<cvb_entry_t *>(cpu_cvb_table_head);
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for (size_t i = 0; i < customize_entry_count; i++) {
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if (entry->freq >= cpu_freq_threshold) {
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if (isMariko) {
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PATCH_OFFSET(&(entry->cvb_pll_param.c0), cpu_max_volt * 1000);
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} else {
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PATCH_OFFSET(&(entry->cvb_dfll_param.c0), cpu_max_volt * 1000);
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}
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}
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entry++;
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}
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}
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R_SUCCEED();
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}
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template <bool isMariko>
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Result GpuFreqCvbTable(u32 *ptr) {
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cvb_entry_t *default_table = isMariko ? (cvb_entry_t *)(&mariko::GpuCvbTableDefault) : (cvb_entry_t *)(&erista::GpuCvbTableDefault);
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cvb_entry_t *customize_table;
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if (isMariko) {
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switch (C.marikoGpuUV) {
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case 0:
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customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTable);
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break;
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case 1:
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customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTableSLT);
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break;
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case 2:
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case 3:
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customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTableHiOPT);
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break;
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default:
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customize_table = const_cast<cvb_entry_t *>(C.marikoGpuDvfsTable);
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break;
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}
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} else {
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switch (C.eristaGpuUV) {
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case 0:
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customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTable);
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break;
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case 1:
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customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTableSLT);
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break;
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case 2:
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case 3:
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customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTableHigh);
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break;
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default:
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customize_table = const_cast<cvb_entry_t *>(C.eristaGpuDvfsTable);
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break;
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}
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}
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size_t default_entry_count = GetDvfsTableEntryCount(default_table);
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size_t default_table_size = default_entry_count * sizeof(cvb_entry_t);
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size_t customize_entry_count = GetDvfsTableEntryCount(customize_table);
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size_t customize_table_size = customize_entry_count * sizeof(cvb_entry_t);
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// Validate existing table
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cvb_entry_t *table_free = reinterpret_cast<cvb_entry_t *>(ptr) + 1;
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void *gpu_cvb_table_head = reinterpret_cast<u8 *>(table_free) - default_table_size;
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bool validated = std::memcmp(gpu_cvb_table_head, default_table, default_table_size) == 0;
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R_UNLESS(validated, ldr::ResultInvalidGpuDvfs());
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std::memcpy(gpu_cvb_table_head, (void *)customize_table, customize_table_size);
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// Patch GPU volt
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if (C.marikoGpuUV == 3 || C.eristaGpuUV == 3) {
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cvb_entry_t *entry = static_cast<cvb_entry_t *>(gpu_cvb_table_head);
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for (size_t i = 0; i < customize_entry_count; i++) {
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if (isMariko) {
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if (C.marikoGpuVoltArray[i] == 0) {
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continue;
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}
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PATCH_OFFSET(&(entry->cvb_pll_param.c0), C.marikoGpuVoltArray[i] * 1000);
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} else {
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if (C.eristaGpuVoltArray[i] == 0) {
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continue;
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}
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PATCH_OFFSET(&(entry->cvb_pll_param.c0), C.eristaGpuVoltArray[i] * 1000);
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}
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PATCH_OFFSET(&(entry->cvb_pll_param.c1), 0);
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PATCH_OFFSET(&(entry->cvb_pll_param.c2), 0);
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PATCH_OFFSET(&(entry->cvb_pll_param.c3), 0);
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PATCH_OFFSET(&(entry->cvb_pll_param.c4), 0);
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PATCH_OFFSET(&(entry->cvb_pll_param.c5), 0);
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entry++;
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}
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} else if (C.commonGpuVoltOffset) {
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cvb_entry_t *entry = static_cast<cvb_entry_t *>(gpu_cvb_table_head);
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for (size_t i = 0; i < customize_entry_count; i++) {
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PATCH_OFFSET(&(entry->cvb_pll_param.c0), (entry->cvb_pll_param.c0 - C.commonGpuVoltOffset * 1000));
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entry++;
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}
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}
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R_SUCCEED();
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};
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Result MemFreqPllmLimit(u32 *ptr);
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Result MemVoltHandler(u32 *ptr); // Used for Erista MEM Vdd2 + EMC Vddq or Mariko MEM Vdd2
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template <typename T>
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Result MemMtcCustomizeTable(T *dst, T *src) {
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constexpr u32 mtc_magic = std::is_same_v<T, MarikoMtcTable> ? MARIKO_MTC_MAGIC : ERISTA_MTC_MAGIC;
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R_UNLESS(src->rev == mtc_magic, ldr::ResultInvalidMtcMagic());
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constexpr u32 ZERO_VAL = UINT32_MAX;
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// Skip params from dvfs_ver to clock_src;
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for (size_t offset = offsetof(T, clk_src_emc); offset < sizeof(T); offset += sizeof(u32)) {
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u32 *src_ent = reinterpret_cast<u32 *>(reinterpret_cast<size_t>(src) + offset);
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u32 *dst_ent = reinterpret_cast<u32 *>(reinterpret_cast<size_t>(dst) + offset);
|
|
u32 src_val = *src_ent;
|
|
|
|
if (src_val){
|
|
PATCH_OFFSET(dst_ent, src_val == ZERO_VAL ? 0 : src_val);
|
|
}
|
|
}
|
|
|
|
R_SUCCEED();
|
|
};
|
|
|
|
void SafetyCheck();
|
|
void Patch(uintptr_t mapped_nso, size_t nso_size);
|
|
|
|
}
|