diff --git a/bdk/mem/sdram.c b/bdk/mem/sdram.c
index 00ec355..da4b149 100644
--- a/bdk/mem/sdram.c
+++ b/bdk/mem/sdram.c
@@ -34,6 +34,8 @@
 #include <soc/t210.h>
 #include <utils/util.h>
 
+#define DRAM_OVERVOLT 600000 // default: 600mV
+
 #define CONFIG_SDRAM_KEEP_ALIVE
 
 typedef struct _sdram_vendor_patch_t
@@ -1481,6 +1483,11 @@ static void _sdram_init_t210b01()
 {
 	const sdram_params_t210b01_t *params = (const sdram_params_t210b01_t *)sdram_get_params_t210b01();
 
+#ifdef DRAM_OVERVOLT
+	// Set DRAM voltage.
+	max7762x_regulator_set_voltage(REGULATOR_77812_DRAM, DRAM_OVERVOLT);
+#endif
+
 	// VDDP Select.
 	PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel;
 	usleep(params->pmc_vddp_sel_wait);
diff --git a/bdk/power/max7762x.c b/bdk/power/max7762x.c
index a7d30ce..376c87e 100644
--- a/bdk/power/max7762x.c
+++ b/bdk/power/max7762x.c
@@ -92,7 +92,7 @@ static const max77620_regulator_t _pmic_regulators[] = {
 	{ "max77621_GPU", 6250, 606250, 1200000, 1400000,  REGULATOR_BC0, MAX77621_VOUT_REG,    MAX77621_VOUT_DVS_REG,  MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
 	{ "max77812_CPU", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
 	//{ "max77812_GPU", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
-	//{ "max77812_RAM", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
+	{ "max77812_RAM", 5000, 250000,  600000, 1525000,  REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL,   MAX77812_BUCK_VOLT_MASK,    {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
 };
 
 static u8 _max77812_get_address()
diff --git a/bdk/power/max7762x.h b/bdk/power/max7762x.h
index 3478530..d01f787 100644
--- a/bdk/power/max7762x.h
+++ b/bdk/power/max7762x.h
@@ -62,8 +62,8 @@
 #define REGULATOR_GPU0 14
 #define REGULATOR_CPU1 15
 //#define REGULATOR_GPU1 16
-//#define REGULATOR_GPU1 17
-#define REGULATOR_MAX  15
+#define REGULATOR_77812_DRAM 16
+#define REGULATOR_MAX  16
 
 #define MAX77621_CPU_I2C_ADDR 0x1B
 #define MAX77621_GPU_I2C_ADDR 0x1C