4 Commits

Author	SHA1	Message	Date
souldbminersmwc	fde9a5b1a3	hoc-clk: add reversenx sync	2025-10-02 15:08:06 -04:00
souldbminersmwc	9964405586	Revert "Fix tW2R and tR2W patch and multiple ram freqs" ... This reverts commit 49f3e73b10.	2025-09-24 17:21:50 -04:00
souldbminersmwc	49f3e73b10	Fix tW2R and tR2W patch and multiple ram freqs	2025-09-24 15:38:08 -04:00
souldbminersmwc	342f9dd116	v2.0.0 ... re-add sys-clk manager, default to mtc auto adj (others are useless), new gpu table for erista units, custom sys-clk updates	2025-09-18 22:20:44 -04:00