More precise timing params (accounting for 8Gb density)

Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp

@@ -264,9 +264,178 @@ namespace pcv {
 
     #include "mtc_timing_table.hpp"
 
-    #if 0
+    void AdjustMtcTable(MarikoMtcTable* table, MarikoMtcTable* ref)
-    #define ADJUST_PROP(TARGET, REF) (REF + ((GetEmcClock()-1331200)*(TARGET-REF))/(1600000-1331200))
+    {
+        /* Official Tegra X1 TRM, sign up for nvidia developer program (free) to download:
+         *     https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual
+         *     Section 18.11: MC Registers
+         *
+         * Retail Mariko: 200FBGA 16Gb DDP LPDDR4X SDRAM x 2
+         * x16/Ch, 1Ch/die, Double-die, 2Ch, 1CS(rank), 8Gb density per die
+         * 64Mb x 16DQ x 8banks x 2channels = 2048MB (x32DQ) per package
+         *
+         * Devkit Mariko: 200FBGA 32Gb DDP LPDDR4X SDRAM x 2
+         * x16/Ch, 1Ch/die, Quad-die,   2Ch, 2CS(rank), 8Gb density per die
+         * X1+ EMC can R/W to both ranks at the same time, resulting in doubled DQ
+         * 64Mb x 32DQ x 8banks x 2channels = 4096MB (x64DQ) per package
+         *
+         * If you have access to LPDDR4(X) specs or datasheets (from manufacturers or Google),
+         * you'd better calculate timings yourself rather than relying on following algorithm.
+         */
 
+        #define ADJUST_PARAM(TARGET, REF)                TARGET = std::ceil(REF + ((GetEmcClock()-1331200)*(TARGET-REF))/(1600000-1331200));
+
+        #define ADJUST_PARAM_TABLE(TABLE, PARAM, REF)    ADJUST_PARAM(TABLE->PARAM, REF->PARAM)
+
+        #define ADJUST_PARAM_ALL_REG(TABLE, PARAM, REF)                 \
+            ADJUST_PARAM_TABLE(TABLE, burst_regs.PARAM, REF)            \
+            ADJUST_PARAM_TABLE(TABLE, shadow_regs_ca_train.PARAM, REF)  \
+            ADJUST_PARAM_TABLE(TABLE, shadow_regs_rdwr_train.PARAM, REF)
+
+        #define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE)\
+            TABLE->burst_regs.PARAM = VALUE;            \
+            TABLE->shadow_regs_ca_train.PARAM = VALUE;  \
+            TABLE->shadow_regs_rdwr_train.PARAM = VALUE;
+
+        // tCK_avg (average clock period) in ns (10E-3 ns)
+        const double tCK_avg = GetEmcClock() == 2131200 ? 0.468 : 1000'000. / GetEmcClock();
+        // tRPpb (row precharge time per bank) in ns
+        const u32 tRPpb = 18;
+        // tRPab (row precharge time all banks) in ns
+        const u32 tRPab = 21;
+        // tRAS (row active time) in ns
+        const u32 tRAS = 42;
+        // tRC (ACTIVATE-ACTIVATE command period same bank) in ns
+        const u32 tRC = tRPpb + tRAS;
+        // tRFCab (refresh cycle time all banks) in ns for 8Gb density
+        const u32 tRFCab = 280;
+        // tRFCpb (refresh cycle time per bank) in ns for 8Gb density
+        const u32 tRFCpb = 140;
+        // tRCD (RAS-CAS delay) in ns
+        const u32 tRCD = 18;
+        // tRRD (Active bank-A to Active bank-B) in ns
+        const double tRRD = GetEmcClock() == 2131200 ? 7.5 : 10.;
+        // tREFpb (average refresh interval per bank) in ns for 8Gb density
+        const u32 tREFpb = 488;
+        // tREFab (average refresh interval all 8 banks) in ns for 8Gb density
+        // const u32 tREFab = tREFpb * 8;
+        // #_of_rows per die for 8Gb density
+        const u32 numOfRows = 65536;
+        // {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
+        // emc_clk_period = dram_clk / 2;
+        // 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
+        const u32 REFRESH = std::ceil((double(tREFpb) * GetEmcClock() / numOfRows * (1.048) / 2 - 64)) / 4 * 4;
+        // tPDEX2WR, tPDEX2RD (timing delay from exiting powerdown mode to a write/read command) in ns
+        const u32 tPDEX2 = 10;
+        // [Guessed] tACT2PDEN (timing delay from an activate, MRS or EMRS command to power-down entry) in ns
+        const u32 tACT2PDEN = 14;
+        // [Guessed] tPDEX2MRR (timing delay from exiting powerdown mode to MRR command) in ns
+        const double tPDEX2MRR = 28.75;
+        // [Guessed] tCKE2PDEN (timing delay from turning off CKE to power-down entry) in ns
+        const double tCKE2PDEN = 8.5;
+        // tXSR (SELF REFRESH exit to next valid command delay) in ns
+        const double tXSR = tRFCab + 7.5;
+        // tCKE (minimum CKE high pulse width) in ns
+        const u32 tCKE = 8;
+        // tCKELPD (minimum CKE low pulse width in SELF REFRESH) in ns
+        const u32 tCKELPD = 15;
+        // [Guessed] tPD (minimum CKE low pulse width in power-down mode) in ns
+        const double tPD = 7.5;
+        // tFAW (Four-bank Activate Window) in ns
+        const u32 tFAW = GetEmcClock() == 2131200 ? 30 : 40;
+
+        #define GET_CYCLE_CEIL(PARAM) std::ceil(double(PARAM) / tCK_avg)
+
+        WRITE_PARAM_ALL_REG(table, emc_rc,      GET_CYCLE_CEIL(tRC));
+        WRITE_PARAM_ALL_REG(table, emc_rfc,     GET_CYCLE_CEIL(tRFCab));
+        WRITE_PARAM_ALL_REG(table, emc_rfcpb,   GET_CYCLE_CEIL(tRFCpb));
+        WRITE_PARAM_ALL_REG(table, emc_ras,     GET_CYCLE_CEIL(tRAS));
+        WRITE_PARAM_ALL_REG(table, emc_rp,      GET_CYCLE_CEIL(tRPpb));
+        ADJUST_PARAM_ALL_REG(table, emc_r2w, ref);
+        ADJUST_PARAM_ALL_REG(table, emc_w2r, ref);
+        ADJUST_PARAM_ALL_REG(table, emc_r2p, ref);
+        ADJUST_PARAM_ALL_REG(table, emc_w2p, ref);
+        ADJUST_PARAM_ALL_REG(table, emc_trtm, ref);
+        ADJUST_PARAM_ALL_REG(table, emc_twtm, ref);
+        ADJUST_PARAM_ALL_REG(table, emc_tratm, ref);
+        ADJUST_PARAM_ALL_REG(table, emc_twatm, ref);
+        WRITE_PARAM_ALL_REG(table, emc_rd_rcd,  GET_CYCLE_CEIL(tRCD));
+        WRITE_PARAM_ALL_REG(table, emc_wr_rcd,  GET_CYCLE_CEIL(tRCD));
+        WRITE_PARAM_ALL_REG(table, emc_rrd,     GET_CYCLE_CEIL(tRRD));
+        WRITE_PARAM_ALL_REG(table, emc_refresh, REFRESH);
+        WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
+        WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tPDEX2));
+        WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tPDEX2));
+        WRITE_PARAM_ALL_REG(table, emc_act2pden,GET_CYCLE_CEIL(tACT2PDEN));
+        ADJUST_PARAM_ALL_REG(table, emc_rw2pden, ref);
+        WRITE_PARAM_ALL_REG(table, emc_cke2pden,GET_CYCLE_CEIL(tCKE2PDEN));
+        WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,GET_CYCLE_CEIL(tPDEX2MRR));
+        WRITE_PARAM_ALL_REG(table, emc_txsr,    GET_CYCLE_CEIL(tXSR));
+        WRITE_PARAM_ALL_REG(table, emc_txsrdll, GET_CYCLE_CEIL(tXSR));
+        WRITE_PARAM_ALL_REG(table, emc_tcke,    GET_CYCLE_CEIL(tCKE));
+        WRITE_PARAM_ALL_REG(table, emc_tckesr,  GET_CYCLE_CEIL(tCKELPD));
+        WRITE_PARAM_ALL_REG(table, emc_tpd,     GET_CYCLE_CEIL(tPD));
+        WRITE_PARAM_ALL_REG(table, emc_tfaw,    GET_CYCLE_CEIL(tFAW));
+        WRITE_PARAM_ALL_REG(table, emc_trpab,   GET_CYCLE_CEIL(tRPab));
+        ADJUST_PARAM_ALL_REG(table, emc_tclkstop, ref);
+        WRITE_PARAM_ALL_REG(table, emc_trefbw,  REFRESH + 64);
+
+        ADJUST_PARAM_ALL_REG(table, emc_pmacro_dll_cfg_2, ref); // EMC_DLL_CFG_2_0: level select for VDDA?
+
+        // ADJUST_PARAM_TABLE(table, dram_timings.rl); // not used on Mariko
+
+        constexpr u32 DIV = 4; // ?
+        table->burst_mc_regs.mc_emem_arb_timing_rcd = std::ceil(GET_CYCLE_CEIL(tRCD) / DIV - 2);
+        table->burst_mc_regs.mc_emem_arb_timing_rp  = std::ceil(GET_CYCLE_CEIL(tRPpb) / DIV - 1);
+        table->burst_mc_regs.mc_emem_arb_timing_rc  = std::ceil(std::max(GET_CYCLE_CEIL(tRC), GET_CYCLE_CEIL(tRAS)+GET_CYCLE_CEIL(tRPpb))/ DIV);
+        table->burst_mc_regs.mc_emem_arb_timing_ras = std::ceil(GET_CYCLE_CEIL(tRAS) / DIV - 2);
+        table->burst_mc_regs.mc_emem_arb_timing_faw = std::ceil(GET_CYCLE_CEIL(tFAW) / DIV - 1);
+        table->burst_mc_regs.mc_emem_arb_timing_rrd = std::ceil(GET_CYCLE_CEIL(tRRD) / DIV - 1);
+        table->burst_mc_regs.mc_emem_arb_timing_rap2pre = std::ceil(table->burst_regs.emc_r2p / DIV);
+        table->burst_mc_regs.mc_emem_arb_timing_wap2pre = std::ceil(table->burst_regs.emc_w2p / DIV);
+        table->burst_mc_regs.mc_emem_arb_timing_r2w = std::ceil(table->burst_regs.emc_r2w / DIV + 1);
+        table->burst_mc_regs.mc_emem_arb_timing_w2r = std::ceil(table->burst_regs.emc_w2r / DIV + 1);
+        table->burst_mc_regs.mc_emem_arb_timing_rfcpb = std::ceil(GET_CYCLE_CEIL(tRFCpb) / DIV + 1); // ?
+
+        ADJUST_PARAM_TABLE(table, la_scale_regs.mc_mll_mpcorer_ptsa_rate, ref);
+        ADJUST_PARAM_TABLE(table, la_scale_regs.mc_ptsa_grant_decrement, ref);
+
+        // ADJUST_PARAM_TABLE(table, min_mrs_wait); // not used on LPDDR4X
+        // ADJUST_PARAM_TABLE(table, latency); // not used
+
+        // Calculate DIVM and DIVN (clock DIVisors)
+        // Common PLL oscillator is 38.4 MHz
+        // PLLMB_OUT = 38.4 MHz / PLLLMB_DIVM * PLLMB_DIVN
+        u32 divm = 1;
+        u32 divn = GetEmcClock() / 38400;
+        u32 remainder = GetEmcClock() % 38400;
+        if (remainder >= 38400 * (3/4)) {
+            divm = 4;
+            divn = divn * divm + 3;
+        } else
+        if (remainder >= 38400 * (2/3)) {
+            divm = 3;
+            divn = divn * divm + 2;
+        } else
+        if (remainder >= 38400 * (1/2)) {
+            divm = 2;
+            divn = divn * divm + 1;
+        } else
+        if (remainder >= 38400 * (1/3)) {
+            divm = 3;
+            divn = divn * divm + 1;
+        } else
+        if (remainder >= 38400 * (1/4)) {
+            divm = 4;
+            divn = divn * divm + 1;
+        }
+
+        /* Patch PLLMB divisors */
+        table->pllmb_divm = divm;
+        table->pllmb_divn = divn;
+
+        #ifdef EXPERIMENTAL
+        {
             #define ADJUST_PARAM_ROUND2_ALL_REG(TARGET_TABLE, REF_TABLE, PARAM)                                                        \
                 TARGET_TABLE->burst_regs.PARAM =                                                                                       \
                     ((ADJUST_PROP(TARGET_TABLE->burst_regs.PARAM, REF_TABLE->burst_regs.PARAM) + 1) >> 1) << 1;                        \
@@ -317,124 +486,10 @@ namespace pcv {
             /* For latency allowance */
             #define ADJUST_INVERSE(TARGET) ((TARGET*1000) / (GetEmcClock()/1600))
 
-    #endif
-
-    #define ADJUST_PARAM(PARAM)                 PARAM = GetEmcClock()*PARAM/1600000;
-
-    #define ADJUST_PARAM_TABLE(TABLE, PARAM)    ADJUST_PARAM(TABLE->PARAM)
-
-    #define ADJUST_PARAM_ALL_REG(TABLE, PARAM)                 \
-        ADJUST_PARAM_TABLE(TABLE, burst_regs.PARAM)            \
-        ADJUST_PARAM_TABLE(TABLE, shadow_regs_ca_train.PARAM)  \
-        ADJUST_PARAM_TABLE(TABLE, shadow_regs_rdwr_train.PARAM)
-
-    void AdjustMtcTable(MarikoMtcTable* table)
-    {
-        /* Official Tegra X1 TRM, sign up for nvidia developer program (free) to download:
-         *     https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual
-         *     Section 18.11: MC Registers
-         *
-         * Retail Mariko: 200FBGA 16Gb DDP LPDDR4X SDRAM x 2
-         * x16/Ch, 1Ch/die, Double-die, 2Ch, 1CS(rank), 8Gb density per die
-         * 64Mb x 16DQ x 8banks x 2channels = 2048MB (x32DQ) per package
-         *
-         * Devkit Mariko: 200FBGA 32Gb DDP LPDDR4X SDRAM x 2
-         * x16/Ch, 1Ch/die, Quad-die,   2Ch, 2CS(rank), 8Gb density per die
-         * X1+ EMC can R/W to both ranks at the same time, resulting in doubled DQ
-         * 64Mb x 32DQ x 8banks x 2channels = 4096MB (x64DQ) per package
-         *
-         * If you have access to LPDDR4(X) specs or datasheets (from manufacturers or Google),
-         * you'd better calculate timings yourself rather than relying on following algorithm.
-         */
-
-        ADJUST_PARAM_ALL_REG(table, emc_rc);
-        ADJUST_PARAM_ALL_REG(table, emc_rfc);
-        ADJUST_PARAM_ALL_REG(table, emc_rfcpb);
-        ADJUST_PARAM_ALL_REG(table, emc_ras);
-        ADJUST_PARAM_ALL_REG(table, emc_rp);
-        ADJUST_PARAM_ALL_REG(table, emc_r2w);
-        ADJUST_PARAM_ALL_REG(table, emc_w2r);
-        ADJUST_PARAM_ALL_REG(table, emc_r2p);
-        ADJUST_PARAM_ALL_REG(table, emc_w2p);
-        ADJUST_PARAM_ALL_REG(table, emc_trtm);
-        ADJUST_PARAM_ALL_REG(table, emc_twtm);
-        ADJUST_PARAM_ALL_REG(table, emc_tratm);
-        ADJUST_PARAM_ALL_REG(table, emc_twatm);
-        ADJUST_PARAM_ALL_REG(table, emc_rd_rcd);
-        ADJUST_PARAM_ALL_REG(table, emc_wr_rcd);
-        ADJUST_PARAM_ALL_REG(table, emc_rrd);
-
-        ADJUST_PARAM_ALL_REG(table, emc_refresh);
-        ADJUST_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt);
-
-        ADJUST_PARAM_ALL_REG(table, emc_pdex2wr);
-        ADJUST_PARAM_ALL_REG(table, emc_pdex2rd);
-        ADJUST_PARAM_ALL_REG(table, emc_act2pden);
-        ADJUST_PARAM_ALL_REG(table, emc_rw2pden);
-        ADJUST_PARAM_ALL_REG(table, emc_cke2pden);
-        ADJUST_PARAM_ALL_REG(table, emc_pdex2mrr);
-
-        ADJUST_PARAM_ALL_REG(table, emc_txsr);
-        ADJUST_PARAM_ALL_REG(table, emc_txsrdll);
-        ADJUST_PARAM_ALL_REG(table, emc_tcke);
-        ADJUST_PARAM_ALL_REG(table, emc_tckesr);
-        ADJUST_PARAM_ALL_REG(table, emc_tpd);
-        ADJUST_PARAM_ALL_REG(table, emc_tfaw);
-        ADJUST_PARAM_ALL_REG(table, emc_trpab);
-        ADJUST_PARAM_ALL_REG(table, emc_tclkstop);
-        ADJUST_PARAM_ALL_REG(table, emc_trefbw);
-
-        ADJUST_PARAM_ALL_REG(table, emc_pmacro_dll_cfg_2);
-
-        ADJUST_PARAM_TABLE(table, dram_timings.rl);
-
-        ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_timing_rcd);
-        ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_timing_rp);
-        ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_timing_rc);
-        ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_timing_ras);
-        ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_timing_faw);
-        ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_timing_wap2pre);
-        ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_timing_r2w);
-        ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_timing_w2r);
-        ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_timing_rfcpb);
-
-        ADJUST_PARAM_TABLE(table, la_scale_regs.mc_mll_mpcorer_ptsa_rate);
-        ADJUST_PARAM_TABLE(table, la_scale_regs.mc_ptsa_grant_decrement);
-
-        ADJUST_PARAM_TABLE(table, min_mrs_wait);
-        ADJUST_PARAM_TABLE(table, latency);
-    }
-
-    #if 0
-    void AdjustMtcTable(MarikoMtcTable* target_table, MarikoMtcTable* ref_table)
-    {
-        /* Official Tegra X1 TRM, sign up for nvidia developer program (free) to download: */
-        /*     https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual */
-        /* Section 18.11: MC Registers */
-
-        /* Apparent timing parameters, simply adjust proportionally. */
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_rc);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_rfc);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_rfcpb);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_ras);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_rp);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_r2w);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_w2r);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_r2p);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_w2p);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_trtm);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_twtm);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_tratm);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_twatm);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_rd_rcd);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_wr_rcd);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_rrd);
-
             /* emc_wdv, emc_wsv, emc_wev, emc_wdv_mask,
                emc_quse, emc_quse_width, emc_ibdly, emc_obdly,
                emc_einput, emc_einput_duration, emc_qrst, emc_qsafe,
                emc_rdv, emc_rdv_mask, emc_rdv_early, emc_rdv_early_mask */
-        #ifdef EXPERIMENTAL
             ADJUST_PARAM_ROUND2_ALL_REG(target_table, ref_table, emc_wdv);
             ADJUST_PARAM_ROUND2_ALL_REG(target_table, ref_table, emc_wsv);
             ADJUST_PARAM_ROUND2_ALL_REG(target_table, ref_table, emc_wev);
@@ -461,36 +516,12 @@ namespace pcv {
             target_table->burst_regs.emc_rdv_early_mask = target_table->burst_regs.emc_rdv_early + 2;
             target_table->shadow_regs_ca_train.emc_rdv_early_mask = target_table->shadow_regs_ca_train.emc_rdv_early + 2;
             target_table->shadow_regs_rdwr_train.emc_rdv_early_mask = target_table->shadow_regs_rdwr_train.emc_rdv_early + 2;
-        #endif
-
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_refresh);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_pre_refresh_req_cnt);
-
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_pdex2wr);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_pdex2rd);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_act2pden);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_rw2pden);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_cke2pden);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_pdex2mrr);
-
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_txsr);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_txsrdll);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_tcke);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_tckesr);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_tpd);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_tfaw);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_trpab);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_tclkstop);
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_trefbw);
-
-        ADJUST_PARAM_ALL_REG(target_table, ref_table, emc_pmacro_dll_cfg_2);
 
             /* emc_pmacro_...,
                emc_zcal_wait_cnt, emc_mrs_wait_cnt(2),
                emc_pmacro_autocal_cfg_common, emc_dyn_self_ref_control, emc_qpop, emc_pmacro_cmd_pad_tx_ctrl,
                emc_tr_timing_0, emc_tr_rdv, emc_tr_qpop, emc_tr_rdv_mask, emc_tr_qsafe, emc_tr_qrst,
                emc_training_vref_settle */
-        #ifdef EXPERIMENTAL
             /* DDLL values */
             {
                 #define OFFSET_ALL_REG(PARAM)                               \
@@ -593,27 +624,6 @@ namespace pcv {
 
             ADJUST_BIT_ALL_REG_SINGLE_OP(target_table, ref_table, emc_training_vref_settle, 15,0, | (4 << 16));
 
-        #endif
-
-        ADJUST_PARAM_TABLE(target_table, ref_table, dram_timings.rl);
-
-        ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_timing_rcd);
-        ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_timing_rp);
-        ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_timing_rc);
-        ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_timing_ras);
-        ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_timing_faw);
-        ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_timing_wap2pre);
-        ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_timing_r2w);
-        ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_timing_w2r);
-        ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_timing_rfcpb);
-
-        ADJUST_PARAM_TABLE(target_table, ref_table, la_scale_regs.mc_mll_mpcorer_ptsa_rate);
-        ADJUST_PARAM_TABLE(target_table, ref_table, la_scale_regs.mc_ptsa_grant_decrement);
-
-        ADJUST_PARAM_TABLE(target_table, ref_table, min_mrs_wait);
-        ADJUST_PARAM_TABLE(target_table, ref_table, latency);
-
-        #ifdef EXPERIMENTAL
             /* External Memory Arbitration Configuration */
             /* BIT 20:16 - EXTRA_TICKS_PER_UPDATE: 0 */
             /* BIT 8:0   - CYCLES_PER_UPDATE: 12(1600MHz), 10(1331.2MHz) */
@@ -729,12 +739,36 @@ namespace pcv {
                  * pllm(b)_ss_ctrl2:
                  *      2,   1365 (1600MHz)
                  *      6, 0xFAAB (1331MHz)
+                 *
+                 * No need to care about this if Spread Spectrum (SS) is disabled
                  */
+                // Disable PLL Spread Spectrum Control
+                table->pll_en_ssc = 0;
+                table->pllm_ss_cfg = 1 << 30;
             }
 
             /* EMC misc. configuration */
             {
-            /* ? Command Trigger: MRW, MRW2: MRW_OP - [PMC] data to be written ? */
+                /* ? Command Trigger: MRW, MRW2: MRW_OP - [PMC] data to be written ?
+                 *
+                 *  EMC_MRW: MRW_OP
+                 * 1600 MHz: 0x54
+                 * 1331 MHz: 0x44
+                 * 1065 MHz: 0x34
+                 *  800 MHz: 0x34
+                 *  665 MHz: 0x14
+                 *  408 MHz: 0x04
+                 *  204 MHz: 0x04
+                 *
+                 * EMC_MRW2: MRW2_OP
+                 * 1600 MHz: 0x2D 45 5*9
+                 * 1331 MHz: 0x24 36 4*9
+                 * 1065 MHz: 0x1B 27 3*9
+                 *  800 MHz: 0x12 18 2*9
+                 *  665 MHz: 0x09  9 1*9
+                 *  408 MHz: 0x00
+                 *  204 MHz: 0x00
+                 */
                 {
 
                 }
@@ -746,10 +780,9 @@ namespace pcv {
                     target_table->emc_cfg_2 |= 7 << 3;
                 }
             }
-
-        #endif
         }
         #endif
+    }
 
     /* Unlock the second sub-partition for retail Mariko, and double the bandwidth (~60GB/s)
      * https://github.com/CTCaer/hekate/blob/01b6e645b3cb69ddf28cc9eff40c4b35bf03dbd4/bdk/mem/sdram.h#L30

Source/Atmosphere/stratosphere/loader/source/ldr_patcher.cpp

@@ -179,32 +179,18 @@ namespace ams::ldr {
                     /* Patch max GPU voltage on Mariko */
                     std::memcpy(reinterpret_cast<void *>(mapped_nso + pcv::GpuVoltageLimitOffsets[i]), &pcv::NewGpuVoltageLimit, sizeof(pcv::NewGpuVoltageLimit));
 
-                    /* Calculate DIVM and DIVN (clock DIVisors) */
-                    /* Assume oscillator (PLLMB_IN) is 38.4 MHz */
-                    /* PLLMB_OUT = PLLMB_IN / DIVM * DIVN */
-                    u32 divm = 1;
-                    u32 divn = GetEmcClock() / 38400;
-                    if (GetEmcClock() - divn * 38400 >= 38400 / 2) {
-                        divm = 2;
-                        divn = divn * 2 + 1;
-                    }
-
                     if (i >= 2) {
                         for (u32 j = 0; j < sizeof(pcv::MtcTable_1600[i-2])/sizeof(u32); j++) {
                             pcv::MarikoMtcTable* mtc_table_new = reinterpret_cast<pcv::MarikoMtcTable *>(mapped_nso + pcv::MtcTable_1600[i-2][j]);
                             pcv::MarikoMtcTable* mtc_table_old = reinterpret_cast<pcv::MarikoMtcTable *>(mapped_nso + pcv::MtcTable_1600[i-2][j] - pcv::MtcTableOffset);
 
                             #ifdef REPLACE_1331
-                            /* Replace 1331 MHz with 1600 MHz */
+                            /* Replace 1331 MHz with 1600 MHz, not possible without proper timings for oc clock */
                             std::memcpy(reinterpret_cast<void *>(mtc_table_old), reinterpret_cast<void *>(mtc_table_new), sizeof(pcv::MarikoMtcTable));
                             #endif
 
                             /* Generate new table for OC MHz */
-                            pcv::AdjustMtcTable(mtc_table_new);
+                            pcv::AdjustMtcTable(mtc_table_new, mtc_table_old);
-
-                            /* Patch clock divisors */
-                            mtc_table_1600->pllmb_divm = divm;
-                            mtc_table_1600->pllmb_divn = divn;
                         }
                     }