diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp
index c096757a..1c7db18e 100644
--- a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp
@@ -8,22 +8,29 @@ namespace ams::ldr::oc {
     #define CEIL(A)     std::ceil(A)
     #define FLOOR(A)    std::floor(A)
 
+    //Preset One
     const std::array<u32, 6> tRCD_values = {18, 17, 16, 15, 14, 13};
-    const std::array<u32, 6> tRP_values = {18, 17, 16, 15, 14, 13};
+    const std::array<u32, 6> tRP_values  = {18, 17, 16, 15, 14, 13};
     const std::array<u32, 6> tRAS_values = {42, 39, 36, 34, 32, 30};
 
+    // Preset Two
     const std::array<double, 5> tRRD_values = {10, 7.5, 6, 4, 3};
     const std::array<double, 5> tFAW_values = {40, 30, 24, 16, 12};
 
-    const std::array<u32, 6> tWR_values =     {18, 15, 15, 12, 12, 8};
+    // Preset Three
+    const std::array<u32, 6> tWR_values     = {18, 15, 15, 12, 12, 8};
     const std::array<double, 6> tRTP_values = {7.5, 7.5, 6, 6, 4, 4};
 
+    // Preset Four
     const std::array<u32, 5> tRFC_values = {140, 120, 100, 80, 60};
 
+    // Preset Five
     const std::array<u32, 6> tWTR_values = {10, 8, 6, 4, 2, 1};
 
+    // Preset Six
     const std::array<u32, 5> tREFpb_values = {488, 976, 1952, 3256, 9999};
 
+    // Preset Seven
     const std::array<u32, 6> tWL_values = {14, 12, 10, 8, 6, 4};
 
     const u32 TIMING_PRESET_ONE = C.ramTimingPresetOne;
@@ -34,20 +41,27 @@ namespace ams::ldr::oc {
     const u32 TIMING_PRESET_SIX = C.ramTimingPresetSix;
     const u32 TIMING_PRESET_SEVEN = C.ramTimingPresetSeven;
 
+    // Burst Length
     const u32 BL = 16;
 
     // tRFCpb (refresh cycle time per bank) in ns for 8Gb density
     const u32 tRFCpb = !TIMING_PRESET_FOUR ? 140 : tRFC_values[TIMING_PRESET_FOUR-1];
+    
     // tRFCab (refresh cycle time all banks) in ns for 8Gb density
     const u32 tRFCab = !TIMING_PRESET_FOUR ? 280 : 2*tRFCpb;
+    
     // tRAS (row active time) in ns
     const u32 tRAS = !TIMING_PRESET_ONE ? 42 : tRAS_values[TIMING_PRESET_ONE-1];
+    
     // tRPpb (row precharge time per bank) in ns
     const u32 tRPpb = !TIMING_PRESET_ONE ? 18 : tRP_values[TIMING_PRESET_ONE-1];
+    
     // tRPab (row precharge time all banks) in ns
     const u32 tRPab = !TIMING_PRESET_ONE ? 21 : tRPpb + 3;
+    
     // tRC (ACTIVATE-ACTIVATE command period same bank) in ns
     const u32 tRC = tRPpb + tRAS;
+    
     // DQS output access time from CK_t/CK_c
     const double tDQSCK_min = 1.5;
     // DQS output access time from CK_t/CK_c
@@ -56,62 +70,90 @@ namespace ams::ldr::oc {
     const double tWPRE = 1.8;
     // Read postamble (tCK)
     const double tRPST = 0.4;
-     // Write-to-Read delay
+    // WRITE command to first DQS transition(max) (tCK)
+    const double tDQSS_max = 1.25;
+    // DQ-to-DQS offset(max) (ns)
+    const double tDQS2DQ_max = 0.8;
+    // DQS_t, DQS_c to DQ skew total, per group, per access (DBI Disabled)
+    const double tDQSQ = 0.18;
+
+    // Write-to-Read delay
     const u32 tWTR = !TIMING_PRESET_FIVE ? 10 : tWTR_values[TIMING_PRESET_FIVE-1];
+    
     // Internal READ-to-PRE-CHARGE command delay in ns
     const double tRTP = !TIMING_PRESET_THREE ? 7.5 : tRTP_values[TIMING_PRESET_THREE-1];
+    
     // write recovery time
     const u32 tWR = !TIMING_PRESET_THREE ? 18 : tWR_values[TIMING_PRESET_THREE-1];
+    
     // Read to refresh delay
     const u32 tR2REF = tRTP + tRPpb;
+    
     // tRCD (RAS-CAS delay) in ns
     const u32 tRCD = !TIMING_PRESET_ONE ? 18 : tRCD_values[TIMING_PRESET_ONE-1];
+    
     // tRRD (Active bank-A to Active bank-B) in ns
     const double tRRD = !TIMING_PRESET_TWO ? 10. : tRRD_values[TIMING_PRESET_TWO-1];
+    
     // tREFpb (average refresh interval per bank) in ns for 8Gb density
     const u32 tREFpb = !TIMING_PRESET_SIX ? 488 : tREFpb_values[TIMING_PRESET_SIX-1];
     // tREFab (average refresh interval all 8 banks) in ns for 8Gb density
     // const u32 tREFab = tREFpb * 8;
+    
     // tPDEX2WR, tPDEX2RD (timing delay from exiting powerdown mode to a write/read command) in ns
     // const u32 tPDEX2 = 10;
     // Exit power-down to next valid command delay
     const double tXP = 7.5;
+    
     // Delay from valid command to CKE input LOW in ns
     const double tCMDCKE = 1.75;
+    
+    // tACT2PDEN (timing delay from an activate, MRS or EMRS command to power-down entry) in ns
     // Valid clock and CS requirement after CKE input LOW after MRW command
     const u32 tMRWCKEL = 14;
-    const double tDQSS_max = 1.25;
-    const double tDQS2DQ_max = 0.8;
+    
     // Valid CS requirement after CKE input LOW
     const double tCKELCS = 5;
+    
     // Valid CS requirement before CKE input HIGH
     const double tCSCKEH = 1.75;
+    
     // tXSR (SELF REFRESH exit to next valid command delay) in ns
     const double tXSR = tRFCab + 7.5;
+    
     // tCKE (minimum pulse width(HIGH and LOW pulse width)) in ns
     const double tCKE = 7.5;
+    
     // Minimum self refresh time (entry to exit)
     const u32 tSR = 15;
+    
     // tFAW (Four-bank Activate Window) in ns
     const u32 tFAW = !TIMING_PRESET_TWO ? 40 : tFAW_values[TIMING_PRESET_TWO-1];
+    
     // Valid Clock requirement before CKE Input HIGH in ns
     const double tCKCKEH = 1.75;
-    //const double tDQSQ = 0.18;
+    
     // p78 The first valid data is available RL × t CK + t DQSCK + t DQSQ
     //const u32 QUSE = RL + CEIL(tDQSCK_min/tCK_avg + tDQSQ);
 
     namespace pcv::erista {
         // tCK_avg (average clock period) in ns
         const double tCK_avg = 1000'000. / C.eristaEmcMaxClock;
+
+        // Write Latency
         const u32 WL = 18 - 2*TIMING_PRESET_SEVEN; //?
+        // Read Latency
         const u32 RL = 40 - 4*TIMING_PRESET_SEVEN; //?
 
         // minimum number of cycles from any read command to any write command, irrespective of bank
         const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6;
+        
         // Delay Time From WRITE-to-READ
         const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg) - 6;
+        
         // write-to-precharge time for commands to the same bank in cycles
         const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
+        
         // #_of_rows per die for 8Gb density
         const u32 numOfRows = 65536;
         // {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
@@ -119,35 +161,45 @@ namespace ams::ldr::oc {
         // 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
         const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.eristaEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
         const u32 REFBW = MIN((u32)65536, REFRESH+64);
+        
         // Write With Auto Precharge to to Power-Down Entry
         const u32 WTPDEN = WTP + 1 + CEIL(tDQSS_max/tCK_avg) + CEIL(tDQS2DQ_max/tCK_avg) + 6;
+        
         // Additional time after t XP hasexpired until the MRR commandmay be issued
         const double tMRRI = tRCD + 3 * tCK_avg;
-        // tACT2PDEN (timing delay from an activate, MRS or EMRS command to power-down entry) in ns
-        // tMRWCKEL : Valid clock and CS requirement after CKE input LOW after MRW command
+        
         // tPDEX2MRR (timing delay from exiting powerdown mode to MRR command) in ns
         const double tPDEX2MRR = tXP + tMRRI;
     }
     namespace pcv::mariko {
         // tCK_avg (average clock period) in ns
         const double tCK_avg = 1000'000. / C.marikoEmcMaxClock;
+        // Write Latency
         const u32 WL = 14 - 2*TIMING_PRESET_SEVEN; //?
+        // Read Latency
         const u32 RL = 28 - 4*TIMING_PRESET_SEVEN; //?
 
         // minimum number of cycles from any read command to any write command, irrespective of bank
         const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST));
+        
         // Delay Time From WRITE-to-READ
         const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg);
+        
         // write-to-precharge time for commands to the same bank in cycles
         const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg);
+        
         // Read-To-MRW delay
         const u32 RTM = RL + BL/2 + CEIL(tDQSCK_max/tCK_avg) + FLOOR(tRPST) + CEIL(7.5/tCK_avg);
+        
         // Write-To-MRW/MRR delay
         const u32 WTM = WL + 1 + BL/2 + CEIL(7.5/tCK_avg);
+        
         // Read With AP-To-MRW/MRR delay
         const u32 RATM = RTM + CEIL(tRTP/tCK_avg) - 8;
+        
         // Write With AP-To-MRW/MRR delay
         const u32 WATM = WTM + CEIL(tWR/tCK_avg);
+        
         // #_of_rows per die for 8Gb density
         const u32 numOfRows = 65536;
         // {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
@@ -155,12 +207,13 @@ namespace ams::ldr::oc {
         // 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
         const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.marikoEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
         const u32 REFBW = MIN((u32)65536, REFRESH+64);
+        
         // Write With Auto Precharge to to Power-Down Entry
         const u32 WTPDEN = WTP + 1 + CEIL(tDQSS_max/tCK_avg) + CEIL(tDQS2DQ_max/tCK_avg) + 6;
+        
         // Additional time after t XP hasexpired until the MRR commandmay be issued
         const double tMRRI = tRCD + 3 * tCK_avg;
-        // tACT2PDEN (timing delay from an activate, MRS or EMRS command to power-down entry) in ns
-        // tMRWCKEL : Valid clock and CS requirement after CKE input LOW after MRW command
+        
         // tPDEX2MRR (timing delay from exiting powerdown mode to MRR command) in ns
         const double tPDEX2MRR = tXP + tMRRI;
     }
diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp
index 851af181..1e003416 100644
--- a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp
@@ -38,53 +38,53 @@ void MemMtcTableAutoAdjust(EristaMtcTable* table) {
     if (C.mtcConf != AUTO_ADJ_ALL)
     	return;
 
-    #define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE)\
-    TABLE->burst_regs.PARAM = VALUE;            \
-    TABLE->shadow_regs_ca_train.PARAM = VALUE;  \
-    TABLE->shadow_regs_quse_train.PARAM = VALUE;  \
+    #define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \
+    TABLE->burst_regs.PARAM = VALUE;                 \
+    TABLE->shadow_regs_ca_train.PARAM = VALUE;       \
+    TABLE->shadow_regs_quse_train.PARAM = VALUE;     \
     TABLE->shadow_regs_rdwr_train.PARAM = VALUE;
  
-    #define GET_CYCLE_CEIL(PARAM) u32(CEIL(double(PARAM) / tCK_avg))
+    #define GET_CYCLE_CEIL(PARAM)   u32(CEIL(double(PARAM) / tCK_avg))
 
-    WRITE_PARAM_ALL_REG(table, emc_rc,      GET_CYCLE_CEIL(tRC));
-    WRITE_PARAM_ALL_REG(table, emc_rfc,     GET_CYCLE_CEIL(tRFCab));
-    WRITE_PARAM_ALL_REG(table, emc_rfcpb,   GET_CYCLE_CEIL(tRFCpb));
-    WRITE_PARAM_ALL_REG(table, emc_ras,     GET_CYCLE_CEIL(tRAS));
-    WRITE_PARAM_ALL_REG(table, emc_rp,      GET_CYCLE_CEIL(tRPpb));
-    WRITE_PARAM_ALL_REG(table, emc_r2w,     R2W);
-    WRITE_PARAM_ALL_REG(table, emc_w2r,     W2R);
-    WRITE_PARAM_ALL_REG(table, emc_r2p,     GET_CYCLE_CEIL(tRTP));
-    WRITE_PARAM_ALL_REG(table, emc_w2p,     WTP);
-    WRITE_PARAM_ALL_REG(table, emc_rd_rcd,  GET_CYCLE_CEIL(tRCD));
-    WRITE_PARAM_ALL_REG(table, emc_wr_rcd,  GET_CYCLE_CEIL(tRCD));
-    WRITE_PARAM_ALL_REG(table, emc_rrd,     GET_CYCLE_CEIL(tRRD));
-    WRITE_PARAM_ALL_REG(table, emc_refresh, REFRESH);
+    WRITE_PARAM_ALL_REG(table, emc_rc,                  GET_CYCLE_CEIL(tRC));
+    WRITE_PARAM_ALL_REG(table, emc_rfc,                 GET_CYCLE_CEIL(tRFCab));
+    WRITE_PARAM_ALL_REG(table, emc_rfcpb,               GET_CYCLE_CEIL(tRFCpb));
+    WRITE_PARAM_ALL_REG(table, emc_ras,                 GET_CYCLE_CEIL(tRAS));
+    WRITE_PARAM_ALL_REG(table, emc_rp,                  GET_CYCLE_CEIL(tRPpb));
+    WRITE_PARAM_ALL_REG(table, emc_r2w,                 R2W);
+    WRITE_PARAM_ALL_REG(table, emc_w2r,                 W2R);
+    WRITE_PARAM_ALL_REG(table, emc_r2p,                 GET_CYCLE_CEIL(tRTP));
+    WRITE_PARAM_ALL_REG(table, emc_w2p,                 WTP);
+    WRITE_PARAM_ALL_REG(table, emc_rd_rcd,              GET_CYCLE_CEIL(tRCD));
+    WRITE_PARAM_ALL_REG(table, emc_wr_rcd,              GET_CYCLE_CEIL(tRCD));
+    WRITE_PARAM_ALL_REG(table, emc_rrd,                 GET_CYCLE_CEIL(tRRD));
+    WRITE_PARAM_ALL_REG(table, emc_refresh,             REFRESH);
     WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
-    WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tXP));
-    WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tXP));
-    WRITE_PARAM_ALL_REG(table, emc_pchg2pden, GET_CYCLE_CEIL(tCMDCKE));
-    WRITE_PARAM_ALL_REG(table, emc_act2pden,GET_CYCLE_CEIL(tMRWCKEL));
-    WRITE_PARAM_ALL_REG(table, emc_ar2pden, GET_CYCLE_CEIL(tCMDCKE));
-    WRITE_PARAM_ALL_REG(table, emc_rw2pden, WTPDEN);
-    WRITE_PARAM_ALL_REG(table, emc_cke2pden, GET_CYCLE_CEIL(tCKELCS));
-    WRITE_PARAM_ALL_REG(table, emc_pdex2cke, GET_CYCLE_CEIL(tCSCKEH));
-    WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,GET_CYCLE_CEIL(tPDEX2MRR));
-    WRITE_PARAM_ALL_REG(table, emc_txsr,    MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
-    WRITE_PARAM_ALL_REG(table, emc_txsrdll, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
-    WRITE_PARAM_ALL_REG(table, emc_tcke,    GET_CYCLE_CEIL(tCKE));
-    WRITE_PARAM_ALL_REG(table, emc_tckesr,  GET_CYCLE_CEIL(tSR));
-    WRITE_PARAM_ALL_REG(table, emc_tpd,     GET_CYCLE_CEIL(tCKE));
-    WRITE_PARAM_ALL_REG(table, emc_tfaw,    GET_CYCLE_CEIL(tFAW));
-    WRITE_PARAM_ALL_REG(table, emc_trpab,   GET_CYCLE_CEIL(tRPab));
-    WRITE_PARAM_ALL_REG(table, emc_tclkstable, GET_CYCLE_CEIL(tCKCKEH));
-    WRITE_PARAM_ALL_REG(table, emc_tclkstop, GET_CYCLE_CEIL(tCKE)+8);
-    WRITE_PARAM_ALL_REG(table, emc_trefbw,  REFBW);
+    WRITE_PARAM_ALL_REG(table, emc_pdex2wr,             GET_CYCLE_CEIL(tXP));
+    WRITE_PARAM_ALL_REG(table, emc_pdex2rd,             GET_CYCLE_CEIL(tXP));
+    WRITE_PARAM_ALL_REG(table, emc_pchg2pden,           GET_CYCLE_CEIL(tCMDCKE));
+    WRITE_PARAM_ALL_REG(table, emc_act2pden,            GET_CYCLE_CEIL(tMRWCKEL));
+    WRITE_PARAM_ALL_REG(table, emc_ar2pden,             GET_CYCLE_CEIL(tCMDCKE));
+    WRITE_PARAM_ALL_REG(table, emc_rw2pden,             WTPDEN);
+    WRITE_PARAM_ALL_REG(table, emc_cke2pden,            GET_CYCLE_CEIL(tCKELCS));
+    WRITE_PARAM_ALL_REG(table, emc_pdex2cke,            GET_CYCLE_CEIL(tCSCKEH));
+    WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,            GET_CYCLE_CEIL(tPDEX2MRR));
+    WRITE_PARAM_ALL_REG(table, emc_txsr,                MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
+    WRITE_PARAM_ALL_REG(table, emc_txsrdll,             MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
+    WRITE_PARAM_ALL_REG(table, emc_tcke,                GET_CYCLE_CEIL(tCKE));
+    WRITE_PARAM_ALL_REG(table, emc_tckesr,              GET_CYCLE_CEIL(tSR));
+    WRITE_PARAM_ALL_REG(table, emc_tpd,                 GET_CYCLE_CEIL(tCKE));
+    WRITE_PARAM_ALL_REG(table, emc_tfaw,                GET_CYCLE_CEIL(tFAW));
+    WRITE_PARAM_ALL_REG(table, emc_trpab,               GET_CYCLE_CEIL(tRPab));
+    WRITE_PARAM_ALL_REG(table, emc_tclkstable,          GET_CYCLE_CEIL(tCKCKEH));
+    WRITE_PARAM_ALL_REG(table, emc_tclkstop,            GET_CYCLE_CEIL(tCKE)+8);
+    WRITE_PARAM_ALL_REG(table, emc_trefbw,              REFBW);
     
     constexpr u32 MC_ARB_DIV = 4;
     constexpr u32 MC_ARB_SFA = 2;
     table->burst_mc_regs.mc_emem_arb_timing_rcd     = CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV) - 2;
     table->burst_mc_regs.mc_emem_arb_timing_rp      = CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV) - 1 + MC_ARB_SFA;
-    table->burst_mc_regs.mc_emem_arb_timing_rc      = CEIL(MAX(GET_CYCLE_CEIL(tRC), GET_CYCLE_CEIL(tRAS)+GET_CYCLE_CEIL(tRPpb)) / MC_ARB_DIV) - 1;
+    table->burst_mc_regs.mc_emem_arb_timing_rc      = CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV) - 1;
     table->burst_mc_regs.mc_emem_arb_timing_ras     = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2;
     table->burst_mc_regs.mc_emem_arb_timing_faw     = CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1;
     table->burst_mc_regs.mc_emem_arb_timing_rrd     = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1;
@@ -103,71 +103,71 @@ void MemMtcTableCustomAdjust(EristaMtcTable* table) {
     	return;
        
     constexpr u32 MC_ARB_DIV = 4;
-    constexpr u32 SFA = 2;
+    constexpr u32 MC_ARB_SFA = 2;
 
     if (TIMING_PRESET_ONE) {
-        WRITE_PARAM_ALL_REG(table, emc_rc,      GET_CYCLE_CEIL(tRC));
-        WRITE_PARAM_ALL_REG(table, emc_ras,     GET_CYCLE_CEIL(tRAS));
-        WRITE_PARAM_ALL_REG(table, emc_rp,      GET_CYCLE_CEIL(tRPpb));
-        WRITE_PARAM_ALL_REG(table, emc_trpab,   GET_CYCLE_CEIL(tRPab));
-        WRITE_PARAM_ALL_REG(table, emc_rd_rcd,  GET_CYCLE_CEIL(tRCD));
-        WRITE_PARAM_ALL_REG(table, emc_wr_rcd,  GET_CYCLE_CEIL(tRCD));
-        WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,GET_CYCLE_CEIL(tPDEX2MRR));
+        WRITE_PARAM_ALL_REG(table, emc_rc,       GET_CYCLE_CEIL(tRC));
+        WRITE_PARAM_ALL_REG(table, emc_ras,      GET_CYCLE_CEIL(tRAS));
+        WRITE_PARAM_ALL_REG(table, emc_rp,       GET_CYCLE_CEIL(tRPpb));
+        WRITE_PARAM_ALL_REG(table, emc_trpab,    GET_CYCLE_CEIL(tRPab));
+        WRITE_PARAM_ALL_REG(table, emc_rd_rcd,   GET_CYCLE_CEIL(tRCD));
+        WRITE_PARAM_ALL_REG(table, emc_wr_rcd,   GET_CYCLE_CEIL(tRCD));
+        WRITE_PARAM_ALL_REG(table, emc_pdex2mrr, GET_CYCLE_CEIL(tPDEX2MRR));
 
         table->burst_mc_regs.mc_emem_arb_timing_rcd     = CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV - 2);
         table->burst_mc_regs.mc_emem_arb_timing_rc      = CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV - 1);
-        table->burst_mc_regs.mc_emem_arb_timing_rp      = CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV - 1 + SFA);
+        table->burst_mc_regs.mc_emem_arb_timing_rp      = CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV - 1 + MC_ARB_SFA);
         table->burst_mc_regs.mc_emem_arb_timing_ras     = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV - 2);
-        
     }
+
     if (TIMING_PRESET_TWO) {
-        WRITE_PARAM_ALL_REG(table, emc_tfaw,    GET_CYCLE_CEIL(tFAW));
-        WRITE_PARAM_ALL_REG(table, emc_rrd,     GET_CYCLE_CEIL(tRRD));
+        WRITE_PARAM_ALL_REG(table, emc_tfaw,     GET_CYCLE_CEIL(tFAW));
+        WRITE_PARAM_ALL_REG(table, emc_rrd,      GET_CYCLE_CEIL(tRRD));
 
         table->burst_mc_regs.mc_emem_arb_timing_faw     = CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1;
         table->burst_mc_regs.mc_emem_arb_timing_rrd     = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1;
     }
 
     if (TIMING_PRESET_THREE) {
-        WRITE_PARAM_ALL_REG(table, emc_r2p,     GET_CYCLE_CEIL(tRTP));
-        WRITE_PARAM_ALL_REG(table, emc_w2p,     WTP);
-        WRITE_PARAM_ALL_REG(table, emc_rw2pden, WTPDEN);
+        WRITE_PARAM_ALL_REG(table, emc_r2p,      GET_CYCLE_CEIL(tRTP));
+        WRITE_PARAM_ALL_REG(table, emc_w2p,      WTP);
+        WRITE_PARAM_ALL_REG(table, emc_rw2pden,  WTPDEN);
 
         table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV);
         table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
     }
 
     if (TIMING_PRESET_FOUR) {
-        WRITE_PARAM_ALL_REG(table, emc_rfc,     GET_CYCLE_CEIL(tRFCab));
-        WRITE_PARAM_ALL_REG(table, emc_rfcpb,   GET_CYCLE_CEIL(tRFCpb));
-        WRITE_PARAM_ALL_REG(table, emc_txsr,    MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
-        WRITE_PARAM_ALL_REG(table, emc_txsrdll, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
+        WRITE_PARAM_ALL_REG(table, emc_rfc,      GET_CYCLE_CEIL(tRFCab));
+        WRITE_PARAM_ALL_REG(table, emc_rfcpb,    GET_CYCLE_CEIL(tRFCpb));
+        WRITE_PARAM_ALL_REG(table, emc_txsr,     MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
+        WRITE_PARAM_ALL_REG(table, emc_txsrdll,  MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
 
         table->burst_mc_regs.mc_emem_arb_timing_rfcpb   = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV);
     }
+
     if (TIMING_PRESET_FIVE) {
         WRITE_PARAM_ALL_REG(table, emc_w2r, W2R);
 
-        table->burst_mc_regs.mc_emem_arb_timing_w2r     = CEIL(W2R / MC_ARB_DIV) - 1 + SFA;
+        table->burst_mc_regs.mc_emem_arb_timing_w2r     = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
     }
 
     if (TIMING_PRESET_SIX) {
-        WRITE_PARAM_ALL_REG(table, emc_refresh, REFRESH);
+        WRITE_PARAM_ALL_REG(table, emc_refresh,  REFRESH);
         WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
-        WRITE_PARAM_ALL_REG(table, emc_trefbw,  REFRESH + 64);
+        WRITE_PARAM_ALL_REG(table, emc_trefbw,   REFBW);
     }
 
     if (TIMING_PRESET_SEVEN) {
-        WRITE_PARAM_ALL_REG(table, emc_w2r,     W2R);
-        WRITE_PARAM_ALL_REG(table, emc_w2p,     WTP);
-        WRITE_PARAM_ALL_REG(table, emc_rw2pden, WTPDEN);
-        WRITE_PARAM_ALL_REG(table, emc_r2w,     R2W);
-
+        WRITE_PARAM_ALL_REG(table, emc_r2w,      R2W);
+        WRITE_PARAM_ALL_REG(table, emc_w2r,      W2R);
+        WRITE_PARAM_ALL_REG(table, emc_w2p,      WTP);
+        WRITE_PARAM_ALL_REG(table, emc_rw2pden,  WTPDEN);
+        
         table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
-        table->burst_mc_regs.mc_emem_arb_timing_r2w     = CEIL(R2W / MC_ARB_DIV) - 1 + SFA;
-        table->burst_mc_regs.mc_emem_arb_timing_w2r     = CEIL(W2R / MC_ARB_DIV) - 1 + SFA;
+        table->burst_mc_regs.mc_emem_arb_timing_r2w     = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA;
+        table->burst_mc_regs.mc_emem_arb_timing_w2r     = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
     }
-    
 }
 
 Result MemFreqMtcTable(u32* ptr) {
diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp
index 7b83291e..f3f6e2c0 100644
--- a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp
@@ -139,49 +139,48 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
     TABLE->shadow_regs_rdwr_train.PARAM = VALUE;
  
     ADJUST_PARAM_TABLE(table, la_scale_regs.mc_mll_mpcorer_ptsa_rate, ref);
-    ADJUST_PARAM_TABLE(table, la_scale_regs.mc_ftop_ptsa_rate, ref);
     ADJUST_PARAM_TABLE(table, la_scale_regs.mc_ptsa_grant_decrement, ref);
 
     #define GET_CYCLE_CEIL(PARAM) u32(CEIL(double(PARAM) / tCK_avg))
-
-    WRITE_PARAM_ALL_REG(table, emc_rc,      GET_CYCLE_CEIL(tRC));
-    WRITE_PARAM_ALL_REG(table, emc_rfc,     GET_CYCLE_CEIL(tRFCab));
-    WRITE_PARAM_ALL_REG(table, emc_rfcpb,   GET_CYCLE_CEIL(tRFCpb));
-    WRITE_PARAM_ALL_REG(table, emc_ras,     GET_CYCLE_CEIL(tRAS));
-    WRITE_PARAM_ALL_REG(table, emc_rp,      GET_CYCLE_CEIL(tRPpb));
-    WRITE_PARAM_ALL_REG(table, emc_r2w,     R2W);
-    WRITE_PARAM_ALL_REG(table, emc_w2r,     W2R);
-    WRITE_PARAM_ALL_REG(table, emc_r2p,     GET_CYCLE_CEIL(tRTP));
-    WRITE_PARAM_ALL_REG(table, emc_w2p,     WTP);
-    WRITE_PARAM_ALL_REG(table, emc_trtm,    RTM);
-    WRITE_PARAM_ALL_REG(table, emc_twtm,    WTM);
-    WRITE_PARAM_ALL_REG(table, emc_tratm,   RATM);
-    WRITE_PARAM_ALL_REG(table, emc_twatm,   WATM);
-    WRITE_PARAM_ALL_REG(table, emc_tr2ref,  GET_CYCLE_CEIL(tR2REF));
-    WRITE_PARAM_ALL_REG(table, emc_rd_rcd,  GET_CYCLE_CEIL(tRCD));
-    WRITE_PARAM_ALL_REG(table, emc_wr_rcd,  GET_CYCLE_CEIL(tRCD));
-    WRITE_PARAM_ALL_REG(table, emc_rrd,     GET_CYCLE_CEIL(tRRD));
-    WRITE_PARAM_ALL_REG(table, emc_refresh, REFRESH);
+   
+    WRITE_PARAM_ALL_REG(table, emc_rc,                  GET_CYCLE_CEIL(tRC));
+    WRITE_PARAM_ALL_REG(table, emc_rfc,                 GET_CYCLE_CEIL(tRFCab));
+    WRITE_PARAM_ALL_REG(table, emc_rfcpb,               GET_CYCLE_CEIL(tRFCpb));
+    WRITE_PARAM_ALL_REG(table, emc_ras,                 GET_CYCLE_CEIL(tRAS));
+    WRITE_PARAM_ALL_REG(table, emc_rp,                  GET_CYCLE_CEIL(tRPpb));
+    WRITE_PARAM_ALL_REG(table, emc_r2w,                 R2W);
+    WRITE_PARAM_ALL_REG(table, emc_w2r,                 W2R);
+    WRITE_PARAM_ALL_REG(table, emc_r2p,                 GET_CYCLE_CEIL(tRTP));
+    WRITE_PARAM_ALL_REG(table, emc_w2p,                 WTP);
+    WRITE_PARAM_ALL_REG(table, emc_trtm,                RTM);
+    WRITE_PARAM_ALL_REG(table, emc_twtm,                WTM);
+    WRITE_PARAM_ALL_REG(table, emc_tratm,               RATM);
+    WRITE_PARAM_ALL_REG(table, emc_twatm,               WATM);
+    WRITE_PARAM_ALL_REG(table, emc_tr2ref,              GET_CYCLE_CEIL(tR2REF));
+    WRITE_PARAM_ALL_REG(table, emc_rd_rcd,              GET_CYCLE_CEIL(tRCD));
+    WRITE_PARAM_ALL_REG(table, emc_wr_rcd,              GET_CYCLE_CEIL(tRCD));
+    WRITE_PARAM_ALL_REG(table, emc_rrd,                 GET_CYCLE_CEIL(tRRD));
+    WRITE_PARAM_ALL_REG(table, emc_refresh,             REFRESH);
     WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
-    WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tXP));
-    WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tXP));
-    WRITE_PARAM_ALL_REG(table, emc_pchg2pden, GET_CYCLE_CEIL(tCMDCKE));
-    WRITE_PARAM_ALL_REG(table, emc_act2pden,GET_CYCLE_CEIL(tMRWCKEL));
-    WRITE_PARAM_ALL_REG(table, emc_ar2pden, GET_CYCLE_CEIL(tCMDCKE));
-    WRITE_PARAM_ALL_REG(table, emc_rw2pden, WTPDEN);
-    WRITE_PARAM_ALL_REG(table, emc_cke2pden, GET_CYCLE_CEIL(tCKELCS));
-    WRITE_PARAM_ALL_REG(table, emc_pdex2cke, GET_CYCLE_CEIL(tCSCKEH));
-    WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,GET_CYCLE_CEIL(tPDEX2MRR));
-    WRITE_PARAM_ALL_REG(table, emc_txsr,    MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
-    WRITE_PARAM_ALL_REG(table, emc_txsrdll, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
-    WRITE_PARAM_ALL_REG(table, emc_tcke,    GET_CYCLE_CEIL(tCKE));
-    WRITE_PARAM_ALL_REG(table, emc_tckesr,  GET_CYCLE_CEIL(tSR));
-    WRITE_PARAM_ALL_REG(table, emc_tpd,     GET_CYCLE_CEIL(tCKE));
-    WRITE_PARAM_ALL_REG(table, emc_tfaw,    GET_CYCLE_CEIL(tFAW));
-    WRITE_PARAM_ALL_REG(table, emc_trpab,   GET_CYCLE_CEIL(tRPab));
-    WRITE_PARAM_ALL_REG(table, emc_tclkstable, GET_CYCLE_CEIL(tCKCKEH));
-    WRITE_PARAM_ALL_REG(table, emc_tclkstop, GET_CYCLE_CEIL(tCKE)+8);
-    WRITE_PARAM_ALL_REG(table, emc_trefbw,  REFBW);
+    WRITE_PARAM_ALL_REG(table, emc_pdex2wr,             GET_CYCLE_CEIL(tXP));
+    WRITE_PARAM_ALL_REG(table, emc_pdex2rd,             GET_CYCLE_CEIL(tXP));
+    WRITE_PARAM_ALL_REG(table, emc_pchg2pden,           GET_CYCLE_CEIL(tCMDCKE));
+    WRITE_PARAM_ALL_REG(table, emc_act2pden,            GET_CYCLE_CEIL(tMRWCKEL));
+    WRITE_PARAM_ALL_REG(table, emc_ar2pden,             GET_CYCLE_CEIL(tCMDCKE));
+    WRITE_PARAM_ALL_REG(table, emc_rw2pden,             WTPDEN);
+    WRITE_PARAM_ALL_REG(table, emc_cke2pden,            GET_CYCLE_CEIL(tCKELCS));
+    WRITE_PARAM_ALL_REG(table, emc_pdex2cke,            GET_CYCLE_CEIL(tCSCKEH));
+    WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,            GET_CYCLE_CEIL(tPDEX2MRR));
+    WRITE_PARAM_ALL_REG(table, emc_txsr,                MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
+    WRITE_PARAM_ALL_REG(table, emc_txsrdll,             MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
+    WRITE_PARAM_ALL_REG(table, emc_tcke,                GET_CYCLE_CEIL(tCKE));
+    WRITE_PARAM_ALL_REG(table, emc_tckesr,              GET_CYCLE_CEIL(tSR));
+    WRITE_PARAM_ALL_REG(table, emc_tpd,                 GET_CYCLE_CEIL(tCKE));
+    WRITE_PARAM_ALL_REG(table, emc_tfaw,                GET_CYCLE_CEIL(tFAW));
+    WRITE_PARAM_ALL_REG(table, emc_trpab,               GET_CYCLE_CEIL(tRPab));
+    WRITE_PARAM_ALL_REG(table, emc_tclkstable,          GET_CYCLE_CEIL(tCKCKEH));
+    WRITE_PARAM_ALL_REG(table, emc_tclkstop,            GET_CYCLE_CEIL(tCKE)+8);
+    WRITE_PARAM_ALL_REG(table, emc_trefbw,              REFBW);
     
     constexpr u32 MC_ARB_DIV = 4;
     constexpr u32 MC_ARB_SFA = 2;
@@ -206,7 +205,7 @@ void MemMtcTableCustomAdjust(MarikoMtcTable* table) {
     	return;
        
     constexpr u32 MC_ARB_DIV = 4;
-    constexpr u32 SFA = 2;
+    constexpr u32 MC_ARB_SFA = 2;
 
     if (TIMING_PRESET_ONE) {
         WRITE_PARAM_ALL_REG(table, emc_rc,      GET_CYCLE_CEIL(tRC));
@@ -217,12 +216,13 @@ void MemMtcTableCustomAdjust(MarikoMtcTable* table) {
         WRITE_PARAM_ALL_REG(table, emc_wr_rcd,  GET_CYCLE_CEIL(tRCD));
         WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,GET_CYCLE_CEIL(tPDEX2MRR));
 
-        table->burst_mc_regs.mc_emem_arb_timing_rcd     = CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV - 2);
-        table->burst_mc_regs.mc_emem_arb_timing_rc      = CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV - 1);
-        table->burst_mc_regs.mc_emem_arb_timing_rp      = CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV - 1 + SFA);
-        table->burst_mc_regs.mc_emem_arb_timing_ras     = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV - 2);
+        table->burst_mc_regs.mc_emem_arb_timing_rcd     = CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV) - 2;
+        table->burst_mc_regs.mc_emem_arb_timing_rc      = CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV) - 1;
+        table->burst_mc_regs.mc_emem_arb_timing_rp      = CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV) - 1 + MC_ARB_SFA;
+        table->burst_mc_regs.mc_emem_arb_timing_ras     = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2;
         
     }
+    
     if (TIMING_PRESET_TWO) {
         WRITE_PARAM_ALL_REG(table, emc_tfaw,    GET_CYCLE_CEIL(tFAW));
         WRITE_PARAM_ALL_REG(table, emc_rrd,     GET_CYCLE_CEIL(tRRD));
@@ -250,33 +250,33 @@ void MemMtcTableCustomAdjust(MarikoMtcTable* table) {
 
         table->burst_mc_regs.mc_emem_arb_timing_rfcpb   = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV);
     }
+
     if (TIMING_PRESET_FIVE) {
         WRITE_PARAM_ALL_REG(table, emc_w2r, W2R);
 
-        table->burst_mc_regs.mc_emem_arb_timing_w2r     = CEIL(W2R / MC_ARB_DIV) - 1 + SFA;
+        table->burst_mc_regs.mc_emem_arb_timing_w2r     = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
     }
 
     if (TIMING_PRESET_SIX) {
         WRITE_PARAM_ALL_REG(table, emc_refresh, REFRESH);
         WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
-        WRITE_PARAM_ALL_REG(table, emc_trefbw,  REFRESH + 64);
+        WRITE_PARAM_ALL_REG(table, emc_trefbw,  REFBW);
     }
 
     if (TIMING_PRESET_SEVEN) {
+        WRITE_PARAM_ALL_REG(table, emc_r2w,     R2W);
         WRITE_PARAM_ALL_REG(table, emc_w2r,     W2R);
         WRITE_PARAM_ALL_REG(table, emc_w2p,     WTP);
-        WRITE_PARAM_ALL_REG(table, emc_rw2pden, WTPDEN);
-        WRITE_PARAM_ALL_REG(table, emc_r2w,     R2W);
         WRITE_PARAM_ALL_REG(table, emc_trtm,    RTM);
         WRITE_PARAM_ALL_REG(table, emc_twtm,    WTM);
         WRITE_PARAM_ALL_REG(table, emc_tratm,   RATM);
         WRITE_PARAM_ALL_REG(table, emc_twatm,   WATM);
+        WRITE_PARAM_ALL_REG(table, emc_rw2pden, WTPDEN);
 
         table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
-        table->burst_mc_regs.mc_emem_arb_timing_r2w     = CEIL(R2W / MC_ARB_DIV) - 1 + SFA;
-        table->burst_mc_regs.mc_emem_arb_timing_w2r     = CEIL(W2R / MC_ARB_DIV) - 1 + SFA;
+        table->burst_mc_regs.mc_emem_arb_timing_r2w     = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA;
+        table->burst_mc_regs.mc_emem_arb_timing_w2r     = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
     }
-    
 }
 
 void MemMtcPllmbDivisor(MarikoMtcTable* table) {