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This commit is contained in:
KazushiM
2021-11-15 20:44:53 +08:00
parent 64f35449c9
commit e3feada420
39 changed files with 236 additions and 1012 deletions
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153
Source/Atmosphere/ldr_oc_patch.inc Normal file
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@@ -0,0 +1,153 @@
constexpr ro::ModuleId PcvModuleId[] = {
ParseModuleId("91D61D59D7002378E35584FC0B38C7693A3ABAB5"), //11.0.0
ParseModuleId("C503E96550F302E121873136B814A529863D949B"), //12.x
ParseModuleId("2058C97C551571506656AA04EC85E2B1B01B155C"), //13.0.0-13.1.0
};
constexpr ro::ModuleId PtmModuleId[] = {
ParseModuleId("A79706954C6C45568B0FFE610627E2E89D8FB0D4"), //12.x
ParseModuleId("2CA78D4066C1C11317CC2705EBADA9A51D3AC981"), //13.0.0-13.1.0
};
constexpr ro::ModuleId AmModuleId[] = {
ParseModuleId("5E5F1CC24D374591AFC2A2336C9453CCFA3961C1"), //12.x
ParseModuleId("2C1AD224328D2AF8B2C1A240D0175A108916AC8C"), //13.0.0
ParseModuleId("75A273B296056EAC7A453C4C5B38C257EA9F4A6E"), //13.1.0
};
constexpr u32 AmCopyrightOffset[] = {
0xCA314,
0xCB80C,
0xCBA8C,
};
constexpr u8 AmCopyrightPatch[] = { 0xE0, 0x03, 0x1F, 0xAA, 0xC0, 0x03, 0x5F, 0xD6 };
constexpr u32 EmcFreqOffsets[][30] = {
{ 0xD7C60, 0xD7C68, 0xD7C70, 0xD7C78, 0xD7C80, 0xD7C88, 0xD7C90, 0xD7C98, 0xD7CA0, 0xD7CA8, 0xE1800, 0xEEFA0, 0xF2478, 0xFE284, 0x10A304, 0x10D7DC, 0x110A40, 0x113CA4, 0x116F08, 0x11A16C, 0x11D3D0, 0x120634, 0x123898, 0x126AFC, 0x129D60, 0x12CFC4, 0x130228, 0x13BFE0, 0x140D00, 0x140D50, },
{ 0xE1810, 0xE6530, 0xE6580, 0xE6AB0, 0xE6AB8, 0xE6AC0, 0xE6AC8, 0xE6AD0, 0xE6AD8, 0xE6AE0, 0xE6AE8, 0xE6AF0, 0xE6AF8, 0xF0650, 0xFDDF0, 0x1012C8, 0x10D0D4, 0x119154, 0x11C62C, 0x11F890, 0x122AF4, 0x125D58, 0x128FBC, 0x12C220, 0x12F484, 0x1326E8, 0x13594C, 0x138BB0, 0x13BE14, 0x13F078, },
{ 0xE1860, 0xE6580, 0xE65D0, 0xE6B00, 0xE6B08, 0xE6B10, 0xE6B18, 0xE6B20, 0xE6B28, 0xE6B30, 0xE6B38, 0xE6B40, 0xE6B48, 0xF06A0, 0xFDE40, 0x101318, 0x10D124, 0x1191A4, 0x11C67C, 0x11F8E0, 0x122B44, 0x125DA8, 0x12900C, 0x12C270, 0x12F4D4, 0x132738, 0x13599C, 0x138C00, 0x13BE64, 0x13F0C8, },
};
typedef struct {
u32 hz = 0;
u32 volt = 0;
u32 unk[6] = {0};
s32 coeffs[6] = {0};
} gpu_clock_table_t;
typedef struct {
u32 hz = 0;
u32 unk1 = 0;
s32 coeffs[6] = {0};
u32 volt = 0;
u32 unk3[5] = {0};
} cpu_clock_table_t;
/* CPU */
constexpr u32 CpuVoltageLimitOffsets[][11] = {
{ 0xE1A8C, 0xE1A98, 0xE1AA4, 0xE1AB0, 0xE1AF8, 0xE1B04, 0xE1B10, 0xE1B1C, 0xE1B28, 0xE1B34, 0xE1F4C },
{ 0xF08DC, 0xF08E8, 0xF08F4, 0xF0900, 0xF0948, 0xF0954, 0xF0960, 0xF096C, 0xF0978, 0xF0984, 0xF0D9C },
{ 0xF092C, 0xF0938, 0xF0944, 0xF0950, 0xF0998, 0xF09A4, 0xF09B0, 0xF09BC, 0xF09C8, 0xF09D4, 0xF0DEC },
};
constexpr u32 NewCpuVoltageLimit = 1220;
static_assert(NewCpuVoltageLimit <= 1300); //1300mV hangs for me
constexpr u32 CpuVoltageOldTableCoeff[][10] = {
{ 0xE2140, 0xE2178, 0xE21B0, 0xE21E8, 0xE2220, 0xE2258, 0xE2290, 0xE22C8, 0xE2300, 0xE2338 },
{ 0xF0F90, 0xF0FC8, 0xF1000, 0xF1038, 0xF1070, 0xF10A8, 0xF10E0, 0xF1118, 0xF1150, 0xF1188 },
{ 0xF0FE0, 0xF1018, 0xF1050, 0xF1088, 0xF10C0, 0xF10F8, 0xF1130, 0xF1168, 0xF11A0, 0xF11D8 },
};
constexpr u32 NewCpuVoltageCoeff = NewCpuVoltageLimit * 1000;
constexpr u32 CpuTablesFreeSpace[] = {
0xE2350,
0xF11A0,
0xF11F0,
};
constexpr cpu_clock_table_t NewCpuTables[] = {
{ 2091000, 0, {1719782, -40440, 27}, NewCpuVoltageCoeff, {} },
{ 2193000, 0, {1809766, -41939, 27}, NewCpuVoltageCoeff, {} },
{ 2295000, 0, {1904458, -43439, 27}, NewCpuVoltageCoeff, {} },
{ 2397000, 0, {2004105, -44938, 27}, NewCpuVoltageCoeff, {} },
// calculated using linear regression:
// coeffs[0]=604531*exp(0.0000005*hz)
// coeffs[1]=-0.0147*hz-9702.1
};
static_assert(sizeof(NewCpuTables) <= sizeof(cpu_clock_table_t)*14);
constexpr u32 MaxCpuClockOffset[] = {
0xE2740,
0xF1590,
0xF15E0,
};
constexpr u32 NewMaxCpuClock = 2397000;
/* GPU */
constexpr u32 GpuTablesFreeSpace[] = {
0xE3410,
0xF2260,
0xF22B0,
};
constexpr gpu_clock_table_t NewGpuTables[] = {
{ 1305600, 0, {}, {1380113, -13465, -874, 0, 2580, 648} },
{ 1344000, 0, {}, {1420000, -14000, -870, 0, 2193, 824} },
// some arbitrary coeffs I guessed and tested, YMMV
};
static_assert(sizeof(NewGpuTables) <= sizeof(gpu_clock_table_t)*15);
constexpr u32 Reg1MaxGpuOffset[] = {
0x2E0AC,
0x3F6CC,
0x3F12C,
};
constexpr u8 Reg1NewMaxGpuClock[][0xC] = {
// Original: 1267MHz
/*
MOV W13,#0x5600
MOVK W13,#0x13,LSL #16
NOP
*/
// Bump to 1536MHz
/*
MOV W13,#0x7000
MOVK W13,#0x17,LSL #16
NOP
*/
//0x0D, 0xC0, 0x8A, 0x52, 0x6D, 0x02, 0xA0, 0x72, 0x1F, 0x20, 0x03, 0xD5
{ 0x0D, 0x00, 0x8E, 0x52, 0xED, 0x02, 0xA0, 0x72, 0x1F, 0x20, 0x03, 0xD5 },
{ 0x0B, 0x00, 0x8E, 0x52, 0xEB, 0x02, 0xA0, 0x72, 0x1F, 0x20, 0x03, 0xD5 },
{ 0x0B, 0x00, 0x8E, 0x52, 0xEB, 0x02, 0xA0, 0x72, 0x1F, 0x20, 0x03, 0xD5 },
};
constexpr u32 Reg2MaxGpuOffset[] = {
0x2E110,
0x3F730,
0x3F190,
};
constexpr u8 Reg2NewMaxGpuClock[][0x8] = {
// Original: 1267MHz
/*
MOV W13,#0x5600
MOVK W13,#0x13,LSL #16
*/
// Bump to 1536MHz
/*
MOV W13,#0x7000
MOVK W13,#0x17,LSL #16
*/
//0x0D, 0xC0, 0x8A, 0x52, 0x6D, 0x02, 0xA0, 0x72
{ 0x0D, 0x00, 0x8E, 0x52, 0xED, 0x02, 0xA0, 0x72, },
{ 0x0B, 0x00, 0x8E, 0x52, 0xEB, 0x02, 0xA0, 0x72, },
{ 0x0B, 0x00, 0x8E, 0x52, 0xEB, 0x02, 0xA0, 0x72, },
};
constexpr u32 PtmEmcOffsetStart[] = {
0xC5E24,
0xA032C,
};
constexpr u32 PtmOffsetInterval = 0x20;
constexpr u32 PtmCpuBoostOffset = 0x170;

75
Source/Atmosphere/ldr_patcher.cpp
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@@ -1,4 +1,3 @@
// placed in Atmosphere/stratosphere/loader/source/
/*
* Copyright (c) Atmosphère-NX
*
@@ -16,7 +15,6 @@
*/
#include <stratosphere.hpp>
#include "ldr_patcher.hpp"
#include "ldr_pcv_patch.hpp"
namespace ams::ldr {
@@ -68,6 +66,17 @@ namespace ams::ldr {
return g_force_enable_usb30;
}
u32 GetEmcClock() {
// RAM freqs to choose: 1600000, 1728000, 1795200, 1862400, 1894400, 1932800, 1996800, 2064000, 2099200, 2131200
// RAM overclock could be UNSTABLE on some RAM without bumping up voltage,
// and therefore show graphical glitches, hang randomly or even worse, corrupt your NAND
return 1862400;
}
u32 GetCpuBoostClock() {
return 1963500;
}
consteval u8 ParseNybble(char c) {
AMS_ASSUME(('0' <= c && c <= '9') || ('A' <= c && c <= 'F') || ('a' <= c && c <= 'f'));
if ('0' <= c && c <= '9') {
@@ -113,16 +122,10 @@ namespace ams::ldr {
}
#include "ldr_oc_patch.inc"
/* Apply IPS patches. */
void LocateAndApplyIpsPatchesToModule(const u8 *module_id_data, uintptr_t mapped_nso, size_t mapped_size) {
for(int i = 0; i < VERS; i++)
{
if(std::memcmp(PcvModuleId[i], module_id_data, sizeof(PcvModuleId[i])) == 0) {
ApplyPcvPatch(reinterpret_cast<u8 *>(mapped_nso), mapped_size, i);
return; // Return here since pcv module loads before sd card can be mounted
}
}
if (!EnsureSdCardMounted()) {
return;
}
@@ -150,6 +153,58 @@ namespace ams::ldr {
}
}
}
u32 EmcClock = GetEmcClock();
if (spl::GetSocType() == spl::SocType_Mariko && EmcClock) {
for (u32 i = 0; i < sizeof(PcvModuleId)/sizeof(ro::ModuleId); i++) {
if (std::memcmp(std::addressof(PcvModuleId[i]), std::addressof(module_id), sizeof(module_id)) == 0) {
/* Add new CPU and GPU clock tables for Mariko */
std::memcpy(reinterpret_cast<void *>(mapped_nso + CpuTablesFreeSpace[i]), NewCpuTables, sizeof(NewCpuTables));
std::memcpy(reinterpret_cast<void *>(mapped_nso + GpuTablesFreeSpace[i]), NewGpuTables, sizeof(NewGpuTables));
/* Patch Mariko max CPU and GPU clockrates */
std::memcpy(reinterpret_cast<void *>(mapped_nso + MaxCpuClockOffset[i]), &NewMaxCpuClock, sizeof(NewMaxCpuClock));
std::memcpy(reinterpret_cast<void *>(mapped_nso + Reg1MaxGpuOffset[i]), Reg1NewMaxGpuClock, sizeof(Reg1NewMaxGpuClock[i]));
std::memcpy(reinterpret_cast<void *>(mapped_nso + Reg2MaxGpuOffset[i]), Reg2NewMaxGpuClock, sizeof(Reg2NewMaxGpuClock[i]));
/* Patch max cpu voltage on Mariko */
for (u32 j = 0; j < sizeof(CpuVoltageLimitOffsets[i])/sizeof(u32); j++) {
std::memcpy(reinterpret_cast<void *>(mapped_nso + CpuVoltageLimitOffsets[i][j]), &NewCpuVoltageLimit, sizeof(NewCpuVoltageLimit));
}
for (u32 j = 0; j < sizeof(CpuVoltageOldTableCoeff[i])/sizeof(u32); j++) {
std::memcpy(reinterpret_cast<void *>(mapped_nso + CpuVoltageOldTableCoeff[i][j]), &NewCpuVoltageCoeff, sizeof(NewCpuVoltageCoeff));
}
/* Patch RAM Clock */
for (u32 j = 0; j < sizeof(EmcFreqOffsets[i])/sizeof(u32); j++) {
std::memcpy(reinterpret_cast<void *>(mapped_nso + EmcFreqOffsets[i][j]), &EmcClock, sizeof(EmcClock));
}
}
}
EmcClock = GetEmcClock() * 1000;
u32 CpuBoostClock = GetCpuBoostClock() * 1000;
for (u32 i = 0; i < sizeof(PtmModuleId)/sizeof(ro::ModuleId); i++) {
if (std::memcmp(std::addressof(PtmModuleId[i]), std::addressof(module_id), sizeof(module_id)) == 0) {
for (u32 j = 0; j < 16; j++) {
std::memcpy(reinterpret_cast<void *>(mapped_nso + PtmEmcOffsetStart[i] + PtmOffsetInterval * j), &EmcClock, sizeof(EmcClock));
std::memcpy(reinterpret_cast<void *>(mapped_nso + PtmEmcOffsetStart[i] + PtmOffsetInterval * j + 0x4), &EmcClock, sizeof(EmcClock));
}
for (u32 j = 0; j < 2; j++) {
std::memcpy(reinterpret_cast<void *>(mapped_nso + PtmEmcOffsetStart[i] + PtmCpuBoostOffset + PtmOffsetInterval * j), &CpuBoostClock, sizeof(CpuBoostClock));
std::memcpy(reinterpret_cast<void *>(mapped_nso + PtmEmcOffsetStart[i] + PtmCpuBoostOffset + PtmOffsetInterval * j + 0x4), &CpuBoostClock, sizeof(CpuBoostClock));
}
}
}
}
for (u32 i = 0; i < sizeof(AmModuleId)/sizeof(ro::ModuleId); i++) {
if(std::memcmp(std::addressof(AmModuleId[i]), std::addressof(module_id), sizeof(module_id)) == 0) {
std::memcpy(reinterpret_cast<void *>(mapped_nso + AmCopyrightOffset[i]), AmCopyrightPatch, sizeof(AmCopyrightPatch));
}
}
}
}

295
Source/Atmosphere/ldr_pcv_patch.cpp
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@@ -1,295 +0,0 @@
// placed in Atmosphere/stratosphere/loader/source/
#include <stratosphere.hpp>
#define VERS 3
#define EMC_OVERCLOCK 1
//#define EMC_OVERVOLT
//I'm dropping support for Erista on >= HOS 13.0.0, you may port these offsets by yourself.
//#define ERISTA_SUPPORT
namespace ams::ldr {
namespace {
constexpr u32 CopyrightIPSOffset[] = { 0xC6128, 0xCA414, 0xCB90C, 0xCBB8C };
// am_no_copyright port, grab exefs patches instead
constexpr u8 RET0[8] = { 0xE0, 0x03, 0x1F, 0xAA, 0xC0, 0x03, 0x5F, 0xD6 };
// MOV X0, XZR
// RET
typedef struct {
u32 hz = 0;
u32 volt = 0;
u32 unk[6] = {0};
s32 coeffs[6] = {0};
} gpu_clock_table_t;
constexpr u32 EmcFreqOffsets[VERS][30] = {
{ 0xD7C60, 0xD7C68, 0xD7C70, 0xD7C78, 0xD7C80, 0xD7C88, 0xD7C90, 0xD7C98, 0xD7CA0, 0xD7CA8, 0xE1800, 0xEEFA0, 0xF2478, 0xFE284, 0x10A304, 0x10D7DC, 0x110A40, 0x113CA4, 0x116F08, 0x11A16C, 0x11D3D0, 0x120634, 0x123898, 0x126AFC, 0x129D60, 0x12CFC4, 0x130228, 0x13BFE0, 0x140D00, 0x140D50, },
{ 0xE1810, 0xE6530, 0xE6580, 0xE6AB0, 0xE6AB8, 0xE6AC0, 0xE6AC8, 0xE6AD0, 0xE6AD8, 0xE6AE0, 0xE6AE8, 0xE6AF0, 0xE6AF8, 0xF0650, 0xFDDF0, 0x1012C8, 0x10D0D4, 0x119154, 0x11C62C, 0x11F890, 0x122AF4, 0x125D58, 0x128FBC, 0x12C220, 0x12F484, 0x1326E8, 0x13594C, 0x138BB0, 0x13BE14, 0x13F078, },
{ 0xE1860, 0xE6580, 0xE65D0, 0xE6B00, 0xE6B08, 0xE6B10, 0xE6B18, 0xE6B20, 0xE6B28, 0xE6B30, 0xE6B38, 0xE6B40, 0xE6B48, 0xF06A0, 0xFDE40, 0x101318, 0x10D124, 0x1191A4, 0x11C67C, 0x11F8E0, 0x122B44, 0x125DA8, 0x12900C, 0x12C270, 0x12F4D4, 0x132738, 0x13599C, 0x138C00, 0x13BE64, 0x13F0C8, }
};
// RAM freqs to choose: 1600000, 1728000, 1795200, 1862400, 1894400, 1932800, 1996800, 2064000, 2099200, 2131200
constexpr u32 NewEmcFreq = 1862400;
// RAM overclock could be UNSTABLE on some RAM without bumping up voltage,
// and therefore show graphical glitches, hang randomly or even worse, corrupt your NAND
#ifdef ERISTA_SUPPORT
namespace Erista {
typedef struct {
u32 hz = 0;
u32 unk = 0;
u32 volt = 0;
u32 unk2[5] = {0};
s32 coeffs[6] = {0};
} cpu_clock_table_t;
/* CPU */
constexpr u32 CpuVoltageLimitOffsets[VERS][3] = {
{ 0xE1AC8, 0xE1AD4, 0xE37E4 },
{ 0xF0918, 0xF0924, 0xF2634 },
{ 0xF0968, 0xF0974, 0xF2684 },
};
constexpr u32 NewCpuVoltageLimit = 1358;
static_assert(NewCpuVoltageLimit <= 1400);
constexpr u32 CpuTablesFreeSpace[VERS] = { 0xE3B78, 0xF29C8, 0xF2A18 };
constexpr cpu_clock_table_t NewCpuTables[] = {
{ 1887000, 0, 1240000, {}, { 5100873, -279186, 4747 } },
{ 1963500, 0, 1262000, {}, { 5100873, -279186, 4747 } },
{ 2091000, 0, 1298000, {}, { 5100873, -279186, 4747 } },
{ 2193000, 0, 1328000, {}, { 5100873, -279186, 4747 } },
{ 2295000, 0, 1358000, {}, { 5100873, -279186, 4747 } },
};
static_assert(sizeof(NewCpuTables) <= sizeof(cpu_clock_table_t)*16);
/* GPU */
constexpr u32 GpuTablesFreeSpace[VERS] = { 0xE2B58, 0xF19A8, 0xF19F8 };
constexpr gpu_clock_table_t NewGpuTables[] = {
{ 998400, 0, {}, { 1316991, 8144, -940, 808, -21583, 226 } },
{ 1075200, 0, {}, { 1358883, 8144, -940, 808, -21583, 226 } },
};
static_assert(sizeof(NewGpuTables) <= sizeof(gpu_clock_table_t)*20);
/* EMC */
constexpr u32 EmcVoltageOffsets[VERS][2] = {
{ 0x143998, 0x14399C },
{ 0x142878, 0x14287C },
{ 0x1428B8, 0x1428BC },
};
constexpr u32 NewEmcVoltage = 1150000;
static_assert(NewEmcVoltage <= 1250000);
// 1150mV for 1862.4 MHz and 1200 mV for 2131.2 MHz, according to the feedback in RetroNX Discord
// 1125mV(HOS default) for 1731.2 MHz and 1175mV for 1996.8 MHz
};
#endif
namespace Mariko {
typedef struct {
u32 hz = 0;
u32 unk1 = 0;
s32 coeffs[6] = {0};
u32 volt = 0;
u32 unk3[5] = {0};
} cpu_clock_table_t;
/* CPU */
constexpr u32 CpuVoltageLimitOffsets[VERS][11] = {
{ 0xE1A8C, 0xE1A98, 0xE1AA4, 0xE1AB0, 0xE1AF8, 0xE1B04, 0xE1B10, 0xE1B1C, 0xE1B28, 0xE1B34, 0xE1F4C },
{ 0xF08DC, 0xF08E8, 0xF08F4, 0xF0900, 0xF0948, 0xF0954, 0xF0960, 0xF096C, 0xF0978, 0xF0984, 0xF0D9C },
{ 0xF092C, 0xF0938, 0xF0944, 0xF0950, 0xF0998, 0xF09A4, 0xF09B0, 0xF09BC, 0xF09C8, 0xF09D4, 0xF0DEC }
};
constexpr u32 NewCpuVoltageLimit = 1220;
static_assert(NewCpuVoltageLimit <= 1300); //1300mV hangs for me
constexpr u32 CpuVoltageCoeffTable[VERS][10] = {
{ 0xE2140, 0xE2178, 0xE21B0, 0xE21E8, 0xE2220, 0xE2258, 0xE2290, 0xE22C8, 0xE2300, 0xE2338 },
{ 0xF0F90, 0xF0FC8, 0xF1000, 0xF1038, 0xF1070, 0xF10A8, 0xF10E0, 0xF1118, 0xF1150, 0xF1188 },
{ 0xF0FE0, 0xF1018, 0xF1050, 0xF1088, 0xF10C0, 0xF10F8, 0xF1130, 0xF1168, 0xF11A0, 0xF11D8 }
};
constexpr u32 NewCpuVoltageCoeff = NewCpuVoltageLimit * 1000;
constexpr u32 CpuTablesFreeSpace[VERS] = { 0xE2350, 0xF11A0, 0xF11F0 };
constexpr cpu_clock_table_t NewCpuTables[] = {
{2091000, 0, {1719782, -40440, 27}, NewCpuVoltageCoeff, {}},
{2193000, 0, {1809766, -41939, 27}, NewCpuVoltageCoeff, {}},
{2295000, 0, {1904458, -43439, 27}, NewCpuVoltageCoeff, {}},
{2397000, 0, {2004105, -44938, 27}, NewCpuVoltageCoeff, {}},
/*{2499000, 0, {2108966, -46437, 27}, NewCpuVoltageCoeff, {}},
{2601000, 0, {2219313, -47937, 27}, NewCpuVoltageCoeff, {}},
{2703000, 0, {2335434, -49436, 27}, NewCpuVoltageCoeff, {}},
{2805000, 0, {2457630, -50936, 27}, NewCpuVoltageCoeff, {}},
{2907000, 0, {2586221, -52435, 27}, NewCpuVoltageCoeff, {}},
{3009000, 0, {2721539, -53934, 27}, NewCpuVoltageCoeff, {}},*/
// calculated using linear regression:
// coeffs[0]=604531*exp(0.0000005*hz)
// coeffs[1]=-0.0147*hz-9702.1
};
static_assert(sizeof(NewCpuTables) <= sizeof(cpu_clock_table_t)*14);
constexpr u32 MaxCpuClockOffset[VERS] = { 0xE2740, 0xF1590, 0xF15E0 };
constexpr u32 NewMaxCpuClock = 2397000;
/* GPU */
constexpr u32 GpuTablesFreeSpace[VERS] = { 0xE3410, 0xF2260, 0xF22B0 };
constexpr gpu_clock_table_t NewGpuTables[] = {
{ 1305600, 0, {}, {1380113, -13465, -874, 0, 2580, 648} },
{ 1344000, 0, {}, {1420000, -14000, -870, 0, 2193, 824} },
/*{ 1382400, 0, {}, {1423200, -14188, -868, 0, 2150, 830} },
{ 1420800, 0, {}, {1426290, -14368, -860, 0, 2100, 850} },
{ 1305600, 0, {}, {1380113, -13465, -874, 0, 2580, 648} },
{ 1344000, 0, {}, {1420000, -14100, -870, 0, 2193, 824} },
{ 1382400, 0, {}, {1426290, -14368, -860, 0, 2100, 850} },
{ 1420800, 0, {}, {1450000, -14600, -860, 0, 2000, 850} },
{ 1382400, 0, {}, {1454061, -14500, -868, 0, 2000, 900} },
{ 1382400, 0, {}, {1474061, -15277, -866, 0, 1710, 1024} },
{ 1382400, 0, {}, {1500000, -15500, -880, 0, 1000, 548} },
{ 1420800, 0, {}, {1550000, -16500, -885, 0, 1500, 300} },*/
// some arbitrary coeffs I guessed and tested, YMMV
};
static_assert(sizeof(NewGpuTables) <= sizeof(gpu_clock_table_t)*15);
constexpr u32 Reg1MaxGpuOffset[VERS] = { 0x2E0AC, 0x3F6CC, 0x3F12C };
constexpr u8 Reg1NewMaxGpuClock[VERS][0xC] = {
// Original: 1267MHz
/*
MOV W13,#0x5600
MOVK W13,#0x13,LSL #16
NOP
*/
// Bump to 1536MHz
/*
MOV W13,#0x7000
MOVK W13,#0x17,LSL #16
NOP
*/
//0x0D, 0xC0, 0x8A, 0x52, 0x6D, 0x02, 0xA0, 0x72, 0x1F, 0x20, 0x03, 0xD5
{ 0x0D, 0x00, 0x8E, 0x52, 0xED, 0x02, 0xA0, 0x72, 0x1F, 0x20, 0x03, 0xD5 },
{ 0x0B, 0x00, 0x8E, 0x52, 0xEB, 0x02, 0xA0, 0x72, 0x1F, 0x20, 0x03, 0xD5 },
{ 0x0B, 0x00, 0x8E, 0x52, 0xEB, 0x02, 0xA0, 0x72, 0x1F, 0x20, 0x03, 0xD5 },
};
constexpr u32 Reg2MaxGpuOffset[VERS] = { 0x2E110, 0x3F730, 0x3F190 };
constexpr u8 Reg2NewMaxGpuClock[VERS][0x8] = {
// Original: 1267MHz
/*
MOV W13,#0x5600
MOVK W13,#0x13,LSL #16
*/
// Bump to 1536MHz
/*
MOV W13,#0x7000
MOVK W13,#0x17,LSL #16
*/
//0x0D, 0xC0, 0x8A, 0x52, 0x6D, 0x02, 0xA0, 0x72
{ 0x0D, 0x00, 0x8E, 0x52, 0xED, 0x02, 0xA0, 0x72, },
{ 0x0B, 0x00, 0x8E, 0x52, 0xEB, 0x02, 0xA0, 0x72, },
{ 0x0B, 0x00, 0x8E, 0x52, 0xEB, 0x02, 0xA0, 0x72, },
};
#ifdef EMC_OVERVOLT
/*
* EMC: Work in progress
*
* References:
* [1] https://nv-tegra.nvidia.com/gitweb/?p=linux-4.9.git;a=blob;f=drivers/regulator/max77812-regulator.c;h=015f90b297b5f58bac6ac3c92c72be878542c667
* [2] https://github.com/CTCaer/hekate/blob/master/bdk/power/max77812.h
* [3] https://github.com/CTCaer/hekate/blob/master/bdk/power/max7762x.c
*/
constexpr u32 EmcVoltageMax = 1525000;
constexpr u32 EmcVoltageMinOffsets[VERS][2] = {
{ 0x145FD8, 0x144B98, },
{ 0x143A78, 0x144EB8, },
{ 0x143AB8, 0x144EF8, },
};
constexpr u32 EmcVoltageDefOffsets[VERS][2] = {
{ 0x145FE4, 0x144BA4, },
{ 0x143A84, 0x144EC4, },
{ 0x143AC4, 0x144F04, },
};
/* constexpr u32 EmcVoltageMin = 250000; */
constexpr u32 EmcVoltageDef = 650000; // 600000mV
static_assert(sizeof(EmcVoltageMinOffsets) == sizeof(EmcVoltageDefOffsets));
static_assert(NewEmcVoltageDef <= EmcVoltageMax);
#endif
};
}
void ApplyPcvPatch(u8 *mapped_module, size_t mapped_size, int i) {
#ifdef ERISTA_SUPPORT
/* Add new CPU and GPU clock tables for Erista */
AMS_ABORT_UNLESS(Erista::CpuTablesFreeSpace[i] <= mapped_size && Erista::GpuTablesFreeSpace[i] <= mapped_size);
std::memcpy(mapped_module + Erista::CpuTablesFreeSpace[i], Erista::NewCpuTables, sizeof(Erista::NewCpuTables));
std::memcpy(mapped_module + Erista::GpuTablesFreeSpace[i], Erista::NewGpuTables, sizeof(Erista::NewGpuTables));
/* Patch max CPU voltage on Erista */
for(int j = 0; j < 3; j++) {
std::memcpy(mapped_module + Erista::CpuVoltageLimitOffsets[i][j], &Erista::NewCpuVoltageLimit, sizeof(Erista::NewCpuVoltageLimit));
}
#endif
/* Add new CPU and GPU clock tables for Mariko */
AMS_ABORT_UNLESS(Mariko::CpuTablesFreeSpace[i] <= mapped_size && Mariko::GpuTablesFreeSpace[i] <= mapped_size);
std::memcpy(mapped_module + Mariko::CpuTablesFreeSpace[i], Mariko::NewCpuTables, sizeof(Mariko::NewCpuTables));
std::memcpy(mapped_module + Mariko::GpuTablesFreeSpace[i], Mariko::NewGpuTables, sizeof(Mariko::NewGpuTables));
/* Patch Mariko max CPU and GPU clockrates */
AMS_ABORT_UNLESS(Mariko::MaxCpuClockOffset[i] <= mapped_size && Mariko::Reg1MaxGpuOffset[i] <= mapped_size && Mariko::Reg2MaxGpuOffset[i] <= mapped_size);
std::memcpy(mapped_module + Mariko::MaxCpuClockOffset[i], &Mariko::NewMaxCpuClock, sizeof(Mariko::NewMaxCpuClock));
std::memcpy(mapped_module + Mariko::Reg1MaxGpuOffset[i], Mariko::Reg1NewMaxGpuClock, sizeof(Mariko::Reg1NewMaxGpuClock[i]));
std::memcpy(mapped_module + Mariko::Reg2MaxGpuOffset[i], Mariko::Reg2NewMaxGpuClock, sizeof(Mariko::Reg2NewMaxGpuClock[i]));
/* Patch max cpu voltage on Mariko */
for(int j = 0; j < 11; j++) {
std::memcpy(mapped_module + Mariko::CpuVoltageLimitOffsets[i][j], &Mariko::NewCpuVoltageLimit, sizeof(Mariko::NewCpuVoltageLimit));
}
for(int j = 0; j < 10; j++) {
std::memcpy(mapped_module + Mariko::CpuVoltageCoeffTable[i][j], &Mariko::NewCpuVoltageCoeff, sizeof(Mariko::NewCpuVoltageCoeff));
}
/* Patch EMC clocks and voltage if enabled.
Note: On Erista, this requires removing or modifiying minerva */
if constexpr(EMC_OVERCLOCK) {
for(u32 j = 0; j < sizeof(EmcFreqOffsets[i])/sizeof(u32); j++) {
AMS_ABORT_UNLESS(EmcFreqOffsets[i][j] <= mapped_size);
std::memcpy(mapped_module + EmcFreqOffsets[i][j], &NewEmcFreq, sizeof(NewEmcFreq));
}
}
#ifdef EMC_OVERVOLT
#ifdef ERISTA_SUPPORT
if(spl::GetSocType() == spl::SocType_Erista) {
for(u32 j = 0; j < sizeof(Erista::EmcVoltageOffsets[i])/sizeof(u32); j++) {
AMS_ABORT_UNLESS(Erista::EmcVoltageOffsets[i][j] <= mapped_size);
std::memcpy(mapped_module + Erista::EmcVoltageOffsets[i][j], &Erista::NewEmcVoltage, sizeof(Erista::NewEmcVoltage));
}
#endif
else if(spl::GetSocType() == spl::SocType_Mariko) {
for(u32 j = 0; j < sizeof(Mariko::EmcVoltageMinOffsets[i])/sizeof(u32); j++) {
AMS_ABORT_UNLESS(Mariko::EmcVoltageMinOffsets[i][j] <= mapped_size);
//std::memcpy(mapped_module + Mariko::EmcVoltageMinOffsets[i][j], &Mariko::EmcVoltageMin, sizeof(Mariko::EmcVoltageMin));
std::memcpy(mapped_module + Mariko::EmcVoltageDefOffsets[i][j], &Mariko::EmcVoltageDef, sizeof(Mariko::EmcVoltageDef));
}
}
#endif
return;
}
void ApplyCopyrightPatch(u8 *mapped_module, size_t mapped_size, int i) {
AMS_ABORT_UNLESS(CopyrightIPSOffset[i] - 0x100 <= mapped_size);
std::memcpy(mapped_module + CopyrightIPSOffset[i] - 0x100, RET0, sizeof(RET0));
}
}

26
Source/Atmosphere/ldr_pcv_patch.hpp
View File

@@ -1,26 +0,0 @@
// placed in Atmosphere/stratosphere/loader/source/
#pragma once
#include <stratosphere.hpp>
#define VERS 3
namespace ams::ldr {
constexpr u8 PcvModuleId[VERS][20] = {
{ 0x91, 0xD6, 0x1D, 0x59, 0xD7, 0x00, 0x23, 0x78, 0xE3, 0x55, 0x84, 0xFC, 0x0B, 0x38, 0xC7, 0x69, 0x3A, 0x3A, 0xBA, 0xB5, }, //11.0.0
{ 0xC5, 0x03, 0xE9, 0x65, 0x50, 0xF3, 0x02, 0xE1, 0x21, 0x87, 0x31, 0x36, 0xB8, 0x14, 0xA5, 0x29, 0x86, 0x3D, 0x94, 0x9B, }, //12.0.0-12.1.0
{ 0x20, 0x58, 0xC9, 0x7C, 0x55, 0x15, 0x71, 0x50, 0x66, 0x56, 0xAA, 0x04, 0xEC, 0x85, 0xE2, 0xB1, 0xB0, 0x1B, 0x15, 0x5C, }, //13.0.0
};
constexpr u8 AmModuleId[VERS][20] = {
{ 0x25, 0x50, 0x97, 0xEF, 0x11, 0xC0, 0x75, 0x9B, 0x1F, 0x36, 0x13, 0x2F, 0x73, 0xBD, 0xDB, 0x04, 0xC3, 0xEF, 0x9A, 0xBE, }, //11.0.0
{ 0x5E, 0x5F, 0x1C, 0xC2, 0x4D, 0x37, 0x45, 0x91, 0xAF, 0xC2, 0xA2, 0x33, 0x6C, 0x94, 0x53, 0xCC, 0xFA, 0x39, 0x61, 0xC1, }, //12.0.0-12.1.0
{ 0x2C, 0x1A, 0xD2, 0x24, 0x32, 0x8D, 0x2A, 0xF8, 0xB2, 0xC1, 0xA2, 0x40, 0xD0, 0x17, 0x5A, 0x10, 0x89, 0x16, 0xAC, 0x8C, }, //13.0.0
};
void ApplyPcvPatch(u8 *mapped_module, size_t mapped_size, int i);
void ApplyCopyrightPatch(u8 *mapped_module, size_t mapped_size, int i);
}