From e1c66815f9b8e26ab7ed6295dbeed12026ed98f9 Mon Sep 17 00:00:00 2001 From: souldbminersmwc Date: Sun, 8 Mar 2026 18:13:15 -0400 Subject: [PATCH] add bpmp basics --- Source/sys-clk/bpmp/Makefile | 54 +++++++++ Source/sys-clk/bpmp/firmware.bin | Bin 0 -> 736 bytes Source/sys-clk/bpmp/firmware.elf | Bin 0 -> 6320 bytes Source/sys-clk/bpmp/linker.ld | 69 ++++++++++++ Source/sys-clk/bpmp/src/main.c | 184 +++++++++++++++++++++++++++++++ 5 files changed, 307 insertions(+) create mode 100644 Source/sys-clk/bpmp/Makefile create mode 100644 Source/sys-clk/bpmp/firmware.bin create mode 100644 Source/sys-clk/bpmp/firmware.elf create mode 100644 Source/sys-clk/bpmp/linker.ld create mode 100644 Source/sys-clk/bpmp/src/main.c diff --git a/Source/sys-clk/bpmp/Makefile b/Source/sys-clk/bpmp/Makefile new file mode 100644 index 00000000..22121ad9 --- /dev/null +++ b/Source/sys-clk/bpmp/Makefile @@ -0,0 +1,54 @@ +# Configuration +PROJECT_NAME = firmware +CPU = arm7tdmi +ARCH = armv4t +OPTIMIZATION = -Ofast + +# Toolchain +CC = arm-none-eabi-gcc +OBJCOPY = arm-none-eabi-objcopy +SIZE = arm-none-eabi-size + +# Directories +SRC_DIR = src +BUILD_DIR = build + +# Source files +SOURCES = $(wildcard $(SRC_DIR)/*.c) +OBJECTS = $(patsubst $(SRC_DIR)/%.c, $(BUILD_DIR)/%.o, $(SOURCES)) + +# Output files +ELF = $(PROJECT_NAME).elf +BIN = $(PROJECT_NAME).bin + +# Compiler flags +CFLAGS = -mcpu=$(CPU) -march=$(ARCH) \ + $(OPTIMIZATION) -Wall -ffunction-sections -fdata-sections \ + -I$(SRC_DIR) + +# Linker flags +LDFLAGS = -mcpu=$(CPU) -march=$(ARCH) \ + -T linker.ld -Wl,--gc-sections + +# Targets +.PHONY: all clean + +all: $(BIN) + @echo "✓ Built: $(BIN)" + @$(SIZE) $(ELF) + +$(BIN): $(ELF) + @$(OBJCOPY) -O binary $(ELF) $(BIN) + +$(ELF): $(OBJECTS) + @echo "Linking..." + @$(CC) $(LDFLAGS) $(OBJECTS) -o $(ELF) + +$(BUILD_DIR)/%.o: $(SRC_DIR)/%.c + @mkdir -p $(BUILD_DIR) + @echo "Compiling: $<" + @$(CC) $(CFLAGS) -c $< -o $@ + +clean: + @rm -rf $(BUILD_DIR) $(ELF) $(BIN) + @echo "✓ Cleaned" \ No newline at end of file diff --git a/Source/sys-clk/bpmp/firmware.bin b/Source/sys-clk/bpmp/firmware.bin new file mode 100644 index 0000000000000000000000000000000000000000..1e4ecd8bffce83875cf391836d645d02854c0a67 GIT binary patch literal 736 zcmZ8eO=}ZT6uoa|`eAv^yhe19#qj7x5JR6E7p2f?vJvcJY_=lv6Y>+1RB;n#<;qQF z*@cV#0bwYDE~Mx$@O@;^R44^Siyw?ag8)ap__?>AI#qH4ozsY$s-lagdli?}^oAZjV})c;<9dj3X=N%?^2 z%XjQ0k-KZie<0T$rB^Y3GmkzAr?CGX(F)O?W2$2}>RjihlFTxq6Q+9hHqj=N$5Wpo z_p_>6KJ{Eg^r9-5<*&y&M9trh^)2*-?AkCsax%$mkUZ7vo!khSSy6Z;2bO^V5OQP} zXwRHuACpfkr|ZsJ&vdAKE5ISpUF+*(7wF73^hgKAXzI~p^Si!}8N$s-h1>Ps+AGW(%-gT?UXh!#o%T%hJ2vdUaiags3O%$-YM{j+D#c(t-?=*`H;d^${OH2p z=hGm0SuSE%&5aeA^(Efk-Pe3=sQ-OaaD<*F^faMI`1QUkn$C7E{91*E^N;OWaJXwP G=YIh)b2;n) literal 0 HcmV?d00001 diff --git a/Source/sys-clk/bpmp/firmware.elf b/Source/sys-clk/bpmp/firmware.elf new file mode 100644 index 0000000000000000000000000000000000000000..599bd0f20ec82e4a77c405ee9d2b17a1a0b3494a GIT binary patch literal 6320 zcmeHMU1%It6h3!nvQ5)zaXg@K^6BQ3Z-`W} zg1(3*kL`i{t@X&9b7gk&I_?A}EZD3K zn+~kzm~yT64AIZOBQD8ycPsjTppUx*zEjxL)EuQXl3fe&pCDXF&}>&&Q~p8jyKS#; z3LkeEH-t6kKSuPVFt4s_l*Y615_;S@912(R#x{typ&1ruu`$gBx zw|qVSmb-VV?Mbuc%TA(apbewxXwqEqhiKNjjd;R5?;EtEo7mfO$1Kgq^~Z?rPWzgB zwX3@=f7D%Z_0GzAf?oFSaDMm@a`vT2X;w?(+GIpXt}h(7vY-9LJSMP?-r?(%{p+r*zwJwR+23L+g-Z}1T#c#R?ytbDto&z7#;P=A1p8vR) zL@cgNbXvYz9uE(SGh> z9OjZ;DpyH7gznIx=O~#N7F$J1-zj#9J=z0e0*B>3Qe?Xp-guF@@os2@U4vY~8D*{E zhvnJ;>L3@4@^I^Qaon zNANaSFGMiMyLb=gcOGU)0{47@6hkFwH0%UVRo~@^|DJyt|3uu4$J?Mp%~$*}LtKyI zk4UEjz=}T!{`fAE>tnwZ>dS5#Ptpu9Y=iL^fjR$9>@E8jfFVT_k8!a58uZbK{~N&3 zeCL5xeJRrDolWCOdKZ}aReMg><4`83DH9~l1UWKXUM4sDY^LNmjcWO{V>dzOe-!@Az!Aa@ z1XAStZ8Pi#&+ttr+6Tmb{AQcjClh`bHzvV^9S#NGM*}}TUsqB@_}m_d^26Q_{P-MQ zyN@5f{{lY^n$M35zo>9cEQitf>?uFCMMe4LV1!Ryjd8q36o6KKtRu^#;T?ECVZe7d lJ&4BZ00jZ&oJub5BEl~d15xqDVTt;Ei2pmB7y`wuNg`bGc% literal 0 HcmV?d00001 diff --git a/Source/sys-clk/bpmp/linker.ld b/Source/sys-clk/bpmp/linker.ld new file mode 100644 index 00000000..ab7381e7 --- /dev/null +++ b/Source/sys-clk/bpmp/linker.ld @@ -0,0 +1,69 @@ +/* + * Copyright (c) Souldbminer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +MEMORY +{ + SRAM (rwx) : ORIGIN = 0x60000000, LENGTH = 32K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + + .vectors : + { + KEEP(*(.vectors)) + . = ALIGN(4); + } > SRAM + + .text : + { + *(.text*) + *(.rodata*) + . = ALIGN(4); + } > SRAM + + .data : + { + _sdata = .; + *(.data*) + _edata = .; + . = ALIGN(4); + } > SRAM + + _sidata = _edata; + + .bss : + { + _sbss = .; + *(.bss*) + *(COMMON) + _ebss = .; + . = ALIGN(4); + } > SRAM + + /* Stack at end of SRAM */ + _estack = ORIGIN(SRAM) + LENGTH(SRAM); + + /* Discard debug sections */ + /DISCARD/ : + { + *(.debug_*) + *(.comment) + } +} \ No newline at end of file diff --git a/Source/sys-clk/bpmp/src/main.c b/Source/sys-clk/bpmp/src/main.c new file mode 100644 index 00000000..7bab04bb --- /dev/null +++ b/Source/sys-clk/bpmp/src/main.c @@ -0,0 +1,184 @@ +/* + * Copyright (c) Souldbminer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + +/* + * Exception Vector Table (ARM7TDMI): + * 0x00: Reset + * 0x04: Undefined Instruction + * 0x08: Software Interrupt (SWI) + * 0x0C: Prefetch Abort + * 0x10: Data Abort + * 0x14: Reserved + * 0x18: IRQ + * 0x1C: FIQ + */ + +#include +#include + +extern uint32_t _sdata; /* Start of .data section */ +extern uint32_t _edata; /* End of .data section */ +extern uint32_t _sidata; /* Start of .data in SRAM */ +extern uint32_t _sbss; /* Start of .bss section */ +extern uint32_t _ebss; /* End of .bss section */ +extern uint32_t _estack; /* End of stack */ + +extern int main(void); + +/* Forward declarations */ +void Reset_Handler(void); +void Undefined_Handler(void); +void SWI_Handler(void); +void PrefetchAbort_Handler(void); +void DataAbort_Handler(void); +void IRQ_Handler(void); +void FIQ_Handler(void); + + +void Reset_Handler(void) { + uint32_t data_size = (uint32_t)(&_edata) - (uint32_t)(&_sdata); + if (data_size > 0) { + memcpy(&_sdata, &_sidata, data_size); + } + + uint32_t bss_size = (uint32_t)(&_ebss) - (uint32_t)(&_sbss); + if (bss_size > 0) { + memset(&_sbss, 0, bss_size); + } + + main(); + + while (1) { + __asm__ volatile("wfi"); + } +} + + +void DataAbort_Handler(void) { + uint32_t fault_addr; + uint32_t fault_status; + + __asm__ volatile("mrc p15, 0, %0, c6, c0, 0" : "=r"(fault_addr)); /* DFAR */ + __asm__ volatile("mrc p15, 0, %0, c5, c0, 0" : "=r"(fault_status)); /* DFSR */ + + (void)fault_addr; + (void)fault_status; + + while (1) { + __asm__ volatile("nop"); + } +} + +void PrefetchAbort_Handler(void) { + uint32_t fault_addr; + uint32_t fault_status; + + __asm__ volatile("mrc p15, 0, %0, c6, c0, 2" : "=r"(fault_addr)); /* IFAR */ + __asm__ volatile("mrc p15, 0, %0, c5, c0, 1" : "=r"(fault_status)); /* IFSR */ + + (void)fault_addr; + (void)fault_status; + + while (1) { + __asm__ volatile("nop"); + } +} + +void Undefined_Handler(void) { + while (1) { + __asm__ volatile("nop"); + } +} + +void SWI_Handler(void) { + uint32_t *lr; + uint32_t swi_instr; + uint32_t swi_number; + + __asm__ volatile("mov %0, lr" : "=r"(lr)); + swi_instr = *(lr - 1); + swi_number = swi_instr & 0xFFFFFF; /* Lower 24 bits = SWI number */ + + (void)swi_number; /* Use SWI number for dispatch */ +} + +void IRQ_Handler(void) { + while (1) { + __asm__ volatile("nop"); + } +} + +void FIQ_Handler(void) { + while (1) { + __asm__ volatile("nop"); + } +} + +void Default_Handler(void) { + while (1) { + __asm__ volatile("swi 0"); + } +} + +__attribute__((section(".vectors"))) +void (*const exception_vectors[])(void) = { + Reset_Handler, /* 0x00 - Reset */ + Undefined_Handler, /* 0x04 - Undefined Instruction */ + SWI_Handler, /* 0x08 - Software Interrupt */ + PrefetchAbort_Handler, /* 0x0C - Prefetch Abort */ + DataAbort_Handler, /* 0x10 - Data Abort */ + (void (*)(void))0, /* 0x14 - Reserved */ + IRQ_Handler, /* 0x18 - IRQ */ + FIQ_Handler /* 0x1C - FIQ */ +}; + +static inline uint32_t get_cpsr(void) { + uint32_t cpsr; + __asm__ volatile("mrs %0, cpsr" : "=r"(cpsr)); + return cpsr; +} + +static inline void set_cpsr(uint32_t cpsr) { + __asm__ volatile("msr cpsr, %0" : : "r"(cpsr)); +} + +static inline void disable_irq(void) { + uint32_t cpsr = get_cpsr(); + set_cpsr(cpsr | 0x80); /* Set I bit (disable IRQ) */ +} + +static inline void enable_irq(void) { + uint32_t cpsr = get_cpsr(); + set_cpsr(cpsr & ~0x80); /* Clear I bit (enable IRQ) */ +} + +static inline void disable_fiq(void) { + uint32_t cpsr = get_cpsr(); + set_cpsr(cpsr | 0x40); /* Set F bit (disable FIQ) */ +} + +static inline void enable_fiq(void) { + uint32_t cpsr = get_cpsr(); + set_cpsr(cpsr & ~0x40); /* Clear F bit (enable FIQ) */ +} + +int main(void) { + while (1) { + __asm__("nop"); + } + return 0; +} \ No newline at end of file