add entire atmosphere source code and also add ram timing fixes
This commit is contained in:
souldbminersmwc
@@ -0,0 +1,357 @@
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/*
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* Copyright (c) Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <exosphere.hpp>
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namespace ams::clkrst {
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namespace {
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constinit uintptr_t g_register_address = secmon::MemoryRegionPhysicalDeviceClkRst.GetAddress();
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constinit BpmpClockRate g_bpmp_clock_rate = BpmpClockRate_408MHz;
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struct ClockParameters {
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uintptr_t reset_offset;
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uintptr_t clk_enb_offset;
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uintptr_t clk_src_offset;
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u8 index;
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u8 clk_src;
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u8 clk_div;
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};
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void EnableClock(const ClockParameters ¶m) {
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/* Hold reset. */
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reg::ReadWrite(g_register_address + param.reset_offset, REG_BITS_VALUE(param.index, 1, 1));
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/* Disable clock. */
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reg::ReadWrite(g_register_address + param.clk_enb_offset, REG_BITS_VALUE(param.index, 1, 0));
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/* Set the clock source. */
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if (param.clk_src_offset != 0) {
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reg::Write(g_register_address + param.clk_src_offset, (param.clk_src << 29) | (param.clk_div << 0));
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}
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/* Enable clk. */
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reg::ReadWrite(g_register_address + param.clk_enb_offset, REG_BITS_VALUE(param.index, 1, 1));
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/* Release reset. */
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reg::ReadWrite(g_register_address + param.reset_offset, REG_BITS_VALUE(param.index, 1, 0));
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}
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void DisableClock(const ClockParameters ¶m) {
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/* Hold reset. */
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reg::ReadWrite(g_register_address + param.reset_offset, REG_BITS_VALUE(param.index, 1, 1));
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/* Disable clock. */
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reg::ReadWrite(g_register_address + param.clk_enb_offset, REG_BITS_VALUE(param.index, 1, 0));
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}
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#define DEFINE_CLOCK_PARAMETERS(_VARNAME_, _REG_, _NAME_, _CLK_, _DIV_) \
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constexpr inline const ClockParameters _VARNAME_ = { \
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.reset_offset = CLK_RST_CONTROLLER_RST_DEVICES_##_REG_, \
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.clk_enb_offset = CLK_RST_CONTROLLER_CLK_OUT_ENB_##_REG_, \
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.clk_src_offset = CLK_RST_CONTROLLER_CLK_SOURCE_##_NAME_, \
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.index = CLK_RST_CONTROLLER_CLK_ENB_##_NAME_##_INDEX, \
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.clk_src = CLK_RST_CONTROLLER_CLK_SOURCE_##_NAME_##_##_NAME_##_CLK_SRC_##_CLK_, \
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.clk_div = _DIV_, \
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}
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#define DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(_VARNAME_, _REG_, _NAME_) \
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constexpr inline const ClockParameters _VARNAME_ = { \
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.reset_offset = CLK_RST_CONTROLLER_RST_DEVICES_##_REG_, \
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.clk_enb_offset = CLK_RST_CONTROLLER_CLK_OUT_ENB_##_REG_, \
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.clk_src_offset = 0, \
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.index = CLK_RST_CONTROLLER_CLK_ENB_##_NAME_##_INDEX, \
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.clk_src = 0, \
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.clk_div = 0, \
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}
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DEFINE_CLOCK_PARAMETERS(UartAClock, L, UARTA, PLLP_OUT0, 0);
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DEFINE_CLOCK_PARAMETERS(UartBClock, L, UARTB, PLLP_OUT0, 0);
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DEFINE_CLOCK_PARAMETERS(UartCClock, H, UARTC, PLLP_OUT0, 0);
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DEFINE_CLOCK_PARAMETERS(I2c1Clock, L, I2C1, CLK_M, 0);
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DEFINE_CLOCK_PARAMETERS(I2c5Clock, H, I2C5, CLK_M, 0);
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DEFINE_CLOCK_PARAMETERS(SeClock, V, SE, PLLP_OUT0, 0);
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DEFINE_CLOCK_PARAMETERS(ActmonClock, V, ACTMON, CLK_M, 0);
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DEFINE_CLOCK_PARAMETERS(CsiteClock, U, CSITE, PLLP_OUT0, 4);
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DEFINE_CLOCK_PARAMETERS(Host1xClock, L, HOST1X, PLLP_OUT0, 3);
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DEFINE_CLOCK_PARAMETERS(TsecClock, U, TSEC, PLLP_OUT0, 2);
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DEFINE_CLOCK_PARAMETERS(Sor1Clock, X, SOR1, PLLP_OUT0, 2);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(CldvfsClock, W, DVFS);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(TzramClock, V, TZRAM);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(SorSafeClock, Y, SOR_SAFE);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(Sor0Clock, X, SOR0);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(KfuseClock, H, KFUSE);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(Cache2Clock, L, CACHE2);
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DEFINE_CLOCK_PARAMETERS_WITHOUT_CLKDIV(Cram2Clock, U, CRAM2);
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constexpr const u32 PllcDivn[] = {
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[BpmpClockRate_408MHz] = 0,
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[BpmpClockRate_544MHz] = 85,
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[BpmpClockRate_576MHz] = 90,
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[BpmpClockRate_589MHz] = 92,
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};
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void EnablePllc(BpmpClockRate rate) {
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const u32 desired_divn = PllcDivn[rate];
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/* Check if we're already enabled. */
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const bool is_enabled = reg::HasValue(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, ENABLE));
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const bool is_good_divn = reg::HasValue(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_VALUE(PLLC_BASE_PLLC_DIVN, desired_divn));
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if (is_enabled && is_good_divn) {
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return;
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}
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/* Take PLLC out of reset. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC, (reg::Read(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC) & 0xBFF0000F) | (0x80000 << 4));
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reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC2, 0xF0 << 8);
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/* Disable pll. */
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, DISABLE));
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reg::ClearBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC1, (1u << 27));
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util::WaitMicroSeconds(10);
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/* Set dividers. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_VALUE(PLLC_BASE_PLLC_DIVM, 4),
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CLK_RST_REG_BITS_VALUE(PLLC_BASE_PLLC_DIVN, desired_divn));
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/* Enable pll. */
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, ENABLE));
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while (!reg::HasValue(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_LOCK, LOCK))) {
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/* ... */
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}
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/* Disable PLLC_OUT1. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_PLLC_OUT, CLK_RST_REG_BITS_VALUE(PLLC_OUT_PLLC_OUT1_RATIO, 1));
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/* Enable PLLC_OUT1. */
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_OUT, CLK_RST_REG_BITS_ENUM(PLLC_OUT_PLLC_OUT1_RSTN, RESET_DISABLE),
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CLK_RST_REG_BITS_ENUM(PLLC_OUT_PLLC_OUT1_CLKEN, ENABLE));
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util::WaitMicroSeconds(1'000);
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}
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void DisablePllc() {
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/* Disable PLLC/PLLC_OUT1. */
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_OUT, CLK_RST_REG_BITS_ENUM(PLLC_OUT_PLLC_OUT1_RSTN, RESET_ENABLE),
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CLK_RST_REG_BITS_ENUM(PLLC_OUT_PLLC_OUT1_CLKEN, DISABLE));
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_ENABLE, DISABLE));
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_PLLC_BASE, CLK_RST_REG_BITS_ENUM(PLLC_BASE_PLLC_REF_DIS, REF_DISABLE));
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reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC1, (1u << 27));
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reg::SetBits(g_register_address + CLK_RST_CONTROLLER_PLLC_MISC, (1u << 30));
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util::WaitMicroSeconds(10);
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}
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}
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void SetRegisterAddress(uintptr_t address) {
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g_register_address = address;
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}
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void SetFuseVisibility(bool visible) {
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_MISC_CLK_ENB, CLK_RST_REG_BITS_VALUE(MISC_CLK_ENB_CFG_ALL_VISIBLE, visible ? 1 : 0));
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}
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void EnableUartAClock() {
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EnableClock(UartAClock);
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}
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void EnableUartBClock() {
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EnableClock(UartBClock);
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}
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void EnableUartCClock() {
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EnableClock(UartCClock);
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}
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void EnableActmonClock() {
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EnableClock(ActmonClock);
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}
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void EnableI2c1Clock() {
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EnableClock(I2c1Clock);
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}
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void EnableI2c5Clock() {
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EnableClock(I2c5Clock);
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}
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void EnableSeClock() {
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EnableClock(SeClock);
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if (fuse::GetSocType() == fuse::SocType_Mariko) {
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reg::ReadWrite(g_register_address + CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_RST_REG_BITS_ENUM(CLK_SOURCE_SE_CLK_LOCK, ENABLE));
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}
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}
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void EnableCldvfsClock() {
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EnableClock(CldvfsClock);
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}
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void EnableCsiteClock() {
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EnableClock(CsiteClock);
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}
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void EnableTzramClock() {
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EnableClock(TzramClock);
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}
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void EnableCache2Clock() {
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EnableClock(Cache2Clock);
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}
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void EnableCram2Clock() {
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EnableClock(Cram2Clock);
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}
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void EnableHost1xClock() {
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EnableClock(Host1xClock);
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}
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void EnableTsecClock() {
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EnableClock(TsecClock);
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}
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void EnableSorSafeClock() {
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EnableClock(SorSafeClock);
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}
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void EnableSor0Clock() {
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EnableClock(Sor0Clock);
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}
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void EnableSor1Clock() {
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EnableClock(Sor1Clock);
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}
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void EnableKfuseClock() {
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EnableClock(KfuseClock);
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}
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void DisableI2c1Clock() {
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DisableClock(I2c1Clock);
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}
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void DisableHost1xClock() {
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DisableClock(Host1xClock);
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}
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void DisableTsecClock() {
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DisableClock(TsecClock);
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}
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void DisableSorSafeClock() {
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DisableClock(SorSafeClock);
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}
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void DisableSor0Clock() {
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DisableClock(Sor0Clock);
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}
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void DisableSor1Clock() {
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DisableClock(Sor1Clock);
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}
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void DisableKfuseClock() {
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DisableClock(KfuseClock);
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}
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BpmpClockRate GetBpmpClockRate() {
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return g_bpmp_clock_rate;
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}
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BpmpClockRate SetBpmpClockRate(BpmpClockRate rate) {
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/* Get the current rate. */
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const auto prev_rate = g_bpmp_clock_rate;
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/* Cap our rate. */
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if (rate >= BpmpClockRate_Count) {
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rate = BpmpClockRate_589MHz;
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}
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/* Change the rate, if we need to. */
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if (rate == prev_rate) {
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return prev_rate;
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}
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/* Configure the rate. */
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if (rate != BpmpClockRate_408MHz) {
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/* If we were previously overclocked, restore to PLLP_OUT. */
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if (prev_rate != BpmpClockRate_408MHz) {
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reg::Write(g_register_address + CLK_RST_CONTROLLER_SCLK_BURST_POLICY, CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SYS_STATE, RUN),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, PLLP_OUT0));
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util::WaitMicroSeconds(1'000);
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}
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/* Configure PLLC. */
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EnablePllc(rate);
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/* Set SCLK. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_CLK_SYSTEM_RATE, CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_HCLK_DIS, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_AHB_RATE, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_PCLK_DIS, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_APB_RATE, 3));
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reg::Write(g_register_address + CLK_RST_CONTROLLER_SCLK_BURST_POLICY, CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SYS_STATE, RUN),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, PLLC_OUT1),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, CLKM));
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} else {
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/* Configure to use PLLP_OUT0. */
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reg::Write(g_register_address + CLK_RST_CONTROLLER_SCLK_BURST_POLICY, CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SYS_STATE, RUN),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_FIQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_IRQ, NOP),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, PLLP_OUT0),
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CLK_RST_REG_BITS_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, CLKM));
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util::WaitMicroSeconds(1'000);
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reg::Write(g_register_address + CLK_RST_CONTROLLER_CLK_SYSTEM_RATE, CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_HCLK_DIS, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_AHB_RATE, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_PCLK_DIS, 0),
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CLK_RST_REG_BITS_VALUE(CLK_SYSTEM_RATE_APB_RATE, 2));
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/* Disable PLLC. */
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DisablePllc();
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}
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/* Set the clock rate. */
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g_bpmp_clock_rate = rate;
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/* Return the previous rate. */
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return prev_rate;
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}
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}
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