GPU Max frequency is now 1497.6MHz; RAM clocks could be set in sys-clk-OC (1331 and Max); DRAM manu as suffixes in loader.kip file names for references; README

This commit is contained in:
KazushiM
2021-12-03 23:46:43 +08:00
parent 6826fafe16
commit c66c836ae3
26 changed files with 113 additions and 93 deletions

View File

@@ -100,7 +100,7 @@ namespace pcv {
0xF1E94,
0xF1EE4,
};
constexpr u32 NewGpuVoltageLimit = 1050; // default max 1050mV
constexpr u32 NewGpuVoltageLimit = 1170; // default max 1050mV
constexpr u32 GpuTablesFreeSpace[] = {
0xE3410,
@@ -122,11 +122,11 @@ namespace pcv {
// { 1228800, {}, { 1277303, -11675, -859, 0, 3722, 313 } },
// { 1267200, {}, { 1335531, -12567, -867, 0, 3681, 559 } },
{ 1305600, {}, { 955000 } },
{ 1344000, {}, { 995000 } },
// { 1382400, {}, { 1040000 } },
// { 1420800, {}, { 1090000 } },
// { 1459200, {}, { 1145000 } },
// { 1497600, {}, { 1200000 } },
{ 1344000, {}, { 990000 } },
{ 1382400, {}, { 1030000 } },
{ 1420800, {}, { 1075000 } },
{ 1459200, {}, { 1120000 } },
{ 1497600, {}, { 1170000 } },
// { 1536000, {}, { 1250000 } },
};
static_assert(sizeof(NewGpuTables) <= sizeof(gpu_cvb_pll_table_t)*15);

View File

@@ -197,11 +197,11 @@ namespace ams::ldr {
ADJUST_PROPORTIONAL(TARGET_TABLE, REF_TABLE, shadow_regs_ca_train.PARAM) \
ADJUST_PROPORTIONAL(TARGET_TABLE, REF_TABLE, shadow_regs_rdwr_train.PARAM)
/* Calculate DIVM and DIVN */
/* Calculate DIVM and DIVN (clock DIVisors) */
/* Assume oscillator (PLLMB_IN) is 38.4 MHz */
/* PLLMB_OUT = PLLMB_IN / DIVM * DIVN */
u32 divn = GetEmcClock() / 38400;
u32 divm = 1;
u32 divn = GetEmcClock() / 38400;
if (GetEmcClock() - divn * 38400 >= 38400 / 2) {
divm = 2;
divn = divn * 2 + 1;
@@ -212,7 +212,7 @@ namespace ams::ldr {
pcv::MarikoMtcTable* mtc_table_1600 = reinterpret_cast<pcv::MarikoMtcTable *>(mapped_nso + pcv::MtcTable_1600[j]);
pcv::MarikoMtcTable* mtc_table_1331 = reinterpret_cast<pcv::MarikoMtcTable *>(mapped_nso + pcv::MtcTable_1600[j] - pcv::MtcTableOffset);
/* Normal and reasonable values */
/* Patch parameters that seem like timings */
ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rc);
ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rfc);
ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rfcpb);
@@ -280,6 +280,7 @@ namespace ams::ldr {
ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, min_mrs_wait);
ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, latency);
/* Patch clock divisors */
mtc_table_1600->pllmb_divm = divm;
mtc_table_1600->pllmb_divn = divn;
}
@@ -288,16 +289,16 @@ namespace ams::ldr {
}
}
EmcClock = GetEmcClock() * 1000;
// u32 PtmEmcClock = GetEmcClock() * 1000;
u32 CpuBoostClock = GetCpuBoostClock() * 1000;
for (u32 i = 0; i < sizeof(PtmModuleId)/sizeof(ro::ModuleId); i++) {
if (std::memcmp(std::addressof(PtmModuleId[i]), std::addressof(module_id), sizeof(module_id)) == 0) {
for (u32 j = 0; j < 16; j++) {
std::memcpy(reinterpret_cast<void *>(mapped_nso + ptm::EmcOffsetStart[i] + ptm::OffsetInterval * j), &EmcClock, sizeof(EmcClock));
std::memcpy(reinterpret_cast<void *>(mapped_nso + ptm::EmcOffsetStart[i] + ptm::OffsetInterval * j + 0x4), &EmcClock, sizeof(EmcClock));
}
// for (u32 j = 0; j < 16; j++) {
// std::memcpy(reinterpret_cast<void *>(mapped_nso + ptm::EmcOffsetStart[i] + ptm::OffsetInterval * j), &PtmEmcClock, sizeof(PtmEmcClock));
// std::memcpy(reinterpret_cast<void *>(mapped_nso + ptm::EmcOffsetStart[i] + ptm::OffsetInterval * j + 0x4), &PtmEmcClock, sizeof(PtmEmcClock));
// }
for (u32 j = 0; j < 2; j++) {
std::memcpy(reinterpret_cast<void *>(mapped_nso + ptm::EmcOffsetStart[i] + ptm::CpuBoostOffset + ptm::OffsetInterval * j), &CpuBoostClock, sizeof(CpuBoostClock));
std::memcpy(reinterpret_cast<void *>(mapped_nso + ptm::EmcOffsetStart[i] + ptm::CpuBoostOffset + ptm::OffsetInterval * j + 0x4), &CpuBoostClock, sizeof(CpuBoostClock));