diff --git a/Source/Atmosphere/stratosphere/loader/source/ldr_process_creation.cpp b/Source/Atmosphere/stratosphere/loader/source/ldr_process_creation.cpp
index 4a5bed22..1ddc399e 100644
--- a/Source/Atmosphere/stratosphere/loader/source/ldr_process_creation.cpp
+++ b/Source/Atmosphere/stratosphere/loader/source/ldr_process_creation.cpp
@@ -23,7 +23,7 @@
 #include "ldr_patcher.hpp"
 #include "ldr_process_creation.hpp"
 #include "ldr_ro_manager.hpp"
-#include "ldr_oc_suite.hpp"
+#include "oc/ldr_oc_suite.hpp"
 
 namespace ams::ldr {
 
diff --git a/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp b/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp
deleted file mode 100644
index d5b2488e..00000000
--- a/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp
+++ /dev/null
@@ -1,2373 +0,0 @@
-/*
- * Copyright (c) Atmosphère-NX
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- *
- * from GCC preprocessor output
- */
-
-struct MarikoMtcTable {
-    uint32_t rev;
-    char dvfs_ver[60];
-    uint32_t rate_khz;
-    uint32_t min_volt;
-    uint32_t gpu_min_volt;
-    char clock_src[32];
-    uint32_t clk_src_emc;
-    uint32_t pll_en_ssc;
-    uint32_t needs_training;
-    uint32_t training_pattern;
-    uint32_t trained;
-
-    uint32_t periodic_training;
-    uint32_t trained_dram_clktree_c0d0u0;
-    uint32_t trained_dram_clktree_c0d0u1;
-    uint32_t trained_dram_clktree_c0d1u0;
-    uint32_t trained_dram_clktree_c0d1u1;
-    uint32_t trained_dram_clktree_c1d0u0;
-    uint32_t trained_dram_clktree_c1d0u1;
-    uint32_t trained_dram_clktree_c1d1u0;
-    uint32_t trained_dram_clktree_c1d1u1;
-    uint32_t current_dram_clktree_c0d0u0;
-    uint32_t current_dram_clktree_c0d0u1;
-    uint32_t current_dram_clktree_c0d1u0;
-    uint32_t current_dram_clktree_c0d1u1;
-    uint32_t current_dram_clktree_c1d0u0;
-    uint32_t current_dram_clktree_c1d0u1;
-    uint32_t current_dram_clktree_c1d1u0;
-    uint32_t current_dram_clktree_c1d1u1;
-    uint32_t emc_fbio_cfg7;
-    uint32_t run_clocks;
-    uint32_t tree_margin;
-
-    uint32_t num_burst;
-    uint32_t num_burst_per_ch;
-    uint32_t num_trim;
-    uint32_t num_trim_per_ch;
-    uint32_t num_mc_regs;
-    uint32_t num_up_down;
-    uint32_t vref_num;
-    uint32_t training_mod_num;
-    uint32_t dram_timing_num;
-
-    uint32_t ptfv_dqsosc_movavg_c0d0u0;
-    uint32_t ptfv_dqsosc_movavg_c0d0u1;
-    uint32_t ptfv_dqsosc_movavg_c0d1u0;
-    uint32_t ptfv_dqsosc_movavg_c0d1u1;
-    uint32_t ptfv_dqsosc_movavg_c1d0u0;
-    uint32_t ptfv_dqsosc_movavg_c1d0u1;
-    uint32_t ptfv_dqsosc_movavg_c1d1u0;
-    uint32_t ptfv_dqsosc_movavg_c1d1u1;
-    uint32_t ptfv_write_samples;
-    uint32_t ptfv_dvfs_samples;
-    uint32_t ptfv_movavg_weight;
-    uint32_t ptfv_config_ctrl;
-
-    struct {
-        uint32_t emc_rc;
-        uint32_t emc_rfc;
-        uint32_t emc_rfcpb;
-        uint32_t emc_refctrl2;
-        uint32_t emc_rfc_slr;
-        uint32_t emc_ras;
-        uint32_t emc_rp;
-        uint32_t emc_r2w;
-        uint32_t emc_w2r;
-        uint32_t emc_r2p;
-        uint32_t emc_w2p;
-        uint32_t emc_r2r;
-        uint32_t emc_tppd;
-        uint32_t emc_trtm;
-        uint32_t emc_twtm;
-        uint32_t emc_tratm;
-        uint32_t emc_twatm;
-        uint32_t emc_tr2ref;
-        uint32_t emc_ccdmw;
-        uint32_t emc_rd_rcd;
-        uint32_t emc_wr_rcd;
-        uint32_t emc_rrd;
-        uint32_t emc_rext;
-        uint32_t emc_wext;
-        uint32_t emc_wdv_chk;
-        uint32_t emc_wdv;
-        uint32_t emc_wsv;
-        uint32_t emc_wev;
-        uint32_t emc_wdv_mask;
-        uint32_t emc_ws_duration;
-        uint32_t emc_we_duration;
-        uint32_t emc_quse;
-        uint32_t emc_quse_width;
-        uint32_t emc_ibdly;
-        uint32_t emc_obdly;
-        uint32_t emc_einput;
-        uint32_t emc_mrw6;
-        uint32_t emc_einput_duration;
-        uint32_t emc_puterm_extra;
-        uint32_t emc_puterm_width;
-        uint32_t emc_qrst;
-        uint32_t emc_qsafe;
-        uint32_t emc_rdv;
-        uint32_t emc_rdv_mask;
-        uint32_t emc_rdv_early;
-        uint32_t emc_rdv_early_mask;
-        uint32_t emc_refresh;
-        uint32_t emc_burst_refresh_num;
-        uint32_t emc_pre_refresh_req_cnt;
-        uint32_t emc_pdex2wr;
-        uint32_t emc_pdex2rd;
-        uint32_t emc_pchg2pden;
-        uint32_t emc_act2pden;
-        uint32_t emc_ar2pden;
-        uint32_t emc_rw2pden;
-        uint32_t emc_cke2pden;
-        uint32_t emc_pdex2cke;
-        uint32_t emc_pdex2mrr;
-        uint32_t emc_txsr;
-        uint32_t emc_txsrdll;
-        uint32_t emc_tcke;
-        uint32_t emc_tckesr;
-        uint32_t emc_tpd;
-        uint32_t emc_tfaw;
-        uint32_t emc_trpab;
-        uint32_t emc_tclkstable;
-        uint32_t emc_tclkstop;
-        uint32_t emc_mrw7;
-        uint32_t emc_trefbw;
-        uint32_t emc_odt_write;
-        uint32_t emc_fbio_cfg5;
-        uint32_t emc_fbio_cfg7;
-        uint32_t emc_cfg_dig_dll;
-        uint32_t emc_cfg_dig_dll_period;
-        uint32_t emc_pmacro_ib_rxrt;
-        uint32_t emc_cfg_pipe_1;
-        uint32_t emc_cfg_pipe_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_4;
-        uint32_t emc_pmacro_quse_ddll_rank0_5;
-        uint32_t emc_pmacro_quse_ddll_rank1_4;
-        uint32_t emc_pmacro_quse_ddll_rank1_5;
-        uint32_t emc_mrw8;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
-        uint32_t emc_pmacro_ddll_long_cmd_0;
-        uint32_t emc_pmacro_ddll_long_cmd_1;
-        uint32_t emc_pmacro_ddll_long_cmd_2;
-        uint32_t emc_pmacro_ddll_long_cmd_3;
-        uint32_t emc_pmacro_ddll_long_cmd_4;
-        uint32_t emc_pmacro_ddll_short_cmd_0;
-        uint32_t emc_pmacro_ddll_short_cmd_1;
-        uint32_t emc_pmacro_ddll_short_cmd_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
-        uint32_t emc_txdsrvttgen;
-        uint32_t emc_fdpd_ctrl_dq;
-        uint32_t emc_fdpd_ctrl_cmd;
-        uint32_t emc_fbio_spare;
-        uint32_t emc_zcal_interval;
-        uint32_t emc_zcal_wait_cnt;
-        uint32_t emc_mrs_wait_cnt;
-        uint32_t emc_mrs_wait_cnt2;
-        uint32_t emc_auto_cal_channel;
-        uint32_t emc_pmacro_dll_cfg_0;
-        uint32_t emc_pmacro_dll_cfg_1;
-        uint32_t emc_pmacro_dll_cfg_2;
-        uint32_t emc_pmacro_autocal_cfg_common;
-        uint32_t emc_pmacro_zctrl;
-        uint32_t emc_cfg;
-        uint32_t emc_cfg_pipe;
-        uint32_t emc_dyn_self_ref_control;
-        uint32_t emc_qpop;
-        uint32_t emc_dqs_brlshft_0;
-        uint32_t emc_dqs_brlshft_1;
-        uint32_t emc_cmd_brlshft_2;
-        uint32_t emc_cmd_brlshft_3;
-        uint32_t emc_pmacro_pad_cfg_ctrl;
-        uint32_t emc_pmacro_data_pad_rx_ctrl;
-        uint32_t emc_pmacro_cmd_pad_rx_ctrl;
-        uint32_t emc_pmacro_data_rx_term_mode;
-        uint32_t emc_pmacro_cmd_rx_term_mode;
-        uint32_t emc_pmacro_cmd_pad_tx_ctrl;
-        uint32_t emc_pmacro_data_pad_tx_ctrl;
-        uint32_t emc_pmacro_vttgen_ctrl_0;
-        uint32_t emc_pmacro_vttgen_ctrl_1;
-        uint32_t emc_pmacro_vttgen_ctrl_2;
-        uint32_t emc_pmacro_brick_ctrl_rfu1;
-        uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_brick_ctrl_rfu2;
-        uint32_t emc_pmacro_data_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_bg_bias_ctrl_0;
-        uint32_t emc_cfg_3;
-        uint32_t emc_pmacro_tx_pwrd_0;
-        uint32_t emc_pmacro_tx_pwrd_1;
-        uint32_t emc_pmacro_tx_pwrd_2;
-        uint32_t emc_pmacro_tx_pwrd_3;
-        uint32_t emc_pmacro_tx_pwrd_4;
-        uint32_t emc_pmacro_tx_pwrd_5;
-        uint32_t emc_config_sample_delay;
-        uint32_t emc_pmacro_tx_sel_clk_src_0;
-        uint32_t emc_pmacro_tx_sel_clk_src_1;
-        uint32_t emc_pmacro_tx_sel_clk_src_2;
-        uint32_t emc_pmacro_tx_sel_clk_src_3;
-        uint32_t emc_pmacro_tx_sel_clk_src_4;
-        uint32_t emc_pmacro_tx_sel_clk_src_5;
-        uint32_t emc_pmacro_ddll_bypass;
-        uint32_t emc_pmacro_ddll_pwrd_0;
-        uint32_t emc_pmacro_ddll_pwrd_1;
-        uint32_t emc_pmacro_ddll_pwrd_2;
-        uint32_t emc_pmacro_cmd_ctrl_0;
-        uint32_t emc_pmacro_cmd_ctrl_1;
-        uint32_t emc_pmacro_cmd_ctrl_2;
-        uint32_t emc_pmacro_data_pi_ctrl;
-        uint32_t emc_pmacro_cmd_pi_ctrl;
-        uint32_t emc_tr_timing_0;
-        uint32_t emc_tr_dvfs;
-        uint32_t emc_tr_ctrl_1;
-        uint32_t emc_tr_rdv;
-        uint32_t emc_tr_qpop;
-        uint32_t emc_tr_rdv_mask;
-        uint32_t emc_mrw14;
-        uint32_t emc_tr_qsafe;
-        uint32_t emc_tr_qrst;
-        uint32_t emc_training_ctrl;
-        uint32_t emc_training_settle;
-        uint32_t emc_training_vref_settle;
-        uint32_t emc_training_ca_fine_ctrl;
-        uint32_t emc_training_ca_ctrl_misc;
-        uint32_t emc_training_ca_ctrl_misc1;
-        uint32_t emc_training_ca_vref_ctrl;
-        uint32_t emc_training_quse_cors_ctrl;
-        uint32_t emc_training_quse_fine_ctrl;
-        uint32_t emc_training_quse_ctrl_misc;
-        uint32_t emc_training_quse_vref_ctrl;
-        uint32_t emc_training_read_fine_ctrl;
-        uint32_t emc_training_read_ctrl_misc;
-        uint32_t emc_training_read_vref_ctrl;
-        uint32_t emc_training_write_fine_ctrl;
-        uint32_t emc_training_write_ctrl_misc;
-        uint32_t emc_training_write_vref_ctrl;
-        uint32_t emc_training_mpc;
-        uint32_t emc_mrw15;
-    }
-    burst_regs;
-
-    struct {
-        uint32_t emc0_mrw10;
-        uint32_t emc1_mrw10;
-        uint32_t emc0_mrw11;
-        uint32_t emc1_mrw11;
-        uint32_t emc0_mrw12;
-        uint32_t emc1_mrw12;
-        uint32_t emc0_mrw13;
-        uint32_t emc1_mrw13;
-    }
-    burst_perch_regs;
-
-    struct {
-        uint32_t emc_rc;
-        uint32_t emc_rfc;
-        uint32_t emc_rfcpb;
-        uint32_t emc_refctrl2;
-        uint32_t emc_rfc_slr;
-        uint32_t emc_ras;
-        uint32_t emc_rp;
-        uint32_t emc_r2w;
-        uint32_t emc_w2r;
-        uint32_t emc_r2p;
-        uint32_t emc_w2p;
-        uint32_t emc_r2r;
-        uint32_t emc_tppd;
-        uint32_t emc_trtm;
-        uint32_t emc_twtm;
-        uint32_t emc_tratm;
-        uint32_t emc_twatm;
-        uint32_t emc_tr2ref;
-        uint32_t emc_ccdmw;
-        uint32_t emc_rd_rcd;
-        uint32_t emc_wr_rcd;
-        uint32_t emc_rrd;
-        uint32_t emc_rext;
-        uint32_t emc_wext;
-        uint32_t emc_wdv_chk;
-        uint32_t emc_wdv;
-        uint32_t emc_wsv;
-        uint32_t emc_wev;
-        uint32_t emc_wdv_mask;
-        uint32_t emc_ws_duration;
-        uint32_t emc_we_duration;
-        uint32_t emc_quse;
-        uint32_t emc_quse_width;
-        uint32_t emc_ibdly;
-        uint32_t emc_obdly;
-        uint32_t emc_einput;
-        uint32_t emc_mrw6;
-        uint32_t emc_einput_duration;
-        uint32_t emc_puterm_extra;
-        uint32_t emc_puterm_width;
-        uint32_t emc_qrst;
-        uint32_t emc_qsafe;
-        uint32_t emc_rdv;
-        uint32_t emc_rdv_mask;
-        uint32_t emc_rdv_early;
-        uint32_t emc_rdv_early_mask;
-        uint32_t emc_refresh;
-        uint32_t emc_burst_refresh_num;
-        uint32_t emc_pre_refresh_req_cnt;
-        uint32_t emc_pdex2wr;
-        uint32_t emc_pdex2rd;
-        uint32_t emc_pchg2pden;
-        uint32_t emc_act2pden;
-        uint32_t emc_ar2pden;
-        uint32_t emc_rw2pden;
-        uint32_t emc_cke2pden;
-        uint32_t emc_pdex2cke;
-        uint32_t emc_pdex2mrr;
-        uint32_t emc_txsr;
-        uint32_t emc_txsrdll;
-        uint32_t emc_tcke;
-        uint32_t emc_tckesr;
-        uint32_t emc_tpd;
-        uint32_t emc_tfaw;
-        uint32_t emc_trpab;
-        uint32_t emc_tclkstable;
-        uint32_t emc_tclkstop;
-        uint32_t emc_mrw7;
-        uint32_t emc_trefbw;
-        uint32_t emc_odt_write;
-        uint32_t emc_fbio_cfg5;
-        uint32_t emc_fbio_cfg7;
-        uint32_t emc_cfg_dig_dll;
-        uint32_t emc_cfg_dig_dll_period;
-        uint32_t emc_pmacro_ib_rxrt;
-        uint32_t emc_cfg_pipe_1;
-        uint32_t emc_cfg_pipe_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_4;
-        uint32_t emc_pmacro_quse_ddll_rank0_5;
-        uint32_t emc_pmacro_quse_ddll_rank1_4;
-        uint32_t emc_pmacro_quse_ddll_rank1_5;
-        uint32_t emc_mrw8;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
-        uint32_t emc_pmacro_ddll_long_cmd_0;
-        uint32_t emc_pmacro_ddll_long_cmd_1;
-        uint32_t emc_pmacro_ddll_long_cmd_2;
-        uint32_t emc_pmacro_ddll_long_cmd_3;
-        uint32_t emc_pmacro_ddll_long_cmd_4;
-        uint32_t emc_pmacro_ddll_short_cmd_0;
-        uint32_t emc_pmacro_ddll_short_cmd_1;
-        uint32_t emc_pmacro_ddll_short_cmd_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
-        uint32_t emc_txdsrvttgen;
-        uint32_t emc_fdpd_ctrl_dq;
-        uint32_t emc_fdpd_ctrl_cmd;
-        uint32_t emc_fbio_spare;
-        uint32_t emc_zcal_interval;
-        uint32_t emc_zcal_wait_cnt;
-        uint32_t emc_mrs_wait_cnt;
-        uint32_t emc_mrs_wait_cnt2;
-        uint32_t emc_auto_cal_channel;
-        uint32_t emc_pmacro_dll_cfg_0;
-        uint32_t emc_pmacro_dll_cfg_1;
-        uint32_t emc_pmacro_dll_cfg_2;
-        uint32_t emc_pmacro_autocal_cfg_common;
-        uint32_t emc_pmacro_zctrl;
-        uint32_t emc_cfg;
-        uint32_t emc_cfg_pipe;
-        uint32_t emc_dyn_self_ref_control;
-        uint32_t emc_qpop;
-        uint32_t emc_dqs_brlshft_0;
-        uint32_t emc_dqs_brlshft_1;
-        uint32_t emc_cmd_brlshft_2;
-        uint32_t emc_cmd_brlshft_3;
-        uint32_t emc_pmacro_pad_cfg_ctrl;
-        uint32_t emc_pmacro_data_pad_rx_ctrl;
-        uint32_t emc_pmacro_cmd_pad_rx_ctrl;
-        uint32_t emc_pmacro_data_rx_term_mode;
-        uint32_t emc_pmacro_cmd_rx_term_mode;
-        uint32_t emc_pmacro_cmd_pad_tx_ctrl;
-        uint32_t emc_pmacro_data_pad_tx_ctrl;
-        uint32_t emc_pmacro_vttgen_ctrl_0;
-        uint32_t emc_pmacro_vttgen_ctrl_1;
-        uint32_t emc_pmacro_vttgen_ctrl_2;
-        uint32_t emc_pmacro_brick_ctrl_rfu1;
-        uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_brick_ctrl_rfu2;
-        uint32_t emc_pmacro_data_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_bg_bias_ctrl_0;
-        uint32_t emc_cfg_3;
-        uint32_t emc_pmacro_tx_pwrd_0;
-        uint32_t emc_pmacro_tx_pwrd_1;
-        uint32_t emc_pmacro_tx_pwrd_2;
-        uint32_t emc_pmacro_tx_pwrd_3;
-        uint32_t emc_pmacro_tx_pwrd_4;
-        uint32_t emc_pmacro_tx_pwrd_5;
-        uint32_t emc_config_sample_delay;
-        uint32_t emc_pmacro_tx_sel_clk_src_0;
-        uint32_t emc_pmacro_tx_sel_clk_src_1;
-        uint32_t emc_pmacro_tx_sel_clk_src_2;
-        uint32_t emc_pmacro_tx_sel_clk_src_3;
-        uint32_t emc_pmacro_tx_sel_clk_src_4;
-        uint32_t emc_pmacro_tx_sel_clk_src_5;
-        uint32_t emc_pmacro_ddll_bypass;
-        uint32_t emc_pmacro_ddll_pwrd_0;
-        uint32_t emc_pmacro_ddll_pwrd_1;
-        uint32_t emc_pmacro_ddll_pwrd_2;
-        uint32_t emc_pmacro_cmd_ctrl_0;
-        uint32_t emc_pmacro_cmd_ctrl_1;
-        uint32_t emc_pmacro_cmd_ctrl_2;
-        uint32_t emc_pmacro_data_pi_ctrl;
-        uint32_t emc_pmacro_cmd_pi_ctrl;
-        uint32_t emc_tr_timing_0;
-        uint32_t emc_tr_dvfs;
-        uint32_t emc_tr_ctrl_1;
-        uint32_t emc_tr_rdv;
-        uint32_t emc_tr_qpop;
-        uint32_t emc_tr_rdv_mask;
-        uint32_t emc_mrw14;
-        uint32_t emc_tr_qsafe;
-        uint32_t emc_tr_qrst;
-        uint32_t emc_training_ctrl;
-        uint32_t emc_training_settle;
-        uint32_t emc_training_vref_settle;
-        uint32_t emc_training_ca_fine_ctrl;
-        uint32_t emc_training_ca_ctrl_misc;
-        uint32_t emc_training_ca_ctrl_misc1;
-        uint32_t emc_training_ca_vref_ctrl;
-        uint32_t emc_training_quse_cors_ctrl;
-        uint32_t emc_training_quse_fine_ctrl;
-        uint32_t emc_training_quse_ctrl_misc;
-        uint32_t emc_training_quse_vref_ctrl;
-        uint32_t emc_training_read_fine_ctrl;
-        uint32_t emc_training_read_ctrl_misc;
-        uint32_t emc_training_read_vref_ctrl;
-        uint32_t emc_training_write_fine_ctrl;
-        uint32_t emc_training_write_ctrl_misc;
-        uint32_t emc_training_write_vref_ctrl;
-        uint32_t emc_training_mpc;
-        uint32_t emc_mrw15;
-    }
-    shadow_regs_ca_train;
-
-    struct {
-        uint32_t emc_rc;
-        uint32_t emc_rfc;
-        uint32_t emc_rfcpb;
-        uint32_t emc_refctrl2;
-        uint32_t emc_rfc_slr;
-        uint32_t emc_ras;
-        uint32_t emc_rp;
-        uint32_t emc_r2w;
-        uint32_t emc_w2r;
-        uint32_t emc_r2p;
-        uint32_t emc_w2p;
-        uint32_t emc_r2r;
-        uint32_t emc_tppd;
-        uint32_t emc_trtm;
-        uint32_t emc_twtm;
-        uint32_t emc_tratm;
-        uint32_t emc_twatm;
-        uint32_t emc_tr2ref;
-        uint32_t emc_ccdmw;
-        uint32_t emc_rd_rcd;
-        uint32_t emc_wr_rcd;
-        uint32_t emc_rrd;
-        uint32_t emc_rext;
-        uint32_t emc_wext;
-        uint32_t emc_wdv_chk;
-        uint32_t emc_wdv;
-        uint32_t emc_wsv;
-        uint32_t emc_wev;
-        uint32_t emc_wdv_mask;
-        uint32_t emc_ws_duration;
-        uint32_t emc_we_duration;
-        uint32_t emc_quse;
-        uint32_t emc_quse_width;
-        uint32_t emc_ibdly;
-        uint32_t emc_obdly;
-        uint32_t emc_einput;
-        uint32_t emc_mrw6;
-        uint32_t emc_einput_duration;
-        uint32_t emc_puterm_extra;
-        uint32_t emc_puterm_width;
-        uint32_t emc_qrst;
-        uint32_t emc_qsafe;
-        uint32_t emc_rdv;
-        uint32_t emc_rdv_mask;
-        uint32_t emc_rdv_early;
-        uint32_t emc_rdv_early_mask;
-        uint32_t emc_refresh;
-        uint32_t emc_burst_refresh_num;
-        uint32_t emc_pre_refresh_req_cnt;
-        uint32_t emc_pdex2wr;
-        uint32_t emc_pdex2rd;
-        uint32_t emc_pchg2pden;
-        uint32_t emc_act2pden;
-        uint32_t emc_ar2pden;
-        uint32_t emc_rw2pden;
-        uint32_t emc_cke2pden;
-        uint32_t emc_pdex2cke;
-        uint32_t emc_pdex2mrr;
-        uint32_t emc_txsr;
-        uint32_t emc_txsrdll;
-        uint32_t emc_tcke;
-        uint32_t emc_tckesr;
-        uint32_t emc_tpd;
-        uint32_t emc_tfaw;
-        uint32_t emc_trpab;
-        uint32_t emc_tclkstable;
-        uint32_t emc_tclkstop;
-        uint32_t emc_mrw7;
-        uint32_t emc_trefbw;
-        uint32_t emc_odt_write;
-        uint32_t emc_fbio_cfg5;
-        uint32_t emc_fbio_cfg7;
-        uint32_t emc_cfg_dig_dll;
-        uint32_t emc_cfg_dig_dll_period;
-        uint32_t emc_pmacro_ib_rxrt;
-        uint32_t emc_cfg_pipe_1;
-        uint32_t emc_cfg_pipe_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_4;
-        uint32_t emc_pmacro_quse_ddll_rank0_5;
-        uint32_t emc_pmacro_quse_ddll_rank1_4;
-        uint32_t emc_pmacro_quse_ddll_rank1_5;
-        uint32_t emc_mrw8;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
-        uint32_t emc_pmacro_ddll_long_cmd_0;
-        uint32_t emc_pmacro_ddll_long_cmd_1;
-        uint32_t emc_pmacro_ddll_long_cmd_2;
-        uint32_t emc_pmacro_ddll_long_cmd_3;
-        uint32_t emc_pmacro_ddll_long_cmd_4;
-        uint32_t emc_pmacro_ddll_short_cmd_0;
-        uint32_t emc_pmacro_ddll_short_cmd_1;
-        uint32_t emc_pmacro_ddll_short_cmd_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
-        uint32_t emc_txdsrvttgen;
-        uint32_t emc_fdpd_ctrl_dq;
-        uint32_t emc_fdpd_ctrl_cmd;
-        uint32_t emc_fbio_spare;
-        uint32_t emc_zcal_interval;
-        uint32_t emc_zcal_wait_cnt;
-        uint32_t emc_mrs_wait_cnt;
-        uint32_t emc_mrs_wait_cnt2;
-        uint32_t emc_auto_cal_channel;
-        uint32_t emc_pmacro_dll_cfg_0;
-        uint32_t emc_pmacro_dll_cfg_1;
-        uint32_t emc_pmacro_dll_cfg_2;
-        uint32_t emc_pmacro_autocal_cfg_common;
-        uint32_t emc_pmacro_zctrl;
-        uint32_t emc_cfg;
-        uint32_t emc_cfg_pipe;
-        uint32_t emc_dyn_self_ref_control;
-        uint32_t emc_qpop;
-        uint32_t emc_dqs_brlshft_0;
-        uint32_t emc_dqs_brlshft_1;
-        uint32_t emc_cmd_brlshft_2;
-        uint32_t emc_cmd_brlshft_3;
-        uint32_t emc_pmacro_pad_cfg_ctrl;
-        uint32_t emc_pmacro_data_pad_rx_ctrl;
-        uint32_t emc_pmacro_cmd_pad_rx_ctrl;
-        uint32_t emc_pmacro_data_rx_term_mode;
-        uint32_t emc_pmacro_cmd_rx_term_mode;
-        uint32_t emc_pmacro_cmd_pad_tx_ctrl;
-        uint32_t emc_pmacro_data_pad_tx_ctrl;
-        uint32_t emc_pmacro_vttgen_ctrl_0;
-        uint32_t emc_pmacro_vttgen_ctrl_1;
-        uint32_t emc_pmacro_vttgen_ctrl_2;
-        uint32_t emc_pmacro_brick_ctrl_rfu1;
-        uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_brick_ctrl_rfu2;
-        uint32_t emc_pmacro_data_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_bg_bias_ctrl_0;
-        uint32_t emc_cfg_3;
-        uint32_t emc_pmacro_tx_pwrd_0;
-        uint32_t emc_pmacro_tx_pwrd_1;
-        uint32_t emc_pmacro_tx_pwrd_2;
-        uint32_t emc_pmacro_tx_pwrd_3;
-        uint32_t emc_pmacro_tx_pwrd_4;
-        uint32_t emc_pmacro_tx_pwrd_5;
-        uint32_t emc_config_sample_delay;
-        uint32_t emc_pmacro_tx_sel_clk_src_0;
-        uint32_t emc_pmacro_tx_sel_clk_src_1;
-        uint32_t emc_pmacro_tx_sel_clk_src_2;
-        uint32_t emc_pmacro_tx_sel_clk_src_3;
-        uint32_t emc_pmacro_tx_sel_clk_src_4;
-        uint32_t emc_pmacro_tx_sel_clk_src_5;
-        uint32_t emc_pmacro_ddll_bypass;
-        uint32_t emc_pmacro_ddll_pwrd_0;
-        uint32_t emc_pmacro_ddll_pwrd_1;
-        uint32_t emc_pmacro_ddll_pwrd_2;
-        uint32_t emc_pmacro_cmd_ctrl_0;
-        uint32_t emc_pmacro_cmd_ctrl_1;
-        uint32_t emc_pmacro_cmd_ctrl_2;
-        uint32_t emc_pmacro_data_pi_ctrl;
-        uint32_t emc_pmacro_cmd_pi_ctrl;
-        uint32_t emc_tr_timing_0;
-        uint32_t emc_tr_dvfs;
-        uint32_t emc_tr_ctrl_1;
-        uint32_t emc_tr_rdv;
-        uint32_t emc_tr_qpop;
-        uint32_t emc_tr_rdv_mask;
-        uint32_t emc_mrw14;
-        uint32_t emc_tr_qsafe;
-        uint32_t emc_tr_qrst;
-        uint32_t emc_training_ctrl;
-        uint32_t emc_training_settle;
-        uint32_t emc_training_vref_settle;
-        uint32_t emc_training_ca_fine_ctrl;
-        uint32_t emc_training_ca_ctrl_misc;
-        uint32_t emc_training_ca_ctrl_misc1;
-        uint32_t emc_training_ca_vref_ctrl;
-        uint32_t emc_training_quse_cors_ctrl;
-        uint32_t emc_training_quse_fine_ctrl;
-        uint32_t emc_training_quse_ctrl_misc;
-        uint32_t emc_training_quse_vref_ctrl;
-        uint32_t emc_training_read_fine_ctrl;
-        uint32_t emc_training_read_ctrl_misc;
-        uint32_t emc_training_read_vref_ctrl;
-        uint32_t emc_training_write_fine_ctrl;
-        uint32_t emc_training_write_ctrl_misc;
-        uint32_t emc_training_write_vref_ctrl;
-        uint32_t emc_training_mpc;
-        uint32_t emc_mrw15;
-    }
-    shadow_regs_rdwr_train;
-
-    struct {
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;
-        uint32_t emc_pmacro_ib_vref_dqs_0;
-        uint32_t emc_pmacro_ib_vref_dqs_1;
-        uint32_t emc_pmacro_ib_vref_dq_0;
-        uint32_t emc_pmacro_ib_vref_dq_1;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_0;
-        uint32_t emc_pmacro_quse_ddll_rank0_1;
-        uint32_t emc_pmacro_quse_ddll_rank0_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_3;
-        uint32_t emc_pmacro_quse_ddll_rank1_0;
-        uint32_t emc_pmacro_quse_ddll_rank1_1;
-        uint32_t emc_pmacro_quse_ddll_rank1_2;
-        uint32_t emc_pmacro_quse_ddll_rank1_3;
-    }
-    trim_regs;
-
-    struct {
-        uint32_t emc0_cmd_brlshft_0;
-        uint32_t emc1_cmd_brlshft_1;
-        uint32_t emc0_data_brlshft_0;
-        uint32_t emc1_data_brlshft_0;
-        uint32_t emc0_data_brlshft_1;
-        uint32_t emc1_data_brlshft_1;
-        uint32_t emc0_quse_brlshft_0;
-        uint32_t emc1_quse_brlshft_1;
-        uint32_t emc0_quse_brlshft_2;
-        uint32_t emc1_quse_brlshft_3;
-    }
-    trim_perch_regs;
-
-    struct {
-        uint32_t emc0_training_opt_dqs_ib_vref_rank0;
-        uint32_t emc1_training_opt_dqs_ib_vref_rank0;
-        uint32_t emc0_training_opt_dqs_ib_vref_rank1;
-        uint32_t emc1_training_opt_dqs_ib_vref_rank1;
-    }
-    vref_perch_regs;
-
-    struct {
-        uint32_t t_rp;
-        uint32_t t_fc_lpddr4;
-        uint32_t t_rfc;
-        uint32_t t_pdex;
-        uint32_t rl;
-    }
-    dram_timings;
-
-    uint32_t zq_op_cc_long_zcal;
-    uint32_t zq_op_cc_short_zcal;
-    uint32_t zcal_wait_time_ps_cc_long_zcal;
-    uint32_t zcal_wait_time_ps_cc_short_zcal;
-    uint32_t tZQCAL_lpddr4;
-    uint32_t zqcal_before_cc_cutoff;
-    uint32_t opt_cc_short_zcal;
-    uint32_t opt_short_zcal;
-    uint32_t opt_do_sw_qrst;
-    uint32_t save_restore_clkstop_pd;
-    uint32_t opt_E90;
-    uint32_t cya_allow_ref_cc;
-    uint32_t ref_b4_sref_en;
-    uint32_t cya_issue_pc_ref;
-
-    struct {
-        uint32_t emc0_training_rw_offset_ib_byte0;
-        uint32_t emc1_training_rw_offset_ib_byte0;
-        uint32_t emc0_training_rw_offset_ib_byte1;
-        uint32_t emc1_training_rw_offset_ib_byte1;
-        uint32_t emc0_training_rw_offset_ib_byte2;
-        uint32_t emc1_training_rw_offset_ib_byte2;
-        uint32_t emc0_training_rw_offset_ib_byte3;
-        uint32_t emc1_training_rw_offset_ib_byte3;
-        uint32_t emc0_training_rw_offset_ib_misc;
-        uint32_t emc1_training_rw_offset_ib_misc;
-        uint32_t emc0_training_rw_offset_ob_byte0;
-        uint32_t emc1_training_rw_offset_ob_byte0;
-        uint32_t emc0_training_rw_offset_ob_byte1;
-        uint32_t emc1_training_rw_offset_ob_byte1;
-        uint32_t emc0_training_rw_offset_ob_byte2;
-        uint32_t emc1_training_rw_offset_ob_byte2;
-        uint32_t emc0_training_rw_offset_ob_byte3;
-        uint32_t emc1_training_rw_offset_ob_byte3;
-        uint32_t emc0_training_rw_offset_ob_misc;
-        uint32_t emc1_training_rw_offset_ob_misc;
-    }
-    training_mod_regs;
-
-    uint32_t save_restore_mod_regs[12];
-
-    struct {
-        uint32_t mc_emem_arb_cfg;
-        uint32_t mc_emem_arb_outstanding_req;
-        uint32_t mc_emem_arb_refpb_hp_ctrl;
-        uint32_t mc_emem_arb_refpb_bank_ctrl;
-        uint32_t mc_emem_arb_timing_rcd;
-        uint32_t mc_emem_arb_timing_rp;
-        uint32_t mc_emem_arb_timing_rc;
-        uint32_t mc_emem_arb_timing_ras;
-        uint32_t mc_emem_arb_timing_faw;
-        uint32_t mc_emem_arb_timing_rrd;
-        uint32_t mc_emem_arb_timing_rap2pre;
-        uint32_t mc_emem_arb_timing_wap2pre;
-        uint32_t mc_emem_arb_timing_r2r;
-        uint32_t mc_emem_arb_timing_w2w;
-        uint32_t mc_emem_arb_timing_r2w;
-        uint32_t mc_emem_arb_timing_ccdmw;
-        uint32_t mc_emem_arb_timing_w2r;
-        uint32_t mc_emem_arb_timing_rfcpb;
-        uint32_t mc_emem_arb_da_turns;
-        uint32_t mc_emem_arb_da_covers;
-        uint32_t mc_emem_arb_misc0;
-        uint32_t mc_emem_arb_misc1;
-        uint32_t mc_emem_arb_misc2;
-        uint32_t mc_emem_arb_ring1_throttle;
-        uint32_t mc_emem_arb_dhyst_ctrl;
-        uint32_t mc_emem_arb_dhyst_timeout_util_0;
-        uint32_t mc_emem_arb_dhyst_timeout_util_1;
-        uint32_t mc_emem_arb_dhyst_timeout_util_2;
-        uint32_t mc_emem_arb_dhyst_timeout_util_3;
-        uint32_t mc_emem_arb_dhyst_timeout_util_4;
-        uint32_t mc_emem_arb_dhyst_timeout_util_5;
-        uint32_t mc_emem_arb_dhyst_timeout_util_6;
-        uint32_t mc_emem_arb_dhyst_timeout_util_7;
-    }
-    burst_mc_regs;
-
-    struct {
-        uint32_t mc_mll_mpcorer_ptsa_rate;
-        uint32_t mc_ftop_ptsa_rate;
-        uint32_t mc_ptsa_grant_decrement;
-        uint32_t mc_latency_allowance_xusb_0;
-        uint32_t mc_latency_allowance_xusb_1;
-        uint32_t mc_latency_allowance_tsec_0;
-        uint32_t mc_latency_allowance_sdmmca_0;
-        uint32_t mc_latency_allowance_sdmmcaa_0;
-        uint32_t mc_latency_allowance_sdmmc_0;
-        uint32_t mc_latency_allowance_sdmmcab_0;
-        uint32_t mc_latency_allowance_ppcs_0;
-        uint32_t mc_latency_allowance_ppcs_1;
-        uint32_t mc_latency_allowance_mpcore_0;
-        uint32_t mc_latency_allowance_hc_0;
-        uint32_t mc_latency_allowance_hc_1;
-        uint32_t mc_latency_allowance_avpc_0;
-        uint32_t mc_latency_allowance_gpu_0;
-        uint32_t mc_latency_allowance_gpu2_0;
-        uint32_t mc_latency_allowance_nvenc_0;
-        uint32_t mc_latency_allowance_nvdec_0;
-        uint32_t mc_latency_allowance_vic_0;
-        uint32_t mc_latency_allowance_vi2_0;
-        uint32_t mc_latency_allowance_isp2_0;
-        uint32_t mc_latency_allowance_isp2_1;
-    }
-    la_scale_regs;
-
-    uint32_t unk_0;
-    uint32_t vtt_vdda_ctrl_0;
-    uint32_t src_clock_div;
-    uint32_t vtt_vdda_dual_channel;
-    uint32_t vtt_vdda_ctrl_1;
-    uint32_t vtt_vdda_ctrl_2;
-    uint32_t vtt_vdda_ctrl_3;
-    uint32_t vtt_vdda_ctrl_4;
-    uint32_t misc_cfg_0;
-    uint32_t misc_cfg_1;
-    uint32_t misc_cfg_2;
-    uint32_t unk_1;
-    uint32_t unk_2;
-    uint32_t pipe_clk_delay;
-    uint32_t clkchange_delay;
-    uint32_t pllm_ss_cfg;
-    uint32_t pllm_ss_ctrl1;
-    uint32_t pllm_ss_ctrl2;
-    uint32_t pllmb_ss_cfg;
-    uint32_t pllmb_ss_ctrl1;
-    uint32_t pllmb_ss_ctrl2;
-    uint32_t pllmb_divm;
-    uint32_t pllmb_divn;
-    uint32_t pllmb_divp;
-    uint32_t min_mrs_wait;
-    uint32_t ramp_wait;
-    uint32_t emc_mrw;
-    uint32_t emc_mrw2;
-    uint32_t emc_mrw3;
-    uint32_t emc_mrw4;
-    uint32_t emc_mrw9;
-    uint32_t emc_mrs;
-    uint32_t emc_emrs;
-    uint32_t emc_emrs2;
-    uint32_t emc_auto_cal_config;
-    uint32_t emc_auto_cal_config2;
-    uint32_t emc_auto_cal_config3;
-    uint32_t emc_auto_cal_config4;
-    uint32_t emc_auto_cal_config5;
-    uint32_t emc_auto_cal_config6;
-    uint32_t emc_auto_cal_config7;
-    uint32_t emc_auto_cal_config8;
-    uint32_t emc_cfg_2;
-    uint32_t emc_sel_dpd_ctrl;
-    uint32_t emc_fdpd_ctrl_cmd_no_ramp;
-    uint32_t emc_tr_ctrl_0;
-    uint32_t dll_clk_src;
-    uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
-    uint32_t latency;
-    uint32_t pllm_misc1_0_pllm_clamp_ph90;
-};
-
-static_assert(sizeof(MarikoMtcTable) == 0x10CC);
-
-struct EristaMtcTable {
-    uint32_t rev;
-    char dvfs_ver[60];
-    uint32_t rate_khz;
-    uint32_t min_volt;
-    uint32_t gpu_min_volt;
-    char clock_src[32];
-    uint32_t clk_src_emc;
-    uint32_t needs_training;
-    uint32_t training_pattern;
-    uint32_t trained;
-
-    uint32_t periodic_training;
-    uint32_t trained_dram_clktree_c0d0u0;
-    uint32_t trained_dram_clktree_c0d0u1;
-    uint32_t trained_dram_clktree_c0d1u0;
-    uint32_t trained_dram_clktree_c0d1u1;
-    uint32_t trained_dram_clktree_c1d0u0;
-    uint32_t trained_dram_clktree_c1d0u1;
-    uint32_t trained_dram_clktree_c1d1u0;
-    uint32_t trained_dram_clktree_c1d1u1;
-    uint32_t current_dram_clktree_c0d0u0;
-    uint32_t current_dram_clktree_c0d0u1;
-    uint32_t current_dram_clktree_c0d1u0;
-    uint32_t current_dram_clktree_c0d1u1;
-    uint32_t current_dram_clktree_c1d0u0;
-    uint32_t current_dram_clktree_c1d0u1;
-    uint32_t current_dram_clktree_c1d1u0;
-    uint32_t current_dram_clktree_c1d1u1;
-    uint32_t run_clocks;
-    uint32_t tree_margin;
-
-    uint32_t num_burst;
-    uint32_t num_burst_per_ch;
-    uint32_t num_trim;
-    uint32_t num_trim_per_ch;
-    uint32_t num_mc_regs;
-    uint32_t num_up_down;
-    uint32_t vref_num;
-    uint32_t training_mod_num;
-    uint32_t dram_timing_num;
-
-    uint32_t ptfv_dqsosc_movavg_c0d0u0;
-    uint32_t ptfv_dqsosc_movavg_c0d0u1;
-    uint32_t ptfv_dqsosc_movavg_c0d1u0;
-    uint32_t ptfv_dqsosc_movavg_c0d1u1;
-    uint32_t ptfv_dqsosc_movavg_c1d0u0;
-    uint32_t ptfv_dqsosc_movavg_c1d0u1;
-    uint32_t ptfv_dqsosc_movavg_c1d1u0;
-    uint32_t ptfv_dqsosc_movavg_c1d1u1;
-    uint32_t ptfv_write_samples;
-    uint32_t ptfv_dvfs_samples;
-    uint32_t ptfv_movavg_weight;
-    uint32_t ptfv_config_ctrl;
-
-    struct {
-        uint32_t emc_rc;
-        uint32_t emc_rfc;
-        uint32_t emc_rfcpb;
-        uint32_t emc_refctrl2;
-        uint32_t emc_rfc_slr;
-        uint32_t emc_ras;
-        uint32_t emc_rp;
-        uint32_t emc_r2w;
-        uint32_t emc_w2r;
-        uint32_t emc_r2p;
-        uint32_t emc_w2p;
-        uint32_t emc_r2r;
-        uint32_t emc_tppd;
-        uint32_t emc_ccdmw;
-        uint32_t emc_rd_rcd;
-        uint32_t emc_wr_rcd;
-        uint32_t emc_rrd;
-        uint32_t emc_rext;
-        uint32_t emc_wext;
-        uint32_t emc_wdv_chk;
-        uint32_t emc_wdv;
-        uint32_t emc_wsv;
-        uint32_t emc_wev;
-        uint32_t emc_wdv_mask;
-        uint32_t emc_ws_duration;
-        uint32_t emc_we_duration;
-        uint32_t emc_quse;
-        uint32_t emc_quse_width;
-        uint32_t emc_ibdly;
-        uint32_t emc_obdly;
-        uint32_t emc_einput;
-        uint32_t emc_mrw6;
-        uint32_t emc_einput_duration;
-        uint32_t emc_puterm_extra;
-        uint32_t emc_puterm_width;
-        uint32_t emc_qrst;
-        uint32_t emc_qsafe;
-        uint32_t emc_rdv;
-        uint32_t emc_rdv_mask;
-        uint32_t emc_rdv_early;
-        uint32_t emc_rdv_early_mask;
-        uint32_t emc_refresh;
-        uint32_t emc_burst_refresh_num;
-        uint32_t emc_pre_refresh_req_cnt;
-        uint32_t emc_pdex2wr;
-        uint32_t emc_pdex2rd;
-        uint32_t emc_pchg2pden;
-        uint32_t emc_act2pden;
-        uint32_t emc_ar2pden;
-        uint32_t emc_rw2pden;
-        uint32_t emc_cke2pden;
-        uint32_t emc_pdex2cke;
-        uint32_t emc_pdex2mrr;
-        uint32_t emc_txsr;
-        uint32_t emc_txsrdll;
-        uint32_t emc_tcke;
-        uint32_t emc_tckesr;
-        uint32_t emc_tpd;
-        uint32_t emc_tfaw;
-        uint32_t emc_trpab;
-        uint32_t emc_tclkstable;
-        uint32_t emc_tclkstop;
-        uint32_t emc_mrw7;
-        uint32_t emc_trefbw;
-        uint32_t emc_odt_write;
-        uint32_t emc_fbio_cfg5;
-        uint32_t emc_fbio_cfg7;
-        uint32_t emc_cfg_dig_dll;
-        uint32_t emc_cfg_dig_dll_period;
-        uint32_t emc_pmacro_ib_rxrt;
-        uint32_t emc_cfg_pipe_1;
-        uint32_t emc_cfg_pipe_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_4;
-        uint32_t emc_pmacro_quse_ddll_rank0_5;
-        uint32_t emc_pmacro_quse_ddll_rank1_4;
-        uint32_t emc_pmacro_quse_ddll_rank1_5;
-        uint32_t emc_mrw8;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
-        uint32_t emc_pmacro_ddll_long_cmd_0;
-        uint32_t emc_pmacro_ddll_long_cmd_1;
-        uint32_t emc_pmacro_ddll_long_cmd_2;
-        uint32_t emc_pmacro_ddll_long_cmd_3;
-        uint32_t emc_pmacro_ddll_long_cmd_4;
-        uint32_t emc_pmacro_ddll_short_cmd_0;
-        uint32_t emc_pmacro_ddll_short_cmd_1;
-        uint32_t emc_pmacro_ddll_short_cmd_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
-        uint32_t emc_txdsrvttgen;
-        uint32_t emc_fdpd_ctrl_dq;
-        uint32_t emc_fdpd_ctrl_cmd;
-        uint32_t emc_fbio_spare;
-        uint32_t emc_zcal_interval;
-        uint32_t emc_zcal_wait_cnt;
-        uint32_t emc_mrs_wait_cnt;
-        uint32_t emc_mrs_wait_cnt2;
-        uint32_t emc_auto_cal_channel;
-        uint32_t emc_dll_cfg_0;
-        uint32_t emc_dll_cfg_1;
-        uint32_t emc_pmacro_autocal_cfg_common;
-        uint32_t emc_pmacro_zctrl;
-        uint32_t emc_cfg;
-        uint32_t emc_cfg_pipe;
-        uint32_t emc_dyn_self_ref_control;
-        uint32_t emc_qpop;
-        uint32_t emc_dqs_brlshft_0;
-        uint32_t emc_dqs_brlshft_1;
-        uint32_t emc_cmd_brlshft_2;
-        uint32_t emc_cmd_brlshft_3;
-        uint32_t emc_pmacro_pad_cfg_ctrl;
-        uint32_t emc_pmacro_data_pad_rx_ctrl;
-        uint32_t emc_pmacro_cmd_pad_rx_ctrl;
-        uint32_t emc_pmacro_data_rx_term_mode;
-        uint32_t emc_pmacro_cmd_rx_term_mode;
-        uint32_t emc_pmacro_cmd_pad_tx_ctrl;
-        uint32_t emc_pmacro_data_pad_tx_ctrl;
-        uint32_t emc_pmacro_common_pad_tx_ctrl;
-        uint32_t emc_pmacro_vttgen_ctrl_0;
-        uint32_t emc_pmacro_vttgen_ctrl_1;
-        uint32_t emc_pmacro_vttgen_ctrl_2;
-        uint32_t emc_pmacro_brick_ctrl_rfu1;
-        uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_brick_ctrl_rfu2;
-        uint32_t emc_pmacro_data_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_bg_bias_ctrl_0;
-        uint32_t emc_cfg_3;
-        uint32_t emc_pmacro_tx_pwrd_0;
-        uint32_t emc_pmacro_tx_pwrd_1;
-        uint32_t emc_pmacro_tx_pwrd_2;
-        uint32_t emc_pmacro_tx_pwrd_3;
-        uint32_t emc_pmacro_tx_pwrd_4;
-        uint32_t emc_pmacro_tx_pwrd_5;
-        uint32_t emc_config_sample_delay;
-        uint32_t emc_pmacro_tx_sel_clk_src_0;
-        uint32_t emc_pmacro_tx_sel_clk_src_1;
-        uint32_t emc_pmacro_tx_sel_clk_src_2;
-        uint32_t emc_pmacro_tx_sel_clk_src_3;
-        uint32_t emc_pmacro_tx_sel_clk_src_4;
-        uint32_t emc_pmacro_tx_sel_clk_src_5;
-        uint32_t emc_pmacro_ddll_bypass;
-        uint32_t emc_pmacro_ddll_pwrd_0;
-        uint32_t emc_pmacro_ddll_pwrd_1;
-        uint32_t emc_pmacro_ddll_pwrd_2;
-        uint32_t emc_pmacro_cmd_ctrl_0;
-        uint32_t emc_pmacro_cmd_ctrl_1;
-        uint32_t emc_pmacro_cmd_ctrl_2;
-        uint32_t emc_tr_timing_0;
-        uint32_t emc_tr_dvfs;
-        uint32_t emc_tr_ctrl_1;
-        uint32_t emc_tr_rdv;
-        uint32_t emc_tr_qpop;
-        uint32_t emc_tr_rdv_mask;
-        uint32_t emc_mrw14;
-        uint32_t emc_tr_qsafe;
-        uint32_t emc_tr_qrst;
-        uint32_t emc_training_ctrl;
-        uint32_t emc_training_settle;
-        uint32_t emc_training_vref_settle;
-        uint32_t emc_training_ca_fine_ctrl;
-        uint32_t emc_training_ca_ctrl_misc;
-        uint32_t emc_training_ca_ctrl_misc1;
-        uint32_t emc_training_ca_vref_ctrl;
-        uint32_t emc_training_quse_cors_ctrl;
-        uint32_t emc_training_quse_fine_ctrl;
-        uint32_t emc_training_quse_ctrl_misc;
-        uint32_t emc_training_quse_vref_ctrl;
-        uint32_t emc_training_read_fine_ctrl;
-        uint32_t emc_training_read_ctrl_misc;
-        uint32_t emc_training_read_vref_ctrl;
-        uint32_t emc_training_write_fine_ctrl;
-        uint32_t emc_training_write_ctrl_misc;
-        uint32_t emc_training_write_vref_ctrl;
-        uint32_t emc_training_mpc;
-        uint32_t emc_mrw15;
-    }
-    burst_regs;
-
-    struct {
-        uint32_t emc0_mrw10;
-        uint32_t emc1_mrw10;
-        uint32_t emc0_mrw11;
-        uint32_t emc1_mrw11;
-        uint32_t emc0_mrw12;
-        uint32_t emc1_mrw12;
-        uint32_t emc0_mrw13;
-        uint32_t emc1_mrw13;
-    }
-    burst_perch_regs;
-
-    struct {
-        uint32_t emc_rc;
-        uint32_t emc_rfc;
-        uint32_t emc_rfcpb;
-        uint32_t emc_refctrl2;
-        uint32_t emc_rfc_slr;
-        uint32_t emc_ras;
-        uint32_t emc_rp;
-        uint32_t emc_r2w;
-        uint32_t emc_w2r;
-        uint32_t emc_r2p;
-        uint32_t emc_w2p;
-        uint32_t emc_r2r;
-        uint32_t emc_tppd;
-        uint32_t emc_ccdmw;
-        uint32_t emc_rd_rcd;
-        uint32_t emc_wr_rcd;
-        uint32_t emc_rrd;
-        uint32_t emc_rext;
-        uint32_t emc_wext;
-        uint32_t emc_wdv_chk;
-        uint32_t emc_wdv;
-        uint32_t emc_wsv;
-        uint32_t emc_wev;
-        uint32_t emc_wdv_mask;
-        uint32_t emc_ws_duration;
-        uint32_t emc_we_duration;
-        uint32_t emc_quse;
-        uint32_t emc_quse_width;
-        uint32_t emc_ibdly;
-        uint32_t emc_obdly;
-        uint32_t emc_einput;
-        uint32_t emc_mrw6;
-        uint32_t emc_einput_duration;
-        uint32_t emc_puterm_extra;
-        uint32_t emc_puterm_width;
-        uint32_t emc_qrst;
-        uint32_t emc_qsafe;
-        uint32_t emc_rdv;
-        uint32_t emc_rdv_mask;
-        uint32_t emc_rdv_early;
-        uint32_t emc_rdv_early_mask;
-        uint32_t emc_refresh;
-        uint32_t emc_burst_refresh_num;
-        uint32_t emc_pre_refresh_req_cnt;
-        uint32_t emc_pdex2wr;
-        uint32_t emc_pdex2rd;
-        uint32_t emc_pchg2pden;
-        uint32_t emc_act2pden;
-        uint32_t emc_ar2pden;
-        uint32_t emc_rw2pden;
-        uint32_t emc_cke2pden;
-        uint32_t emc_pdex2cke;
-        uint32_t emc_pdex2mrr;
-        uint32_t emc_txsr;
-        uint32_t emc_txsrdll;
-        uint32_t emc_tcke;
-        uint32_t emc_tckesr;
-        uint32_t emc_tpd;
-        uint32_t emc_tfaw;
-        uint32_t emc_trpab;
-        uint32_t emc_tclkstable;
-        uint32_t emc_tclkstop;
-        uint32_t emc_mrw7;
-        uint32_t emc_trefbw;
-        uint32_t emc_odt_write;
-        uint32_t emc_fbio_cfg5;
-        uint32_t emc_fbio_cfg7;
-        uint32_t emc_cfg_dig_dll;
-        uint32_t emc_cfg_dig_dll_period;
-        uint32_t emc_pmacro_ib_rxrt;
-        uint32_t emc_cfg_pipe_1;
-        uint32_t emc_cfg_pipe_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_4;
-        uint32_t emc_pmacro_quse_ddll_rank0_5;
-        uint32_t emc_pmacro_quse_ddll_rank1_4;
-        uint32_t emc_pmacro_quse_ddll_rank1_5;
-        uint32_t emc_mrw8;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
-        uint32_t emc_pmacro_ddll_long_cmd_0;
-        uint32_t emc_pmacro_ddll_long_cmd_1;
-        uint32_t emc_pmacro_ddll_long_cmd_2;
-        uint32_t emc_pmacro_ddll_long_cmd_3;
-        uint32_t emc_pmacro_ddll_long_cmd_4;
-        uint32_t emc_pmacro_ddll_short_cmd_0;
-        uint32_t emc_pmacro_ddll_short_cmd_1;
-        uint32_t emc_pmacro_ddll_short_cmd_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
-        uint32_t emc_txdsrvttgen;
-        uint32_t emc_fdpd_ctrl_dq;
-        uint32_t emc_fdpd_ctrl_cmd;
-        uint32_t emc_fbio_spare;
-        uint32_t emc_zcal_interval;
-        uint32_t emc_zcal_wait_cnt;
-        uint32_t emc_mrs_wait_cnt;
-        uint32_t emc_mrs_wait_cnt2;
-        uint32_t emc_auto_cal_channel;
-        uint32_t emc_dll_cfg_0;
-        uint32_t emc_dll_cfg_1;
-        uint32_t emc_pmacro_autocal_cfg_common;
-        uint32_t emc_pmacro_zctrl;
-        uint32_t emc_cfg;
-        uint32_t emc_cfg_pipe;
-        uint32_t emc_dyn_self_ref_control;
-        uint32_t emc_qpop;
-        uint32_t emc_dqs_brlshft_0;
-        uint32_t emc_dqs_brlshft_1;
-        uint32_t emc_cmd_brlshft_2;
-        uint32_t emc_cmd_brlshft_3;
-        uint32_t emc_pmacro_pad_cfg_ctrl;
-        uint32_t emc_pmacro_data_pad_rx_ctrl;
-        uint32_t emc_pmacro_cmd_pad_rx_ctrl;
-        uint32_t emc_pmacro_data_rx_term_mode;
-        uint32_t emc_pmacro_cmd_rx_term_mode;
-        uint32_t emc_pmacro_cmd_pad_tx_ctrl;
-        uint32_t emc_pmacro_data_pad_tx_ctrl;
-        uint32_t emc_pmacro_common_pad_tx_ctrl;
-        uint32_t emc_pmacro_vttgen_ctrl_0;
-        uint32_t emc_pmacro_vttgen_ctrl_1;
-        uint32_t emc_pmacro_vttgen_ctrl_2;
-        uint32_t emc_pmacro_brick_ctrl_rfu1;
-        uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_brick_ctrl_rfu2;
-        uint32_t emc_pmacro_data_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_bg_bias_ctrl_0;
-        uint32_t emc_cfg_3;
-        uint32_t emc_pmacro_tx_pwrd_0;
-        uint32_t emc_pmacro_tx_pwrd_1;
-        uint32_t emc_pmacro_tx_pwrd_2;
-        uint32_t emc_pmacro_tx_pwrd_3;
-        uint32_t emc_pmacro_tx_pwrd_4;
-        uint32_t emc_pmacro_tx_pwrd_5;
-        uint32_t emc_config_sample_delay;
-        uint32_t emc_pmacro_tx_sel_clk_src_0;
-        uint32_t emc_pmacro_tx_sel_clk_src_1;
-        uint32_t emc_pmacro_tx_sel_clk_src_2;
-        uint32_t emc_pmacro_tx_sel_clk_src_3;
-        uint32_t emc_pmacro_tx_sel_clk_src_4;
-        uint32_t emc_pmacro_tx_sel_clk_src_5;
-        uint32_t emc_pmacro_ddll_bypass;
-        uint32_t emc_pmacro_ddll_pwrd_0;
-        uint32_t emc_pmacro_ddll_pwrd_1;
-        uint32_t emc_pmacro_ddll_pwrd_2;
-        uint32_t emc_pmacro_cmd_ctrl_0;
-        uint32_t emc_pmacro_cmd_ctrl_1;
-        uint32_t emc_pmacro_cmd_ctrl_2;
-        uint32_t emc_tr_timing_0;
-        uint32_t emc_tr_dvfs;
-        uint32_t emc_tr_ctrl_1;
-        uint32_t emc_tr_rdv;
-        uint32_t emc_tr_qpop;
-        uint32_t emc_tr_rdv_mask;
-        uint32_t emc_mrw14;
-        uint32_t emc_tr_qsafe;
-        uint32_t emc_tr_qrst;
-        uint32_t emc_training_ctrl;
-        uint32_t emc_training_settle;
-        uint32_t emc_training_vref_settle;
-        uint32_t emc_training_ca_fine_ctrl;
-        uint32_t emc_training_ca_ctrl_misc;
-        uint32_t emc_training_ca_ctrl_misc1;
-        uint32_t emc_training_ca_vref_ctrl;
-        uint32_t emc_training_quse_cors_ctrl;
-        uint32_t emc_training_quse_fine_ctrl;
-        uint32_t emc_training_quse_ctrl_misc;
-        uint32_t emc_training_quse_vref_ctrl;
-        uint32_t emc_training_read_fine_ctrl;
-        uint32_t emc_training_read_ctrl_misc;
-        uint32_t emc_training_read_vref_ctrl;
-        uint32_t emc_training_write_fine_ctrl;
-        uint32_t emc_training_write_ctrl_misc;
-        uint32_t emc_training_write_vref_ctrl;
-        uint32_t emc_training_mpc;
-        uint32_t emc_mrw15;
-    }
-    shadow_regs_ca_train;
-
-    struct {
-        uint32_t emc_rc;
-        uint32_t emc_rfc;
-        uint32_t emc_rfcpb;
-        uint32_t emc_refctrl2;
-        uint32_t emc_rfc_slr;
-        uint32_t emc_ras;
-        uint32_t emc_rp;
-        uint32_t emc_r2w;
-        uint32_t emc_w2r;
-        uint32_t emc_r2p;
-        uint32_t emc_w2p;
-        uint32_t emc_r2r;
-        uint32_t emc_tppd;
-        uint32_t emc_ccdmw;
-        uint32_t emc_rd_rcd;
-        uint32_t emc_wr_rcd;
-        uint32_t emc_rrd;
-        uint32_t emc_rext;
-        uint32_t emc_wext;
-        uint32_t emc_wdv_chk;
-        uint32_t emc_wdv;
-        uint32_t emc_wsv;
-        uint32_t emc_wev;
-        uint32_t emc_wdv_mask;
-        uint32_t emc_ws_duration;
-        uint32_t emc_we_duration;
-        uint32_t emc_quse;
-        uint32_t emc_quse_width;
-        uint32_t emc_ibdly;
-        uint32_t emc_obdly;
-        uint32_t emc_einput;
-        uint32_t emc_mrw6;
-        uint32_t emc_einput_duration;
-        uint32_t emc_puterm_extra;
-        uint32_t emc_puterm_width;
-        uint32_t emc_qrst;
-        uint32_t emc_qsafe;
-        uint32_t emc_rdv;
-        uint32_t emc_rdv_mask;
-        uint32_t emc_rdv_early;
-        uint32_t emc_rdv_early_mask;
-        uint32_t emc_refresh;
-        uint32_t emc_burst_refresh_num;
-        uint32_t emc_pre_refresh_req_cnt;
-        uint32_t emc_pdex2wr;
-        uint32_t emc_pdex2rd;
-        uint32_t emc_pchg2pden;
-        uint32_t emc_act2pden;
-        uint32_t emc_ar2pden;
-        uint32_t emc_rw2pden;
-        uint32_t emc_cke2pden;
-        uint32_t emc_pdex2cke;
-        uint32_t emc_pdex2mrr;
-        uint32_t emc_txsr;
-        uint32_t emc_txsrdll;
-        uint32_t emc_tcke;
-        uint32_t emc_tckesr;
-        uint32_t emc_tpd;
-        uint32_t emc_tfaw;
-        uint32_t emc_trpab;
-        uint32_t emc_tclkstable;
-        uint32_t emc_tclkstop;
-        uint32_t emc_mrw7;
-        uint32_t emc_trefbw;
-        uint32_t emc_odt_write;
-        uint32_t emc_fbio_cfg5;
-        uint32_t emc_fbio_cfg7;
-        uint32_t emc_cfg_dig_dll;
-        uint32_t emc_cfg_dig_dll_period;
-        uint32_t emc_pmacro_ib_rxrt;
-        uint32_t emc_cfg_pipe_1;
-        uint32_t emc_cfg_pipe_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_4;
-        uint32_t emc_pmacro_quse_ddll_rank0_5;
-        uint32_t emc_pmacro_quse_ddll_rank1_4;
-        uint32_t emc_pmacro_quse_ddll_rank1_5;
-        uint32_t emc_mrw8;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
-        uint32_t emc_pmacro_ddll_long_cmd_0;
-        uint32_t emc_pmacro_ddll_long_cmd_1;
-        uint32_t emc_pmacro_ddll_long_cmd_2;
-        uint32_t emc_pmacro_ddll_long_cmd_3;
-        uint32_t emc_pmacro_ddll_long_cmd_4;
-        uint32_t emc_pmacro_ddll_short_cmd_0;
-        uint32_t emc_pmacro_ddll_short_cmd_1;
-        uint32_t emc_pmacro_ddll_short_cmd_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
-        uint32_t emc_txdsrvttgen;
-        uint32_t emc_fdpd_ctrl_dq;
-        uint32_t emc_fdpd_ctrl_cmd;
-        uint32_t emc_fbio_spare;
-        uint32_t emc_zcal_interval;
-        uint32_t emc_zcal_wait_cnt;
-        uint32_t emc_mrs_wait_cnt;
-        uint32_t emc_mrs_wait_cnt2;
-        uint32_t emc_auto_cal_channel;
-        uint32_t emc_dll_cfg_0;
-        uint32_t emc_dll_cfg_1;
-        uint32_t emc_pmacro_autocal_cfg_common;
-        uint32_t emc_pmacro_zctrl;
-        uint32_t emc_cfg;
-        uint32_t emc_cfg_pipe;
-        uint32_t emc_dyn_self_ref_control;
-        uint32_t emc_qpop;
-        uint32_t emc_dqs_brlshft_0;
-        uint32_t emc_dqs_brlshft_1;
-        uint32_t emc_cmd_brlshft_2;
-        uint32_t emc_cmd_brlshft_3;
-        uint32_t emc_pmacro_pad_cfg_ctrl;
-        uint32_t emc_pmacro_data_pad_rx_ctrl;
-        uint32_t emc_pmacro_cmd_pad_rx_ctrl;
-        uint32_t emc_pmacro_data_rx_term_mode;
-        uint32_t emc_pmacro_cmd_rx_term_mode;
-        uint32_t emc_pmacro_cmd_pad_tx_ctrl;
-        uint32_t emc_pmacro_data_pad_tx_ctrl;
-        uint32_t emc_pmacro_common_pad_tx_ctrl;
-        uint32_t emc_pmacro_vttgen_ctrl_0;
-        uint32_t emc_pmacro_vttgen_ctrl_1;
-        uint32_t emc_pmacro_vttgen_ctrl_2;
-        uint32_t emc_pmacro_brick_ctrl_rfu1;
-        uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_brick_ctrl_rfu2;
-        uint32_t emc_pmacro_data_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_bg_bias_ctrl_0;
-        uint32_t emc_cfg_3;
-        uint32_t emc_pmacro_tx_pwrd_0;
-        uint32_t emc_pmacro_tx_pwrd_1;
-        uint32_t emc_pmacro_tx_pwrd_2;
-        uint32_t emc_pmacro_tx_pwrd_3;
-        uint32_t emc_pmacro_tx_pwrd_4;
-        uint32_t emc_pmacro_tx_pwrd_5;
-        uint32_t emc_config_sample_delay;
-        uint32_t emc_pmacro_tx_sel_clk_src_0;
-        uint32_t emc_pmacro_tx_sel_clk_src_1;
-        uint32_t emc_pmacro_tx_sel_clk_src_2;
-        uint32_t emc_pmacro_tx_sel_clk_src_3;
-        uint32_t emc_pmacro_tx_sel_clk_src_4;
-        uint32_t emc_pmacro_tx_sel_clk_src_5;
-        uint32_t emc_pmacro_ddll_bypass;
-        uint32_t emc_pmacro_ddll_pwrd_0;
-        uint32_t emc_pmacro_ddll_pwrd_1;
-        uint32_t emc_pmacro_ddll_pwrd_2;
-        uint32_t emc_pmacro_cmd_ctrl_0;
-        uint32_t emc_pmacro_cmd_ctrl_1;
-        uint32_t emc_pmacro_cmd_ctrl_2;
-        uint32_t emc_tr_timing_0;
-        uint32_t emc_tr_dvfs;
-        uint32_t emc_tr_ctrl_1;
-        uint32_t emc_tr_rdv;
-        uint32_t emc_tr_qpop;
-        uint32_t emc_tr_rdv_mask;
-        uint32_t emc_mrw14;
-        uint32_t emc_tr_qsafe;
-        uint32_t emc_tr_qrst;
-        uint32_t emc_training_ctrl;
-        uint32_t emc_training_settle;
-        uint32_t emc_training_vref_settle;
-        uint32_t emc_training_ca_fine_ctrl;
-        uint32_t emc_training_ca_ctrl_misc;
-        uint32_t emc_training_ca_ctrl_misc1;
-        uint32_t emc_training_ca_vref_ctrl;
-        uint32_t emc_training_quse_cors_ctrl;
-        uint32_t emc_training_quse_fine_ctrl;
-        uint32_t emc_training_quse_ctrl_misc;
-        uint32_t emc_training_quse_vref_ctrl;
-        uint32_t emc_training_read_fine_ctrl;
-        uint32_t emc_training_read_ctrl_misc;
-        uint32_t emc_training_read_vref_ctrl;
-        uint32_t emc_training_write_fine_ctrl;
-        uint32_t emc_training_write_ctrl_misc;
-        uint32_t emc_training_write_vref_ctrl;
-        uint32_t emc_training_mpc;
-        uint32_t emc_mrw15;
-    }
-    shadow_regs_quse_train;
-
-    struct {
-        uint32_t emc_rc;
-        uint32_t emc_rfc;
-        uint32_t emc_rfcpb;
-        uint32_t emc_refctrl2;
-        uint32_t emc_rfc_slr;
-        uint32_t emc_ras;
-        uint32_t emc_rp;
-        uint32_t emc_r2w;
-        uint32_t emc_w2r;
-        uint32_t emc_r2p;
-        uint32_t emc_w2p;
-        uint32_t emc_r2r;
-        uint32_t emc_tppd;
-        uint32_t emc_ccdmw;
-        uint32_t emc_rd_rcd;
-        uint32_t emc_wr_rcd;
-        uint32_t emc_rrd;
-        uint32_t emc_rext;
-        uint32_t emc_wext;
-        uint32_t emc_wdv_chk;
-        uint32_t emc_wdv;
-        uint32_t emc_wsv;
-        uint32_t emc_wev;
-        uint32_t emc_wdv_mask;
-        uint32_t emc_ws_duration;
-        uint32_t emc_we_duration;
-        uint32_t emc_quse;
-        uint32_t emc_quse_width;
-        uint32_t emc_ibdly;
-        uint32_t emc_obdly;
-        uint32_t emc_einput;
-        uint32_t emc_mrw6;
-        uint32_t emc_einput_duration;
-        uint32_t emc_puterm_extra;
-        uint32_t emc_puterm_width;
-        uint32_t emc_qrst;
-        uint32_t emc_qsafe;
-        uint32_t emc_rdv;
-        uint32_t emc_rdv_mask;
-        uint32_t emc_rdv_early;
-        uint32_t emc_rdv_early_mask;
-        uint32_t emc_refresh;
-        uint32_t emc_burst_refresh_num;
-        uint32_t emc_pre_refresh_req_cnt;
-        uint32_t emc_pdex2wr;
-        uint32_t emc_pdex2rd;
-        uint32_t emc_pchg2pden;
-        uint32_t emc_act2pden;
-        uint32_t emc_ar2pden;
-        uint32_t emc_rw2pden;
-        uint32_t emc_cke2pden;
-        uint32_t emc_pdex2cke;
-        uint32_t emc_pdex2mrr;
-        uint32_t emc_txsr;
-        uint32_t emc_txsrdll;
-        uint32_t emc_tcke;
-        uint32_t emc_tckesr;
-        uint32_t emc_tpd;
-        uint32_t emc_tfaw;
-        uint32_t emc_trpab;
-        uint32_t emc_tclkstable;
-        uint32_t emc_tclkstop;
-        uint32_t emc_mrw7;
-        uint32_t emc_trefbw;
-        uint32_t emc_odt_write;
-        uint32_t emc_fbio_cfg5;
-        uint32_t emc_fbio_cfg7;
-        uint32_t emc_cfg_dig_dll;
-        uint32_t emc_cfg_dig_dll_period;
-        uint32_t emc_pmacro_ib_rxrt;
-        uint32_t emc_cfg_pipe_1;
-        uint32_t emc_cfg_pipe_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_4;
-        uint32_t emc_pmacro_quse_ddll_rank0_5;
-        uint32_t emc_pmacro_quse_ddll_rank1_4;
-        uint32_t emc_pmacro_quse_ddll_rank1_5;
-        uint32_t emc_mrw8;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
-        uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
-        uint32_t emc_pmacro_ddll_long_cmd_0;
-        uint32_t emc_pmacro_ddll_long_cmd_1;
-        uint32_t emc_pmacro_ddll_long_cmd_2;
-        uint32_t emc_pmacro_ddll_long_cmd_3;
-        uint32_t emc_pmacro_ddll_long_cmd_4;
-        uint32_t emc_pmacro_ddll_short_cmd_0;
-        uint32_t emc_pmacro_ddll_short_cmd_1;
-        uint32_t emc_pmacro_ddll_short_cmd_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
-        uint32_t emc_txdsrvttgen;
-        uint32_t emc_fdpd_ctrl_dq;
-        uint32_t emc_fdpd_ctrl_cmd;
-        uint32_t emc_fbio_spare;
-        uint32_t emc_zcal_interval;
-        uint32_t emc_zcal_wait_cnt;
-        uint32_t emc_mrs_wait_cnt;
-        uint32_t emc_mrs_wait_cnt2;
-        uint32_t emc_auto_cal_channel;
-        uint32_t emc_dll_cfg_0;
-        uint32_t emc_dll_cfg_1;
-        uint32_t emc_pmacro_autocal_cfg_common;
-        uint32_t emc_pmacro_zctrl;
-        uint32_t emc_cfg;
-        uint32_t emc_cfg_pipe;
-        uint32_t emc_dyn_self_ref_control;
-        uint32_t emc_qpop;
-        uint32_t emc_dqs_brlshft_0;
-        uint32_t emc_dqs_brlshft_1;
-        uint32_t emc_cmd_brlshft_2;
-        uint32_t emc_cmd_brlshft_3;
-        uint32_t emc_pmacro_pad_cfg_ctrl;
-        uint32_t emc_pmacro_data_pad_rx_ctrl;
-        uint32_t emc_pmacro_cmd_pad_rx_ctrl;
-        uint32_t emc_pmacro_data_rx_term_mode;
-        uint32_t emc_pmacro_cmd_rx_term_mode;
-        uint32_t emc_pmacro_cmd_pad_tx_ctrl;
-        uint32_t emc_pmacro_data_pad_tx_ctrl;
-        uint32_t emc_pmacro_common_pad_tx_ctrl;
-        uint32_t emc_pmacro_vttgen_ctrl_0;
-        uint32_t emc_pmacro_vttgen_ctrl_1;
-        uint32_t emc_pmacro_vttgen_ctrl_2;
-        uint32_t emc_pmacro_brick_ctrl_rfu1;
-        uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_brick_ctrl_rfu2;
-        uint32_t emc_pmacro_data_brick_ctrl_fdpd;
-        uint32_t emc_pmacro_bg_bias_ctrl_0;
-        uint32_t emc_cfg_3;
-        uint32_t emc_pmacro_tx_pwrd_0;
-        uint32_t emc_pmacro_tx_pwrd_1;
-        uint32_t emc_pmacro_tx_pwrd_2;
-        uint32_t emc_pmacro_tx_pwrd_3;
-        uint32_t emc_pmacro_tx_pwrd_4;
-        uint32_t emc_pmacro_tx_pwrd_5;
-        uint32_t emc_config_sample_delay;
-        uint32_t emc_pmacro_tx_sel_clk_src_0;
-        uint32_t emc_pmacro_tx_sel_clk_src_1;
-        uint32_t emc_pmacro_tx_sel_clk_src_2;
-        uint32_t emc_pmacro_tx_sel_clk_src_3;
-        uint32_t emc_pmacro_tx_sel_clk_src_4;
-        uint32_t emc_pmacro_tx_sel_clk_src_5;
-        uint32_t emc_pmacro_ddll_bypass;
-        uint32_t emc_pmacro_ddll_pwrd_0;
-        uint32_t emc_pmacro_ddll_pwrd_1;
-        uint32_t emc_pmacro_ddll_pwrd_2;
-        uint32_t emc_pmacro_cmd_ctrl_0;
-        uint32_t emc_pmacro_cmd_ctrl_1;
-        uint32_t emc_pmacro_cmd_ctrl_2;
-        uint32_t emc_tr_timing_0;
-        uint32_t emc_tr_dvfs;
-        uint32_t emc_tr_ctrl_1;
-        uint32_t emc_tr_rdv;
-        uint32_t emc_tr_qpop;
-        uint32_t emc_tr_rdv_mask;
-        uint32_t emc_mrw14;
-        uint32_t emc_tr_qsafe;
-        uint32_t emc_tr_qrst;
-        uint32_t emc_training_ctrl;
-        uint32_t emc_training_settle;
-        uint32_t emc_training_vref_settle;
-        uint32_t emc_training_ca_fine_ctrl;
-        uint32_t emc_training_ca_ctrl_misc;
-        uint32_t emc_training_ca_ctrl_misc1;
-        uint32_t emc_training_ca_vref_ctrl;
-        uint32_t emc_training_quse_cors_ctrl;
-        uint32_t emc_training_quse_fine_ctrl;
-        uint32_t emc_training_quse_ctrl_misc;
-        uint32_t emc_training_quse_vref_ctrl;
-        uint32_t emc_training_read_fine_ctrl;
-        uint32_t emc_training_read_ctrl_misc;
-        uint32_t emc_training_read_vref_ctrl;
-        uint32_t emc_training_write_fine_ctrl;
-        uint32_t emc_training_write_ctrl_misc;
-        uint32_t emc_training_write_vref_ctrl;
-        uint32_t emc_training_mpc;
-        uint32_t emc_mrw15;
-    }
-    shadow_regs_rdwr_train;
-
-    struct {
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
-        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;
-        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;
-        uint32_t emc_pmacro_ib_vref_dqs_0;
-        uint32_t emc_pmacro_ib_vref_dqs_1;
-        uint32_t emc_pmacro_ib_vref_dq_0;
-        uint32_t emc_pmacro_ib_vref_dq_1;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
-        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_2;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_0;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_1;
-        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_0;
-        uint32_t emc_pmacro_quse_ddll_rank0_1;
-        uint32_t emc_pmacro_quse_ddll_rank0_2;
-        uint32_t emc_pmacro_quse_ddll_rank0_3;
-        uint32_t emc_pmacro_quse_ddll_rank1_0;
-        uint32_t emc_pmacro_quse_ddll_rank1_1;
-        uint32_t emc_pmacro_quse_ddll_rank1_2;
-        uint32_t emc_pmacro_quse_ddll_rank1_3;
-    }
-    trim_regs;
-
-    struct {
-        uint32_t emc0_cmd_brlshft_0;
-        uint32_t emc1_cmd_brlshft_1;
-        uint32_t emc0_data_brlshft_0;
-        uint32_t emc1_data_brlshft_0;
-        uint32_t emc0_data_brlshft_1;
-        uint32_t emc1_data_brlshft_1;
-        uint32_t emc0_quse_brlshft_0;
-        uint32_t emc1_quse_brlshft_1;
-        uint32_t emc0_quse_brlshft_2;
-        uint32_t emc1_quse_brlshft_3;
-    }
-    trim_perch_regs;
-
-    struct {
-        uint32_t emc0_training_opt_dqs_ib_vref_rank0;
-        uint32_t emc1_training_opt_dqs_ib_vref_rank0;
-        uint32_t emc0_training_opt_dqs_ib_vref_rank1;
-        uint32_t emc1_training_opt_dqs_ib_vref_rank1;
-    }
-    vref_perch_regs;
-
-    struct {
-        uint32_t t_rp;
-        uint32_t t_fc_lpddr4;
-        uint32_t t_rfc;
-        uint32_t t_pdex;
-        uint32_t rl;
-    }
-    dram_timings;
-
-    struct {
-        uint32_t emc0_training_rw_offset_ib_byte0;
-        uint32_t emc1_training_rw_offset_ib_byte0;
-        uint32_t emc0_training_rw_offset_ib_byte1;
-        uint32_t emc1_training_rw_offset_ib_byte1;
-        uint32_t emc0_training_rw_offset_ib_byte2;
-        uint32_t emc1_training_rw_offset_ib_byte2;
-        uint32_t emc0_training_rw_offset_ib_byte3;
-        uint32_t emc1_training_rw_offset_ib_byte3;
-        uint32_t emc0_training_rw_offset_ib_misc;
-        uint32_t emc1_training_rw_offset_ib_misc;
-        uint32_t emc0_training_rw_offset_ob_byte0;
-        uint32_t emc1_training_rw_offset_ob_byte0;
-        uint32_t emc0_training_rw_offset_ob_byte1;
-        uint32_t emc1_training_rw_offset_ob_byte1;
-        uint32_t emc0_training_rw_offset_ob_byte2;
-        uint32_t emc1_training_rw_offset_ob_byte2;
-        uint32_t emc0_training_rw_offset_ob_byte3;
-        uint32_t emc1_training_rw_offset_ob_byte3;
-        uint32_t emc0_training_rw_offset_ob_misc;
-        uint32_t emc1_training_rw_offset_ob_misc;
-    }
-    training_mod_regs;
-
-    uint32_t save_restore_mod_regs[12];
-
-    struct {
-        uint32_t mc_emem_arb_cfg;
-        uint32_t mc_emem_arb_outstanding_req;
-        uint32_t mc_emem_arb_refpb_hp_ctrl;
-        uint32_t mc_emem_arb_refpb_bank_ctrl;
-        uint32_t mc_emem_arb_timing_rcd;
-        uint32_t mc_emem_arb_timing_rp;
-        uint32_t mc_emem_arb_timing_rc;
-        uint32_t mc_emem_arb_timing_ras;
-        uint32_t mc_emem_arb_timing_faw;
-        uint32_t mc_emem_arb_timing_rrd;
-        uint32_t mc_emem_arb_timing_rap2pre;
-        uint32_t mc_emem_arb_timing_wap2pre;
-        uint32_t mc_emem_arb_timing_r2r;
-        uint32_t mc_emem_arb_timing_w2w;
-        uint32_t mc_emem_arb_timing_r2w;
-        uint32_t mc_emem_arb_timing_ccdmw;
-        uint32_t mc_emem_arb_timing_w2r;
-        uint32_t mc_emem_arb_timing_rfcpb;
-        uint32_t mc_emem_arb_da_turns;
-        uint32_t mc_emem_arb_da_covers;
-        uint32_t mc_emem_arb_misc0;
-        uint32_t mc_emem_arb_misc1;
-        uint32_t mc_emem_arb_misc2;
-        uint32_t mc_emem_arb_ring1_throttle;
-        uint32_t mc_emem_arb_dhyst_ctrl;
-        uint32_t mc_emem_arb_dhyst_timeout_util_0;
-        uint32_t mc_emem_arb_dhyst_timeout_util_1;
-        uint32_t mc_emem_arb_dhyst_timeout_util_2;
-        uint32_t mc_emem_arb_dhyst_timeout_util_3;
-        uint32_t mc_emem_arb_dhyst_timeout_util_4;
-        uint32_t mc_emem_arb_dhyst_timeout_util_5;
-        uint32_t mc_emem_arb_dhyst_timeout_util_6;
-        uint32_t mc_emem_arb_dhyst_timeout_util_7;
-    }
-    burst_mc_regs;
-
-    struct {
-        uint32_t mc_mll_mpcorer_ptsa_rate;
-        uint32_t mc_ftop_ptsa_rate;
-        uint32_t mc_ptsa_grant_decrement;
-        uint32_t mc_latency_allowance_xusb_0;
-        uint32_t mc_latency_allowance_xusb_1;
-        uint32_t mc_latency_allowance_tsec_0;
-        uint32_t mc_latency_allowance_sdmmca_0;
-        uint32_t mc_latency_allowance_sdmmcaa_0;
-        uint32_t mc_latency_allowance_sdmmc_0;
-        uint32_t mc_latency_allowance_sdmmcab_0;
-        uint32_t mc_latency_allowance_ppcs_0;
-        uint32_t mc_latency_allowance_ppcs_1;
-        uint32_t mc_latency_allowance_mpcore_0;
-        uint32_t mc_latency_allowance_hc_0;
-        uint32_t mc_latency_allowance_hc_1;
-        uint32_t mc_latency_allowance_avpc_0;
-        uint32_t mc_latency_allowance_gpu_0;
-        uint32_t mc_latency_allowance_gpu2_0;
-        uint32_t mc_latency_allowance_nvenc_0;
-        uint32_t mc_latency_allowance_nvdec_0;
-        uint32_t mc_latency_allowance_vic_0;
-        uint32_t mc_latency_allowance_vi2_0;
-        uint32_t mc_latency_allowance_isp2_0;
-        uint32_t mc_latency_allowance_isp2_1;
-    }
-    la_scale_regs;
-
-    uint32_t min_mrs_wait;
-    uint32_t emc_mrw;
-    uint32_t emc_mrw2;
-    uint32_t emc_mrw3;
-    uint32_t emc_mrw4;
-    uint32_t emc_mrw9;
-    uint32_t emc_mrs;
-    uint32_t emc_emrs;
-    uint32_t emc_emrs2;
-    uint32_t emc_auto_cal_config;
-    uint32_t emc_auto_cal_config2;
-    uint32_t emc_auto_cal_config3;
-    uint32_t emc_auto_cal_config4;
-    uint32_t emc_auto_cal_config5;
-    uint32_t emc_auto_cal_config6;
-    uint32_t emc_auto_cal_config7;
-    uint32_t emc_auto_cal_config8;
-    uint32_t emc_cfg_2;
-    uint32_t emc_sel_dpd_ctrl;
-    uint32_t emc_fdpd_ctrl_cmd_no_ramp;
-    uint32_t dll_clk_src;
-    uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
-    uint32_t latency;
-};
-
-static_assert(sizeof(EristaMtcTable) == 0x1340);
diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/Makefile b/Source/Atmosphere/stratosphere/loader/source/oc/Makefile
new file mode 100644
index 00000000..428a28a4
--- /dev/null
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/Makefile
@@ -0,0 +1,9 @@
+export CC := g++-11
+
+all: test
+
+test:
+	$(CC) ldr_oc_suite.cpp test.cpp -o ./test -O2 -std=c++20 -DOC_TEST
+
+clean:
+	rm ./test
diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_customize.inc b/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_customize.inc
new file mode 100644
index 00000000..e74e9acc
--- /dev/null
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_customize.inc
@@ -0,0 +1,67 @@
+namespace ams::ldr::oc {
+#include "mtc_empty_table.inc"
+static const volatile CustomizeTable C = {
+/* DRAM Timing:
+ * AUTO_ADJ_MARIKO_SAFE: Auto adjust timings for LPDDR4 ≤3733 Mbps specs, 8Gb density (Default).
+ * AUTO_ADJ_MARIKO_4266: Auto adjust timings for LPDDR4X 4266 Mbps specs, 8Gb density.
+ * ENTIRE_TABLE_ERISTA/ENTIRE_TABLE_MARIKO:
+ *                       Replace the entire max mtc table with customized one.
+ */
+.mtcConf = AUTO_ADJ_MARIKO_SAFE,
+
+/* Mariko CPU:
+ * - Max Clock in kHz:
+ *   Default: 1785000
+ *   >= 2193000 will enable overvolting (> 1120 mV)
+ * - Max Voltage in mV:
+ *   Default voltage: 1120
+ *   Haven't tested anything higher than 1220.
+ */
+.marikoCpuMaxClock = 2397000,
+.marikoCpuMaxVolt  = 1220,
+
+/* Mariko GPU:
+ * - Max Clock in kHz:
+ *   Default: 921600
+ *   NVIDIA Maximum: 1267200
+ */
+.marikoGpuMaxClock = 1305600,
+
+/* Mariko EMC:
+ * - RAM Clock in kHz:
+ *   Values should be > 1600000, and divided evenly by 9600 or 12800.
+ *   [WARNING]
+ *   RAM overclock could be UNSTABLE if timing parameters are not suitable for your DRAM:
+ *   - Graphical glitches
+ *   - System instabilities
+ *   - NAND corruption
+ *   Timings from auto-adjustment have been tested safe for up to 1996.8 MHz for all DRAM chips.
+ */
+.marikoEmcMaxClock = 1996800,
+
+/* Erista CPU:
+ * Untested and not enabled by default.
+ * - Enable Overclock
+ *   Require modificaitions towards NewCpuTables!
+ * - Max Voltage in mV
+ */
+.eristaCpuOCEnable = 0,
+.eristaCpuMaxVolt  = 0,
+
+/* Erista EMC:
+ * - RAM Clock in kHz
+ *   [WARNING]
+ *   RAM overclock could be UNSTABLE if timing parameters are not suitable for your DRAM:
+ *   - Graphical glitches
+ *   - System instabilities
+ *   - NAND corruption
+ * - RAM Voltage in mV
+ *   Default(HOS): 1125
+ *   Not enabled by default.
+ */
+.eristaEmcMaxClock = 1862400,
+.eristaEmcVolt     = 0,
+
+.eristaMtc = reinterpret_cast<EristaMtcTable *>(const_cast<u8 *>(EmptyMtcTable)),
+};
+}
\ No newline at end of file
diff --git a/Source/Atmosphere/stratosphere/loader/source/ldr_oc_suite.cpp b/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite.cpp
similarity index 91%
rename from Source/Atmosphere/stratosphere/loader/source/ldr_oc_suite.cpp
rename to Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite.cpp
index 6744397d..5b4f583f 100644
--- a/Source/Atmosphere/stratosphere/loader/source/ldr_oc_suite.cpp
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite.cpp
@@ -15,76 +15,18 @@
  */
 
 //#define EXPERIMENTAL
+
+#ifdef OC_TEST
+#include "ldr_oc_suite_test.hpp"
+#else
 #include <stratosphere.hpp>
 #include "ldr_oc_suite.hpp"
+#include "ldr_oc_customize.inc"
+#endif
 
 namespace ams::ldr::oc {
-    /* Allocate CustomizeTable in loader.kip (could be customized by user without recompiling) */
-    static const volatile CustomizeTable C = {
-    /* DRAM Timing:
-     * AUTO_ADJ_MARIKO_SAFE: Auto adjust timings for LPDDR4 ≤3733 Mbps specs, 8Gb density (Default).
-     * AUTO_ADJ_MARIKO_4266: Auto adjust timings for LPDDR4X 4266 Mbps specs, 8Gb density.
-     * ENTIRE_TABLE_ERISTA/ENTIRE_TABLE_MARIKO:
-     *                       Replace the entire max mtc table with customized one.
-     */
-    .mtcConf = AUTO_ADJ_MARIKO_SAFE,
-
-    /* Mariko CPU:
-     * - Max Clock in kHz:
-     *   Default: 1785000
-     *   >= 2193000 will enable overvolting (> 1120 mV)
-     * - Max Voltage in mV:
-     *   Default voltage: 1120
-     *   Haven't tested anything higher than 1220.
-     */
-    .marikoCpuMaxClock = 2397000,
-    .marikoCpuMaxVolt  = 1220,
-
-    /* Mariko GPU:
-     * - Max Clock in kHz:
-     *   Default: 921600
-     *   NVIDIA Maximum: 1267200
-     */
-    .marikoGpuMaxClock = 1305600,
-
-    /* Mariko EMC:
-     * - RAM Clock in kHz:
-     *   Values should be > 1600000, and divided evenly by 9600 or 12800.
-     *   [WARNING]
-     *   RAM overclock could be UNSTABLE if timing parameters are not suitable for your DRAM:
-     *   - Graphical glitches
-     *   - System instabilities
-     *   - NAND corruption
-     *   Timings from auto-adjustment have been tested safe for up to 1996.8 MHz for all DRAM chips.
-     */
-    .marikoEmcMaxClock = 1996800,
-
-    /* Erista CPU:
-     * Untested and not enabled by default.
-     * - Enable Overclock
-     *   Require modificaitions towards NewCpuTables!
-     * - Max Voltage in mV
-     */
-    .eristaCpuOCEnable = 0,
-    .eristaCpuMaxVolt  = 0,
-
-    /* Erista EMC:
-     * - RAM Clock in kHz
-     *   [WARNING]
-     *   RAM overclock could be UNSTABLE if timing parameters are not suitable for your DRAM:
-     *   - Graphical glitches
-     *   - System instabilities
-     *   - NAND corruption
-     * - RAM Voltage in mV
-     *   Default(HOS): 1125
-     *   Not enabled by default.
-     */
-    .eristaEmcMaxClock = 1862400,
-    .eristaEmcVolt     = 0,
-    };
-
     namespace pcv {
-        static Result MemPllmLimitHandler(u32* ptr) {
+        Result MemPllmLimitHandler(u32* ptr) {
             clk_pll_param* entry = reinterpret_cast<clk_pll_param *>(ptr);
             if (entry->max_0 != entry->max_1)
                 return ResultFailure();
@@ -95,6 +37,25 @@ namespace ams::ldr::oc {
             entry->max_1 = max_clk;
             return ResultSuccess();
         }
+
+        template<typename M>
+        Result MtcOverwrite(M* des, M* src) {
+            constexpr u32 mtc_magic = 0x5F43544D;
+            if (src->rev != mtc_magic)
+                return ResultFailure();
+
+            // Ignore params from dvfs_ver to clock_src;
+            for (size_t offset = offsetof(M, clk_src_emc); offset < sizeof(M); offset += sizeof(u32)) {
+                u32* src_ent = reinterpret_cast<u32 *>(reinterpret_cast<size_t>(src) + offset);
+                u32* des_ent = reinterpret_cast<u32 *>(reinterpret_cast<size_t>(des) + offset);
+                u32 src_val = *src_ent;
+                if (src_val != UINT32_MAX) {
+                    PatchOffset(des_ent, src_val);
+                }
+            }
+
+            return ResultSuccess();
+        }
     }
 
     namespace pcv::Mariko {
@@ -182,6 +143,7 @@ namespace ams::ldr::oc {
             (gpuOfficialMarikoPattern[0] & 0xFFE00000) | ((C.marikoGpuMaxClock & 0xFFFF) << 5),
             (gpuOfficialMarikoPattern[1] & 0xFFE00000) | (((C.marikoGpuMaxClock >> 16) & 0xFFFF) << 5)
         };
+
         #define COMPARE_HIGH(val1, val2, bit_div) (((val1 ^ val2) >> bit_div) == 0)
 
         /* EMC */
@@ -197,7 +159,7 @@ namespace ams::ldr::oc {
         //     { 1600000, {  675,  650,  637, } },
         // };
 
-        static void MtcPllmbDivHandler(MarikoMtcTable* table) {
+        void MtcPllmbDivHandler(MarikoMtcTable* table) {
             // Calculate DIVM and DIVN (clock divisors)
             // Common PLL oscillator is 38.4 MHz
             // PLLMB_OUT = 38.4 MHz / PLLLMB_DIVM * PLLMB_DIVN
@@ -226,7 +188,7 @@ namespace ams::ldr::oc {
             table->pllmb_divn = divn;
         }
 
-        static void MtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref)
+        void MtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref)
         {
             /* Official Tegra X1 TRM, sign up for nvidia developer program (free) to download:
              *     https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual
@@ -713,7 +675,7 @@ namespace ams::ldr::oc {
             #endif
         }
 
-        static Result CpuClockVddHandler(u32* ptr) {
+        Result CpuClockVddHandler(u32* ptr) {
             if (C.marikoCpuMaxClock) {
                 u32 value_next2 = *(ptr + 2);
                 constexpr u32 cpuClockVddCpuPatternNext = 0;
@@ -725,7 +687,7 @@ namespace ams::ldr::oc {
             return ResultSuccess();
         }
 
-        static Result CpuDvfsHandler(u32* ptr, uintptr_t nso_end_offset) {
+        Result CpuDvfsHandler(u32* ptr, uintptr_t nso_end_offset) {
             cpu_freq_cvb_table_t* entry_1963 = reinterpret_cast<cpu_freq_cvb_table_t *>(ptr);
             cpu_freq_cvb_table_t* entry_free = entry_1963 + 1;
             cpu_freq_cvb_table_t* entry_204  = entry_free - 18;
@@ -748,7 +710,7 @@ namespace ams::ldr::oc {
 
             if (C.marikoCpuMaxVolt) {
                 while (entry_current->cvb_pll_param.c0 == CpuVoltOfficial * 1000) {
-                    PatchOffset(reinterpret_cast<u32 *>(std::addressof(entry_current->cvb_pll_param)), C.marikoCpuMaxVolt * 1000);
+                    PatchOffset(reinterpret_cast<u32 *>(&(entry_current->cvb_pll_param)), C.marikoCpuMaxVolt * 1000);
                     entry_current--;
                 }
             }
@@ -756,7 +718,7 @@ namespace ams::ldr::oc {
             return ResultSuccess();
         }
 
-        static Result GpuDvfsHandler(u32* ptr, uintptr_t nso_end_offset) {
+        Result GpuDvfsHandler(u32* ptr, uintptr_t nso_end_offset) {
             gpu_cvb_pll_table_t* entry_1267 = reinterpret_cast<gpu_cvb_pll_table_t *>(ptr);
             gpu_cvb_pll_table_t* entry_free = entry_1267 + 1;
             gpu_cvb_pll_table_t* entry_76_8 = entry_free - 17;
@@ -774,7 +736,7 @@ namespace ams::ldr::oc {
             return ResultSuccess();
         }
 
-        static Result CpuVoltRangeHandler(u32* ptr) {
+        Result CpuVoltRangeHandler(u32* ptr) {
             if (!C.marikoCpuMaxVolt)
                 return ResultSuccess();
 
@@ -791,7 +753,7 @@ namespace ams::ldr::oc {
             }
         }
 
-        static Result GpuMaxClockHandler(u32* ptr) {
+        Result GpuMaxClockHandler(u32* ptr) {
             u32  value      = *(ptr);
             u32* ptr_next   = ptr + 1;
             u32  value_next = *(ptr_next);
@@ -810,7 +772,7 @@ namespace ams::ldr::oc {
             return ResultFailure();
         }
 
-        static Result MtcTableHandler(u32* ptr) {
+        Result MtcTableHandler(u32* ptr) {
             MarikoMtcTable* const mtc_table_max = reinterpret_cast<MarikoMtcTable *>(ptr - offsetof(MarikoMtcTable, rate_khz) / sizeof(u32));
             MarikoMtcTable* const mtc_table_alt = mtc_table_max - 1;
             constexpr u32 mtc_mariko_rev = 3;
@@ -819,12 +781,11 @@ namespace ams::ldr::oc {
                 || mtc_table_alt->rate_khz != MemClkOSAlt )
                 return ResultFailure();
 
-            MarikoMtcTable* const table = const_cast<MarikoMtcTable *>(std::addressof(C.marikoMtc));
+            MarikoMtcTable* const table = const_cast<MarikoMtcTable *>(C.marikoMtc);
             bool replace_entire_table = (C.mtcConf == ENTIRE_TABLE_MARIKO);
             if (replace_entire_table) {
                 std::memcpy(reinterpret_cast<void *>(mtc_table_alt), reinterpret_cast<void *>(mtc_table_max), sizeof(MarikoMtcTable));
-                std::memcpy(reinterpret_cast<void *>(mtc_table_max), reinterpret_cast<void *>(table), sizeof(MarikoMtcTable));
-                return ResultSuccess();
+                return MtcOverwrite(mtc_table_max, table);
             }
 
             std::memcpy(reinterpret_cast<void *>(table), reinterpret_cast<void *>(mtc_table_max), sizeof(MarikoMtcTable));
@@ -834,7 +795,7 @@ namespace ams::ldr::oc {
             return ResultSuccess();
         }
 
-        static Result DvbTableHandler(u32* ptr) {
+        Result DvbTableHandler(u32* ptr) {
             emc_dvb_dvfs_table_t* dvb_max_entry  = reinterpret_cast<emc_dvb_dvfs_table_t *>(ptr);
             emc_dvb_dvfs_table_t* dvb_1331_entry = dvb_max_entry - 1;
 
@@ -846,7 +807,7 @@ namespace ams::ldr::oc {
             return ResultSuccess();
         }
 
-        static Result MemMaxClockHandler(u32* ptr) {
+        Result MemMaxClockHandler(u32* ptr) {
             u32 value_next  = *(ptr + 1);
             u32 value_next2 = *(ptr + 2);
 
@@ -867,7 +828,7 @@ namespace ams::ldr::oc {
             return rc;
         }
 
-        static Result GpuPllLimitHandler(u32* ptr) {
+        Result GpuPllLimitHandler(u32* ptr) {
             u32 value_next = *(ptr + 1);
             if (value_next != 0)
                 return ResultFailure();
@@ -877,7 +838,7 @@ namespace ams::ldr::oc {
             return ResultSuccess();
         }
 
-        static void Patch(uintptr_t mapped_nso, size_t nso_size) {
+        void Patch(uintptr_t mapped_nso, size_t nso_size) {
             enum PatchSuccessCnt {
                 MEM_CLOCK,
                 CPU_CLOCK_VDD,
@@ -939,17 +900,33 @@ namespace ams::ldr::oc {
                 }
             }
 
-            if (   !cnt[MEM_CLOCK]
-                || cnt[CPU_CLOCK_VDD] != 1
+            LOGGING("CpuClkOSLimit   Count: %u\n"\
+                    "CpuClkOfficial  Count: %u\n"\
+                    "GpuClkOfficial  Count: %u\n"\
+                    "CpuVoltOfficial Count: %u\n"\
+                    "MemClkOSLimit   Count: %u\n"\
+                    "GpuClkPllLimit  Count: %u\n"\
+                    "MemClkPllmLimit Count: %u\n"\
+                    "GpuAsmPattern   Count: %u",
+                    cnt[CPU_CLOCK_VDD],
+                    cnt[CPU_TABLE],
+                    cnt[GPU_TABLE],
+                    cnt[CPU_MAX_VOLT],
+                    cnt[MEM_CLOCK],
+                    cnt[GPU_PLL_CLK],
+                    cnt[MEM_PLL_CLK],
+                    cnt[GPU_MAX_CLOCK]);
+
+            if (   cnt[CPU_CLOCK_VDD] != 1
                 || cnt[CPU_TABLE]     != 1
                 || cnt[GPU_TABLE]     != 1
-                || cnt[CPU_MAX_VOLT]   > 13 || !cnt[CPU_MAX_VOLT]
-                || cnt[GPU_MAX_CLOCK] != 2
+                || cnt[CPU_MAX_VOLT]  > 13 || !cnt[CPU_MAX_VOLT]
+                || cnt[MEM_CLOCK]     == 0
                 || cnt[GPU_PLL_CLK]   != 1
-                || cnt[MEM_PLL_CLK]   != 2)
+                || cnt[MEM_PLL_CLK]   != 2
+                || cnt[GPU_MAX_CLOCK] != 2)
             {
-                AMS_ABORT();
-                __builtin_unreachable();
+                CRASH();
             }
         }
     }
@@ -986,7 +963,7 @@ namespace ams::ldr::oc {
             { 2091000, {}, {} },
         };
 
-        static Result CpuDvfsHandler(u32* ptr, uintptr_t nso_end_offset) {
+        Result CpuDvfsHandler(u32* ptr, uintptr_t nso_end_offset) {
             if (!C.eristaCpuOCEnable)
                 return ResultSuccess();
 
@@ -1007,7 +984,7 @@ namespace ams::ldr::oc {
             return ResultSuccess();
         }
 
-        static Result CpuVoltRangeHandler(u32* ptr) {
+        Result CpuVoltRangeHandler(u32* ptr) {
             if (!C.eristaCpuMaxVolt)
                 return ResultSuccess();
 
@@ -1020,22 +997,23 @@ namespace ams::ldr::oc {
                     PatchOffset(ptr, C.eristaCpuMaxVolt);
                     return ResultSuccess();
                 default:
+                    LOGGING("Invalid min voltage: %u @%p!", *(ptr-1), ptr-1);
                     return ResultFailure();
             }
         }
 
-        static Result MtcTableHandler(u32* ptr) {
+        Result MtcTableHandler(u32* ptr) {
             bool replace_entire_table = (C.mtcConf == ENTIRE_TABLE_ERISTA);
             if (replace_entire_table) {
                 EristaMtcTable* const mtc_table_max = reinterpret_cast<EristaMtcTable *>(ptr - offsetof(EristaMtcTable, rate_khz) / sizeof(u32));
-                EristaMtcTable* const table         = const_cast<EristaMtcTable *>(std::addressof(C.eristaMtc));
-                std::memcpy(reinterpret_cast<void *>(mtc_table_max), reinterpret_cast<void *>(table), sizeof(EristaMtcTable));
+                EristaMtcTable* const table         = const_cast<EristaMtcTable *>(C.eristaMtc);
+                return MtcOverwrite(mtc_table_max, table);
             }
 
             return ResultSuccess();
         }
 
-        static Result MemMaxClockHandler(u32* ptr) {
+        Result MemMaxClockHandler(u32* ptr) {
             u32 value_next = *(ptr + 1);
             constexpr u32 mtc_min_volt = 887;
 
@@ -1048,14 +1026,14 @@ namespace ams::ldr::oc {
             return rc;
         }
 
-        static Result MemVoltHandler(u32* ptr) {
+        Result MemVoltHandler(u32* ptr) {
             if (C.eristaEmcVolt)
                 PatchOffset(ptr, C.eristaEmcVolt);
 
             return ResultSuccess();
         }
 
-        static void Patch(uintptr_t mapped_nso, size_t nso_size) {
+        void Patch(uintptr_t mapped_nso, size_t nso_size) {
             enum PatchSuccessCnt {
                 CPU_CLOCK,
                 CPU_MAX_VOLT,
@@ -1102,9 +1080,24 @@ namespace ams::ldr::oc {
                 }
             }
 
-            if (!cnt[MEM_CLOCK] || cnt[MEM_VOLT] != 2 || cnt[MEM_PLL_CLK] != 2) {
-                AMS_ABORT();
-                __builtin_unreachable();
+            LOGGING("CpuClkOSLimit   Count: %u\n"\
+                    "CpuVoltLimit*   Count: %u\n"\
+                    "MemClkOSLimit   Count: %u\n"\
+                    "MemVoltHOS      Count: %u\n"\
+                    "MemClkPllmLimit Count: %u",
+                    cnt[CPU_CLOCK],
+                    cnt[CPU_MAX_VOLT],
+                    cnt[MEM_CLOCK],
+                    cnt[MEM_VOLT],
+                    cnt[MEM_PLL_CLK]);
+
+            if (   cnt[CPU_CLOCK]    != 1
+                || cnt[CPU_MAX_VOLT]  < 2
+                || cnt[MEM_CLOCK]    == 0
+                || cnt[MEM_VOLT]     != 2
+                || cnt[MEM_PLL_CLK]  != 2)
+            {
+                CRASH();
             }
         }
     }
@@ -1112,24 +1105,34 @@ namespace ams::ldr::oc {
     namespace pcv {
         void Patch(uintptr_t mapped_nso, size_t nso_size) {
             if (C.custRev != CUST_REV) {
-                AMS_ABORT();
-                __builtin_unreachable();
+                CRASH();
             }
 
+            #ifdef OC_TEST
+            void* buf = malloc(nso_size);
+            uintptr_t mapped_exe = reinterpret_cast<uintptr_t>(buf);
+            std::memcpy(buf, reinterpret_cast<void *>(mapped_nso), nso_size);
+            Erista::Patch(mapped_exe, nso_size);
+            std::memcpy(buf, reinterpret_cast<void *>(mapped_nso), nso_size);
+            Mariko::Patch(mapped_exe, nso_size);
+            free(buf);
+            #else
             bool isMariko = (spl::GetSocType() == spl::SocType_Mariko);
             if (isMariko)
                 Mariko::Patch(mapped_nso, nso_size);
             else
                 Erista::Patch(mapped_nso, nso_size);
+            #endif
         }
     }
 
     namespace ptm {
         void Patch(uintptr_t mapped_nso, size_t nso_size) {
-            /* No abort here as ptm is not that critical */
+            #ifndef OC_TEST
             bool isMariko = (spl::GetSocType() == spl::SocType_Mariko);
             if (!isMariko)
                 return;
+            #endif
 
             perf_conf_entry* confTable = 0;
             constexpr u32 entryCnt     = 16;
@@ -1151,29 +1154,34 @@ namespace ams::ldr::oc {
                 }
             }
 
-            if (!confTable)
-                return;
+            if (!confTable) {
+                LOGGING("confTable not found!");
+                CRASH();
+            }
 
             for (u32 i = 0; i < entryCnt; i++)
             {
                 perf_conf_entry* entry_current = confTable + i;
 
-                if (entry_current->emc_freq_1 != entry_current->emc_freq_2)
-                    return;
+                if (entry_current->emc_freq_1 != entry_current->emc_freq_2) {
+                    LOGGING("@%p: emc_freq_1(%u) != emc_freq_2(%u)", &(entry_current->emc_freq_1), entry_current->emc_freq_1, entry_current->emc_freq_2);
+                    CRASH();
+                }
 
                 switch (entry_current->emc_freq_1)
                 {
                     case memPtmLimit:
-                        PatchOffset(std::addressof(entry_current->emc_freq_1), memPtmMax);
-                        PatchOffset(std::addressof(entry_current->emc_freq_2), memPtmMax);
+                        PatchOffset(&(entry_current->emc_freq_1), memPtmMax);
+                        PatchOffset(&(entry_current->emc_freq_2), memPtmMax);
                         break;
                     case memPtmAlt:
                     case memPtmClamp:
-                        PatchOffset(std::addressof(entry_current->emc_freq_1), memPtmLimit);
-                        PatchOffset(std::addressof(entry_current->emc_freq_2), memPtmLimit);
+                        PatchOffset(&(entry_current->emc_freq_1), memPtmLimit);
+                        PatchOffset(&(entry_current->emc_freq_2), memPtmLimit);
                         break;
                     default:
-                        return;
+                        LOGGING("Wrong mem freq: %u @%p!", entry_current->emc_freq_1, &(entry_current->emc_freq_1));
+                        CRASH();
                 }
             }
         }
diff --git a/Source/Atmosphere/stratosphere/loader/source/ldr_oc_suite.hpp b/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite.hpp
similarity index 91%
rename from Source/Atmosphere/stratosphere/loader/source/ldr_oc_suite.hpp
rename to Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite.hpp
index 2ee6f0aa..ba87354f 100644
--- a/Source/Atmosphere/stratosphere/loader/source/ldr_oc_suite.hpp
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite.hpp
@@ -13,12 +13,12 @@
  * You should have received a copy of the GNU General Public License
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
+#pragma once
 
 #define CUST_REV 1
+#include "mtc_timing_table.hpp"
 
 namespace ams::ldr::oc {
-    #include "mtc_timing_table.hpp"
-
     enum MtcConfig {
         AUTO_ADJ_MARIKO_SAFE = 0,
         AUTO_ADJ_MARIKO_4266 = 1,
@@ -39,8 +39,8 @@ namespace ams::ldr::oc {
         u32 eristaEmcMaxClock;
         u32 eristaEmcVolt;
         union {
-            EristaMtcTable eristaMtc;
-            MarikoMtcTable marikoMtc;
+            EristaMtcTable* eristaMtc;
+            MarikoMtcTable* marikoMtc;
         };
     } CustomizeTable;
 
@@ -48,6 +48,12 @@ namespace ams::ldr::oc {
 
     inline Result ResultFailure() { return -1; }
 
+    #ifndef OC_TEST
+    #define LOGGING(fmt, ...) ((void)0)
+    #endif
+
+    #define CRASH() { AMS_ABORT(); __builtin_unreachable(); }
+
     namespace pcv {
         typedef struct {
             s32 c0 = 0;
diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite_test.hpp b/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite_test.hpp
new file mode 100644
index 00000000..3a334652
--- /dev/null
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/ldr_oc_suite_test.hpp
@@ -0,0 +1,37 @@
+#ifdef OC_TEST
+#include <iostream>
+#include <cstdint>
+#include <cstring>
+#include <cmath>
+
+typedef uint8_t  u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+typedef int32_t  s32;
+typedef uint64_t u64;
+typedef int      Result;
+
+#define R_SUCCEEDED(arg)  (arg == ResultSuccess())
+#define LOGGING(fmt, ...) { printf(fmt "\n\tin %s\n", ##__VA_ARGS__, __PRETTY_FUNCTION__); }
+#define AMS_ABORT()       { fprintf(stderr, "Failed!\n"); exit(-1); }
+
+inline Result ResultSuccess() { return 0; }
+
+#include "ldr_oc_suite.hpp"
+
+namespace ams::ldr::oc {
+    volatile u8 EmptyMtcTable[0x1340] = { 'M', 'T', 'C', '_', };
+    static const volatile CustomizeTable C = {
+    .mtcConf = AUTO_ADJ_MARIKO_SAFE,
+    .marikoCpuMaxClock = 2397000,
+    .marikoCpuMaxVolt  = 1220,
+    .marikoGpuMaxClock = 1305600,
+    .marikoEmcMaxClock = 1996800,
+    .eristaCpuOCEnable = 1,
+    .eristaCpuMaxVolt  = 1300,
+    .eristaEmcMaxClock = 1862400,
+    .eristaEmcVolt     = 1250,
+    .eristaMtc = reinterpret_cast<EristaMtcTable *>(const_cast<u8 *>(EmptyMtcTable)),
+    };
+}
+#endif
\ No newline at end of file
diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_empty_table.inc b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_empty_table.inc
new file mode 100644
index 00000000..47f069f5
--- /dev/null
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_empty_table.inc
@@ -0,0 +1,310 @@
+volatile u8 EmptyMtcTable[0x1340] = {
+     'M',  'T',  'C',  '_', 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+};
diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_table.hpp b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_table.hpp
new file mode 100644
index 00000000..cc9a51dd
--- /dev/null
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_table.hpp
@@ -0,0 +1,1246 @@
+/*
+ * Copyright (c) Atmosphère-NX
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * from GCC preprocessor output
+ */
+
+struct MarikoTiming {
+    uint32_t emc_rc;
+    uint32_t emc_rfc;
+    uint32_t emc_rfcpb;
+    uint32_t emc_refctrl2;
+    uint32_t emc_rfc_slr;
+    uint32_t emc_ras;
+    uint32_t emc_rp;
+    uint32_t emc_r2w;
+    uint32_t emc_w2r;
+    uint32_t emc_r2p;
+    uint32_t emc_w2p;
+    uint32_t emc_r2r;
+    uint32_t emc_tppd;
+    uint32_t emc_trtm;
+    uint32_t emc_twtm;
+    uint32_t emc_tratm;
+    uint32_t emc_twatm;
+    uint32_t emc_tr2ref;
+    uint32_t emc_ccdmw;
+    uint32_t emc_rd_rcd;
+    uint32_t emc_wr_rcd;
+    uint32_t emc_rrd;
+    uint32_t emc_rext;
+    uint32_t emc_wext;
+    uint32_t emc_wdv_chk;
+    uint32_t emc_wdv;
+    uint32_t emc_wsv;
+    uint32_t emc_wev;
+    uint32_t emc_wdv_mask;
+    uint32_t emc_ws_duration;
+    uint32_t emc_we_duration;
+    uint32_t emc_quse;
+    uint32_t emc_quse_width;
+    uint32_t emc_ibdly;
+    uint32_t emc_obdly;
+    uint32_t emc_einput;
+    uint32_t emc_mrw6;
+    uint32_t emc_einput_duration;
+    uint32_t emc_puterm_extra;
+    uint32_t emc_puterm_width;
+    uint32_t emc_qrst;
+    uint32_t emc_qsafe;
+    uint32_t emc_rdv;
+    uint32_t emc_rdv_mask;
+    uint32_t emc_rdv_early;
+    uint32_t emc_rdv_early_mask;
+    uint32_t emc_refresh;
+    uint32_t emc_burst_refresh_num;
+    uint32_t emc_pre_refresh_req_cnt;
+    uint32_t emc_pdex2wr;
+    uint32_t emc_pdex2rd;
+    uint32_t emc_pchg2pden;
+    uint32_t emc_act2pden;
+    uint32_t emc_ar2pden;
+    uint32_t emc_rw2pden;
+    uint32_t emc_cke2pden;
+    uint32_t emc_pdex2cke;
+    uint32_t emc_pdex2mrr;
+    uint32_t emc_txsr;
+    uint32_t emc_txsrdll;
+    uint32_t emc_tcke;
+    uint32_t emc_tckesr;
+    uint32_t emc_tpd;
+    uint32_t emc_tfaw;
+    uint32_t emc_trpab;
+    uint32_t emc_tclkstable;
+    uint32_t emc_tclkstop;
+    uint32_t emc_mrw7;
+    uint32_t emc_trefbw;
+    uint32_t emc_odt_write;
+    uint32_t emc_fbio_cfg5;
+    uint32_t emc_fbio_cfg7;
+    uint32_t emc_cfg_dig_dll;
+    uint32_t emc_cfg_dig_dll_period;
+    uint32_t emc_pmacro_ib_rxrt;
+    uint32_t emc_cfg_pipe_1;
+    uint32_t emc_cfg_pipe_2;
+    uint32_t emc_pmacro_quse_ddll_rank0_4;
+    uint32_t emc_pmacro_quse_ddll_rank0_5;
+    uint32_t emc_pmacro_quse_ddll_rank1_4;
+    uint32_t emc_pmacro_quse_ddll_rank1_5;
+    uint32_t emc_mrw8;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
+    uint32_t emc_pmacro_ddll_long_cmd_0;
+    uint32_t emc_pmacro_ddll_long_cmd_1;
+    uint32_t emc_pmacro_ddll_long_cmd_2;
+    uint32_t emc_pmacro_ddll_long_cmd_3;
+    uint32_t emc_pmacro_ddll_long_cmd_4;
+    uint32_t emc_pmacro_ddll_short_cmd_0;
+    uint32_t emc_pmacro_ddll_short_cmd_1;
+    uint32_t emc_pmacro_ddll_short_cmd_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
+    uint32_t emc_txdsrvttgen;
+    uint32_t emc_fdpd_ctrl_dq;
+    uint32_t emc_fdpd_ctrl_cmd;
+    uint32_t emc_fbio_spare;
+    uint32_t emc_zcal_interval;
+    uint32_t emc_zcal_wait_cnt;
+    uint32_t emc_mrs_wait_cnt;
+    uint32_t emc_mrs_wait_cnt2;
+    uint32_t emc_auto_cal_channel;
+    uint32_t emc_pmacro_dll_cfg_0;
+    uint32_t emc_pmacro_dll_cfg_1;
+    uint32_t emc_pmacro_dll_cfg_2;
+    uint32_t emc_pmacro_autocal_cfg_common;
+    uint32_t emc_pmacro_zctrl;
+    uint32_t emc_cfg;
+    uint32_t emc_cfg_pipe;
+    uint32_t emc_dyn_self_ref_control;
+    uint32_t emc_qpop;
+    uint32_t emc_dqs_brlshft_0;
+    uint32_t emc_dqs_brlshft_1;
+    uint32_t emc_cmd_brlshft_2;
+    uint32_t emc_cmd_brlshft_3;
+    uint32_t emc_pmacro_pad_cfg_ctrl;
+    uint32_t emc_pmacro_data_pad_rx_ctrl;
+    uint32_t emc_pmacro_cmd_pad_rx_ctrl;
+    uint32_t emc_pmacro_data_rx_term_mode;
+    uint32_t emc_pmacro_cmd_rx_term_mode;
+    uint32_t emc_pmacro_cmd_pad_tx_ctrl;
+    uint32_t emc_pmacro_data_pad_tx_ctrl;
+    uint32_t emc_pmacro_vttgen_ctrl_0;
+    uint32_t emc_pmacro_vttgen_ctrl_1;
+    uint32_t emc_pmacro_vttgen_ctrl_2;
+    uint32_t emc_pmacro_brick_ctrl_rfu1;
+    uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
+    uint32_t emc_pmacro_brick_ctrl_rfu2;
+    uint32_t emc_pmacro_data_brick_ctrl_fdpd;
+    uint32_t emc_pmacro_bg_bias_ctrl_0;
+    uint32_t emc_cfg_3;
+    uint32_t emc_pmacro_tx_pwrd_0;
+    uint32_t emc_pmacro_tx_pwrd_1;
+    uint32_t emc_pmacro_tx_pwrd_2;
+    uint32_t emc_pmacro_tx_pwrd_3;
+    uint32_t emc_pmacro_tx_pwrd_4;
+    uint32_t emc_pmacro_tx_pwrd_5;
+    uint32_t emc_config_sample_delay;
+    uint32_t emc_pmacro_tx_sel_clk_src_0;
+    uint32_t emc_pmacro_tx_sel_clk_src_1;
+    uint32_t emc_pmacro_tx_sel_clk_src_2;
+    uint32_t emc_pmacro_tx_sel_clk_src_3;
+    uint32_t emc_pmacro_tx_sel_clk_src_4;
+    uint32_t emc_pmacro_tx_sel_clk_src_5;
+    uint32_t emc_pmacro_ddll_bypass;
+    uint32_t emc_pmacro_ddll_pwrd_0;
+    uint32_t emc_pmacro_ddll_pwrd_1;
+    uint32_t emc_pmacro_ddll_pwrd_2;
+    uint32_t emc_pmacro_cmd_ctrl_0;
+    uint32_t emc_pmacro_cmd_ctrl_1;
+    uint32_t emc_pmacro_cmd_ctrl_2;
+    uint32_t emc_pmacro_data_pi_ctrl;
+    uint32_t emc_pmacro_cmd_pi_ctrl;
+    uint32_t emc_tr_timing_0;
+    uint32_t emc_tr_dvfs;
+    uint32_t emc_tr_ctrl_1;
+    uint32_t emc_tr_rdv;
+    uint32_t emc_tr_qpop;
+    uint32_t emc_tr_rdv_mask;
+    uint32_t emc_mrw14;
+    uint32_t emc_tr_qsafe;
+    uint32_t emc_tr_qrst;
+    uint32_t emc_training_ctrl;
+    uint32_t emc_training_settle;
+    uint32_t emc_training_vref_settle;
+    uint32_t emc_training_ca_fine_ctrl;
+    uint32_t emc_training_ca_ctrl_misc;
+    uint32_t emc_training_ca_ctrl_misc1;
+    uint32_t emc_training_ca_vref_ctrl;
+    uint32_t emc_training_quse_cors_ctrl;
+    uint32_t emc_training_quse_fine_ctrl;
+    uint32_t emc_training_quse_ctrl_misc;
+    uint32_t emc_training_quse_vref_ctrl;
+    uint32_t emc_training_read_fine_ctrl;
+    uint32_t emc_training_read_ctrl_misc;
+    uint32_t emc_training_read_vref_ctrl;
+    uint32_t emc_training_write_fine_ctrl;
+    uint32_t emc_training_write_ctrl_misc;
+    uint32_t emc_training_write_vref_ctrl;
+    uint32_t emc_training_mpc;
+    uint32_t emc_mrw15;
+};
+
+struct EristaTiming {
+    uint32_t emc_rc;
+    uint32_t emc_rfc;
+    uint32_t emc_rfcpb;
+    uint32_t emc_refctrl2;
+    uint32_t emc_rfc_slr;
+    uint32_t emc_ras;
+    uint32_t emc_rp;
+    uint32_t emc_r2w;
+    uint32_t emc_w2r;
+    uint32_t emc_r2p;
+    uint32_t emc_w2p;
+    uint32_t emc_r2r;
+    uint32_t emc_tppd;
+    uint32_t emc_ccdmw;
+    uint32_t emc_rd_rcd;
+    uint32_t emc_wr_rcd;
+    uint32_t emc_rrd;
+    uint32_t emc_rext;
+    uint32_t emc_wext;
+    uint32_t emc_wdv_chk;
+    uint32_t emc_wdv;
+    uint32_t emc_wsv;
+    uint32_t emc_wev;
+    uint32_t emc_wdv_mask;
+    uint32_t emc_ws_duration;
+    uint32_t emc_we_duration;
+    uint32_t emc_quse;
+    uint32_t emc_quse_width;
+    uint32_t emc_ibdly;
+    uint32_t emc_obdly;
+    uint32_t emc_einput;
+    uint32_t emc_mrw6;
+    uint32_t emc_einput_duration;
+    uint32_t emc_puterm_extra;
+    uint32_t emc_puterm_width;
+    uint32_t emc_qrst;
+    uint32_t emc_qsafe;
+    uint32_t emc_rdv;
+    uint32_t emc_rdv_mask;
+    uint32_t emc_rdv_early;
+    uint32_t emc_rdv_early_mask;
+    uint32_t emc_refresh;
+    uint32_t emc_burst_refresh_num;
+    uint32_t emc_pre_refresh_req_cnt;
+    uint32_t emc_pdex2wr;
+    uint32_t emc_pdex2rd;
+    uint32_t emc_pchg2pden;
+    uint32_t emc_act2pden;
+    uint32_t emc_ar2pden;
+    uint32_t emc_rw2pden;
+    uint32_t emc_cke2pden;
+    uint32_t emc_pdex2cke;
+    uint32_t emc_pdex2mrr;
+    uint32_t emc_txsr;
+    uint32_t emc_txsrdll;
+    uint32_t emc_tcke;
+    uint32_t emc_tckesr;
+    uint32_t emc_tpd;
+    uint32_t emc_tfaw;
+    uint32_t emc_trpab;
+    uint32_t emc_tclkstable;
+    uint32_t emc_tclkstop;
+    uint32_t emc_mrw7;
+    uint32_t emc_trefbw;
+    uint32_t emc_odt_write;
+    uint32_t emc_fbio_cfg5;
+    uint32_t emc_fbio_cfg7;
+    uint32_t emc_cfg_dig_dll;
+    uint32_t emc_cfg_dig_dll_period;
+    uint32_t emc_pmacro_ib_rxrt;
+    uint32_t emc_cfg_pipe_1;
+    uint32_t emc_cfg_pipe_2;
+    uint32_t emc_pmacro_quse_ddll_rank0_4;
+    uint32_t emc_pmacro_quse_ddll_rank0_5;
+    uint32_t emc_pmacro_quse_ddll_rank1_4;
+    uint32_t emc_pmacro_quse_ddll_rank1_5;
+    uint32_t emc_mrw8;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4;
+    uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4;
+    uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5;
+    uint32_t emc_pmacro_ddll_long_cmd_0;
+    uint32_t emc_pmacro_ddll_long_cmd_1;
+    uint32_t emc_pmacro_ddll_long_cmd_2;
+    uint32_t emc_pmacro_ddll_long_cmd_3;
+    uint32_t emc_pmacro_ddll_long_cmd_4;
+    uint32_t emc_pmacro_ddll_short_cmd_0;
+    uint32_t emc_pmacro_ddll_short_cmd_1;
+    uint32_t emc_pmacro_ddll_short_cmd_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2;
+    uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3;
+    uint32_t emc_txdsrvttgen;
+    uint32_t emc_fdpd_ctrl_dq;
+    uint32_t emc_fdpd_ctrl_cmd;
+    uint32_t emc_fbio_spare;
+    uint32_t emc_zcal_interval;
+    uint32_t emc_zcal_wait_cnt;
+    uint32_t emc_mrs_wait_cnt;
+    uint32_t emc_mrs_wait_cnt2;
+    uint32_t emc_auto_cal_channel;
+    uint32_t emc_dll_cfg_0;
+    uint32_t emc_dll_cfg_1;
+    uint32_t emc_pmacro_autocal_cfg_common;
+    uint32_t emc_pmacro_zctrl;
+    uint32_t emc_cfg;
+    uint32_t emc_cfg_pipe;
+    uint32_t emc_dyn_self_ref_control;
+    uint32_t emc_qpop;
+    uint32_t emc_dqs_brlshft_0;
+    uint32_t emc_dqs_brlshft_1;
+    uint32_t emc_cmd_brlshft_2;
+    uint32_t emc_cmd_brlshft_3;
+    uint32_t emc_pmacro_pad_cfg_ctrl;
+    uint32_t emc_pmacro_data_pad_rx_ctrl;
+    uint32_t emc_pmacro_cmd_pad_rx_ctrl;
+    uint32_t emc_pmacro_data_rx_term_mode;
+    uint32_t emc_pmacro_cmd_rx_term_mode;
+    uint32_t emc_pmacro_cmd_pad_tx_ctrl;
+    uint32_t emc_pmacro_data_pad_tx_ctrl;
+    uint32_t emc_pmacro_common_pad_tx_ctrl;
+    uint32_t emc_pmacro_vttgen_ctrl_0;
+    uint32_t emc_pmacro_vttgen_ctrl_1;
+    uint32_t emc_pmacro_vttgen_ctrl_2;
+    uint32_t emc_pmacro_brick_ctrl_rfu1;
+    uint32_t emc_pmacro_cmd_brick_ctrl_fdpd;
+    uint32_t emc_pmacro_brick_ctrl_rfu2;
+    uint32_t emc_pmacro_data_brick_ctrl_fdpd;
+    uint32_t emc_pmacro_bg_bias_ctrl_0;
+    uint32_t emc_cfg_3;
+    uint32_t emc_pmacro_tx_pwrd_0;
+    uint32_t emc_pmacro_tx_pwrd_1;
+    uint32_t emc_pmacro_tx_pwrd_2;
+    uint32_t emc_pmacro_tx_pwrd_3;
+    uint32_t emc_pmacro_tx_pwrd_4;
+    uint32_t emc_pmacro_tx_pwrd_5;
+    uint32_t emc_config_sample_delay;
+    uint32_t emc_pmacro_tx_sel_clk_src_0;
+    uint32_t emc_pmacro_tx_sel_clk_src_1;
+    uint32_t emc_pmacro_tx_sel_clk_src_2;
+    uint32_t emc_pmacro_tx_sel_clk_src_3;
+    uint32_t emc_pmacro_tx_sel_clk_src_4;
+    uint32_t emc_pmacro_tx_sel_clk_src_5;
+    uint32_t emc_pmacro_ddll_bypass;
+    uint32_t emc_pmacro_ddll_pwrd_0;
+    uint32_t emc_pmacro_ddll_pwrd_1;
+    uint32_t emc_pmacro_ddll_pwrd_2;
+    uint32_t emc_pmacro_cmd_ctrl_0;
+    uint32_t emc_pmacro_cmd_ctrl_1;
+    uint32_t emc_pmacro_cmd_ctrl_2;
+    uint32_t emc_tr_timing_0;
+    uint32_t emc_tr_dvfs;
+    uint32_t emc_tr_ctrl_1;
+    uint32_t emc_tr_rdv;
+    uint32_t emc_tr_qpop;
+    uint32_t emc_tr_rdv_mask;
+    uint32_t emc_mrw14;
+    uint32_t emc_tr_qsafe;
+    uint32_t emc_tr_qrst;
+    uint32_t emc_training_ctrl;
+    uint32_t emc_training_settle;
+    uint32_t emc_training_vref_settle;
+    uint32_t emc_training_ca_fine_ctrl;
+    uint32_t emc_training_ca_ctrl_misc;
+    uint32_t emc_training_ca_ctrl_misc1;
+    uint32_t emc_training_ca_vref_ctrl;
+    uint32_t emc_training_quse_cors_ctrl;
+    uint32_t emc_training_quse_fine_ctrl;
+    uint32_t emc_training_quse_ctrl_misc;
+    uint32_t emc_training_quse_vref_ctrl;
+    uint32_t emc_training_read_fine_ctrl;
+    uint32_t emc_training_read_ctrl_misc;
+    uint32_t emc_training_read_vref_ctrl;
+    uint32_t emc_training_write_fine_ctrl;
+    uint32_t emc_training_write_ctrl_misc;
+    uint32_t emc_training_write_vref_ctrl;
+    uint32_t emc_training_mpc;
+    uint32_t emc_mrw15;
+};
+
+struct MarikoMtcTable {
+    uint32_t rev;
+    char dvfs_ver[60];
+    uint32_t rate_khz;
+    uint32_t min_volt;
+    uint32_t gpu_min_volt;
+    char clock_src[32];
+    uint32_t clk_src_emc;
+    uint32_t pll_en_ssc;
+    uint32_t needs_training;
+    uint32_t training_pattern;
+    uint32_t trained;
+
+    uint32_t periodic_training;
+    uint32_t trained_dram_clktree_c0d0u0;
+    uint32_t trained_dram_clktree_c0d0u1;
+    uint32_t trained_dram_clktree_c0d1u0;
+    uint32_t trained_dram_clktree_c0d1u1;
+    uint32_t trained_dram_clktree_c1d0u0;
+    uint32_t trained_dram_clktree_c1d0u1;
+    uint32_t trained_dram_clktree_c1d1u0;
+    uint32_t trained_dram_clktree_c1d1u1;
+    uint32_t current_dram_clktree_c0d0u0;
+    uint32_t current_dram_clktree_c0d0u1;
+    uint32_t current_dram_clktree_c0d1u0;
+    uint32_t current_dram_clktree_c0d1u1;
+    uint32_t current_dram_clktree_c1d0u0;
+    uint32_t current_dram_clktree_c1d0u1;
+    uint32_t current_dram_clktree_c1d1u0;
+    uint32_t current_dram_clktree_c1d1u1;
+    uint32_t emc_fbio_cfg7;
+    uint32_t run_clocks;
+    uint32_t tree_margin;
+
+    uint32_t num_burst;
+    uint32_t num_burst_per_ch;
+    uint32_t num_trim;
+    uint32_t num_trim_per_ch;
+    uint32_t num_mc_regs;
+    uint32_t num_up_down;
+    uint32_t vref_num;
+    uint32_t training_mod_num;
+    uint32_t dram_timing_num;
+
+    uint32_t ptfv_dqsosc_movavg_c0d0u0;
+    uint32_t ptfv_dqsosc_movavg_c0d0u1;
+    uint32_t ptfv_dqsosc_movavg_c0d1u0;
+    uint32_t ptfv_dqsosc_movavg_c0d1u1;
+    uint32_t ptfv_dqsosc_movavg_c1d0u0;
+    uint32_t ptfv_dqsosc_movavg_c1d0u1;
+    uint32_t ptfv_dqsosc_movavg_c1d1u0;
+    uint32_t ptfv_dqsosc_movavg_c1d1u1;
+    uint32_t ptfv_write_samples;
+    uint32_t ptfv_dvfs_samples;
+    uint32_t ptfv_movavg_weight;
+    uint32_t ptfv_config_ctrl;
+
+    MarikoTiming burst_regs;
+
+    struct {
+        uint32_t emc0_mrw10;
+        uint32_t emc1_mrw10;
+        uint32_t emc0_mrw11;
+        uint32_t emc1_mrw11;
+        uint32_t emc0_mrw12;
+        uint32_t emc1_mrw12;
+        uint32_t emc0_mrw13;
+        uint32_t emc1_mrw13;
+    }
+    burst_perch_regs;
+
+    MarikoTiming shadow_regs_ca_train;
+
+    MarikoTiming shadow_regs_rdwr_train;
+
+    struct {
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;
+        uint32_t emc_pmacro_ib_vref_dqs_0;
+        uint32_t emc_pmacro_ib_vref_dqs_1;
+        uint32_t emc_pmacro_ib_vref_dq_0;
+        uint32_t emc_pmacro_ib_vref_dq_1;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_2;
+        uint32_t emc_pmacro_quse_ddll_rank0_0;
+        uint32_t emc_pmacro_quse_ddll_rank0_1;
+        uint32_t emc_pmacro_quse_ddll_rank0_2;
+        uint32_t emc_pmacro_quse_ddll_rank0_3;
+        uint32_t emc_pmacro_quse_ddll_rank1_0;
+        uint32_t emc_pmacro_quse_ddll_rank1_1;
+        uint32_t emc_pmacro_quse_ddll_rank1_2;
+        uint32_t emc_pmacro_quse_ddll_rank1_3;
+    }
+    trim_regs;
+
+    struct {
+        uint32_t emc0_cmd_brlshft_0;
+        uint32_t emc1_cmd_brlshft_1;
+        uint32_t emc0_data_brlshft_0;
+        uint32_t emc1_data_brlshft_0;
+        uint32_t emc0_data_brlshft_1;
+        uint32_t emc1_data_brlshft_1;
+        uint32_t emc0_quse_brlshft_0;
+        uint32_t emc1_quse_brlshft_1;
+        uint32_t emc0_quse_brlshft_2;
+        uint32_t emc1_quse_brlshft_3;
+    }
+    trim_perch_regs;
+
+    struct {
+        uint32_t emc0_training_opt_dqs_ib_vref_rank0;
+        uint32_t emc1_training_opt_dqs_ib_vref_rank0;
+        uint32_t emc0_training_opt_dqs_ib_vref_rank1;
+        uint32_t emc1_training_opt_dqs_ib_vref_rank1;
+    }
+    vref_perch_regs;
+
+    struct {
+        uint32_t t_rp;
+        uint32_t t_fc_lpddr4;
+        uint32_t t_rfc;
+        uint32_t t_pdex;
+        uint32_t rl;
+    }
+    dram_timings;
+
+    uint32_t zq_op_cc_long_zcal;
+    uint32_t zq_op_cc_short_zcal;
+    uint32_t zcal_wait_time_ps_cc_long_zcal;
+    uint32_t zcal_wait_time_ps_cc_short_zcal;
+    uint32_t tZQCAL_lpddr4;
+    uint32_t zqcal_before_cc_cutoff;
+    uint32_t opt_cc_short_zcal;
+    uint32_t opt_short_zcal;
+    uint32_t opt_do_sw_qrst;
+    uint32_t save_restore_clkstop_pd;
+    uint32_t opt_E90;
+    uint32_t cya_allow_ref_cc;
+    uint32_t ref_b4_sref_en;
+    uint32_t cya_issue_pc_ref;
+
+    struct {
+        uint32_t emc0_training_rw_offset_ib_byte0;
+        uint32_t emc1_training_rw_offset_ib_byte0;
+        uint32_t emc0_training_rw_offset_ib_byte1;
+        uint32_t emc1_training_rw_offset_ib_byte1;
+        uint32_t emc0_training_rw_offset_ib_byte2;
+        uint32_t emc1_training_rw_offset_ib_byte2;
+        uint32_t emc0_training_rw_offset_ib_byte3;
+        uint32_t emc1_training_rw_offset_ib_byte3;
+        uint32_t emc0_training_rw_offset_ib_misc;
+        uint32_t emc1_training_rw_offset_ib_misc;
+        uint32_t emc0_training_rw_offset_ob_byte0;
+        uint32_t emc1_training_rw_offset_ob_byte0;
+        uint32_t emc0_training_rw_offset_ob_byte1;
+        uint32_t emc1_training_rw_offset_ob_byte1;
+        uint32_t emc0_training_rw_offset_ob_byte2;
+        uint32_t emc1_training_rw_offset_ob_byte2;
+        uint32_t emc0_training_rw_offset_ob_byte3;
+        uint32_t emc1_training_rw_offset_ob_byte3;
+        uint32_t emc0_training_rw_offset_ob_misc;
+        uint32_t emc1_training_rw_offset_ob_misc;
+    }
+    training_mod_regs;
+
+    uint32_t save_restore_mod_regs[12];
+
+    struct {
+        uint32_t mc_emem_arb_cfg;
+        uint32_t mc_emem_arb_outstanding_req;
+        uint32_t mc_emem_arb_refpb_hp_ctrl;
+        uint32_t mc_emem_arb_refpb_bank_ctrl;
+        uint32_t mc_emem_arb_timing_rcd;
+        uint32_t mc_emem_arb_timing_rp;
+        uint32_t mc_emem_arb_timing_rc;
+        uint32_t mc_emem_arb_timing_ras;
+        uint32_t mc_emem_arb_timing_faw;
+        uint32_t mc_emem_arb_timing_rrd;
+        uint32_t mc_emem_arb_timing_rap2pre;
+        uint32_t mc_emem_arb_timing_wap2pre;
+        uint32_t mc_emem_arb_timing_r2r;
+        uint32_t mc_emem_arb_timing_w2w;
+        uint32_t mc_emem_arb_timing_r2w;
+        uint32_t mc_emem_arb_timing_ccdmw;
+        uint32_t mc_emem_arb_timing_w2r;
+        uint32_t mc_emem_arb_timing_rfcpb;
+        uint32_t mc_emem_arb_da_turns;
+        uint32_t mc_emem_arb_da_covers;
+        uint32_t mc_emem_arb_misc0;
+        uint32_t mc_emem_arb_misc1;
+        uint32_t mc_emem_arb_misc2;
+        uint32_t mc_emem_arb_ring1_throttle;
+        uint32_t mc_emem_arb_dhyst_ctrl;
+        uint32_t mc_emem_arb_dhyst_timeout_util_0;
+        uint32_t mc_emem_arb_dhyst_timeout_util_1;
+        uint32_t mc_emem_arb_dhyst_timeout_util_2;
+        uint32_t mc_emem_arb_dhyst_timeout_util_3;
+        uint32_t mc_emem_arb_dhyst_timeout_util_4;
+        uint32_t mc_emem_arb_dhyst_timeout_util_5;
+        uint32_t mc_emem_arb_dhyst_timeout_util_6;
+        uint32_t mc_emem_arb_dhyst_timeout_util_7;
+    }
+    burst_mc_regs;
+
+    struct {
+        uint32_t mc_mll_mpcorer_ptsa_rate;
+        uint32_t mc_ftop_ptsa_rate;
+        uint32_t mc_ptsa_grant_decrement;
+        uint32_t mc_latency_allowance_xusb_0;
+        uint32_t mc_latency_allowance_xusb_1;
+        uint32_t mc_latency_allowance_tsec_0;
+        uint32_t mc_latency_allowance_sdmmca_0;
+        uint32_t mc_latency_allowance_sdmmcaa_0;
+        uint32_t mc_latency_allowance_sdmmc_0;
+        uint32_t mc_latency_allowance_sdmmcab_0;
+        uint32_t mc_latency_allowance_ppcs_0;
+        uint32_t mc_latency_allowance_ppcs_1;
+        uint32_t mc_latency_allowance_mpcore_0;
+        uint32_t mc_latency_allowance_hc_0;
+        uint32_t mc_latency_allowance_hc_1;
+        uint32_t mc_latency_allowance_avpc_0;
+        uint32_t mc_latency_allowance_gpu_0;
+        uint32_t mc_latency_allowance_gpu2_0;
+        uint32_t mc_latency_allowance_nvenc_0;
+        uint32_t mc_latency_allowance_nvdec_0;
+        uint32_t mc_latency_allowance_vic_0;
+        uint32_t mc_latency_allowance_vi2_0;
+        uint32_t mc_latency_allowance_isp2_0;
+        uint32_t mc_latency_allowance_isp2_1;
+    }
+    la_scale_regs;
+
+    uint32_t unk_0;
+    uint32_t vtt_vdda_ctrl_0;
+    uint32_t src_clock_div;
+    uint32_t vtt_vdda_dual_channel;
+    uint32_t vtt_vdda_ctrl_1;
+    uint32_t vtt_vdda_ctrl_2;
+    uint32_t vtt_vdda_ctrl_3;
+    uint32_t vtt_vdda_ctrl_4;
+    uint32_t misc_cfg_0;
+    uint32_t misc_cfg_1;
+    uint32_t misc_cfg_2;
+    uint32_t unk_1;
+    uint32_t unk_2;
+    uint32_t pipe_clk_delay;
+    uint32_t clkchange_delay;
+    uint32_t pllm_ss_cfg;
+    uint32_t pllm_ss_ctrl1;
+    uint32_t pllm_ss_ctrl2;
+    uint32_t pllmb_ss_cfg;
+    uint32_t pllmb_ss_ctrl1;
+    uint32_t pllmb_ss_ctrl2;
+    uint32_t pllmb_divm;
+    uint32_t pllmb_divn;
+    uint32_t pllmb_divp;
+    uint32_t min_mrs_wait;
+    uint32_t ramp_wait;
+    uint32_t emc_mrw;
+    uint32_t emc_mrw2;
+    uint32_t emc_mrw3;
+    uint32_t emc_mrw4;
+    uint32_t emc_mrw9;
+    uint32_t emc_mrs;
+    uint32_t emc_emrs;
+    uint32_t emc_emrs2;
+    uint32_t emc_auto_cal_config;
+    uint32_t emc_auto_cal_config2;
+    uint32_t emc_auto_cal_config3;
+    uint32_t emc_auto_cal_config4;
+    uint32_t emc_auto_cal_config5;
+    uint32_t emc_auto_cal_config6;
+    uint32_t emc_auto_cal_config7;
+    uint32_t emc_auto_cal_config8;
+    uint32_t emc_cfg_2;
+    uint32_t emc_sel_dpd_ctrl;
+    uint32_t emc_fdpd_ctrl_cmd_no_ramp;
+    uint32_t emc_tr_ctrl_0;
+    uint32_t dll_clk_src;
+    uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
+    uint32_t latency;
+    uint32_t pllm_misc1_0_pllm_clamp_ph90;
+};
+
+static_assert(sizeof(MarikoMtcTable) == 0x10CC);
+
+struct EristaMtcTable {
+    uint32_t rev;
+    char dvfs_ver[60];
+    uint32_t rate_khz;
+    uint32_t min_volt;
+    uint32_t gpu_min_volt;
+    char clock_src[32];
+    uint32_t clk_src_emc;
+    uint32_t needs_training;
+    uint32_t training_pattern;
+    uint32_t trained;
+
+    uint32_t periodic_training;
+    uint32_t trained_dram_clktree_c0d0u0;
+    uint32_t trained_dram_clktree_c0d0u1;
+    uint32_t trained_dram_clktree_c0d1u0;
+    uint32_t trained_dram_clktree_c0d1u1;
+    uint32_t trained_dram_clktree_c1d0u0;
+    uint32_t trained_dram_clktree_c1d0u1;
+    uint32_t trained_dram_clktree_c1d1u0;
+    uint32_t trained_dram_clktree_c1d1u1;
+    uint32_t current_dram_clktree_c0d0u0;
+    uint32_t current_dram_clktree_c0d0u1;
+    uint32_t current_dram_clktree_c0d1u0;
+    uint32_t current_dram_clktree_c0d1u1;
+    uint32_t current_dram_clktree_c1d0u0;
+    uint32_t current_dram_clktree_c1d0u1;
+    uint32_t current_dram_clktree_c1d1u0;
+    uint32_t current_dram_clktree_c1d1u1;
+    uint32_t run_clocks;
+    uint32_t tree_margin;
+
+    uint32_t num_burst;
+    uint32_t num_burst_per_ch;
+    uint32_t num_trim;
+    uint32_t num_trim_per_ch;
+    uint32_t num_mc_regs;
+    uint32_t num_up_down;
+    uint32_t vref_num;
+    uint32_t training_mod_num;
+    uint32_t dram_timing_num;
+
+    uint32_t ptfv_dqsosc_movavg_c0d0u0;
+    uint32_t ptfv_dqsosc_movavg_c0d0u1;
+    uint32_t ptfv_dqsosc_movavg_c0d1u0;
+    uint32_t ptfv_dqsosc_movavg_c0d1u1;
+    uint32_t ptfv_dqsosc_movavg_c1d0u0;
+    uint32_t ptfv_dqsosc_movavg_c1d0u1;
+    uint32_t ptfv_dqsosc_movavg_c1d1u0;
+    uint32_t ptfv_dqsosc_movavg_c1d1u1;
+    uint32_t ptfv_write_samples;
+    uint32_t ptfv_dvfs_samples;
+    uint32_t ptfv_movavg_weight;
+    uint32_t ptfv_config_ctrl;
+
+    EristaTiming burst_regs;
+
+    struct {
+        uint32_t emc0_mrw10;
+        uint32_t emc1_mrw10;
+        uint32_t emc0_mrw11;
+        uint32_t emc1_mrw11;
+        uint32_t emc0_mrw12;
+        uint32_t emc1_mrw12;
+        uint32_t emc0_mrw13;
+        uint32_t emc1_mrw13;
+    }
+    burst_perch_regs;
+
+    EristaTiming shadow_regs_ca_train;
+
+    EristaTiming shadow_regs_quse_train;
+
+    EristaTiming shadow_regs_rdwr_train;
+
+    struct {
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2;
+        uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_2;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_0;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_1;
+        uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_2;
+        uint32_t emc_pmacro_ib_vref_dqs_0;
+        uint32_t emc_pmacro_ib_vref_dqs_1;
+        uint32_t emc_pmacro_ib_vref_dq_0;
+        uint32_t emc_pmacro_ib_vref_dq_1;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2;
+        uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_2;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_0;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_1;
+        uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_2;
+        uint32_t emc_pmacro_quse_ddll_rank0_0;
+        uint32_t emc_pmacro_quse_ddll_rank0_1;
+        uint32_t emc_pmacro_quse_ddll_rank0_2;
+        uint32_t emc_pmacro_quse_ddll_rank0_3;
+        uint32_t emc_pmacro_quse_ddll_rank1_0;
+        uint32_t emc_pmacro_quse_ddll_rank1_1;
+        uint32_t emc_pmacro_quse_ddll_rank1_2;
+        uint32_t emc_pmacro_quse_ddll_rank1_3;
+    }
+    trim_regs;
+
+    struct {
+        uint32_t emc0_cmd_brlshft_0;
+        uint32_t emc1_cmd_brlshft_1;
+        uint32_t emc0_data_brlshft_0;
+        uint32_t emc1_data_brlshft_0;
+        uint32_t emc0_data_brlshft_1;
+        uint32_t emc1_data_brlshft_1;
+        uint32_t emc0_quse_brlshft_0;
+        uint32_t emc1_quse_brlshft_1;
+        uint32_t emc0_quse_brlshft_2;
+        uint32_t emc1_quse_brlshft_3;
+    }
+    trim_perch_regs;
+
+    struct {
+        uint32_t emc0_training_opt_dqs_ib_vref_rank0;
+        uint32_t emc1_training_opt_dqs_ib_vref_rank0;
+        uint32_t emc0_training_opt_dqs_ib_vref_rank1;
+        uint32_t emc1_training_opt_dqs_ib_vref_rank1;
+    }
+    vref_perch_regs;
+
+    struct {
+        uint32_t t_rp;
+        uint32_t t_fc_lpddr4;
+        uint32_t t_rfc;
+        uint32_t t_pdex;
+        uint32_t rl;
+    }
+    dram_timings;
+
+    struct {
+        uint32_t emc0_training_rw_offset_ib_byte0;
+        uint32_t emc1_training_rw_offset_ib_byte0;
+        uint32_t emc0_training_rw_offset_ib_byte1;
+        uint32_t emc1_training_rw_offset_ib_byte1;
+        uint32_t emc0_training_rw_offset_ib_byte2;
+        uint32_t emc1_training_rw_offset_ib_byte2;
+        uint32_t emc0_training_rw_offset_ib_byte3;
+        uint32_t emc1_training_rw_offset_ib_byte3;
+        uint32_t emc0_training_rw_offset_ib_misc;
+        uint32_t emc1_training_rw_offset_ib_misc;
+        uint32_t emc0_training_rw_offset_ob_byte0;
+        uint32_t emc1_training_rw_offset_ob_byte0;
+        uint32_t emc0_training_rw_offset_ob_byte1;
+        uint32_t emc1_training_rw_offset_ob_byte1;
+        uint32_t emc0_training_rw_offset_ob_byte2;
+        uint32_t emc1_training_rw_offset_ob_byte2;
+        uint32_t emc0_training_rw_offset_ob_byte3;
+        uint32_t emc1_training_rw_offset_ob_byte3;
+        uint32_t emc0_training_rw_offset_ob_misc;
+        uint32_t emc1_training_rw_offset_ob_misc;
+    }
+    training_mod_regs;
+
+    uint32_t save_restore_mod_regs[12];
+
+    struct {
+        uint32_t mc_emem_arb_cfg;
+        uint32_t mc_emem_arb_outstanding_req;
+        uint32_t mc_emem_arb_refpb_hp_ctrl;
+        uint32_t mc_emem_arb_refpb_bank_ctrl;
+        uint32_t mc_emem_arb_timing_rcd;
+        uint32_t mc_emem_arb_timing_rp;
+        uint32_t mc_emem_arb_timing_rc;
+        uint32_t mc_emem_arb_timing_ras;
+        uint32_t mc_emem_arb_timing_faw;
+        uint32_t mc_emem_arb_timing_rrd;
+        uint32_t mc_emem_arb_timing_rap2pre;
+        uint32_t mc_emem_arb_timing_wap2pre;
+        uint32_t mc_emem_arb_timing_r2r;
+        uint32_t mc_emem_arb_timing_w2w;
+        uint32_t mc_emem_arb_timing_r2w;
+        uint32_t mc_emem_arb_timing_ccdmw;
+        uint32_t mc_emem_arb_timing_w2r;
+        uint32_t mc_emem_arb_timing_rfcpb;
+        uint32_t mc_emem_arb_da_turns;
+        uint32_t mc_emem_arb_da_covers;
+        uint32_t mc_emem_arb_misc0;
+        uint32_t mc_emem_arb_misc1;
+        uint32_t mc_emem_arb_misc2;
+        uint32_t mc_emem_arb_ring1_throttle;
+        uint32_t mc_emem_arb_dhyst_ctrl;
+        uint32_t mc_emem_arb_dhyst_timeout_util_0;
+        uint32_t mc_emem_arb_dhyst_timeout_util_1;
+        uint32_t mc_emem_arb_dhyst_timeout_util_2;
+        uint32_t mc_emem_arb_dhyst_timeout_util_3;
+        uint32_t mc_emem_arb_dhyst_timeout_util_4;
+        uint32_t mc_emem_arb_dhyst_timeout_util_5;
+        uint32_t mc_emem_arb_dhyst_timeout_util_6;
+        uint32_t mc_emem_arb_dhyst_timeout_util_7;
+    }
+    burst_mc_regs;
+
+    struct {
+        uint32_t mc_mll_mpcorer_ptsa_rate;
+        uint32_t mc_ftop_ptsa_rate;
+        uint32_t mc_ptsa_grant_decrement;
+        uint32_t mc_latency_allowance_xusb_0;
+        uint32_t mc_latency_allowance_xusb_1;
+        uint32_t mc_latency_allowance_tsec_0;
+        uint32_t mc_latency_allowance_sdmmca_0;
+        uint32_t mc_latency_allowance_sdmmcaa_0;
+        uint32_t mc_latency_allowance_sdmmc_0;
+        uint32_t mc_latency_allowance_sdmmcab_0;
+        uint32_t mc_latency_allowance_ppcs_0;
+        uint32_t mc_latency_allowance_ppcs_1;
+        uint32_t mc_latency_allowance_mpcore_0;
+        uint32_t mc_latency_allowance_hc_0;
+        uint32_t mc_latency_allowance_hc_1;
+        uint32_t mc_latency_allowance_avpc_0;
+        uint32_t mc_latency_allowance_gpu_0;
+        uint32_t mc_latency_allowance_gpu2_0;
+        uint32_t mc_latency_allowance_nvenc_0;
+        uint32_t mc_latency_allowance_nvdec_0;
+        uint32_t mc_latency_allowance_vic_0;
+        uint32_t mc_latency_allowance_vi2_0;
+        uint32_t mc_latency_allowance_isp2_0;
+        uint32_t mc_latency_allowance_isp2_1;
+    }
+    la_scale_regs;
+
+    uint32_t min_mrs_wait;
+    uint32_t emc_mrw;
+    uint32_t emc_mrw2;
+    uint32_t emc_mrw3;
+    uint32_t emc_mrw4;
+    uint32_t emc_mrw9;
+    uint32_t emc_mrs;
+    uint32_t emc_emrs;
+    uint32_t emc_emrs2;
+    uint32_t emc_auto_cal_config;
+    uint32_t emc_auto_cal_config2;
+    uint32_t emc_auto_cal_config3;
+    uint32_t emc_auto_cal_config4;
+    uint32_t emc_auto_cal_config5;
+    uint32_t emc_auto_cal_config6;
+    uint32_t emc_auto_cal_config7;
+    uint32_t emc_auto_cal_config8;
+    uint32_t emc_cfg_2;
+    uint32_t emc_sel_dpd_ctrl;
+    uint32_t emc_fdpd_ctrl_cmd_no_ramp;
+    uint32_t dll_clk_src;
+    uint32_t clk_out_enb_x_0_clk_enb_emc_dll;
+    uint32_t latency;
+};
+
+static_assert(sizeof(EristaMtcTable) == 0x1340);
diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/test.cpp b/Source/Atmosphere/stratosphere/loader/source/oc/test.cpp
new file mode 100644
index 00000000..bc03ce5d
--- /dev/null
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/test.cpp
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) Switch-OC-Suite
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifdef OC_TEST
+#include <cstdio>
+#include <cstring>
+#include <cstdlib>
+
+namespace ams::ldr::oc {
+    namespace pcv {
+        void Patch(uintptr_t mapped_nso, size_t nso_size);
+    }
+
+    namespace ptm {
+        void Patch(uintptr_t mapped_nso, size_t nso_size);
+    }
+}
+
+static void* ReadFile(const char* file_loc, long* out_size) {
+    FILE* fp;
+    void* buf;
+    long size;
+
+    fp = fopen(file_loc, "r");
+    if (!fp) {
+        fprintf(stderr, "Cannot open file: %s\n", file_loc);
+        exit(-1);
+    }
+
+    fseek(fp, 0, SEEK_END);
+    size = ftell(fp);
+    fseek(fp, 0, SEEK_SET);
+    buf = malloc((size + 1) * sizeof(char));
+    fread(buf, sizeof(char), size, fp);
+    fclose(fp);
+    if (size < 8192) {
+        fprintf(stderr, "File is too small to process: %u Bytes\n", size);
+        exit(-1);
+    }
+
+    *out_size = size;
+    return buf;
+}
+
+int main(int argc, char** argv) {
+    const char* pcv_opt = "-pcv";
+    const char* ptm_opt = "-ptm";
+    enum {
+        EXE_PCV,
+        EXE_PTM,
+        UNKNOWN
+    };
+    int option = UNKNOWN;
+    if (argc == 3) {
+        if (!strcmp(argv[1], pcv_opt))
+            option = EXE_PCV;
+
+        if (!strcmp(argv[1], ptm_opt))
+            option = EXE_PTM;
+    }
+    if (option == UNKNOWN) {
+        fprintf(stderr, "Usage: %s %s/%s <executable>\n", argv[0], pcv_opt, ptm_opt);
+        return -1;
+    }
+
+    long file_size;
+    void* file_buffer = ReadFile(argv[2], &file_size);
+    uintptr_t mapped_exe = reinterpret_cast<uintptr_t>(file_buffer);
+    size_t exe_size = reinterpret_cast<size_t>(file_size * sizeof(char));
+    switch (option) {
+        case EXE_PCV:
+            ams::ldr::oc::pcv::Patch(mapped_exe, exe_size);
+            break;
+        case EXE_PTM:
+            ams::ldr::oc::ptm::Patch(mapped_exe, exe_size);
+            break;
+    }
+    free(file_buffer);
+    printf("Passed!\n");
+    return 0;
+}
+#endif