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emc overvolt

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KazushiM
2021-11-26 15:42:43 +08:00
parent 3279aab56c
commit b41946799e
6 changed files with 62 additions and 41 deletions
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17
README.md
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@@ -40,14 +40,15 @@ Overclocking suite for Switch **(Mariko Only)** running on Atmosphere CFW. Suppo
- **RAM clock is set permanently** via **ptm-patch**, rather than sys-clk. - **RAM clock is set permanently** via **ptm-patch**, rather than sys-clk.
- Use Hekate to check out the brand of your RAM chips. - Use Hekate to check out the brand of your RAM chips.
- EM shielding & thermal paste for RAM chips and testing with emuNAND before long-term usage. - EM shielding & thermal paste for RAM chips and testing with emuNAND before long-term usage.
- [WIP] [Mariko RAM overvolting](https://github.com/KazushiMe/Switch-OC-Suite/issues/5): hekate bootloader is required - RAM overvolting: precompiled hekate bootloader is provided
- Let me know if you get stable 1996.8-2131.2MHz to work. Reply in the issue, or DM me in Discord: Hirochi_6831(replace _ with #) - Edit `oc.ini` to change Vddq voltage values:
- Testing voltage > 650mV (not recommended): ```ini
- ```shell [emc]
cd $hekate_repo volt=600000
curl https://github.com/KazushiMe/Switch-OC-Suite/raw/master/Source/hekate.diff | git apply ```
``` - Overvolting beyond 650mV is not recommend and it might fry your DRAM.
- change Vddq voltage (600000) and `make -j` - > Even though Tegra X1+ supports LPDDR4/LPDDR4X, LPDDR4X DRAM chips are not required to be backward-compatible with, or resistant to LPDDR4 1.1V Vddq voltage.
- For more info on DRAM overvolting and timings, see [issue #5](https://github.com/KazushiMe/Switch-OC-Suite/issues/5)
- Mariko variants have much lower power consumption compared to Erista, therefore **GPU clock capping is lifted for Mariko**. - Mariko variants have much lower power consumption compared to Erista, therefore **GPU clock capping is lifted for Mariko**.
- For more info, see [README.md](https://github.com/KazushiMe/Switch-OC-Suite/tree/master/Source/sys-clk-OC) in sys-clk-OC. - For more info, see [README.md](https://github.com/KazushiMe/Switch-OC-Suite/tree/master/Source/sys-clk-OC) in sys-clk-OC.
- **Auto-Boost CPU for faster game loading** - **Auto-Boost CPU for faster game loading**

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SdOut/bootloader/update.bin Executable file
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2
SdOut/oc.ini Normal file
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@@ -0,0 +1,2 @@
[emc]
volt=600000

0
Source/Atmosphere/ldr_oc_patch.hpp → Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp
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0
Source/Atmosphere/ldr_patcher.cpp → Source/Atmosphere/stratosphere/loader/source/ldr_patcher.cpp
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84
Source/hekate.diff
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@@ -1,53 +1,71 @@
diff --git a/bdk/mem/sdram.c b/bdk/mem/sdram.c
index 00ec355..da4b149 100644
--- a/bdk/mem/sdram.c
+++ b/bdk/mem/sdram.c
@@ -34,6 +34,8 @@
#include <soc/t210.h>
#include <utils/util.h>
+#define DRAM_OVERVOLT 600000 // default: 600mV
+
#define CONFIG_SDRAM_KEEP_ALIVE
typedef struct _sdram_vendor_patch_t
@@ -1481,6 +1483,11 @@ static void _sdram_init_t210b01()
{
const sdram_params_t210b01_t *params = (const sdram_params_t210b01_t *)sdram_get_params_t210b01();
+#ifdef DRAM_OVERVOLT
+ // Set DRAM voltage.
+ max7762x_regulator_set_voltage(REGULATOR_77812_DRAM, DRAM_OVERVOLT);
+#endif
+
// VDDP Select.
PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel;
usleep(params->pmc_vddp_sel_wait);
diff --git a/bdk/power/max7762x.c b/bdk/power/max7762x.c diff --git a/bdk/power/max7762x.c b/bdk/power/max7762x.c
index a7d30ce..376c87e 100644 index a7d30ce..d074009 100644
--- a/bdk/power/max7762x.c --- a/bdk/power/max7762x.c
+++ b/bdk/power/max7762x.c +++ b/bdk/power/max7762x.c
@@ -92,7 +92,7 @@ static const max77620_regulator_t _pmic_regulators[] = { @@ -91,8 +91,8 @@ static const max77620_regulator_t _pmic_regulators[] = {
{ "max77621_CPU", 6250, 606250, 1000000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
{ "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} }, { "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
{ "max77812_CPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} }, { "max77812_CPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
//{ "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} }, - //{ "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
- //{ "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration. - //{ "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
+ { "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
+ { "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration. + { "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
}; };
static u8 _max77812_get_address() static u8 _max77812_get_address()
diff --git a/bdk/power/max7762x.h b/bdk/power/max7762x.h diff --git a/bdk/power/max7762x.h b/bdk/power/max7762x.h
index 3478530..d01f787 100644 index 3478530..7a3e518 100644
--- a/bdk/power/max7762x.h --- a/bdk/power/max7762x.h
+++ b/bdk/power/max7762x.h +++ b/bdk/power/max7762x.h
@@ -62,8 +62,8 @@ @@ -61,9 +61,9 @@
#define REGULATOR_CPU0 13
#define REGULATOR_GPU0 14 #define REGULATOR_GPU0 14
#define REGULATOR_CPU1 15 #define REGULATOR_CPU1 15
//#define REGULATOR_GPU1 16 -//#define REGULATOR_GPU1 16
-//#define REGULATOR_GPU1 17 -//#define REGULATOR_GPU1 17
-#define REGULATOR_MAX 15 -#define REGULATOR_MAX 15
+#define REGULATOR_77812_DRAM 16 +#define REGULATOR_GPU1 16
+#define REGULATOR_MAX 16 +#define REGULATOR_DRAM 17
+#define REGULATOR_MAX 17
#define MAX77621_CPU_I2C_ADDR 0x1B #define MAX77621_CPU_I2C_ADDR 0x1B
#define MAX77621_GPU_I2C_ADDR 0x1C #define MAX77621_GPU_I2C_ADDR 0x1C
diff --git a/bootloader/main.c b/bootloader/main.c
index 62f4f5d..9506869 100644
--- a/bootloader/main.c
+++ b/bootloader/main.c
@@ -1503,6 +1503,34 @@ void ipl_main()
if (minerva_init()) //!TODO: Add Tegra210B01 support to minerva.
h_cfg.errors |= ERR_LIBSYS_MTC;
+ // DRAM overvolt.
+ if (h_cfg.t210b01)
+ {
+ u32 dram_uV = 0;
+
+ LIST_INIT(ini_sections);
+ if (ini_parse(&ini_sections, "oc.ini", false))
+ {
+ LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link)
+ {
+ // Only parse emc section.
+ if (strcmp(ini_sec->name, "emc"))
+ continue;
+
+ LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link)
+ {
+ if (!strcmp("volt", kv->key))
+ dram_uV = atoi(kv->val);
+ }
+
+ break;
+ }
+ }
+
+ if (dram_uV)
+ max7762x_regulator_set_voltage(REGULATOR_DRAM, dram_uV);
+ }
+
display_init();
u32 *fb = display_init_framebuffer_pitch();