From b32efcc177f89b68fa71296ac7724e750ff90f4a Mon Sep 17 00:00:00 2001 From: Lightos1 <124387232+Lightos1@users.noreply.github.com> Date: Sun, 15 Feb 2026 01:27:50 +0100 Subject: [PATCH] Erista: dvb + more precise timings/timings from eos & formating --- .../source/oc/mariko/calculate_timings.hpp | 1 + .../loader/source/oc/mtc_timing_value.hpp | 63 +-- .../loader/source/oc/pcv/pcv_erista.cpp | 423 +++--------------- .../loader/source/oc/pcv/pcv_mariko.cpp | 38 +- 4 files changed, 128 insertions(+), 397 deletions(-) diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/mariko/calculate_timings.hpp b/Source/Atmosphere/stratosphere/loader/source/oc/mariko/calculate_timings.hpp index a885c323..4671b734 100644 --- a/Source/Atmosphere/stratosphere/loader/source/oc/mariko/calculate_timings.hpp +++ b/Source/Atmosphere/stratosphere/loader/source/oc/mariko/calculate_timings.hpp @@ -19,5 +19,6 @@ namespace ams::ldr::hoc::pcv::mariko { void CalculateTimings(); + void CalculateMrw2(); } diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp index 4d8d45a3..ff769475 100644 --- a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp +++ b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp @@ -79,52 +79,60 @@ namespace ams::ldr::hoc { namespace pcv::erista { const double tCK_avg = 1000'000.0 / C.eristaEmcMaxClock; - const u32 tRCD = tRCD_values[C.t1_tRCD]; - const u32 tRPpb = tRP_values[C.t2_tRP]; - const u32 tRAS = tRAS_values[C.t3_tRAS]; + const u32 tRCD = tRCD_values[C.t1_tRCD]; + const u32 tRPpb = tRP_values[C.t2_tRP]; + const u32 tRAS = tRAS_values[C.t3_tRAS]; const double tRRD = tRRD_values[C.t4_tRRD]; - const u32 tRFCpb = tRFC_values[C.t5_tRFC]; - const u32 tWTR = 10 - tWTR_values[C.t7_tWTR]; + const u32 tRFCpb = tRFC_values[C.t5_tRFC]; + const u32 tWTR = 10 - tWTR_values[C.t7_tWTR]; + const s32 finetRTW = C.fineTune_t6_tRTW; + const s32 finetWTR = C.fineTune_t7_tWTR; - const u32 tRC = tRAS + tRPpb; - const u32 tRFCab = tRFCpb * 2; - const double tXSR = (double) (tRFCab + 7.5); - const u32 tFAW = static_cast(tRRD * 4.0); + const u32 tRC = tRAS + tRPpb; + const u32 tRFCab = tRFCpb * 2; + const double tXSR = static_cast(tRFCab + 7.5); + const u32 tFAW = static_cast(tRRD * 4.0); const double tRPab = tRPpb + 3; - const u32 tR2P = 12; + const u32 tR2P = CEIL((RL_DBI * 0.426) - 2.0); + const u32 tR2W = FLOOR(FLOOR((5.0 / tCK_avg) + ((FLOOR(48.0 / WL) - 0.478) * 3.0)) / 1.501) + RL_DBI - (C.t6_tRTW * 3) + finetRTW; + inline u32 rext; - const u32 tW2P = (CEIL(WL * 1.7303) * 2) - 5; - const u32 tW2R = CEIL(MAX(WL + (0.010322547033278747 * (C.eristaEmcMaxClock / 1000.0)), (WL * -0.2067922202979121) + FLOOR(((RL_DBI * -0.1331159971685554) + WL) * 3.654131957826108)) - (tWTR / tCK_avg)); + const u32 rdv = RL_DBI + FLOOR((5.105 / tCK_avg) + 17.017); + const u32 qpop = rdv - 14; + const u32 quse_width = CEIL(((4.897 / tCK_avg) - FLOOR(2.538 / tCK_avg)) + 3.782); + const u32 quse = FLOOR(RL_DBI + ((5.082 / tCK_avg) + FLOOR(2.560 / tCK_avg))) - CEIL(4.820 / tCK_avg); + const u32 einput_duration = FLOOR(9.936 / tCK_avg) + 5.0 + quse_width; + const u32 einput = quse - CEIL(9.928 / tCK_avg); + const u32 qrst_duration = FLOOR(8.399 - tCK_avg); + const u32 qrstLow = MAX(static_cast(einput - qrst_duration - 2), static_cast(0)); + const u32 qrst = PACK_U32(qrst_duration, qrstLow); + const u32 ibdly = PACK_U32_NIBBLE_HIGH_BYTE_LOW(1, quse - qrst_duration - 2.0); + const u32 qsafe = (einput_duration + 3) + MAX(MIN(qrstLow * rdv, qrst_duration + qrst_duration), einput); + const u32 tW2P = (CEIL(WL * 1.7303) * 2) - 5; + const u32 tWTPDEN = CEIL(((1.803 / tCK_avg) + MAX(RL_DBI + (2.694 / tCK_avg), static_cast(tW2P))) + (BL / 2)); + const u32 tW2R = FLOOR(MAX((5.020 / tCK_avg) + 1.130, WL - MAX(-CEIL(0.258 * (WL - RL_DBI)), 1.964)) * 1.964) + WL - CEIL(tWTR / tCK_avg) + finetWTR; const u32 wdv = WL; const u32 wsv = WL - 2; const u32 wev = 0xA + (WL - 14); - const double freq_mhz = C.eristaEmcMaxClock / 1000.0; - - const u32 quse_width = CEIL(((3.7165006256863955 - freq_mhz) + (-0.002446584377651142 * freq_mhz)) - FLOOR(freq_mhz / -0.9952024303111688)); - const u32 quse = CEIL(MIN(RL_DBI + (2.991255208275918 - (quse_width + (-0.00511180626826906 * freq_mhz))), freq_mhz * 0.021333773138874437)); - const u32 ibdly = 0x10000000 + FLOOR(MAX(RL_DBI - 1.9999956603408224, quse - 5.9999987787411175) + (-0.0011929079761504341 * freq_mhz)); const u32 obdlyHigh = 3 / FLOOR(MIN(static_cast(2), tCK_avg * (WL - 7))); - const u32 obdlyLow = WL - MIN(static_cast(WL), 12 - (CEIL(-0.0003991 * freq_mhz) * 2)); + const u32 obdlyLow = MAX(WL - FLOOR((126.0 / CEIL(tCK_avg + 8.601))), 0.0); const u32 obdly = PACK_U32_NIBBLE_HIGH_BYTE_LOW(obdlyHigh, obdlyLow); - const u32 tCKE = CEIL(1.0795 * CEIL(0.0074472 * (C.eristaEmcMaxClock / 1000.0))); - const double tMMRI = tRCD + (tCK_avg * 3); - const double pdex2mrr = tMMRI + 10; - const u32 tWTPDEN = tW2P + 1 + CEIL(tDQSS_max / tCK_avg) + CEIL(tDQS2DQ_max / tCK_avg) + 6; - const u32 tR2W = CEIL(RL_DBI + (tDQSCK_max / tCK_avg) + (BL / 2) - WL + tWPRE + FLOOR(tRPST) + 9.0) - (C.t6_tRTW * 3); + const u32 pdex2rw = CEIL((CEIL(12.335 - tCK_avg) + (7.430 / tCK_avg) - CEIL(tCK_avg * 11.361))); - const double pdex_local = (0.011 * freq_mhz) - 1.443; - const u32 pdex2rw = static_cast(ROUND(pdex_local)) < 22 ? 22 : (static_cast(ROUND(pdex_local)) > 33 ? 33 : static_cast(ROUND(pdex_local))); + const u32 tCLKSTOP = FLOOR(MIN(8.488 / tCK_avg, 23.0)) + 8.0; - const double cke2pden = (static_cast((C.eristaEmcMaxClock / 1000.0) * 0.00875) - 0.65); + const double tMMRI = tRCD + (tCK_avg * 3); + const double pdex2mrr = tMMRI + 10; /* Do this properly? */ + + inline u8 mrw2; } namespace pcv::mariko { const double tCK_avg = 1000'000.0 / C.marikoEmcMaxClock; - const double ramFreqMhz = C.marikoEmcMaxClock / 1000.0; const u32 tRCD = tRCD_values[C.t1_tRCD]; const u32 tRPpb = tRP_values[C.t2_tRP]; @@ -170,7 +178,6 @@ namespace ams::ldr::hoc { const u32 obdlyHigh = 3 / FLOOR(MIN(static_cast(2), tCK_avg * (WL - 7))); const u32 obdlyLow = MAX(WL - FLOOR((126.0 / CEIL(tCK_avg + 8.601))), 0.0); - const u32 obdly = PACK_U32_NIBBLE_HIGH_BYTE_LOW(obdlyHigh, obdlyLow); const u32 pdex2rw = CEIL((CEIL(12.335 - tCK_avg) + (7.430 / tCK_avg) - CEIL(tCK_avg * 11.361))); diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp index f9e83081..5618a6cc 100644 --- a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp +++ b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp @@ -20,6 +20,7 @@ #include "pcv.hpp" #include "../mtc_timing_value.hpp" +#include "../mariko/calculate_timings.hpp" namespace ams::ldr::hoc::pcv::erista { @@ -180,318 +181,9 @@ namespace ams::ldr::hoc::pcv::erista { R_SUCCEED(); } - // void MemMtcTableAutoAdjustBaseLatency(EristaMtcTable *table) { - // using namespace pcv::erista; - /* #define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \ - TABLE->burst_regs.PARAM = VALUE; \ - TABLE->shadow_regs_ca_train.PARAM = VALUE; \ - TABLE->shadow_regs_quse_train.PARAM = VALUE; \ - TABLE->shadow_regs_rdwr_train.PARAM = VALUE; -*/ - // #define GET_CYCLE(PARAM) ((u32)((double)(PARAM) / tCK_avg)) - - /* This condition is insane but it's done in eos. */ - /* Need to clean up at some point. */ - // u32 rext; - // u32 wext; - // if (C.eristaEmcMaxClock < 3200001) { - // if (C.eristaEmcMaxClock < 2133001) { - // rext = 26; - // wext = 22; - // } else { - // rext = 28; - // wext = 22; - // - // if (2400000 < C.eristaEmcMaxClock) { - // wext = 25; - // } - // } - // } else { - // rext = 30; - // wext = 25; - // } - - // u32 refresh_raw = 0xFFFF; - // u32 trefbw = 0; - // - // if (C.t8_tREFI != 6) { - // refresh_raw = static_cast(std::floor(static_cast(tREFpb_values[C.t8_tREFI]) / tCK_avg)) - 0x40; - // refresh_raw = MIN(refresh_raw, static_cast(0xFFFF)); - // } - // - // trefbw = refresh_raw + 0x40; - // trefbw = MIN(trefbw, static_cast(0x3FFF)); - // - // if (C.hpMode) { - // WRITE_PARAM_ALL_REG(table, emc_cfg, 0x13200000); - // } else { - // WRITE_PARAM_ALL_REG(table, emc_cfg, 0xF3200000); - // } - - // WRITE_PARAM_ALL_REG(table, emc_rc, /*0x00000060*/ GET_CYCLE(tRC)); - // WRITE_PARAM_ALL_REG(table, emc_rfc, /*0x00000120*/ GET_CYCLE(tRFCab)); - // WRITE_PARAM_ALL_REG(table, emc_ras, /*0x00000044*/ GET_CYCLE(tRAS)); - // WRITE_PARAM_ALL_REG(table, emc_rp, /*0x0000001D*/ GET_CYCLE(tRPpb)); - // WRITE_PARAM_ALL_REG(table, emc_r2w, /*0x0000002A*/ tR2W); - // WRITE_PARAM_ALL_REG(table, emc_w2r, /*0x00000021*/ tW2R); - // WRITE_PARAM_ALL_REG(table, emc_r2p, 0x0000000C); - // WRITE_PARAM_ALL_REG(table, emc_w2p, 0x0000002D); - // WRITE_PARAM_ALL_REG(table, emc_rd_rcd, /*0x0000001D*/ GET_CYCLE(tRCD)); - // WRITE_PARAM_ALL_REG(table, emc_wr_rcd, /*0x0000001D*/ GET_CYCLE(tRCD)); - // WRITE_PARAM_ALL_REG(table, emc_rrd, /*0x00000010*/ GET_CYCLE(tRRD)); - // WRITE_PARAM_ALL_REG(table, emc_rext, 0x00000017); - // WRITE_PARAM_ALL_REG(table, emc_wdv, 0x0000000E); - // WRITE_PARAM_ALL_REG(table, emc_quse, 0x00000024); - // WRITE_PARAM_ALL_REG(table, emc_qrst, 0x0006000C); - // WRITE_PARAM_ALL_REG(table, emc_qsafe, 0x00000034); - // WRITE_PARAM_ALL_REG(table, emc_rdv, 0x0000003C); - // WRITE_PARAM_ALL_REG(table, emc_refresh, /*0x00001820*/ refresh_raw); - // WRITE_PARAM_ALL_REG(table, emc_burst_refresh_num, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_pdex2wr, 0x00000010); - // WRITE_PARAM_ALL_REG(table, emc_pdex2rd, 0x00000010); - // WRITE_PARAM_ALL_REG(table, emc_pchg2pden, 0x00000003); - // WRITE_PARAM_ALL_REG(table, emc_act2pden, 0x00000003); - // WRITE_PARAM_ALL_REG(table, emc_ar2pden, 0x00000003); - // WRITE_PARAM_ALL_REG(table, emc_rw2pden, /*0x00000038*/ GET_CYCLE(tRW2PDEN)); - // WRITE_PARAM_ALL_REG(table, emc_txsr, /*0x0000012C*/ MIN(GET_CYCLE(tXSR), (u32) 1022)); - // WRITE_PARAM_ALL_REG(table, emc_tcke, 0x0000000D); - // WRITE_PARAM_ALL_REG(table, emc_tfaw, /*0x00000040*/ GET_CYCLE(tFAW)); - // WRITE_PARAM_ALL_REG(table, emc_trpab, /*0x00000022*/ GET_CYCLE(tRPab)); - // WRITE_PARAM_ALL_REG(table, emc_tclkstable, 0x00000004); - // WRITE_PARAM_ALL_REG(table, emc_tclkstop, 0x00000014); - // WRITE_PARAM_ALL_REG(table, emc_trefbw, /* 0x00001860*/ trefbw); - // WRITE_PARAM_ALL_REG(table, emc_tppd, 0x00000004); - // WRITE_PARAM_ALL_REG(table, emc_odt_write, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_pdex2mrr, /*0x0000002E*/ GET_CYCLE(pdex2mrr)); - // WRITE_PARAM_ALL_REG(table, emc_wext, 0x00000016); - // WRITE_PARAM_ALL_REG(table, emc_rfc_slr, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_mrs_wait_cnt2, 0x01900017); - // WRITE_PARAM_ALL_REG(table, emc_mrs_wait_cnt, 0x0640002F); - // // table->emc_mrs = 0x00000000; - // // table->emc_emrs = 0x00000000; - // // table->emc_mrw = 0x00170040; - // WRITE_PARAM_ALL_REG(table, emc_fbio_spare, 0x00000012); - // WRITE_PARAM_ALL_REG(table, emc_fbio_cfg5, 0x9960A00D); - // WRITE_PARAM_ALL_REG(table, emc_pdex2cke, 0x00000002); - // WRITE_PARAM_ALL_REG(table, emc_cke2pden, 0x0000000E); - // // table->emc_emrs2 = 0x00000000; - // // table->emc_mrw2 = 0x0802002D; - // // table->emc_mrw3 = 0x0C0D00C0; - // // table->emc_mrw4 = 0xC0000000; - // WRITE_PARAM_ALL_REG(table, emc_r2r, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_einput, 0x00000014); - // WRITE_PARAM_ALL_REG(table, emc_einput_duration, 0x0000001D); - // WRITE_PARAM_ALL_REG(table, emc_puterm_extra, 0x0000001F); - // WRITE_PARAM_ALL_REG(table, emc_tckesr, 0x00000018); - // WRITE_PARAM_ALL_REG(table, emc_tpd, 0x0000000C); - // table->emc_auto_cal_config = 0x201A51D8; - // table->emc_cfg_2 = 0x00110835; - // WRITE_PARAM_ALL_REG(table, emc_cfg_dig_dll, 0x002C03A9); - // WRITE_PARAM_ALL_REG(table, emc_cfg_dig_dll_period, 0x00008000); - // WRITE_PARAM_ALL_REG(table, emc_rdv_mask, 0x0000003E); - // WRITE_PARAM_ALL_REG(table, emc_wdv_mask, 0x0000000E); - // WRITE_PARAM_ALL_REG(table, emc_rdv_early_mask, 0x0000003C); - // WRITE_PARAM_ALL_REG(table, emc_rdv_early, 0x0000003A); - // table->emc_auto_cal_config8 = 0x00770000; - // WRITE_PARAM_ALL_REG(table, emc_zcal_interval, 0x00064000); - // WRITE_PARAM_ALL_REG(table, emc_zcal_wait_cnt, 0x00310640); - // WRITE_PARAM_ALL_REG(table, emc_fdpd_ctrl_dq, 0x8020221F); - // WRITE_PARAM_ALL_REG(table, emc_fdpd_ctrl_cmd, 0x0220F40F); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_cmd_brick_ctrl_fdpd, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_data_brick_ctrl_fdpd, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_brick_ctrl_rfu1, 0x1FFF1FFF); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_brick_ctrl_rfu2, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_tr_timing_0, 0x01186190); - // // WRITE_PARAM_ALL_REG(table, emc_tr_ctrl_1, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_tr_rdv, 0x0000003C); - // table->emc_sel_dpd_ctrl = 0x00040000; - // WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, /*0x00000608*/ (u32) (refresh_raw / 4)); - // WRITE_PARAM_ALL_REG(table, emc_dyn_self_ref_control, 0x8000308C); - // WRITE_PARAM_ALL_REG(table, emc_txsrdll, /*0x0000012C*/ MIN(GET_CYCLE(tXSR), (u32) 1022)); - // WRITE_PARAM_ALL_REG(table, emc_tr_qpop, 0x0000002C); - // WRITE_PARAM_ALL_REG(table, emc_tr_rdv_mask, 0x0000003E); - // WRITE_PARAM_ALL_REG(table, emc_tr_qsafe, 0x00000034); - // WRITE_PARAM_ALL_REG(table, emc_tr_qrst, 0x0006000C); - // table->emc_auto_cal_config2 = 0x05500000; - // table->emc_auto_cal_config3 = 0x00770000; - // // WRITE_PARAM_ALL_REG(table, emc_tr_dvfs, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_auto_cal_channel, 0xC1E0030A); - // WRITE_PARAM_ALL_REG(table, emc_ibdly, 0x1000001C); - // WRITE_PARAM_ALL_REG(table, emc_obdly, 0x10000002); - // WRITE_PARAM_ALL_REG(table, emc_txdsrvttgen, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_we_duration, 0x0000000D); - // WRITE_PARAM_ALL_REG(table, emc_ws_duration, 0x00000008); - // WRITE_PARAM_ALL_REG(table, emc_wev, 0x0000000A); - // WRITE_PARAM_ALL_REG(table, emc_wsv, 0x0000000C); - // WRITE_PARAM_ALL_REG(table, emc_cfg_3, 0x00000040); - // // WRITE_PARAM_ALL_REG(table, emc_mrw6, 0x08037171); - // // WRITE_PARAM_ALL_REG(table, emc_mrw7, 0x48037171); - // // WRITE_PARAM_ALL_REG(table, emc_mrw8, 0x080B6666); - // // table->emc_mrw9 = 0x0C0E7272; - // // table->emc_mrw10 = 0x880C4848; - // // table->emc_mrw11 = 0x480C4848; /* Check them maybe */ - // // table->emc_mrw12 = 0x880E1718; - // // table->emc_mrw13 = 0x480E1814; - // // WRITE_PARAM_ALL_REG(table, emc_mrw14, 0x08161414); - // // WRITE_PARAM_ALL_REG(table, emc_mrw15, 0x48161414); - // // table->emc_fdpd_ctrl_cmd_no_ramp = 0x00000001; - // WRITE_PARAM_ALL_REG(table, emc_wdv_chk, 0x00000006); - // // WRITE_PARAM_ALL_REG(table, emc_cfg_pipe_2, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_cfg_pipe_1, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_cfg_pipe, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_qpop, 0x0000002C); - // WRITE_PARAM_ALL_REG(table, emc_quse_width, 0x00000009); - // WRITE_PARAM_ALL_REG(table, emc_puterm_width, 0x0000000E); - // table->emc_auto_cal_config7 = 0x00770000; - // // WRITE_PARAM_ALL_REG(table, emc_refctrl2, 0x00000000); - // WRITE_PARAM_ALL_REG(table, emc_fbio_cfg7, 0x00003BFF); - // WRITE_PARAM_ALL_REG(table, emc_rfcpb, /*0x00000090*/ GET_CYCLE(tRFCpb)); - // // WRITE_PARAM_ALL_REG(table, emc_dqs_brlshft_0, 0x00000000); /* brlshft may or may not be important, I don't think it matters but who knows. */ - // // WRITE_PARAM_ALL_REG(table, emc_dqs_brlshft_1, 0x00000000); - // table->emc_auto_cal_config4 = 0x00770000; - // table->emc_auto_cal_config5 = 0x00770000; - // WRITE_PARAM_ALL_REG(table, emc_ccdmw, 0x00000020); - // table->emc_auto_cal_config6 = 0x00770000; - // WRITE_PARAM_ALL_REG(table, emc_dll_cfg_0, 0x1F13612F); - // WRITE_PARAM_ALL_REG(table, emc_dll_cfg_1, 0x00000014); - // WRITE_PARAM_ALL_REG(table, emc_config_sample_delay, 0x00000020); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_tx_pwrd_0, 0x10000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_tx_pwrd_1, 0x08000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_tx_pwrd_2, 0x08000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_tx_pwrd_3, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_tx_pwrd_4, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_tx_pwrd_5, 0x00001000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_bypass, 0xEFFF2210); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_pwrd_0, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_pwrd_1, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_pwrd_2, 0xDCDCDCDC); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_cmd_ctrl_0, 0x0A0A0A0A); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_cmd_ctrl_1, 0x0A0A0A0A); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_cmd_ctrl_2, 0x000A0A0A); - // // table->trim_regs.emc_pmacro_ib_vref_dq_0 = 0x15171414; - // // table->trim_regs.emc_pmacro_ib_vref_dq_1 = 0x15131513; - // // table->trim_regs.emc_pmacro_ib_vref_dqs_0 = 0x11111111; - // // table->trim_regs.emc_pmacro_ib_vref_dqs_1 = 0x11111111; - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_long_cmd_0, 0x000C000C); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_long_cmd_1, 0x000B000B); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_long_cmd_2, 0x000A000A); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_long_cmd_3, 0x000C000C); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_long_cmd_4, 0x0000000C); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_short_cmd_0, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_short_cmd_1, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ddll_short_cmd_2, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_vttgen_ctrl_0, 0x00030808); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_vttgen_ctrl_1, 0x00015C00); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_bg_bias_ctrl_0, 0x00000034); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_pad_cfg_ctrl, 0x00020000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_zctrl, 0x00000550); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_cmd_pad_rx_ctrl, 0x00000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_data_pad_rx_ctrl, 0x00000033); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_cmd_rx_term_mode, 0x00003000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_data_rx_term_mode, 0x00000011); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_cmd_pad_tx_ctrl, 0x02000000); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_data_pad_tx_ctrl, 0x02000101); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_common_pad_tx_ctrl, 0x00000007); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_autocal_cfg_common, 0x0000080D); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_vttgen_ctrl_2, 0x00102020); - // // WRITE_PARAM_ALL_REG(table, emc_pmacro_ib_rxrt, 0x00000055); - // WRITE_PARAM_ALL_REG(table, emc_training_ctrl, 0x00009080); - // WRITE_PARAM_ALL_REG(table, emc_training_quse_cors_ctrl, 0x01124000); - // WRITE_PARAM_ALL_REG(table, emc_training_quse_fine_ctrl, 0x01125B6A); - // WRITE_PARAM_ALL_REG(table, emc_training_quse_ctrl_misc, 0x0F081000); - // WRITE_PARAM_ALL_REG(table, emc_training_write_fine_ctrl, 0x1114FC00); - // WRITE_PARAM_ALL_REG(table, emc_training_write_ctrl_misc, 0x07004300); - // WRITE_PARAM_ALL_REG(table, emc_training_write_vref_ctrl, 0x00103200); - // WRITE_PARAM_ALL_REG(table, emc_training_read_fine_ctrl, 0x1110FC00); - // WRITE_PARAM_ALL_REG(table, emc_training_read_ctrl_misc, 0x0F085300); - // WRITE_PARAM_ALL_REG(table, emc_training_read_vref_ctrl, 0x00105800); - // WRITE_PARAM_ALL_REG(table, emc_training_ca_fine_ctrl, 0x0513801F); - // WRITE_PARAM_ALL_REG(table, emc_training_ca_ctrl_misc, 0x1F101100); - // WRITE_PARAM_ALL_REG(table, emc_training_ca_ctrl_misc1, 0x00000014); - // WRITE_PARAM_ALL_REG(table, emc_training_ca_vref_ctrl, 0x00103200); - // WRITE_PARAM_ALL_REG(table, emc_training_settle, 0x07070404); - // // WRITE_PARAM_ALL_REG(table, emc_training_mpc, 0x00000000); - // - // const u32 mc_tRCD = (int) ((double) (GET_CYCLE(tRCD) >> 2) - 2.0); - // const u32 mc_tRPpb = (int) (((double) (GET_CYCLE(tRPpb) >> 2) - 1.0) + 2.0); - // const u32 mc_tRC = (uint) ((double) (GET_CYCLE(tRC) >> 2) - 1.0); - // const u32 mc_tR2W = (uint) (((double) ((uint)tR2W >> 2) - 1.0) + 2.0); - // const u32 mc_tW2R = (uint) (((double) (tW2R >> 2) - 1.0) + 2.0); - // const u32 mc_tRAS = MIN(GET_CYCLE(tRAS), (u32) 0x7F); - // const u32 mc_tRRD = MIN(GET_CYCLE(tRRD), (u32) 31); - // - // table->burst_mc_regs.mc_emem_arb_timing_ras = (int) ((double) (mc_tRAS >> 2) - 2.0); - // table->burst_mc_regs.mc_emem_arb_timing_rcd = (int) ((double) (GET_CYCLE(tRCD) >> 2) - 2.0); - // table->burst_mc_regs.mc_emem_arb_timing_rp = (int) (((double) (GET_CYCLE(tRPpb) >> 2) - 1.0) + 2.0); - // table->burst_mc_regs.mc_emem_arb_timing_rc = (int) ((double) (GET_CYCLE(tRC) >> 2) - 1.0); - // table->burst_mc_regs.mc_emem_arb_timing_faw = (int) ((double) (GET_CYCLE(tFAW) >> 2) - 1.0); - // table->burst_mc_regs.mc_emem_arb_timing_rrd = (int) ((double) (mc_tRRD >> 2) - 1.0); - // table->burst_mc_regs.mc_emem_arb_timing_r2w = (uint) (((double) ((uint) tR2W >> 2) - 1.0) + 2.0); - // table->burst_mc_regs.mc_emem_arb_timing_w2r = (uint) (((double) (tW2R >> 2) - 1.0) + 2.0); - // - // table->burst_mc_regs.mc_emem_arb_da_turns = (table->burst_mc_regs.mc_emem_arb_da_turns & 0x0000FFFF) | (mc_tW2R << 24) | (mc_tR2W << 16); - // table->burst_mc_regs.mc_emem_arb_da_covers = (((uint) (mc_tRCD + 3 + mc_tRPpb) >> 1 & 0xff) << 8) | (((uint) (mc_tRCD + 11 + mc_tRPpb) >> 1 & 0xff) << 0x10) | ((mc_tRC >> 1) & 0xff); - // table->burst_mc_regs.mc_emem_arb_misc0 = (table->burst_mc_regs.mc_emem_arb_misc0 & 0xffe08000U) | ((mc_tRC + 1) & 0xff); /* Missing in l4t dump? TODO */ - // table->burst_mc_regs.mc_emem_arb_timing_rfcpb = GET_CYCLE(tRFCpb) >> 2; - // - // table->burst_mc_regs.mc_emem_arb_cfg = 0x0000000c; - // // table->burst_mc_regs.mc_emem_arb_timing_rcd = 0x00000006; - // // table->burst_mc_regs.mc_emem_arb_timing_rp = 0x00000007; - // // table->burst_mc_regs.mc_emem_arb_timing_rc = 0x00000018; - // // table->burst_mc_regs.mc_emem_arb_timing_ras = 0x0000000f; - // // table->burst_mc_regs.mc_emem_arb_timing_faw = 0x0000000f; - // // table->burst_mc_regs.mc_emem_arb_timing_rrd = 0x00000003; - // table->burst_mc_regs.mc_emem_arb_timing_rap2pre = 0x00000003; - // table->burst_mc_regs.mc_emem_arb_timing_wap2pre = 0x0000000d; - // table->burst_mc_regs.mc_emem_arb_timing_r2r = 0x00000007; - // table->burst_mc_regs.mc_emem_arb_timing_w2w = 0x00000007; - // // table->burst_mc_regs.mc_emem_arb_timing_r2w = 0x0000000c; - // // table->burst_mc_regs.mc_emem_arb_timing_w2r = 0x0000000a; - // // table->burst_mc_regs.mc_emem_arb_da_turns = 0x05060303; - // // table->burst_mc_regs.mc_emem_arb_da_covers = 0x000d080c; - // table->burst_mc_regs.mc_emem_arb_ring1_throttle = 0x001f0000; - // // table->burst_mc_regs.mc_emem_arb_timing_rfcpb = 0x00000023; - // table->burst_mc_regs.mc_emem_arb_timing_ccdmw = 0x00000008; - // table->burst_mc_regs.mc_emem_arb_refpb_hp_ctrl = 0x000a1020; - // table->burst_mc_regs.mc_emem_arb_refpb_bank_ctrl = 0x80001028; - // // table->burst_mc_regs.mc_emem_arb_dhyst_ctrl = 0x00000002; - // table->burst_mc_regs.mc_emem_arb_dhyst_timeout_util_0 = 0x0000001a; - // table->burst_mc_regs.mc_emem_arb_dhyst_timeout_util_1 = 0x0000001a; - // table->burst_mc_regs.mc_emem_arb_dhyst_timeout_util_2 = 0x0000001a; - // table->burst_mc_regs.mc_emem_arb_dhyst_timeout_util_3 = 0x0000001a; - // table->burst_mc_regs.mc_emem_arb_dhyst_timeout_util_4 = 0x0000001a; - // table->burst_mc_regs.mc_emem_arb_dhyst_timeout_util_5 = 0x0000001a; - // table->burst_mc_regs.mc_emem_arb_dhyst_timeout_util_6 = 0x0000001a; - // table->burst_mc_regs.mc_emem_arb_dhyst_timeout_util_7 = 0x0000001a; - // table->la_scale_regs.mc_mll_mpcorer_ptsa_rate = 0x000000d0; - // table->la_scale_regs.mc_ftop_ptsa_rate = 0x00000018; - // table->la_scale_regs.mc_ptsa_grant_decrement = 0x00001203; - // table->la_scale_regs.mc_latency_allowance_avpc_0 = 0x00800004; - // table->la_scale_regs.mc_latency_allowance_xusb_1 = 0x00800038; - // table->la_scale_regs.mc_latency_allowance_sdmmcaa_0 = 0x00800005; - // table->la_scale_regs.mc_latency_allowance_sdmmca_0 = 0x00800014; - // table->la_scale_regs.mc_latency_allowance_isp2_0 = 0x0000002c; - // table->la_scale_regs.mc_latency_allowance_isp2_1 = 0x00800080; - // table->la_scale_regs.mc_latency_allowance_vic_0 = 0x0080001d; - // table->la_scale_regs.mc_latency_allowance_nvdec_0 = 0x00800095; - // table->la_scale_regs.mc_latency_allowance_tsec_0 = 0x00800041; - // table->la_scale_regs.mc_latency_allowance_ppcs_1 = 0x00800080; - // table->la_scale_regs.mc_latency_allowance_xusb_0 = 0x0080003d; - // table->la_scale_regs.mc_latency_allowance_ppcs_0 = 0x00340049; - // table->la_scale_regs.mc_latency_allowance_gpu2_0 = 0x00800019; - // table->la_scale_regs.mc_latency_allowance_hc_1 = 0x00000080; - // table->la_scale_regs.mc_latency_allowance_sdmmc_0 = 0x00800090; - // table->la_scale_regs.mc_latency_allowance_mpcore_0 = 0x00800004; - // table->la_scale_regs.mc_latency_allowance_vi2_0 = 0x00000080; - // table->la_scale_regs.mc_latency_allowance_hc_0 = 0x00080016; - // table->la_scale_regs.mc_latency_allowance_gpu_0 = 0x00800019; - // table->la_scale_regs.mc_latency_allowance_sdmmcab_0 = 0x00800005; - // table->la_scale_regs.mc_latency_allowance_nvenc_0 = 0x00800018; - // table->dram_timings.t_rp = tRFCpb; - // table->dram_timings.t_rfc = tRFCab; - // } - - /* These timings are slightly off from eos, I am not sure why but I am going to figure it out at some point. */ + /* Note: This does not have proper timings, so base latency adjustment will not work. */ + /* However, it may still achieve a slightly higher frequency, but not as much as it could be. */ + /* I'm certainly not insane enough to attempt this pain again, so this will have to do *for now*. */ void MemMtcTableAutoAdjust(EristaMtcTable *table) { #define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \ TABLE->burst_regs.PARAM = VALUE; \ @@ -515,6 +207,15 @@ namespace ams::ldr::hoc::pcv::erista { refresh_raw = MIN(refresh_raw, static_cast(0xFFFF)); } + u32 rext; + if (C.eristaEmcMaxClock > 3200000) { + rext = 30; + } else if (C.eristaEmcMaxClock >= 2133001) { + rext = 28; + } else { + rext = 26; + } + u32 trefbw = refresh_raw + 0x40; trefbw = MIN(trefbw, static_cast(0x3FFF)); @@ -531,14 +232,14 @@ namespace ams::ldr::hoc::pcv::erista { WRITE_PARAM_ALL_REG(table, emc_tfaw, GET_CYCLE_CEIL(tFAW)); WRITE_PARAM_ALL_REG(table, emc_trpab, MIN(GET_CYCLE_CEIL(tRPab), static_cast(0x3F))); WRITE_PARAM_ALL_REG(table, emc_tckesr, GET_CYCLE_CEIL(tSR)); - WRITE_PARAM_ALL_REG(table, emc_tcke, tCKE); + WRITE_PARAM_ALL_REG(table, emc_tcke, GET_CYCLE_CEIL(7.425) + 2); WRITE_PARAM_ALL_REG(table, emc_tpd, GET_CYCLE_CEIL(tXP)); - WRITE_PARAM_ALL_REG(table, emc_tclkstop, GET_CYCLE_CEIL(tXP) + 8); + WRITE_PARAM_ALL_REG(table, emc_tclkstop, tCLKSTOP); WRITE_PARAM_ALL_REG(table, emc_r2p, tR2P); WRITE_PARAM_ALL_REG(table, emc_r2w, tR2W); WRITE_PARAM_ALL_REG(table, emc_w2p, tW2P); WRITE_PARAM_ALL_REG(table, emc_w2r, tW2R); - WRITE_PARAM_ALL_REG(table, emc_rext, C.eristaEmcMaxClock < 2133001 ? 26 : 28); // rext shouldn't be causing issues? + WRITE_PARAM_ALL_REG(table, emc_rext, rext); WRITE_PARAM_ALL_REG(table, emc_wext, (C.eristaEmcMaxClock >= 2533000) ? 0x19 : 0x16); WRITE_PARAM_ALL_REG(table, emc_refresh, refresh_raw); WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, refresh_raw / 4); @@ -547,20 +248,46 @@ namespace ams::ldr::hoc::pcv::erista { WRITE_PARAM_ALL_REG(table, emc_dyn_self_ref_control, dyn_self_ref_control); WRITE_PARAM_ALL_REG(table, emc_pdex2wr, pdex2rw); WRITE_PARAM_ALL_REG(table, emc_pdex2rd, pdex2rw); - WRITE_PARAM_ALL_REG(table, emc_pchg2pden, GET_CYCLE_CEIL(1.75)); + WRITE_PARAM_ALL_REG(table, emc_pchg2pden, GET_CYCLE_CEIL(1.763)); WRITE_PARAM_ALL_REG(table, emc_ar2pden, GET_CYCLE_CEIL(1.75)); WRITE_PARAM_ALL_REG(table, emc_pdex2cke, GET_CYCLE_CEIL(1.05)); WRITE_PARAM_ALL_REG(table, emc_act2pden, GET_CYCLE_CEIL(14.0)); - WRITE_PARAM_ALL_REG(table, emc_cke2pden, /* cke2pden */ GET_CYCLE_CEIL(8.5)); - (void) cke2pden; + WRITE_PARAM_ALL_REG(table, emc_cke2pden, GET_CYCLE_CEIL(8.499)); WRITE_PARAM_ALL_REG(table, emc_pdex2mrr, GET_CYCLE_CEIL(pdex2mrr)); WRITE_PARAM_ALL_REG(table, emc_rw2pden, tWTPDEN); + /* Accept imperfection or prepare for suffering. */ + // WRITE_PARAM_ALL_REG(table, emc_einput, einput); + // WRITE_PARAM_ALL_REG(table, emc_einput_duration, einput_duration); + // WRITE_PARAM_ALL_REG(table, emc_obdly, obdly); + // WRITE_PARAM_ALL_REG(table, emc_ibdly, ibdly); + // WRITE_PARAM_ALL_REG(table, emc_wdv_mask, wdv); + // WRITE_PARAM_ALL_REG(table, emc_quse_width, quse_width); + // WRITE_PARAM_ALL_REG(table, emc_quse, quse); + // WRITE_PARAM_ALL_REG(table, emc_wdv, wdv); + // WRITE_PARAM_ALL_REG(table, emc_wsv, wsv); + // WRITE_PARAM_ALL_REG(table, emc_wev, wev); + // WRITE_PARAM_ALL_REG(table, emc_qrst, qrst); + // WRITE_PARAM_ALL_REG(table, emc_tr_qrst, qrst); + // WRITE_PARAM_ALL_REG(table, emc_qsafe, qsafe); + // WRITE_PARAM_ALL_REG(table, emc_tr_qsafe, qsafe); + // WRITE_PARAM_ALL_REG(table, emc_tr_qpop, qpop); + // WRITE_PARAM_ALL_REG(table, emc_qpop, qpop); + // WRITE_PARAM_ALL_REG(table, emc_rdv, rdv); + // WRITE_PARAM_ALL_REG(table, emc_tr_rdv_mask, rdv + 2); + // WRITE_PARAM_ALL_REG(table, emc_rdv_early, rdv - 2); + // WRITE_PARAM_ALL_REG(table, emc_rdv_early_mask, rdv); + // WRITE_PARAM_ALL_REG(table, emc_rdv_mask, rdv + 2); + // WRITE_PARAM_ALL_REG(table, emc_tr_rdv, rdv); + // ams::ldr::hoc::pcv::mariko::CalculateMrw2(); + // table->emc_mrw2 = (table->emc_mrw2 & ~0xFFu) | static_cast(mrw2); + // table->dram_timings.rl = RL_DBI; + /* This needs some clean up. */ constexpr double MC_ARB_DIV = 4.0; constexpr u32 MC_ARB_SFA = 2; - table->burst_mc_regs.mc_emem_arb_cfg = C.eristaEmcMaxClock / (33.3 * 1000) / MC_ARB_DIV; + table->burst_mc_regs.mc_emem_arb_cfg = C.eristaEmcMaxClock / (33.3 * 1000) / MC_ARB_DIV; table->burst_mc_regs.mc_emem_arb_timing_rcd = CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV) - 2; table->burst_mc_regs.mc_emem_arb_timing_rp = CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV) - 1; table->burst_mc_regs.mc_emem_arb_timing_rc = CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV) - 1; @@ -593,15 +320,14 @@ namespace ams::ldr::hoc::pcv::erista { table->burst_mc_regs.mc_emem_arb_misc0 = (table->burst_mc_regs.mc_emem_arb_misc0 & 0xFFE08000) | (table->burst_mc_regs.mc_emem_arb_timing_rc + 1); - table->la_scale_regs.mc_mll_mpcorer_ptsa_rate = 0x115; + u32 mpcorer_ptsa_rate = MAX(static_cast(227), (C.eristaEmcMaxClock / 1600000) * 208); + table->la_scale_regs.mc_mll_mpcorer_ptsa_rate = mpcorer_ptsa_rate; - if (C.eristaEmcMaxClock >= 2133000) { - table->la_scale_regs.mc_ftop_ptsa_rate = 0x1F; - } else { - table->la_scale_regs.mc_ftop_ptsa_rate = 0x1B; - } + u32 ftop_ptsa_rate = MAX(static_cast(31), (C.eristaEmcMaxClock / 1600000) * 24); + table->la_scale_regs.mc_ftop_ptsa_rate = ftop_ptsa_rate; - table->la_scale_regs.mc_ptsa_grant_decrement = 0x17ff; + u32 grant_decrement = MAX(static_cast(6143), (C.eristaEmcMaxClock / 1600000) * 4611); + table->la_scale_regs.mc_ptsa_grant_decrement = grant_decrement; constexpr u32 MaskHigh = 0xFF00FFFF; constexpr u32 Mask2 = 0xFFFFFF00; @@ -613,34 +339,31 @@ namespace ams::ldr::hoc::pcv::erista { const u32 allowance4 = static_cast(0x9600 / (C.eristaEmcMaxClock / 0x3E8)) & 0xFF; const u32 allowance5 = static_cast(0x8980 / (C.eristaEmcMaxClock / 0x3E8)) & 0xFF; - table->la_scale_regs.mc_latency_allowance_xusb_0 = (table->la_scale_regs.mc_latency_allowance_xusb_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_xusb_1 = (table->la_scale_regs.mc_latency_allowance_xusb_1 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_tsec_0 = (table->la_scale_regs.mc_latency_allowance_tsec_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_sdmmcaa_0 = (table->la_scale_regs.mc_latency_allowance_sdmmcaa_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_sdmmcab_0 = (table->la_scale_regs.mc_latency_allowance_sdmmcab_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_sdmmc_0 = (table->la_scale_regs.mc_latency_allowance_sdmmc_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_sdmmca_0 = (table->la_scale_regs.mc_latency_allowance_sdmmca_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_ppcs_1 = (table->la_scale_regs.mc_latency_allowance_ppcs_1 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_nvdec_0 = (table->la_scale_regs.mc_latency_allowance_nvdec_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_mpcore_0 = (table->la_scale_regs.mc_latency_allowance_mpcore_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_avpc_0 = (table->la_scale_regs.mc_latency_allowance_avpc_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_vic_0 = allowance3 | (table->la_scale_regs.mc_latency_allowance_vic_0 & Mask3) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_isp2_1 = (table->la_scale_regs.mc_latency_allowance_isp2_1 & Mask3) | (allowance1 << 16) | allowance1; - table->la_scale_regs.mc_latency_allowance_nvenc_0 = allowance4 | (table->la_scale_regs.mc_latency_allowance_nvenc_0 & Mask3) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_hc_0 = (table->la_scale_regs.mc_latency_allowance_hc_0 & Mask2) | allowance5; - table->la_scale_regs.mc_latency_allowance_gpu_0 = allowance2 | (table->la_scale_regs.mc_latency_allowance_gpu_0 & Mask3) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_gpu2_0 = allowance2 | (table->la_scale_regs.mc_latency_allowance_gpu2_0 & Mask3) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_hc_1 = (table->la_scale_regs.mc_latency_allowance_hc_1 & Mask2) | allowance1; - table->la_scale_regs.mc_latency_allowance_vi2_0 = (table->la_scale_regs.mc_latency_allowance_vi2_0 & Mask2) | allowance1; + table->la_scale_regs.mc_latency_allowance_xusb_0 = (table->la_scale_regs.mc_latency_allowance_xusb_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_xusb_1 = (table->la_scale_regs.mc_latency_allowance_xusb_1 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_tsec_0 = (table->la_scale_regs.mc_latency_allowance_tsec_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_sdmmcaa_0 = (table->la_scale_regs.mc_latency_allowance_sdmmcaa_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_sdmmcab_0 = (table->la_scale_regs.mc_latency_allowance_sdmmcab_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_sdmmc_0 = (table->la_scale_regs.mc_latency_allowance_sdmmc_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_sdmmca_0 = (table->la_scale_regs.mc_latency_allowance_sdmmca_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_ppcs_1 = (table->la_scale_regs.mc_latency_allowance_ppcs_1 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_nvdec_0 = (table->la_scale_regs.mc_latency_allowance_nvdec_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_mpcore_0 = (table->la_scale_regs.mc_latency_allowance_mpcore_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_avpc_0 = (table->la_scale_regs.mc_latency_allowance_avpc_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_isp2_1 = allowance1 | (table->la_scale_regs.mc_latency_allowance_isp2_1 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_gpu_0 = allowance2 | (table->la_scale_regs.mc_latency_allowance_gpu_0 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_gpu2_0 = allowance2 | (table->la_scale_regs.mc_latency_allowance_gpu2_0 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_vic_0 = allowance3 | (table->la_scale_regs.mc_latency_allowance_vic_0 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_nvenc_0 = allowance4 | (table->la_scale_regs.mc_latency_allowance_nvenc_0 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_hc_0 = (table->la_scale_regs.mc_latency_allowance_hc_0 & Mask2) | allowance5; + table->la_scale_regs.mc_latency_allowance_hc_1 = (table->la_scale_regs.mc_latency_allowance_hc_1 & Mask2) | allowance1; + table->la_scale_regs.mc_latency_allowance_vi2_0 = (table->la_scale_regs.mc_latency_allowance_vi2_0 & Mask2) | allowance1; table->dram_timings.t_rp = tRFCpb; table->dram_timings.t_rfc = tRFCab; - table->dram_timings.rl = RL_DBI; - // WRITE_PARAM_ALL_REG(table, emc_obdly, obdly); - // WRITE_PARAM_ALL_REG(table, emc_ibdly, ibdly); - table->emc_cfg_2 = 0x11083D; - } + table->min_volt = std::min(static_cast(1050), 900 + C.emcDvbShift * 25); + } Result MemFreqMtcTable(u32 *ptr) { u32 khz_list[] = {1600000, 1331200, 1065600, 800000, 665600, 408000, 204000, 102000, 68000, 40800}; diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp index c0f70447..9a62f222 100644 --- a/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp +++ b/Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp @@ -547,25 +547,25 @@ namespace ams::ldr::hoc::pcv::mariko { const u32 allowance4 = static_cast(0x9600 / (C.marikoEmcMaxClock / 0x3E8)) & 0xFF; const u32 allowance5 = static_cast(0x8980 / (C.marikoEmcMaxClock / 0x3E8)) & 0xFF; - table->la_scale_regs.mc_latency_allowance_xusb_0 = (table->la_scale_regs.mc_latency_allowance_xusb_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_xusb_1 = (table->la_scale_regs.mc_latency_allowance_xusb_1 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_tsec_0 = (table->la_scale_regs.mc_latency_allowance_tsec_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_sdmmcaa_0 = (table->la_scale_regs.mc_latency_allowance_sdmmcaa_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_sdmmcab_0 = (table->la_scale_regs.mc_latency_allowance_sdmmcab_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_sdmmc_0 = (table->la_scale_regs.mc_latency_allowance_sdmmc_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_sdmmca_0 = (table->la_scale_regs.mc_latency_allowance_sdmmca_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_ppcs_1 = (table->la_scale_regs.mc_latency_allowance_ppcs_1 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_nvdec_0 = (table->la_scale_regs.mc_latency_allowance_nvdec_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_mpcore_0 = (table->la_scale_regs.mc_latency_allowance_mpcore_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_avpc_0 = (table->la_scale_regs.mc_latency_allowance_avpc_0 & MaskHigh) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_vic_0 = allowance3 | (table->la_scale_regs.mc_latency_allowance_vic_0 & Mask3) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_isp2_1 = (table->la_scale_regs.mc_latency_allowance_isp2_1 & Mask3) | (allowance1 << 16) | allowance1; - table->la_scale_regs.mc_latency_allowance_nvenc_0 = allowance4 | (table->la_scale_regs.mc_latency_allowance_nvenc_0 & Mask3) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_hc_0 = (table->la_scale_regs.mc_latency_allowance_hc_0 & Mask2) | allowance5; - table->la_scale_regs.mc_latency_allowance_gpu_0 = allowance2 | (table->la_scale_regs.mc_latency_allowance_gpu_0 & Mask3) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_gpu2_0 = allowance2 | (table->la_scale_regs.mc_latency_allowance_gpu2_0 & Mask3) | (allowance1 << 16); - table->la_scale_regs.mc_latency_allowance_hc_1 = (table->la_scale_regs.mc_latency_allowance_hc_1 & Mask2) | allowance1; - table->la_scale_regs.mc_latency_allowance_vi2_0 = (table->la_scale_regs.mc_latency_allowance_vi2_0 & Mask2) | allowance1; + table->la_scale_regs.mc_latency_allowance_xusb_0 = (table->la_scale_regs.mc_latency_allowance_xusb_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_xusb_1 = (table->la_scale_regs.mc_latency_allowance_xusb_1 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_tsec_0 = (table->la_scale_regs.mc_latency_allowance_tsec_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_sdmmcaa_0 = (table->la_scale_regs.mc_latency_allowance_sdmmcaa_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_sdmmcab_0 = (table->la_scale_regs.mc_latency_allowance_sdmmcab_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_sdmmc_0 = (table->la_scale_regs.mc_latency_allowance_sdmmc_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_sdmmca_0 = (table->la_scale_regs.mc_latency_allowance_sdmmca_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_ppcs_1 = (table->la_scale_regs.mc_latency_allowance_ppcs_1 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_nvdec_0 = (table->la_scale_regs.mc_latency_allowance_nvdec_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_mpcore_0 = (table->la_scale_regs.mc_latency_allowance_mpcore_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_avpc_0 = (table->la_scale_regs.mc_latency_allowance_avpc_0 & MaskHigh) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_isp2_1 = allowance1 | (table->la_scale_regs.mc_latency_allowance_isp2_1 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_gpu_0 = allowance2 | (table->la_scale_regs.mc_latency_allowance_gpu_0 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_gpu2_0 = allowance2 | (table->la_scale_regs.mc_latency_allowance_gpu2_0 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_vic_0 = allowance3 | (table->la_scale_regs.mc_latency_allowance_vic_0 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_nvenc_0 = allowance4 | (table->la_scale_regs.mc_latency_allowance_nvenc_0 & Mask3) | (allowance1 << 16); + table->la_scale_regs.mc_latency_allowance_hc_0 = (table->la_scale_regs.mc_latency_allowance_hc_0 & Mask2) | allowance5; + table->la_scale_regs.mc_latency_allowance_hc_1 = (table->la_scale_regs.mc_latency_allowance_hc_1 & Mask2) | allowance1; + table->la_scale_regs.mc_latency_allowance_vi2_0 = (table->la_scale_regs.mc_latency_allowance_vi2_0 & Mask2) | allowance1; table->dram_timings.t_rp = tRFCpb; table->dram_timings.t_rfc = tRFCab;