- oc_loader: major refactoring
This commit is contained in:
KazushiM
53
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv.cpp
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53
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv.cpp
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@@ -0,0 +1,53 @@
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/*
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* Copyright (C) Switch-OC-Suite
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
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||||
*
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* This program is distributed in the hope it will be useful, but WITHOUT
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||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
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||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "pcv.hpp"
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namespace ams::ldr::oc::pcv {
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Result MemFreqPllmLimit(u32* ptr) {
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clk_pll_param* entry = reinterpret_cast<clk_pll_param *>(ptr);
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R_UNLESS(entry->freq == entry->vco_max, ldr::ResultInvalidMemPllmEntry());
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// Double the max clk simply
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u32 max_clk = entry->freq * 2;
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entry->freq = max_clk;
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entry->vco_max = max_clk;
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R_SUCCEED();
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}
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void SafetyCheck() {
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if (C.custRev != CUST_REV ||
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C.marikoCpuMaxVolt >= 1300 ||
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C.eristaCpuMaxVolt >= 1300 ||
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(C.eristaEmcVolt && (C.eristaEmcVolt < 600'000 || C.eristaEmcVolt > 1250'000)))
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{
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CRASH("Triggered");
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}
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}
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void Patch(uintptr_t mapped_nso, size_t nso_size) {
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#ifdef ATMOSPHERE_IS_STRATOSPHERE
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SafetyCheck();
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bool isMariko = (spl::GetSocType() == spl::SocType_Mariko);
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if (isMariko)
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mariko::Patch(mapped_nso, nso_size);
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else
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erista::Patch(mapped_nso, nso_size);
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#endif
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}
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}
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130
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv.hpp
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130
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv.hpp
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@@ -0,0 +1,130 @@
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/*
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* Copyright (C) Switch-OC-Suite
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*
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* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms and conditions of the GNU General Public License,
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||||
* version 2, as published by the Free Software Foundation.
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||||
*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "../oc_suite_common.hpp"
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namespace ams::ldr::oc::pcv {
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typedef struct cvb_coefficients {
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s32 c0 = 0;
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s32 c1 = 0;
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s32 c2 = 0;
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s32 c3 = 0;
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s32 c4 = 0;
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s32 c5 = 0;
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} cvb_coefficients;
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typedef struct cpu_freq_cvb_table_t {
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u64 freq;
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cvb_coefficients cvb_dfll_param;
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cvb_coefficients cvb_pll_param;
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} cpu_freq_cvb_table_t;
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static_assert(sizeof(cpu_freq_cvb_table_t) == 0x38);
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typedef struct gpu_cvb_pll_table_t {
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u64 freq;
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cvb_coefficients cvb_dfll_param;
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cvb_coefficients cvb_pll_param;
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} gpu_cvb_pll_table_t;
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static_assert(sizeof(gpu_cvb_pll_table_t) == 0x38);
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typedef struct emc_dvb_dvfs_table_t {
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u64 freq;
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s32 volt[4] = {0};
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} emc_dvb_dvfs_table_t;
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typedef struct __attribute__((packed)) div_nmp {
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u8 divn_shift;
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u8 divn_width;
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u8 divm_shift;
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u8 divm_width;
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u8 divp_shift;
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u8 divp_width;
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u8 override_divn_shift;
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u8 override_divm_shift;
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u8 override_divp_shift;
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} div_nmp;
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typedef struct __attribute__((packed)) clk_pll_param {
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u32 freq;
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u32 input_min;
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u32 input_max;
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u32 cf_min;
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u32 cf_max;
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u32 vco_min;
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u32 vco_max;
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s32 lock_delay;
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u32 fixed_rate;
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u32 unk_0;
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struct div_nmp *div_nmp;
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u32 unk_1[4];
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void (*unk_fn)(u64* unk_struct); // set_defaults?
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} clk_pll_param;
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typedef struct __attribute__((packed)) dvfs_rail {
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u32 id;
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u32 unk_0[5];
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u32 freq;
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u32 unk_1[8];
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u32 unk_flag;
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u32 min_mv;
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u32 step_mv;
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u32 max_mv;
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u32 unk_2[11];
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} dvfs_rail;
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constexpr u32 CpuClkOSLimit = 1785'000;
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constexpr u32 MemClkOSLimit = 1600'000;
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#define R_SKIP() R_SUCCEED()
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Result MemFreqPllmLimit(u32* ptr);
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template<typename Table>
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Result MemMtcTableClone(Table* des, Table* src) {
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constexpr u32 mtc_magic = 0x5F43544D;
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R_UNLESS(src->rev == mtc_magic, ldr::ResultInvalidMtcMagic());
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// Skip params from dvfs_ver to clock_src;
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for (size_t offset = offsetof(Table, clk_src_emc); offset < sizeof(Table); offset += sizeof(u32)) {
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u32* src_ent = reinterpret_cast<u32 *>(reinterpret_cast<size_t>(src) + offset);
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u32* des_ent = reinterpret_cast<u32 *>(reinterpret_cast<size_t>(des) + offset);
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u32 src_val = *src_ent;
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constexpr u32 placeholder_val = UINT32_MAX;
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if (src_val != placeholder_val) {
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PatchOffset(des_ent, src_val);
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}
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}
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R_SUCCEED();
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};
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namespace erista {
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void Patch(uintptr_t mapped_nso, size_t nso_size);
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}
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namespace mariko {
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void Patch(uintptr_t mapped_nso, size_t nso_size);
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}
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void SafetyCheck();
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void Patch(uintptr_t mapped_nso, size_t nso_size);
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}
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@@ -0,0 +1,130 @@
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/*
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||||
* Copyright (C) Switch-OC-Suite
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||||
*
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||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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||||
*/
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#include "pcv_erista.hpp"
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namespace ams::ldr::oc::pcv::erista {
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Result CpuFreqCvbTable(u32* ptr) {
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cpu_freq_cvb_table_t* default_end = reinterpret_cast<cpu_freq_cvb_table_t *>(ptr);
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cpu_freq_cvb_table_t* new_start = default_end + 1;
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// Validate existing table
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void* cpu_cvb_table_head = reinterpret_cast<u8 *>(new_start) - sizeof(CpuCvbTableDefault);
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bool validated = std::memcmp(cpu_cvb_table_head, CpuCvbTableDefault, sizeof(CpuCvbTableDefault)) == 0;
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R_UNLESS(validated, ldr::ResultInvalidCpuDvfs());
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if (!C.eristaCpuOCEnabled)
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R_SKIP();
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std::memcpy(reinterpret_cast<void *>(new_start), CpuCvbTableAppend, sizeof(CpuCvbTableAppend));
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R_SUCCEED();
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}
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Result CpuVoltRange(u32* ptr) {
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u32 min_volt_got = *(ptr - 1);
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for (const auto& mv : CpuMinVolts) {
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if (min_volt_got != mv)
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continue;
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if (!C.eristaCpuMaxVolt)
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R_SKIP();
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PatchOffset(ptr, C.eristaCpuMaxVolt);
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R_SUCCEED();
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}
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R_THROW(ldr::ResultInvalidCpuMinVolt());
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}
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Result MemFreqMtcTable(u32* ptr) {
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u32 khz_list[] = { 1600000, 1331200, 1065600, 800000, 665600, 408000, 204000, 102000, 68000, 40800 };
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u32 khz_list_size = sizeof(khz_list) / sizeof(u32);
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// Generate list for mtc table pointers
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EristaMtcTable* table_list[khz_list_size];
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for (u32 i = 0; i < khz_list_size; i++) {
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u8* table = reinterpret_cast<u8 *>(ptr) - offsetof(EristaMtcTable, rate_khz) - i * sizeof(EristaMtcTable);
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table_list[i] = reinterpret_cast<EristaMtcTable *>(table);
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R_UNLESS(table_list[i]->rate_khz == khz_list[i], ldr::ResultInvalidMtcTable());
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R_UNLESS(table_list[i]->rev == MTC_TABLE_REV, ldr::ResultInvalidMtcTable());
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}
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if (C.eristaEmcMaxClock <= MemClkOSLimit)
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R_SKIP();
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// Make room for new mtc table, discarding useless 40.8 MHz table
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// 40800 overwritten by 68000, ..., 1331200 overwritten by 1600000, leaving table_list[0] not overwritten
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for (u32 i = khz_list_size - 1; i > 0; i--)
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std::memcpy(static_cast<void *>(table_list[i]), static_cast<void *>(table_list[i - 1]), sizeof(EristaMtcTable));
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PatchOffset(ptr, C.eristaEmcMaxClock);
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R_SUCCEED();
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}
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Result MemFreqMax(u32* ptr) {
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if (C.eristaEmcMaxClock <= MemClkOSLimit)
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R_SKIP();
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PatchOffset(ptr, C.eristaEmcMaxClock);
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R_SUCCEED();
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}
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Result MemVoltHandler(u32* ptr) {
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u32 emc_uv = C.eristaEmcVolt;
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if (!emc_uv)
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R_SKIP();
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constexpr u32 uv_step = 12'500;
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if (emc_uv % uv_step)
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emc_uv = emc_uv / uv_step * uv_step; // rounding
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PatchOffset(ptr, emc_uv);
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R_SUCCEED();
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}
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void Patch(uintptr_t mapped_nso, size_t nso_size) {
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PatcherEntry<u32> patches[] = {
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{ "CPU Freq Table", &CpuFreqCvbTable, 1, nullptr, CpuClkOSLimit },
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{ "CPU Volt Limit", &CpuVoltRange, 0, &CpuMaxVoltPatternFn },
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{ "MEM Freq Mtc", &MemFreqMtcTable, 0, nullptr, MemClkOSLimit },
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{ "MEM Freq Max", &MemFreqMax, 0, nullptr, MemClkOSLimit },
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{ "MEM Freq PLLM", &MemFreqPllmLimit, 2, nullptr, MemClkPllmLimit },
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{ "MEM Volt", &MemVoltHandler, 2, nullptr, MemVoltHOS },
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};
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for (uintptr_t ptr = mapped_nso;
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ptr <= mapped_nso + nso_size - sizeof(EristaMtcTable);
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ptr += sizeof(u32))
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{
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u32* ptr32 = reinterpret_cast<u32 *>(ptr);
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for (auto& entry : patches) {
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if (R_SUCCEEDED(entry.SearchAndApply(ptr32)))
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break;
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}
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}
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for (auto& entry : patches) {
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LOGGING("%s Count: %zu", entry.description, entry.patched_count);
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if (R_FAILED(entry.CheckResult()))
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CRASH(entry.description);
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}
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}
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}
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@@ -0,0 +1,63 @@
|
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/*
|
||||
* Copyright (C) Switch-OC-Suite
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
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#pragma once
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#include "pcv.hpp"
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namespace ams::ldr::oc::pcv::erista {
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constexpr cpu_freq_cvb_table_t CpuCvbTableDefault[] = {
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// CPU_PLL_CVB_TABLE_ODN
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{ 204000, { 721094 }, {} },
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{ 306000, { 754040 }, {} },
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{ 408000, { 786986 }, {} },
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{ 510000, { 819932 }, {} },
|
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{ 612000, { 852878 }, {} },
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{ 714000, { 885824 }, {} },
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{ 816000, { 918770 }, {} },
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{ 918000, { 951716 }, {} },
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{ 1020000, { 984662 }, { -2875621, 358099, -8585 } },
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{ 1122000, { 1017608 }, { -52225, 104159, -2816 } },
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{ 1224000, { 1050554 }, { 1076868, 8356, -727 } },
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{ 1326000, { 1083500 }, { 2208191, -84659, 1240 } },
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{ 1428000, { 1116446 }, { 2519460, -105063, 1611 } },
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{ 1581000, { 1130000 }, { 2889664, -122173, 1834 } },
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{ 1683000, { 1168000 }, { 5100873, -279186, 4747 } },
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{ 1785000, { 1227500 }, { 5100873, -279186, 4747 } },
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};
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constexpr cpu_freq_cvb_table_t CpuCvbTableAppend[] = {
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{ 1887000, { 1235000 }, { 5100873, -279186, 4747 } },
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{ 1989000, { 1235000 }, { 5100873, -279186, 4747 } },
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{ 2091000, { 1235000 }, { 5100873, -279186, 4747 } },
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};
|
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|
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constexpr u32 CpuMinVolts[] = { 950, 850, 825, 810 };
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|
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inline bool CpuMaxVoltPatternFn(u32* ptr32) {
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u32 val = *ptr32;
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return (val == 1132 || val == 1170 || val == 1227);
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}
|
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|
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constexpr u32 MemVoltHOS = 1125'000;
|
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constexpr u32 MemClkPllmLimit = 1866'000'000;
|
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|
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constexpr u32 MTC_TABLE_REV = 7;
|
||||
|
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void Patch(uintptr_t mapped_nso, size_t nso_size);
|
||||
|
||||
}
|
||||
@@ -0,0 +1,403 @@
|
||||
/*
|
||||
* Copyright (C) Switch-OC-Suite
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include "pcv_mariko.hpp"
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|
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namespace ams::ldr::oc::pcv::mariko {
|
||||
|
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Result CpuFreqVdd(u32* ptr) {
|
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dvfs_rail* entry = reinterpret_cast<dvfs_rail *>(reinterpret_cast<u8 *>(ptr) - offsetof(dvfs_rail, freq));
|
||||
|
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R_UNLESS(entry->id == 1, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
R_UNLESS(entry->min_mv == 250'000, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
R_UNLESS(entry->step_mv == 5000, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
R_UNLESS(entry->max_mv == 1525'000, ldr::ResultInvalidCpuFreqVddEntry());
|
||||
|
||||
if (!C.marikoCpuMaxClock)
|
||||
R_SKIP();
|
||||
|
||||
PatchOffset(ptr, C.marikoCpuMaxClock);
|
||||
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
Result CpuFreqCvbTable(u32* ptr) {
|
||||
cpu_freq_cvb_table_t* default_end = reinterpret_cast<cpu_freq_cvb_table_t *>(ptr);
|
||||
cpu_freq_cvb_table_t* new_start = default_end + 1;
|
||||
|
||||
// Validate existing table
|
||||
void* cpu_cvb_table_head = reinterpret_cast<u8 *>(new_start) - sizeof(CpuCvbTableDefault);
|
||||
bool validated = std::memcmp(cpu_cvb_table_head, CpuCvbTableDefault, sizeof(CpuCvbTableDefault)) == 0;
|
||||
R_UNLESS(validated, ldr::ResultInvalidCpuDvfs());
|
||||
|
||||
if (C.marikoCpuMaxClock > CpuClkOfficial)
|
||||
std::memcpy(reinterpret_cast<void *>(new_start), CpuCvbTableAppend, sizeof(CpuCvbTableAppend));
|
||||
|
||||
// Patch CPU max volt in existing and appended CPU dvfs table
|
||||
if (C.marikoCpuMaxVolt) {
|
||||
size_t table_size = (sizeof(CpuCvbTableDefault) + sizeof(CpuCvbTableAppend)) / sizeof(cpu_freq_cvb_table_t);
|
||||
cpu_freq_cvb_table_t* entry = static_cast<cpu_freq_cvb_table_t *>(cpu_cvb_table_head);
|
||||
for (size_t i = 0; i < table_size; i++) {
|
||||
if (entry->cvb_pll_param.c0 == CpuVoltOfficial * 1000) {
|
||||
PatchOffset(reinterpret_cast<u32 *>(&(entry->cvb_pll_param.c0)), C.marikoCpuMaxVolt * 1000);
|
||||
}
|
||||
entry++;
|
||||
}
|
||||
}
|
||||
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
Result CpuVoltRange(u32* ptr) {
|
||||
u32 min_volt_got = *(ptr - 1);
|
||||
for (const auto& mv : CpuMinVolts) {
|
||||
if (min_volt_got != mv)
|
||||
continue;
|
||||
|
||||
if (!C.marikoCpuMaxVolt)
|
||||
R_SKIP();
|
||||
|
||||
PatchOffset(ptr, C.marikoCpuMaxVolt);
|
||||
R_SUCCEED();
|
||||
}
|
||||
R_THROW(ldr::ResultInvalidCpuMinVolt());
|
||||
}
|
||||
|
||||
Result GpuFreqCvbTable(u32* ptr) {
|
||||
gpu_cvb_pll_table_t* default_end = reinterpret_cast<gpu_cvb_pll_table_t *>(ptr);
|
||||
gpu_cvb_pll_table_t* new_start = default_end + 1;
|
||||
|
||||
// Validate existing table
|
||||
void* gpu_cvb_table_head = reinterpret_cast<u8 *>(new_start) - sizeof(GpuCvbTableDefault);
|
||||
bool validated = std::memcmp(gpu_cvb_table_head, GpuCvbTableDefault, sizeof(GpuCvbTableDefault)) == 0;
|
||||
R_UNLESS(validated, ldr::ResultInvalidGpuDvfs());
|
||||
|
||||
if (C.marikoGpuMaxClock <= GpuClkOfficial)
|
||||
R_SKIP();
|
||||
|
||||
std::memcpy(reinterpret_cast<void *>(new_start), GpuCvbTableAppend, sizeof(GpuCvbTableAppend));
|
||||
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
Result GpuFreqMaxAsm(u32* ptr32) {
|
||||
// Check if both two instructions match the pattern
|
||||
u32 ins1 = *ptr32, ins2 = *(ptr32 + 1);
|
||||
if (!(asm_compare_no_rd(ins1, asm_pattern[0]) && asm_compare_no_rd(ins2, asm_pattern[1])))
|
||||
R_THROW(ldr::ResultInvalidGpuFreqMaxPattern());
|
||||
|
||||
// Both instructions should operate on the same register
|
||||
u8 rd = asm_get_rd(ins1);
|
||||
if (rd != asm_get_rd(ins2))
|
||||
R_THROW(ldr::ResultInvalidGpuFreqMaxPattern());
|
||||
|
||||
if (!C.marikoGpuMaxClock)
|
||||
R_SKIP();
|
||||
|
||||
u32 asm_patch[2] = {
|
||||
asm_set_rd(asm_set_imm16(asm_pattern[0], C.marikoGpuMaxClock), rd),
|
||||
asm_set_rd(asm_set_imm16(asm_pattern[1], C.marikoGpuMaxClock >> 16), rd)
|
||||
};
|
||||
PatchOffset(ptr32, asm_patch[0]);
|
||||
PatchOffset(ptr32 + 1, asm_patch[1]);
|
||||
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
Result GpuFreqPllLimit(u32* ptr) {
|
||||
clk_pll_param* entry = reinterpret_cast<clk_pll_param *>(ptr);
|
||||
|
||||
// All zero except for freq
|
||||
for (size_t i = 1; i < sizeof(clk_pll_param) / sizeof(u32); i++) {
|
||||
R_UNLESS(*(ptr + i) == 0, ldr::ResultInvalidGpuPllEntry());
|
||||
}
|
||||
|
||||
// Double the max clk simply
|
||||
u32 max_clk = entry->freq * 2;
|
||||
entry->freq = max_clk;
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
|
||||
/* Official Tegra X1 TRM, sign up for nvidia developer program (free) to download:
|
||||
* https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual
|
||||
* Section 18.11: MC Registers
|
||||
*
|
||||
* Retail Mariko: 200FBGA 16Gb DDP LPDDR4X SDRAM x 2
|
||||
* x16/Ch, 1Ch/die, Double-die, 2Ch, 1CS(rank), 8Gb density per die
|
||||
* 64Mb x 16DQ x 8banks x 2channels = 2048MB (x32DQ) per package
|
||||
*
|
||||
* Devkit Mariko: 200FBGA 32Gb DDP LPDDR4X SDRAM x 2
|
||||
* x16/Ch, 1Ch/die, Quad-die, 2Ch, 2CS(rank), 8Gb density per die
|
||||
* X1+ EMC can R/W to both ranks at the same time, resulting in doubled DQ
|
||||
* 64Mb x 32DQ x 8banks x 2channels = 4096MB (x64DQ) per package
|
||||
*
|
||||
* If you have access to LPDDR4(X) specs or datasheets (from manufacturers or Google),
|
||||
* you'd better calculate timings yourself rather than relying on following algorithm.
|
||||
*/
|
||||
|
||||
#define ADJUST_PROP(TARGET, REF) \
|
||||
(u32)(std::ceil(REF + ((C.marikoEmcMaxClock-MemClkOSAlt)*(TARGET-REF))/(MemClkOSLimit-MemClkOSAlt)))
|
||||
|
||||
#define ADJUST_PARAM(TARGET, REF) \
|
||||
TARGET = ADJUST_PROP(TARGET, REF);
|
||||
|
||||
#define ADJUST_PARAM_TABLE(TABLE, PARAM, REF) ADJUST_PARAM(TABLE->PARAM, REF->PARAM)
|
||||
|
||||
#define ADJUST_PARAM_ALL_REG(TABLE, PARAM, REF) \
|
||||
ADJUST_PARAM_TABLE(TABLE, burst_regs.PARAM, REF) \
|
||||
ADJUST_PARAM_TABLE(TABLE, shadow_regs_ca_train.PARAM, REF) \
|
||||
ADJUST_PARAM_TABLE(TABLE, shadow_regs_rdwr_train.PARAM, REF)
|
||||
|
||||
#define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE)\
|
||||
TABLE->burst_regs.PARAM = VALUE; \
|
||||
TABLE->shadow_regs_ca_train.PARAM = VALUE; \
|
||||
TABLE->shadow_regs_rdwr_train.PARAM = VALUE;
|
||||
|
||||
ADJUST_PARAM_ALL_REG(table, emc_r2w, ref);
|
||||
ADJUST_PARAM_ALL_REG(table, emc_w2r, ref);
|
||||
ADJUST_PARAM_ALL_REG(table, emc_r2p, ref);
|
||||
ADJUST_PARAM_ALL_REG(table, emc_w2p, ref);
|
||||
ADJUST_PARAM_ALL_REG(table, emc_trtm, ref);
|
||||
ADJUST_PARAM_ALL_REG(table, emc_twtm, ref);
|
||||
ADJUST_PARAM_ALL_REG(table, emc_tratm, ref);
|
||||
ADJUST_PARAM_ALL_REG(table, emc_twatm, ref);
|
||||
|
||||
ADJUST_PARAM_ALL_REG(table, emc_rw2pden, ref);
|
||||
|
||||
ADJUST_PARAM_ALL_REG(table, emc_tclkstop, ref);
|
||||
|
||||
ADJUST_PARAM_ALL_REG(table, emc_pmacro_dll_cfg_2, ref); // EMC_DLL_CFG_2_0: level select for VDDA?
|
||||
|
||||
ADJUST_PARAM_TABLE(table, la_scale_regs.mc_mll_mpcorer_ptsa_rate, ref);
|
||||
ADJUST_PARAM_TABLE(table, la_scale_regs.mc_ptsa_grant_decrement, ref);
|
||||
|
||||
/* Timings that are available in or can be derived from LPDDR4X datasheet or TRM */
|
||||
const bool use_4266_spec = C.mtcConf == AUTO_ADJ_MARIKO_4266;
|
||||
// tCK_avg (average clock period) in ns
|
||||
const double tCK_avg = 1000'000. / C.marikoEmcMaxClock;
|
||||
// tRPpb (row precharge time per bank) in ns
|
||||
const u32 tRPpb = 18;
|
||||
// tRPab (row precharge time all banks) in ns
|
||||
const u32 tRPab = 21;
|
||||
// tRAS (row active time) in ns
|
||||
const u32 tRAS = 42;
|
||||
// tRC (ACTIVATE-ACTIVATE command period same bank) in ns
|
||||
const u32 tRC = tRPpb + tRAS;
|
||||
// tRFCab (refresh cycle time all banks) in ns for 8Gb density
|
||||
const u32 tRFCab = 280;
|
||||
// tRFCpb (refresh cycle time per bank) in ns for 8Gb density
|
||||
const u32 tRFCpb = 140;
|
||||
// tRCD (RAS-CAS delay) in ns
|
||||
const u32 tRCD = 18;
|
||||
// tRRD (Active bank-A to Active bank-B) in ns
|
||||
const double tRRD = use_4266_spec ? 7.5 : 10.;
|
||||
// tREFpb (average refresh interval per bank) in ns for 8Gb density
|
||||
const u32 tREFpb = 488;
|
||||
// tREFab (average refresh interval all 8 banks) in ns for 8Gb density
|
||||
// const u32 tREFab = tREFpb * 8;
|
||||
// #_of_rows per die for 8Gb density
|
||||
const u32 numOfRows = 65536;
|
||||
// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
|
||||
// emc_clk_period = dram_clk / 2;
|
||||
// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
|
||||
const u32 REFRESH = u32(std::ceil((double(tREFpb) * C.marikoEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4;
|
||||
// tPDEX2WR, tPDEX2RD (timing delay from exiting powerdown mode to a write/read command) in ns
|
||||
const u32 tPDEX2 = 10;
|
||||
// [Guessed] tACT2PDEN (timing delay from an activate, MRS or EMRS command to power-down entry) in ns
|
||||
const u32 tACT2PDEN = 14;
|
||||
// [Guessed] tPDEX2MRR (timing delay from exiting powerdown mode to MRR command) in ns
|
||||
const double tPDEX2MRR = 28.75;
|
||||
// [Guessed] tCKE2PDEN (timing delay from turning off CKE to power-down entry) in ns
|
||||
const double tCKE2PDEN = 8.5;
|
||||
// tXSR (SELF REFRESH exit to next valid command delay) in ns
|
||||
const double tXSR = tRFCab + 7.5;
|
||||
// tCKE (minimum CKE high pulse width) in ns
|
||||
const u32 tCKE = 8;
|
||||
// tCKELPD (minimum CKE low pulse width in SELF REFRESH) in ns
|
||||
const u32 tCKELPD = 15;
|
||||
// [Guessed] tPD (minimum CKE low pulse width in power-down mode) in ns
|
||||
const double tPD = 7.5;
|
||||
// tFAW (Four-bank Activate Window) in ns
|
||||
const u32 tFAW = use_4266_spec ? 30 : 40;
|
||||
|
||||
#define GET_CYCLE_CEIL(PARAM) u32(std::ceil(double(PARAM) / tCK_avg))
|
||||
|
||||
WRITE_PARAM_ALL_REG(table, emc_rc, GET_CYCLE_CEIL(tRC));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rfc, GET_CYCLE_CEIL(tRFCab));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb));
|
||||
WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rd_rcd, GET_CYCLE_CEIL(tRCD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_wr_rcd, GET_CYCLE_CEIL(tRCD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rrd, GET_CYCLE_CEIL(tRRD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_refresh, REFRESH);
|
||||
WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
|
||||
WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tPDEX2));
|
||||
WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tPDEX2));
|
||||
WRITE_PARAM_ALL_REG(table, emc_act2pden,GET_CYCLE_CEIL(tACT2PDEN));
|
||||
WRITE_PARAM_ALL_REG(table, emc_cke2pden,GET_CYCLE_CEIL(tCKE2PDEN));
|
||||
WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,GET_CYCLE_CEIL(tPDEX2MRR));
|
||||
WRITE_PARAM_ALL_REG(table, emc_txsr, GET_CYCLE_CEIL(tXSR));
|
||||
WRITE_PARAM_ALL_REG(table, emc_txsrdll, GET_CYCLE_CEIL(tXSR));
|
||||
WRITE_PARAM_ALL_REG(table, emc_tcke, GET_CYCLE_CEIL(tCKE));
|
||||
WRITE_PARAM_ALL_REG(table, emc_tckesr, GET_CYCLE_CEIL(tCKELPD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_tpd, GET_CYCLE_CEIL(tPD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_tfaw, GET_CYCLE_CEIL(tFAW));
|
||||
WRITE_PARAM_ALL_REG(table, emc_trpab, GET_CYCLE_CEIL(tRPab));
|
||||
WRITE_PARAM_ALL_REG(table, emc_trefbw, REFRESH + 64);
|
||||
|
||||
constexpr u32 MC_ARB_DIV = 4; // ?
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rcd = std::ceil(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV - 2);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rp = std::ceil(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV - 1);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rc = std::ceil(std::max(GET_CYCLE_CEIL(tRC), GET_CYCLE_CEIL(tRAS)+GET_CYCLE_CEIL(tRPpb)) / MC_ARB_DIV);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_ras = std::ceil(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV - 2);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_faw = std::ceil(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV - 1);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rrd = std::ceil(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV - 1);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rap2pre = std::ceil(table->burst_regs.emc_r2p / MC_ARB_DIV);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_wap2pre = std::ceil(table->burst_regs.emc_w2p / MC_ARB_DIV);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_r2w = std::ceil(table->burst_regs.emc_r2w / MC_ARB_DIV + 1);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_w2r = std::ceil(table->burst_regs.emc_w2r / MC_ARB_DIV + 1);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rfcpb = std::ceil(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV + 1); // ?
|
||||
}
|
||||
|
||||
void MemMtcPllmbDivisor(MarikoMtcTable* table) {
|
||||
// Calculate DIVM and DIVN (clock divisors)
|
||||
// Common PLL oscillator is 38.4 MHz
|
||||
// PLLMB_OUT = 38.4 MHz / PLLLMB_DIVM * PLLMB_DIVN
|
||||
typedef struct {
|
||||
u8 numerator : 4;
|
||||
u8 denominator : 4;
|
||||
} pllmb_div;
|
||||
|
||||
constexpr pllmb_div div[] = {
|
||||
{3, 4}, {2, 3}, {1, 2}, {1, 3}, {1, 4}, {0, 2}
|
||||
};
|
||||
|
||||
constexpr u32 pll_osc_in = 38'400;
|
||||
u32 divm {}, divn {};
|
||||
const u32 remainder = C.marikoEmcMaxClock % pll_osc_in;
|
||||
for (const auto &index : div) {
|
||||
// Round down
|
||||
if (remainder >= pll_osc_in * index.numerator / index.denominator) {
|
||||
divm = index.denominator;
|
||||
divn = C.marikoEmcMaxClock / pll_osc_in * divm + index.numerator;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
table->pllmb_divm = divm;
|
||||
table->pllmb_divn = divn;
|
||||
}
|
||||
|
||||
Result MemFreqMtcTable(u32* ptr) {
|
||||
u32 khz_list[] = { 1600000, 1331200, 204000 };
|
||||
u32 khz_list_size = sizeof(khz_list) / sizeof(u32);
|
||||
|
||||
// Generate list for mtc table pointers
|
||||
MarikoMtcTable* table_list[khz_list_size];
|
||||
for (u32 i = 0; i < khz_list_size; i++) {
|
||||
u8* table = reinterpret_cast<u8 *>(ptr) - offsetof(MarikoMtcTable, rate_khz) - i * sizeof(MarikoMtcTable);
|
||||
table_list[i] = reinterpret_cast<MarikoMtcTable *>(table);
|
||||
R_UNLESS(table_list[i]->rate_khz == khz_list[i], ldr::ResultInvalidMtcTable());
|
||||
R_UNLESS(table_list[i]->rev == MTC_TABLE_REV, ldr::ResultInvalidMtcTable());
|
||||
}
|
||||
|
||||
if (C.marikoEmcMaxClock <= MemClkOSLimit)
|
||||
R_SKIP();
|
||||
|
||||
MarikoMtcTable *table_alt = table_list[1], *table_max = table_list[0];
|
||||
MarikoMtcTable *tmp = new MarikoMtcTable;
|
||||
|
||||
// Copy unmodified 1600000 table to tmp
|
||||
std::memcpy(reinterpret_cast<void *>(tmp), reinterpret_cast<void *>(table_max), sizeof(MarikoMtcTable));
|
||||
// Adjust max freq mtc timing parameters with reference to 1331200 table
|
||||
MemMtcTableAutoAdjust(table_max, table_alt);
|
||||
MemMtcPllmbDivisor(table_max);
|
||||
// Overwrite 13312000 table with unmodified 1600000 table copied back
|
||||
std::memcpy(reinterpret_cast<void *>(table_alt), reinterpret_cast<void *>(tmp), sizeof(MarikoMtcTable));
|
||||
|
||||
delete tmp;
|
||||
|
||||
PatchOffset(ptr, C.marikoEmcMaxClock);
|
||||
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
Result MemFreqDvbTable(u32* ptr) {
|
||||
emc_dvb_dvfs_table_t* default_end = reinterpret_cast<emc_dvb_dvfs_table_t *>(ptr);
|
||||
emc_dvb_dvfs_table_t* new_start = default_end + 1;
|
||||
|
||||
// Validate existing table
|
||||
void* mem_dvb_table_head = reinterpret_cast<u8 *>(new_start) - sizeof(EmcDvbTableDefault);
|
||||
bool validated = std::memcmp(mem_dvb_table_head, EmcDvbTableDefault, sizeof(EmcDvbTableDefault)) == 0;
|
||||
R_UNLESS(validated, ldr::ResultInvalidDvbTable());
|
||||
|
||||
if (C.marikoEmcMaxClock <= MemClkOSLimit)
|
||||
R_SKIP();
|
||||
|
||||
if (C.marikoEmcMaxClock <= 1862400) {
|
||||
std::memcpy(new_start, default_end, sizeof(emc_dvb_dvfs_table_t));
|
||||
} else {
|
||||
emc_dvb_dvfs_table_t oc_table = { 2131200, { 700, 675, 650, } };
|
||||
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
}
|
||||
new_start->freq = C.marikoEmcMaxClock;
|
||||
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
Result MemFreqMax(u32* ptr) {
|
||||
if (C.marikoEmcMaxClock <= MemClkOSLimit)
|
||||
R_SKIP();
|
||||
|
||||
PatchOffset(ptr, C.marikoEmcMaxClock);
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
void Patch(uintptr_t mapped_nso, size_t nso_size) {
|
||||
PatcherEntry<u32> patches[] = {
|
||||
{ "CPU Freq Vdd", &CpuFreqVdd, 1, nullptr, CpuClkOSLimit },
|
||||
{ "CPU Freq Table", &CpuFreqCvbTable, 1, nullptr, CpuClkOfficial },
|
||||
{ "CPU Volt Limit", &CpuVoltRange, 13, nullptr, CpuVoltOfficial },
|
||||
{ "GPU Freq Table", &GpuFreqCvbTable, 1, nullptr, GpuClkOfficial },
|
||||
{ "GPU Freq Asm", &GpuFreqMaxAsm, 2, &GpuMaxClockPatternFn },
|
||||
{ "GPU Freq PLL", &GpuFreqPllLimit, 1, nullptr, GpuClkPllLimit },
|
||||
{ "MEM Freq Mtc", &MemFreqMtcTable, 0, nullptr, MemClkOSLimit },
|
||||
{ "MEM Freq Dvb", &MemFreqDvbTable, 1, nullptr, MemClkOSLimit },
|
||||
{ "MEM Freq Max", &MemFreqMax, 0, nullptr, MemClkOSLimit },
|
||||
{ "MEM Freq PLLM", &MemFreqPllmLimit, 2, nullptr, MemClkPllmLimit },
|
||||
};
|
||||
|
||||
for (uintptr_t ptr = mapped_nso;
|
||||
ptr <= mapped_nso + nso_size - sizeof(MarikoMtcTable);
|
||||
ptr += sizeof(u32))
|
||||
{
|
||||
u32* ptr32 = reinterpret_cast<u32 *>(ptr);
|
||||
for (auto& entry : patches) {
|
||||
if (R_SUCCEEDED(entry.SearchAndApply(ptr32)))
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
for (auto& entry : patches) {
|
||||
LOGGING("%s Count: %zu", entry.description, entry.patched_count);
|
||||
if (R_FAILED(entry.CheckResult()))
|
||||
CRASH(entry.description);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
@@ -0,0 +1,130 @@
|
||||
/*
|
||||
* Copyright (C) Switch-OC-Suite
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "pcv.hpp"
|
||||
|
||||
namespace ams::ldr::oc::pcv::mariko {
|
||||
|
||||
constexpr cpu_freq_cvb_table_t CpuCvbTableDefault[] = {
|
||||
// CPUB01_CVB_TABLE
|
||||
{ 204000, { 721589, -12695, 27 }, {} },
|
||||
{ 306000, { 747134, -14195, 27 }, {} },
|
||||
{ 408000, { 776324, -15705, 27 }, {} },
|
||||
{ 510000, { 809160, -17205, 27 }, {} },
|
||||
{ 612000, { 845641, -18715, 27 }, {} },
|
||||
{ 714000, { 885768, -20215, 27 }, {} },
|
||||
{ 816000, { 929540, -21725, 27 }, {} },
|
||||
{ 918000, { 976958, -23225, 27 }, {} },
|
||||
{ 1020000, { 1028021, -24725, 27 }, { 1120000 } },
|
||||
{ 1122000, { 1082730, -26235, 27 }, { 1120000 } },
|
||||
{ 1224000, { 1141084, -27735, 27 }, { 1120000 } },
|
||||
{ 1326000, { 1203084, -29245, 27 }, { 1120000 } },
|
||||
{ 1428000, { 1268729, -30745, 27 }, { 1120000 } },
|
||||
{ 1581000, { 1374032, -33005, 27 }, { 1120000 } },
|
||||
{ 1683000, { 1448791, -34505, 27 }, { 1120000 } },
|
||||
{ 1785000, { 1527196, -36015, 27 }, { 1120000 } },
|
||||
{ 1887000, { 1609246, -37515, 27 }, { 1120000 } },
|
||||
{ 1963500, { 1675751, -38635, 27 }, { 1120000 } },
|
||||
};
|
||||
|
||||
constexpr cpu_freq_cvb_table_t CpuCvbTableAppend[] = {
|
||||
{ 2091000, { 1716501, -39395, 27 }, { 1120000 } },
|
||||
{ 2193000, { 1775132, -40505, 27 }, { 1120000 } },
|
||||
{ 2295000, { 1866287, -42005, 27 }, { 1120000 } },
|
||||
// 2397000 kHz is not listed in l4t
|
||||
{ 2397000, { 1961107, -43506, 27 }, { 1120000 } },
|
||||
};
|
||||
|
||||
constexpr u32 CpuMinVolts[] = { 800, 637, 620, 610 };
|
||||
|
||||
constexpr u32 CpuClkOfficial = 1963'500;
|
||||
constexpr u32 CpuVoltOfficial = 1120;
|
||||
|
||||
constexpr gpu_cvb_pll_table_t GpuCvbTableDefault[] = {
|
||||
// GPUB01_NA_CVB_TABLE
|
||||
{ 76800, {}, { 610000, } },
|
||||
{ 153600, {}, { 610000, } },
|
||||
{ 230400, {}, { 610000, } },
|
||||
{ 307200, {}, { 610000, } },
|
||||
{ 384000, {}, { 610000, } },
|
||||
{ 460800, {}, { 610000, } },
|
||||
{ 537600, {}, { 801688, -10900, -163, 298, -10599, 162 } },
|
||||
{ 614400, {}, { 824214, -5743, -452, 238, -6325, 81 } },
|
||||
{ 691200, {}, { 848830, -3903, -552, 119, -4030, -2 } },
|
||||
{ 768000, {}, { 891575, -4409, -584, 0, -2849, 39 } },
|
||||
{ 844800, {}, { 940071, -5367, -602, -60, -63, -93 } },
|
||||
{ 921600, {}, { 986765, -6637, -614, -179, 1905, -13 } },
|
||||
{ 998400, {}, { 1098475, -13529, -497, -179, 3626, 9 } },
|
||||
{ 1075200, {}, { 1163644, -12688, -648, 0, 1077, 40 } },
|
||||
{ 1152000, {}, { 1204812, -9908, -830, 0, 1469, 110 } },
|
||||
{ 1228800, {}, { 1277303, -11675, -859, 0, 3722, 313 } },
|
||||
{ 1267200, {}, { 1335531, -12567, -867, 0, 3681, 559 } },
|
||||
};
|
||||
|
||||
constexpr gpu_cvb_pll_table_t GpuCvbTableAppend[] = {
|
||||
// 1305600 kHz is not listed in l4t
|
||||
{ 1305600, {}, { 1374130, -13725, -859, 0, 4442, 576 } },
|
||||
};
|
||||
|
||||
constexpr u32 GpuClkOfficial = 1267'200;
|
||||
constexpr u32 GpuClkPllLimit = 1300'000'000;
|
||||
|
||||
/* GPU Max Clock asm Pattern:
|
||||
*
|
||||
* MOV W11, #0x1000 MOV (wide immediate) 0x1000 0xB (11)
|
||||
* sf | opc | | hw | imm16 | Rd
|
||||
* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
|
||||
* 0 | 1 0 | 1 0 0 1 0 1| 0 0| 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 |0 1 0 1 1
|
||||
*
|
||||
* MOVK W11, #0xE, LSL#16 <shift>16 0xE 0xB (11)
|
||||
* sf | opc | | hw | imm16 | Rd
|
||||
* #31 |30 29|28 27 26 25 24 23|22 21|20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 |4 3 2 1 0
|
||||
* 0 | 1 1 | 1 0 0 1 0 1| 0 1| 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 |0 1 0 1 1
|
||||
*/
|
||||
inline constexpr u32 asm_pattern[] = { 0x52820000, 0x72A001C0 };
|
||||
inline auto asm_compare_no_rd = [](u32 ins1, u32 ins2) { return ((ins1 ^ ins2) >> 5) == 0; };
|
||||
inline auto asm_get_rd = [](u32 ins) { return ins & ((1 << 5) - 1); };
|
||||
inline auto asm_set_rd = [](u32 ins, u8 rd) { return (ins & 0xFFFFFFE0) | (rd & 0x1F); };
|
||||
inline auto asm_set_imm16 = [](u32 ins, u16 imm) { return (ins & 0xFFE0001F) | ((imm & 0xFFFF) << 5); };
|
||||
|
||||
inline bool GpuMaxClockPatternFn(u32* ptr32) {
|
||||
return asm_compare_no_rd(*ptr32, asm_pattern[0]);
|
||||
}
|
||||
|
||||
constexpr emc_dvb_dvfs_table_t EmcDvbTableDefault[] = {
|
||||
{ 204000, { 637, 637, 637, } },
|
||||
{ 408000, { 637, 637, 637, } },
|
||||
{ 800000, { 637, 637, 637, } },
|
||||
{ 1065600, { 637, 637, 637, } },
|
||||
{ 1331200, { 650, 637, 637, } },
|
||||
{ 1600000, { 675, 650, 637, } },
|
||||
};
|
||||
|
||||
constexpr emc_dvb_dvfs_table_t EmcDvbTableReplaced[] = {
|
||||
{ 1862400, { 675, 650, 637, } },
|
||||
{ 2133000, { 700, 675, 650, } },
|
||||
};
|
||||
|
||||
constexpr u32 MemClkOSAlt = 1331'200;
|
||||
constexpr u32 MemClkPllmLimit = 2133'000'000;
|
||||
|
||||
constexpr u32 MTC_TABLE_REV = 3;
|
||||
|
||||
void Patch(uintptr_t mapped_nso, size_t nso_size);
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user