OmniNX/Horizon-OC
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge pull request #6 from Lightos1/master

Browse Source 
Proper AUTO_ADJ for erista
This commit is contained in:
Souldbminer
2025-09-30 18:34:09 -04:00
committed by GitHub
parent f7c919e47d 9f7008e6e6
commit acf45ffa5e
14 changed files with 405 additions and 502 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
Source/Atmosphere/stratosphere/loader/source/oc/customize.cpp
View File

@@ -1,8 +1,10 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) 2023 hanai3Bi
* *
* Copyright (c) Souldbminer and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation. * version 2, as published by the Free Software Foundation.
@@ -89,7 +91,6 @@ volatile CustomizeTable C = {
.marikoGpuUV = 0, .marikoGpuUV = 0,
.eristaCpuUV = 0, .eristaCpuUV = 0,
.eristaGpuUV = 0, .eristaGpuUV = 0,
@@ -134,7 +135,7 @@ volatile CustomizeTable C = {
675 /* 998 */, 675 /* 998 */,
710 /* 1075 */, 710 /* 1075 */,
735 /* 1152 */, 735 /* 1152 */,
785 /* 1228 (Only safe if GPU Scheduling is on)*/, 785 /* 1228 */,
0 /* 1267 (Disabled by default) */, 0 /* 1267 (Disabled by default) */,
0 /* 1305 (Disabled by default) */, 0 /* 1305 (Disabled by default) */,
0 /* 1344 (Disabled by default) */, 0 /* 1344 (Disabled by default) */,

8
Source/Atmosphere/stratosphere/loader/source/oc/customize.hpp
View File

@@ -1,8 +1,10 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) 2023 hanai3Bi
* *
* Copyright (c) Souldbminer and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation. * version 2, as published by the Free Software Foundation.
@@ -33,6 +35,7 @@
NO_ADJ_ALL = 2, NO_ADJ_ALL = 2,
CUSTOMIZED_ALL = 4, CUSTOMIZED_ALL = 4,
AUTO_ADJ = 5,
}; };
using CustomizeCpuDvfsTable = pcv::cvb_entry_t[pcv::DvfsTableEntryLimit]; using CustomizeCpuDvfsTable = pcv::cvb_entry_t[pcv::DvfsTableEntryLimit];
@@ -46,7 +49,8 @@
typedef struct CustomizeTable { typedef struct CustomizeTable {
u8 cust[4] = {'C', 'U', 'S', 'T'}; u8 cust[4] = {'C', 'U', 'S', 'T'};
u32 custRev = CUST_REV; u32 custRev = CUST_REV;
u32 mtcConf = AUTO_ADJ_ALL; u32 mtcConfErista = AUTO_ADJ;
u32 mtcConfMariko = AUTO_ADJ_ALL; // TODO: Fix mariko and merge into mtcConf
u32 commonCpuBoostClock; u32 commonCpuBoostClock;
u32 commonEmcMemVolt; u32 commonEmcMemVolt;
u32 eristaCpuMaxVolt; u32 eristaCpuMaxVolt;

46
Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp
View File

@@ -1,6 +1,4 @@
/* /*
* Copyright (c) Souldbminer & Horizon OC Contributors
*
* Copyright (c) 2023 hanai3Bi * Copyright (c) 2023 hanai3Bi
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
@@ -81,22 +79,21 @@
// tRC (ACTIVATE-ACTIVATE command period same bank) in ns // tRC (ACTIVATE-ACTIVATE command period same bank) in ns
const u32 tRC = tRPpb + tRAS; const u32 tRC = tRPpb + tRAS;
const u32 tRTW = !C.t6_tRTW ? 10 : tWTR_values[C.t6_tRTW-1]; const u32 tRTW = !C.t6_tRTW ? 10 : tWTR_values[C.t6_tRTW-1];
// DQS output access time from CK_t/CK_c // DQS output access time from CK_t/CK_c
const double tDQSCK_min = 1.5; const double tDQSCK_min = 1.5; // TODO: Fix/remove for mariko if needed
// DQS output access time from CK_t/CK_c // DQS output access time from CK_t/CK_c
const double tDQSCK_max = 3.5; const double tDQSCK_max = 3.5; // TODO: Fix/remove for mariko if needed
// Write preamble (tCK) // Write preamble (tCK)
const double tWPRE = 1.8; const double tWPRE = 1.8; // TODO: Fix/remove for mariko if needed
// Read postamble (tCK) // Read postamble (tCK)
const double tRPST = 0.4; const double tRPST = 0.4; // TODO: Fix/remove for mariko if needed
// WRITE command to first DQS transition(max) (tCK) // WRITE command to first DQS transition(max) (tCK)
const double tDQSS_max = 1.25; const double tDQSS_max = 1.25; // TODO: Fix/remove for mariko if needed
// DQ-to-DQS offset(max) (ns) // DQ-to-DQS offset(max) (ns)
const double tDQS2DQ_max = 0.8; const double tDQS2DQ_max = 0.8; // TODO: Fix/remove for mariko if needed
// DQS_t, DQS_c to DQ skew total, per group, per access (DBI Disabled) // DQS_t, DQS_c to DQ skew total, per group, per access (DBI Disabled)
const double tDQSQ = 0.18; const double tDQSQ = 0.18; // TODO: Fix/remove for mariko if needed
// Write-to-Read delay // Write-to-Read delay
const u32 tWTR = !C.t7_tWTR ? 10 : tWTR_values[C.t7_tWTR-1]; const u32 tWTR = !C.t7_tWTR ? 10 : tWTR_values[C.t7_tWTR-1];
@@ -127,23 +124,23 @@
const double tXP = 10; const double tXP = 10;
// Delay from valid command to CKE input LOW in ns // Delay from valid command to CKE input LOW in ns
const double tCMDCKE = 1.75; const double tCMDCKE = 1.75; // TODO: Fix/remove for mariko if needed
// tACT2PDEN (timing delay from an activate, MRS or EMRS command to power-down entry) in ns // tACT2PDEN (timing delay from an activate, MRS or EMRS command to power-down entry) in ns
// Valid clock and CS requirement after CKE input LOW after MRW command // Valid clock and CS requirement after CKE input LOW after MRW command
const u32 tMRWCKEL = 14; const u32 tMRWCKEL = 14; // TODO: Fix/remove for mariko if needed
// Valid CS requirement after CKE input LOW // Valid CS requirement after CKE input LOW
const double tCKELCS = 5; const double tCKELCS = 5; // TODO: Fix/remove for mariko if needed
// Valid CS requirement before CKE input HIGH // Valid CS requirement before CKE input HIGH
const double tCSCKEH = 1.75; const double tCSCKEH = 1.75; // TODO: Fix/remove for mariko if needed
// tXSR (SELF REFRESH exit to next valid command delay) in ns // tXSR (SELF REFRESH exit to next valid command delay) in ns
const double tXSR = tRFCab + 7.5; const double tXSR = tRFCab + 7.5;
// tCKE (minimum pulse width(HIGH and LOW pulse width)) in ns // tCKE (minimum pulse width(HIGH and LOW pulse width)) in ns
const double tCKE = 7.5; const double tCKE = 7.5; // TODO: Fix/remove for mariko if needed
// Minimum self refresh time (entry to exit) // Minimum self refresh time (entry to exit)
const u32 tSR = 15; const u32 tSR = 15;
@@ -152,7 +149,7 @@
const u32 tFAW = 40;// !TIMING_PRESET_TWO ? 40 : tFAW_values[TIMING_PRESET_TWO-1]; TOGO const u32 tFAW = 40;// !TIMING_PRESET_TWO ? 40 : tFAW_values[TIMING_PRESET_TWO-1]; TOGO
// Valid Clock requirement before CKE Input HIGH in ns // Valid Clock requirement before CKE Input HIGH in ns
const double tCKCKEH = 1.75; const double tCKCKEH = 1.75; // TODO: Fix/remove for mariko if needed
// p78 The first valid data is available RL × t CK + t DQSCK + t DQSQ // p78 The first valid data is available RL × t CK + t DQSCK + t DQSQ
//const u32 QUSE = RL + CEIL(tDQSCK_min/tCK_avg + tDQSQ); //const u32 QUSE = RL + CEIL(tDQSCK_min/tCK_avg + tDQSQ);
@@ -167,16 +164,16 @@
const u32 RL = 32 - C.mem_burst_latency; const u32 RL = 32 - C.mem_burst_latency;
// minimum number of cycles from any read command to any write command, irrespective of bank // minimum number of cycles from any read command to any write command, irrespective of bank
const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6; // const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6;
// Delay Time From WRITE-to-READ // Delay Time From WRITE-to-READ
const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg) - 6; // const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg) - 6;
// write-to-precharge time for commands to the same bank in cycles // write-to-precharge time for commands to the same bank in cycles
const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8; // const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
// #_of_rows per die for 8Gb density // #_of_rows per die for 16Gb density
const u32 numOfRows = 65536; const u32 numOfRows = 131072;
// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%] // {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
// emc_clk_period = dram_clk / 2; // emc_clk_period = dram_clk / 2;
// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin) // 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
@@ -184,13 +181,13 @@
const u32 REFBW = MIN((u32)65536, REFRESH+64); const u32 REFBW = MIN((u32)65536, REFRESH+64);
// Write With Auto Precharge to to Power-Down Entry // Write With Auto Precharge to to Power-Down Entry
const u32 WTPDEN = WTP + 1 + CEIL(tDQSS_max/tCK_avg) + CEIL(tDQS2DQ_max/tCK_avg) + 6; // const u32 WTPDEN = WTP + 1 + CEIL(tDQSS_max/tCK_avg) + CEIL(tDQS2DQ_max/tCK_avg) + 6;
// Additional time after t XP hasexpired until the MRR commandmay be issued // Additional time after t XP hasexpired until the MRR commandmay be issued
const double tMRRI = tRCD + 3 * tCK_avg; // const double tMRRI = tRCD + 3 * tCK_avg;
// tPDEX2MRR (timing delay from exiting powerdown mode to MRR command) in ns // tPDEX2MRR (timing delay from exiting powerdown mode to MRR command) in ns
const double tPDEX2MRR = tXP + tMRRI; // const double tPDEX2MRR = tXP + tMRRI;
} }
namespace pcv::mariko { namespace pcv::mariko {
// tCK_avg (average clock period) in ns // tCK_avg (average clock period) in ns
@@ -239,4 +236,3 @@
const double tPDEX2MRR = tXP + tMRRI; const double tPDEX2MRR = tXP + tMRRI;
} }
} }

4
Source/Atmosphere/stratosphere/loader/source/oc/oc_common.hpp
View File

@@ -1,7 +1,7 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) Souldbminer and Horizon OC Contributors
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,

4
Source/Atmosphere/stratosphere/loader/source/oc/oc_loader.hpp
View File

@@ -1,7 +1,7 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) Souldbminer and Horizon OC Contributors
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,

4
Source/Atmosphere/stratosphere/loader/source/oc/oc_test.cpp
View File

@@ -1,7 +1,7 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) Souldbminer and Horizon OC Contributors
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,

4
Source/Atmosphere/stratosphere/loader/source/oc/oc_test.hpp
View File

@@ -1,7 +1,7 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) Souldbminer and Horizon OC Contributors
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,

4
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv.cpp
View File

@@ -1,8 +1,10 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) 2023 hanai3Bi
* *
* Copyright (c) Souldbminer and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation. * version 2, as published by the Free Software Foundation.

4
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv.hpp
View File

@@ -1,8 +1,10 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) 2023 hanai3Bi
* *
* Copyright (c) Souldbminer and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation. * version 2, as published by the Free Software Foundation.

4
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_common.hpp
View File

@@ -1,7 +1,7 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) Souldbminer and Horizon OC Contributors
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,

162
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp
View File

@@ -1,8 +1,10 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) 2023 hanai3Bi
* *
* Copyright (c) Souldbminer and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation. * version 2, as published by the Free Software Foundation.
@@ -19,8 +21,7 @@
#include "pcv.hpp" #include "pcv.hpp"
#include "../mtc_timing_value.hpp" #include "../mtc_timing_value.hpp"
namespace ams::ldr::oc::pcv::erista namespace ams::ldr::oc::pcv::erista {
{
Result CpuFreqVdd(u32* ptr) { Result CpuFreqVdd(u32* ptr) {
dvfs_rail* entry = reinterpret_cast<dvfs_rail *>(reinterpret_cast<u8 *>(ptr) - offsetof(dvfs_rail, freq)); dvfs_rail* entry = reinterpret_cast<dvfs_rail *>(reinterpret_cast<u8 *>(ptr) - offsetof(dvfs_rail, freq));
@@ -41,18 +42,15 @@
R_SUCCEED(); R_SUCCEED();
} }
Result GpuVmin(u32 *ptr) Result GpuVmin(u32 *ptr) {
{
if (!C.eristaGpuVmin) if (!C.eristaGpuVmin)
R_SKIP(); R_SKIP();
PATCH_OFFSET(ptr, (int)C.eristaGpuVmin); PATCH_OFFSET(ptr, (int)C.eristaGpuVmin);
R_SUCCEED(); R_SUCCEED();
} }
Result CpuVoltRange(u32 *ptr) Result CpuVoltRange(u32 *ptr) {
{
u32 min_volt_got = *(ptr - 1); u32 min_volt_got = *(ptr - 1);
for (const auto &mv : CpuMinVolts) for (const auto &mv : CpuMinVolts) {
{
if (min_volt_got != mv) if (min_volt_got != mv)
continue; continue;
@@ -105,8 +103,7 @@
R_SUCCEED(); R_SUCCEED();
} }
Result GpuFreqMaxAsm(u32 *ptr32) Result GpuFreqMaxAsm(u32 *ptr32) {
{
// Check if both two instructions match the pattern // Check if both two instructions match the pattern
u32 ins1 = *ptr32, ins2 = *(ptr32 + 1); u32 ins1 = *ptr32, ins2 = *(ptr32 + 1);
if (!(asm_compare_no_rd(ins1, asm_pattern[0]) && asm_compare_no_rd(ins2, asm_pattern[1]))) if (!(asm_compare_no_rd(ins1, asm_pattern[0]) && asm_compare_no_rd(ins2, asm_pattern[1])))
@@ -118,8 +115,7 @@
R_THROW(ldr::ResultInvalidGpuFreqMaxPattern()); R_THROW(ldr::ResultInvalidGpuFreqMaxPattern());
u32 max_clock; u32 max_clock;
switch (C.eristaGpuUV) switch (C.eristaGpuUV) {
{
case 0: case 0:
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTable)->freq; max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTable)->freq;
break; break;
@@ -130,12 +126,9 @@
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTableHigh)->freq; max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTableHigh)->freq;
break; break;
case 3: case 3:
if(C.enableEristaGpuUnsafeFreqs) if(C.enableEristaGpuUnsafeFreqs) {
{
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTableUv3UnsafeFreqs)->freq; max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTableUv3UnsafeFreqs)->freq;
} } else {
else
{
max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTable)->freq; max_clock = GetDvfsTableLastEntry(C.eristaGpuDvfsTable)->freq;
} }
break; break;
@@ -152,13 +145,11 @@
R_SUCCEED(); R_SUCCEED();
} }
Result GpuFreqPllLimit(u32 *ptr) Result GpuFreqPllLimit(u32 *ptr) {
{
clk_pll_param *entry = reinterpret_cast<clk_pll_param *>(ptr); clk_pll_param *entry = reinterpret_cast<clk_pll_param *>(ptr);
// All zero except for freq // All zero except for freq
for (size_t i = 1; i < sizeof(clk_pll_param) / sizeof(u32); i++) for (size_t i = 1; i < sizeof(clk_pll_param) / sizeof(u32); i++) {
{
R_UNLESS(*(ptr + i) == 0, ldr::ResultInvalidGpuPllEntry()); R_UNLESS(*(ptr + i) == 0, ldr::ResultInvalidGpuPllEntry());
} }
@@ -168,9 +159,8 @@
R_SUCCEED(); R_SUCCEED();
} }
void MemMtcTableAutoAdjust(EristaMtcTable *table) void MemMtcTableAutoAdjust(EristaMtcTable *table) {
{ if (C.mtcConfErista != AUTO_ADJ)
if (C.mtcConf != AUTO_ADJ_ALL)
return; return;
#define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \ #define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \
@@ -186,10 +176,7 @@
WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb)); WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb));
WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS)); WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS));
WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb)); WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb));
WRITE_PARAM_ALL_REG(table, emc_r2w, R2W);
WRITE_PARAM_ALL_REG(table, emc_w2r, W2R);
WRITE_PARAM_ALL_REG(table, emc_r2p, GET_CYCLE_CEIL(tRTP)); WRITE_PARAM_ALL_REG(table, emc_r2p, GET_CYCLE_CEIL(tRTP));
WRITE_PARAM_ALL_REG(table, emc_w2p, WTP);
WRITE_PARAM_ALL_REG(table, emc_rd_rcd, GET_CYCLE_CEIL(tRCD)); WRITE_PARAM_ALL_REG(table, emc_rd_rcd, GET_CYCLE_CEIL(tRCD));
WRITE_PARAM_ALL_REG(table, emc_wr_rcd, GET_CYCLE_CEIL(tRCD)); WRITE_PARAM_ALL_REG(table, emc_wr_rcd, GET_CYCLE_CEIL(tRCD));
WRITE_PARAM_ALL_REG(table, emc_rrd, GET_CYCLE_CEIL(tRRD)); WRITE_PARAM_ALL_REG(table, emc_rrd, GET_CYCLE_CEIL(tRRD));
@@ -197,22 +184,11 @@
WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4); WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tXP)); WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tXP));
WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tXP)); WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tXP));
WRITE_PARAM_ALL_REG(table, emc_pchg2pden, GET_CYCLE_CEIL(tCMDCKE));
WRITE_PARAM_ALL_REG(table, emc_act2pden, GET_CYCLE_CEIL(tMRWCKEL));
WRITE_PARAM_ALL_REG(table, emc_ar2pden, GET_CYCLE_CEIL(tCMDCKE));
WRITE_PARAM_ALL_REG(table, emc_rw2pden, WTPDEN);
WRITE_PARAM_ALL_REG(table, emc_cke2pden, GET_CYCLE_CEIL(tCKELCS));
WRITE_PARAM_ALL_REG(table, emc_pdex2cke, GET_CYCLE_CEIL(tCSCKEH));
WRITE_PARAM_ALL_REG(table, emc_pdex2mrr, GET_CYCLE_CEIL(tPDEX2MRR));
WRITE_PARAM_ALL_REG(table, emc_txsr, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe)); WRITE_PARAM_ALL_REG(table, emc_txsr, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
WRITE_PARAM_ALL_REG(table, emc_txsrdll, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe)); WRITE_PARAM_ALL_REG(table, emc_txsrdll, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
WRITE_PARAM_ALL_REG(table, emc_tcke, GET_CYCLE_CEIL(tCKE));
WRITE_PARAM_ALL_REG(table, emc_tckesr, GET_CYCLE_CEIL(tSR)); WRITE_PARAM_ALL_REG(table, emc_tckesr, GET_CYCLE_CEIL(tSR));
WRITE_PARAM_ALL_REG(table, emc_tpd, GET_CYCLE_CEIL(tCKE));
WRITE_PARAM_ALL_REG(table, emc_tfaw, GET_CYCLE_CEIL(tFAW)); WRITE_PARAM_ALL_REG(table, emc_tfaw, GET_CYCLE_CEIL(tFAW));
WRITE_PARAM_ALL_REG(table, emc_trpab, GET_CYCLE_CEIL(tRPab)); WRITE_PARAM_ALL_REG(table, emc_trpab, GET_CYCLE_CEIL(tRPab));
WRITE_PARAM_ALL_REG(table, emc_tclkstable, GET_CYCLE_CEIL(tCKCKEH));
WRITE_PARAM_ALL_REG(table, emc_tclkstop, GET_CYCLE_CEIL(tCKE) + 8);
WRITE_PARAM_ALL_REG(table, emc_trefbw, REFBW); WRITE_PARAM_ALL_REG(table, emc_trefbw, REFBW);
#define WRITE_PARAM_BURST_MC_REG(TABLE, PARAM, VALUE) TABLE->burst_mc_regs.PARAM = VALUE; #define WRITE_PARAM_BURST_MC_REG(TABLE, PARAM, VALUE) TABLE->burst_mc_regs.PARAM = VALUE;
@@ -225,98 +201,23 @@
table->burst_mc_regs.mc_emem_arb_timing_ras = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2; table->burst_mc_regs.mc_emem_arb_timing_ras = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2;
table->burst_mc_regs.mc_emem_arb_timing_faw = CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1; table->burst_mc_regs.mc_emem_arb_timing_faw = CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1;
table->burst_mc_regs.mc_emem_arb_timing_rrd = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1; table->burst_mc_regs.mc_emem_arb_timing_rrd = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1;
table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV); //table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV);
table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV); //table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
// table->burst_mc_regs.mc_emem_arb_timing_r2r = CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA; // table->burst_mc_regs.mc_emem_arb_timing_r2r = CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
// table->burst_mc_regs.mc_emem_arb_timing_w2w = CEIL(table->burst_regs.emc_wext / MC_ARB_DIV) - 1 + MC_ARB_SFA; // table->burst_mc_regs.mc_emem_arb_timing_w2w = CEIL(table->burst_regs.emc_wext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
table->burst_mc_regs.mc_emem_arb_timing_r2w = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA; // table->burst_mc_regs.mc_emem_arb_timing_r2w = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA;
table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA; // table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
table->burst_mc_regs.mc_emem_arb_timing_rfcpb = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV); table->burst_mc_regs.mc_emem_arb_timing_rfcpb = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV);
// table->burst_mc_regs.mc_emem_arb_timing_ccdmw = CEIL(tCCDMW / MC_ARB_DIV) -1 + MC_ARB_SFA; // table->burst_mc_regs.mc_emem_arb_timing_ccdmw = CEIL(tCCDMW / MC_ARB_DIV) -1 + MC_ARB_SFA;
} }
void MemMtcTableCustomAdjust(EristaMtcTable *table) Result MemFreqMtcTable(u32 *ptr) {
{
if (C.mtcConf != CUSTOM_ADJ_ALL)
return;
constexpr u32 MC_ARB_DIV = 4;
constexpr u32 MC_ARB_SFA = 2;
WRITE_PARAM_ALL_REG(table, emc_rc, GET_CYCLE_CEIL(tRC));
WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS));
WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb));
WRITE_PARAM_ALL_REG(table, emc_trpab, GET_CYCLE_CEIL(tRPab));
WRITE_PARAM_ALL_REG(table, emc_rd_rcd, GET_CYCLE_CEIL(tRCD));
WRITE_PARAM_ALL_REG(table, emc_wr_rcd, GET_CYCLE_CEIL(tRCD));
WRITE_PARAM_ALL_REG(table, emc_pdex2mrr, GET_CYCLE_CEIL(tPDEX2MRR));
table->burst_mc_regs.mc_emem_arb_timing_rcd = CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV - 2);
table->burst_mc_regs.mc_emem_arb_timing_rc = CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV - 1);
table->burst_mc_regs.mc_emem_arb_timing_rp = CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV - 1 + MC_ARB_SFA);
table->burst_mc_regs.mc_emem_arb_timing_ras = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV - 2);
WRITE_PARAM_ALL_REG(table, emc_tfaw, GET_CYCLE_CEIL(tFAW));
WRITE_PARAM_ALL_REG(table, emc_rrd, GET_CYCLE_CEIL(tRRD));
table->burst_mc_regs.mc_emem_arb_timing_faw = CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1;
table->burst_mc_regs.mc_emem_arb_timing_rrd = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1;
WRITE_PARAM_ALL_REG(table, emc_r2p, GET_CYCLE_CEIL(tRTP));
WRITE_PARAM_ALL_REG(table, emc_w2p, WTP);
WRITE_PARAM_ALL_REG(table, emc_rw2pden, WTPDEN);
table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV);
table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
WRITE_PARAM_ALL_REG(table, emc_rfc, GET_CYCLE_CEIL(tRFCab));
WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb));
WRITE_PARAM_ALL_REG(table, emc_txsr, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
WRITE_PARAM_ALL_REG(table, emc_txsrdll, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
table->burst_mc_regs.mc_emem_arb_timing_rfcpb = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV);
WRITE_PARAM_ALL_REG(table, emc_w2r, W2R);
table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
WRITE_PARAM_ALL_REG(table, emc_refresh, REFRESH);
WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
WRITE_PARAM_ALL_REG(table, emc_trefbw, REFBW);
WRITE_PARAM_ALL_REG(table, emc_r2w, R2W);
WRITE_PARAM_ALL_REG(table, emc_w2r, W2R);
WRITE_PARAM_ALL_REG(table, emc_w2p, WTP);
WRITE_PARAM_ALL_REG(table, emc_rw2pden, WTPDEN);
table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
table->burst_mc_regs.mc_emem_arb_timing_r2w = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA;
table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
u32 DA_TURNS = 0;
DA_TURNS |= u8(table->burst_mc_regs.mc_emem_arb_timing_r2w / 2) << 16; // R2W TURN
DA_TURNS |= u8(table->burst_mc_regs.mc_emem_arb_timing_w2r / 2) << 24; // W2R TURN
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_da_turns, DA_TURNS);
u32 DA_COVERS = 0;
u8 R_COVER = (table->burst_mc_regs.mc_emem_arb_timing_rap2pre + table->burst_mc_regs.mc_emem_arb_timing_rp + table->burst_mc_regs.mc_emem_arb_timing_rcd) / 2;
u8 W_COVER = (table->burst_mc_regs.mc_emem_arb_timing_wap2pre + table->burst_mc_regs.mc_emem_arb_timing_rp + table->burst_mc_regs.mc_emem_arb_timing_rcd) / 2;
DA_COVERS |= (u8)(table->burst_mc_regs.mc_emem_arb_timing_rc / 2); // RC COVER
DA_COVERS |= (R_COVER << 8); // RCD_R COVER
DA_COVERS |= (W_COVER << 16); // RCD_W COVER
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_da_covers, DA_COVERS);
}
Result MemFreqMtcTable(u32 *ptr)
{
u32 khz_list[] = {1600000, 1331200, 1065600, 800000, 665600, 408000, 204000, 102000, 68000, 40800}; u32 khz_list[] = {1600000, 1331200, 1065600, 800000, 665600, 408000, 204000, 102000, 68000, 40800};
u32 khz_list_size = sizeof(khz_list) / sizeof(u32); u32 khz_list_size = sizeof(khz_list) / sizeof(u32);
// Generate list for mtc table pointers // Generate list for mtc table pointers
EristaMtcTable *table_list[khz_list_size]; EristaMtcTable *table_list[khz_list_size];
for (u32 i = 0; i < khz_list_size; i++) for (u32 i = 0; i < khz_list_size; i++) {
{
u8 *table = reinterpret_cast<u8 *>(ptr) - offsetof(EristaMtcTable, rate_khz) - i * sizeof(EristaMtcTable); u8 *table = reinterpret_cast<u8 *>(ptr) - offsetof(EristaMtcTable, rate_khz) - i * sizeof(EristaMtcTable);
table_list[i] = reinterpret_cast<EristaMtcTable *>(table); table_list[i] = reinterpret_cast<EristaMtcTable *>(table);
R_UNLESS(table_list[i]->rate_khz == khz_list[i], ldr::ResultInvalidMtcTable()); R_UNLESS(table_list[i]->rate_khz == khz_list[i], ldr::ResultInvalidMtcTable());
@@ -342,8 +243,7 @@
R_SUCCEED(); R_SUCCEED();
} }
Result MemFreqMax(u32 *ptr) Result MemFreqMax(u32 *ptr) {
{
if (C.eristaEmcMaxClock <= EmcClkOSLimit) if (C.eristaEmcMaxClock <= EmcClkOSLimit)
R_SKIP(); R_SKIP();
@@ -352,16 +252,15 @@
R_SUCCEED(); R_SUCCEED();
} }
void Patch(uintptr_t mapped_nso, size_t nso_size) void Patch(uintptr_t mapped_nso, size_t nso_size) {
{
u32 CpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(CpuCvbTableDefault)->freq); u32 CpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(CpuCvbTableDefault)->freq);
u32 GpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(GpuCvbTableDefault)->freq); u32 GpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(GpuCvbTableDefault)->freq);
PatcherEntry<u32> patches[] = { PatcherEntry<u32> patches[] = {
{ "CPU Freq Vdd", &CpuFreqVdd, 1, nullptr, CpuClkOSLimit }, {"CPU Freq Vdd", &CpuFreqVdd, 1, nullptr, CpuClkOSLimit },
{"CPU Freq Table", CpuFreqCvbTable<false>, 1, nullptr, CpuCvbDefaultMaxFreq}, {"CPU Freq Table", CpuFreqCvbTable<false>, 1, nullptr, CpuCvbDefaultMaxFreq},
{ "CPU Volt Limit", &CpuVoltRange, 13, nullptr, CpuVoltOfficial }, {"CPU Volt Limit", &CpuVoltRange, 13, nullptr, CpuVoltOfficial },
{ "CPU Volt Dfll", &CpuVoltDfll, 1, nullptr, 0xFFEAD0FF }, {"CPU Volt Dfll", &CpuVoltDfll, 1, nullptr, 0xFFEAD0FF },
{"GPU Freq Table", GpuFreqCvbTable<false>, 1, nullptr, GpuCvbDefaultMaxFreq}, {"GPU Freq Table", GpuFreqCvbTable<false>, 1, nullptr, GpuCvbDefaultMaxFreq},
{"GPU Freq Asm", &GpuFreqMaxAsm, 2, &GpuMaxClockPatternFn}, {"GPU Freq Asm", &GpuFreqMaxAsm, 2, &GpuMaxClockPatternFn},
{"GPU Freq PLL", &GpuFreqPllLimit, 1, nullptr, GpuClkPllLimit}, {"GPU Freq PLL", &GpuFreqPllLimit, 1, nullptr, GpuClkPllLimit},
@@ -374,18 +273,15 @@
for (uintptr_t ptr = mapped_nso; for (uintptr_t ptr = mapped_nso;
ptr <= mapped_nso + nso_size - sizeof(EristaMtcTable); ptr <= mapped_nso + nso_size - sizeof(EristaMtcTable);
ptr += sizeof(u32)) ptr += sizeof(u32)) {
{
u32 *ptr32 = reinterpret_cast<u32 *>(ptr); u32 *ptr32 = reinterpret_cast<u32 *>(ptr);
for (auto &entry : patches) for (auto &entry : patches) {
{
if (R_SUCCEEDED(entry.SearchAndApply(ptr32))) if (R_SUCCEEDED(entry.SearchAndApply(ptr32)))
break; break;
} }
} }
for (auto &entry : patches) for (auto &entry : patches) {
{
LOGGING("%s Count: %zu", entry.description, entry.patched_count); LOGGING("%s Count: %zu", entry.description, entry.patched_count);
if (R_FAILED(entry.CheckResult())) if (R_FAILED(entry.CheckResult()))
CRASH(entry.description); CRASH(entry.description);

8
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp
View File

@@ -1,8 +1,10 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) 2023 hanai3Bi
* *
* Copyright (c) Souldbminer and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation. * version 2, as published by the Free Software Foundation.
@@ -225,7 +227,7 @@ Result GpuVmax(u32 *ptr)
* you'd better calculate timings yourself rather than relying on following algorithm. * you'd better calculate timings yourself rather than relying on following algorithm.
*/ */
if (C.mtcConf != AUTO_ADJ_ALL) if (C.mtcConfMariko != AUTO_ADJ_ALL)
return; return;
// scale with linear interpolation // scale with linear interpolation
@@ -398,7 +400,7 @@ Result GpuVmax(u32 *ptr)
} }
void MemMtcTableCustomAdjust(MarikoMtcTable* table) { void MemMtcTableCustomAdjust(MarikoMtcTable* table) {
if (C.mtcConf != CUSTOM_ADJ_ALL) if (C.mtcConfMariko != CUSTOM_ADJ_ALL)
return; return;
constexpr u32 MC_ARB_DIV = 4; constexpr u32 MC_ARB_DIV = 4;

4
Source/Atmosphere/stratosphere/loader/source/oc/ptm/ptm.cpp
View File

@@ -1,7 +1,7 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) Souldbminer and Horizon OC Contributors
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,

4
Source/Atmosphere/stratosphere/loader/source/oc/ptm/ptm.hpp
View File

@@ -1,7 +1,7 @@
/* /*
* Copyright (c) Souldbminer and Horizon OC Contributors * Copyright (C) Switch-OC-Suite
* *
* Copyright (c) 2023 hanai3Bi * Copyright (c) Souldbminer and Horizon OC Contributors
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License, * under the terms and conditions of the GNU General Public License,