From a251178b4c20b352b37ad1077ec1d67500a77fa9 Mon Sep 17 00:00:00 2001 From: KazushiM <85604869+KazushiMe@users.noreply.github.com> Date: Tue, 25 Jan 2022 18:54:12 +0800 Subject: [PATCH] use erista mtc table as tmp buffer for copying and referencing mariko mtc table --- README.md | 2 +- .../loader/source/ldr_oc_patch.hpp | 260 ++-- .../loader/source/mtc_timing_table.hpp | 1260 ++++++++++++++++- 3 files changed, 1396 insertions(+), 126 deletions(-) diff --git a/README.md b/README.md index 9a505f73..a948c845 100644 --- a/README.md +++ b/README.md @@ -115,7 +115,7 @@ If you are to install nro forwarders, remove `R_TRY(ValidateAcidSignature(std::a -### Why no CPU/GPU OC for Erista? +## Why no CPU/GPU OC for Erista? - Tegra X1 on Erista is on TSMC 20nm HPM node, consumes much more power (~2x) and generates much more heat, compared to Tegra X1+ on Mariko (TSMC 16nm FinFET). - Erista Switch uses lower speedo (=== lower quality === higher voltage required) SoC from NVIDIA. You will NOT get comparable performance to NVIDIA Shield TV no matter what. diff --git a/Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp b/Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp index 227c9db9..572f7ebf 100644 --- a/Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp +++ b/Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp @@ -39,6 +39,8 @@ namespace ams::ldr { constexpr u32 GpuClkOfficial = 1267'200; constexpr u32 CpuVoltOfficial = 1120; constexpr u32 MemClkOSLimit = 1600'000; + constexpr u32 MemClkOSAlt = 1331'200; + constexpr u32 MemClkOSClampDn = 1065'600; inline void PatchOffset(uintptr_t offset, u32 value) { *(reinterpret_cast(offset)) = value; @@ -182,7 +184,11 @@ namespace ams::ldr { * you'd better calculate timings yourself rather than relying on following algorithm. */ - #define ADJUST_PARAM(TARGET, REF) TARGET = std::ceil(REF + ((EmcClock-1331200)*(TARGET-REF))/(1600000-1331200)); + #define ADJUST_PROP(TARGET, REF) \ + (u32)(std::ceil(REF + ((EmcClock-MemClkOSAlt)*(TARGET-REF))/(MemClkOSLimit-MemClkOSAlt))) + + #define ADJUST_PARAM(TARGET, REF) \ + TARGET = ADJUST_PROP(TARGET, REF); #define ADJUST_PARAM_TABLE(TABLE, PARAM, REF) ADJUST_PARAM(TABLE->PARAM, REF->PARAM) @@ -196,6 +202,62 @@ namespace ams::ldr { TABLE->shadow_regs_ca_train.PARAM = VALUE; \ TABLE->shadow_regs_rdwr_train.PARAM = VALUE; + ADJUST_PARAM_ALL_REG(table, emc_r2w, ref); + ADJUST_PARAM_ALL_REG(table, emc_w2r, ref); + ADJUST_PARAM_ALL_REG(table, emc_r2p, ref); + ADJUST_PARAM_ALL_REG(table, emc_w2p, ref); + ADJUST_PARAM_ALL_REG(table, emc_trtm, ref); + ADJUST_PARAM_ALL_REG(table, emc_twtm, ref); + ADJUST_PARAM_ALL_REG(table, emc_tratm, ref); + ADJUST_PARAM_ALL_REG(table, emc_twatm, ref); + + ADJUST_PARAM_ALL_REG(table, emc_rw2pden, ref); + + ADJUST_PARAM_ALL_REG(table, emc_tclkstop, ref); + + ADJUST_PARAM_ALL_REG(table, emc_pmacro_dll_cfg_2, ref); // EMC_DLL_CFG_2_0: level select for VDDA? + + // ADJUST_PARAM_TABLE(table, dram_timings.rl); // not used on Mariko + + ADJUST_PARAM_TABLE(table, la_scale_regs.mc_mll_mpcorer_ptsa_rate, ref); + ADJUST_PARAM_TABLE(table, la_scale_regs.mc_ptsa_grant_decrement, ref); + + // ADJUST_PARAM_TABLE(table, min_mrs_wait); // not used on LPDDR4X + // ADJUST_PARAM_TABLE(table, latency); // not used + + /* Patch PLLMB divisors */ + { + // Calculate DIVM and DIVN (clock divisors) + // Common PLL oscillator is 38.4 MHz + // PLLMB_OUT = 38.4 MHz / PLLLMB_DIVM * PLLMB_DIVN + u32 divm = 1; + u32 divn = EmcClock / 38400; + u32 remainder = EmcClock % 38400; + if (remainder >= 38400 * (3/4)) { + divm = 4; + divn = divn * divm + 3; + } else + if (remainder >= 38400 * (2/3)) { + divm = 3; + divn = divn * divm + 2; + } else + if (remainder >= 38400 * (1/2)) { + divm = 2; + divn = divn * divm + 1; + } else + if (remainder >= 38400 * (1/3)) { + divm = 3; + divn = divn * divm + 1; + } else + if (remainder >= 38400 * (1/4)) { + divm = 4; + divn = divn * divm + 1; + } + + table->pllmb_divm = divm; + table->pllmb_divn = divn; + } + /* Timings that are available in or can be derived from LPDDR4X datasheet or TRM */ { // tCK_avg (average clock period) in ns @@ -274,7 +336,7 @@ namespace ams::ldr { constexpr u32 MC_ARB_DIV = 4; // ? table->burst_mc_regs.mc_emem_arb_timing_rcd = std::ceil(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV - 2); table->burst_mc_regs.mc_emem_arb_timing_rp = std::ceil(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV - 1); - table->burst_mc_regs.mc_emem_arb_timing_rc = std::ceil(std::max(GET_CYCLE_CEIL(tRC), GET_CYCLE_CEIL(tRAS)+GET_CYCLE_CEIL(tRPpb))/ MC_ARB_DIV); + table->burst_mc_regs.mc_emem_arb_timing_rc = std::ceil(std::max(GET_CYCLE_CEIL(tRC), GET_CYCLE_CEIL(tRAS)+GET_CYCLE_CEIL(tRPpb)) / MC_ARB_DIV); table->burst_mc_regs.mc_emem_arb_timing_ras = std::ceil(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV - 2); table->burst_mc_regs.mc_emem_arb_timing_faw = std::ceil(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV - 1); table->burst_mc_regs.mc_emem_arb_timing_rrd = std::ceil(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV - 1); @@ -285,62 +347,6 @@ namespace ams::ldr { table->burst_mc_regs.mc_emem_arb_timing_rfcpb = std::ceil(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV + 1); // ? } - ADJUST_PARAM_ALL_REG(table, emc_r2w, ref); - ADJUST_PARAM_ALL_REG(table, emc_w2r, ref); - ADJUST_PARAM_ALL_REG(table, emc_r2p, ref); - ADJUST_PARAM_ALL_REG(table, emc_w2p, ref); - ADJUST_PARAM_ALL_REG(table, emc_trtm, ref); - ADJUST_PARAM_ALL_REG(table, emc_twtm, ref); - ADJUST_PARAM_ALL_REG(table, emc_tratm, ref); - ADJUST_PARAM_ALL_REG(table, emc_twatm, ref); - - ADJUST_PARAM_ALL_REG(table, emc_rw2pden, ref); - - ADJUST_PARAM_ALL_REG(table, emc_tclkstop, ref); - - ADJUST_PARAM_ALL_REG(table, emc_pmacro_dll_cfg_2, ref); // EMC_DLL_CFG_2_0: level select for VDDA? - - // ADJUST_PARAM_TABLE(table, dram_timings.rl); // not used on Mariko - - ADJUST_PARAM_TABLE(table, la_scale_regs.mc_mll_mpcorer_ptsa_rate, ref); - ADJUST_PARAM_TABLE(table, la_scale_regs.mc_ptsa_grant_decrement, ref); - - // ADJUST_PARAM_TABLE(table, min_mrs_wait); // not used on LPDDR4X - // ADJUST_PARAM_TABLE(table, latency); // not used - - /* Patch PLLMB divisors */ - { - // Calculate DIVM and DIVN (clock divisors) - // Common PLL oscillator is 38.4 MHz - // PLLMB_OUT = 38.4 MHz / PLLLMB_DIVM * PLLMB_DIVN - u32 divm = 1; - u32 divn = EmcClock / 38400; - u32 remainder = EmcClock % 38400; - if (remainder >= 38400 * (3/4)) { - divm = 4; - divn = divn * divm + 3; - } else - if (remainder >= 38400 * (2/3)) { - divm = 3; - divn = divn * divm + 2; - } else - if (remainder >= 38400 * (1/2)) { - divm = 2; - divn = divn * divm + 1; - } else - if (remainder >= 38400 * (1/3)) { - divm = 3; - divn = divn * divm + 1; - } else - if (remainder >= 38400 * (1/4)) { - divm = 4; - divn = divn * divm + 1; - } - - table->pllmb_divm = divm; - table->pllmb_divn = divn; - } - #ifdef EXPERIMENTAL { #define ADJUST_PARAM_ROUND2_ALL_REG(TARGET_TABLE, REF_TABLE, PARAM) \ @@ -351,17 +357,6 @@ namespace ams::ldr { TARGET_TABLE->shadow_regs_rdwr_train.PARAM = \ ((ADJUST_PROP(TARGET_TABLE->shadow_regs_rdwr_train.PARAM, REF_TABLE->shadow_regs_rdwr_train.PARAM) + 1) >> 1) << 1; - #define ADJUST_PARAM(TARGET_PARAM, REF_PARAM) \ - TARGET_PARAM = ADJUST_PROP(TARGET_PARAM, REF_PARAM); - - #define ADJUST_PARAM_TABLE(TARGET_TABLE, REF_TABLE, PARAM) \ - ADJUST_PARAM(TARGET_TABLE->PARAM, REF_TABLE->PARAM) - - #define ADJUST_PARAM_ALL_REG(TARGET_TABLE, REF_TABLE, PARAM) \ - ADJUST_PARAM_TABLE(TARGET_TABLE, REF_TABLE, burst_regs.PARAM) \ - ADJUST_PARAM_TABLE(TARGET_TABLE, REF_TABLE, shadow_regs_ca_train.PARAM) \ - ADJUST_PARAM_TABLE(TARGET_TABLE, REF_TABLE, shadow_regs_rdwr_train.PARAM) - #define TRIM_BIT(IN_BITS, HIGH, LOW) \ ((IN_BITS >> LOW) & ( (1u << (HIGH - LOW + 1u)) - 1u )) @@ -391,7 +386,7 @@ namespace ams::ldr { | ADJUST_BIT(TARGET_TABLE->shadow_regs_rdwr_train.PARAM, REF_TABLE->shadow_regs_rdwr_train.PARAM, HIGH2, LOW2) << LOW2; /* For latency allowance */ - #define ADJUST_INVERSE(TARGET) ((TARGET*1000) / (EmcClock/1600)) + #define ADJUST_INVERSE(TARGET) (TARGET * (MemClkOSLimit / 1000) / (EmcClock / 1000)) /* emc_wdv, emc_wsv, emc_wev, emc_wdv_mask, emc_quse, emc_quse_width, emc_ibdly, emc_obdly, @@ -437,7 +432,7 @@ namespace ams::ldr { offsetof(MarikoMtcTable, shadow_regs_rdwr_train.PARAM) \ /* Section 1: adjust HI bits: BIT 26:16 */ - const uint32_t ddll_high[] = { + const std::vector ddll_high = { OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dq_rank1_4), OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dq_rank1_5), OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank0_4), @@ -460,17 +455,17 @@ namespace ams::ldr { offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_2), offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_3), }; - for (uint32_t i = 0; i < sizeof(ddll_high)/sizeof(uint32_t); i++) + for (const auto &offset : ddll_high) { - uint32_t *ddll = reinterpret_cast(reinterpret_cast(target_table) + ddll_high[i]); - uint32_t *ddll_ref = reinterpret_cast(reinterpret_cast(ref_table) + ddll_high[i]); - uint16_t adjusted_ddll = ADJUST_BIT(*ddll, *ddll_ref, 26,16) & ((1 << 10) - 1); + u32 *ddll = reinterpret_cast(reinterpret_cast(table) + offset); + u32 *ddll_ref = reinterpret_cast(reinterpret_cast(ref) + offset); + u16 adjusted_ddll = ADJUST_BIT(*ddll, *ddll_ref, 26,16) & ((1 << (26-16)) - 1); CLEAR_BIT(*ddll, 26,16) *ddll |= adjusted_ddll << 16; } /* Section 2: adjust LOW bits: BIT 10:0 */ - const uint32_t ddll_low[] = { + const std::vector ddll_low = { OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dq_rank1_4), OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dq_rank1_5), OFFSET_ALL_REG(emc_pmacro_ob_ddll_long_dqs_rank0_0), @@ -497,11 +492,11 @@ namespace ams::ldr { offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_2), offsetof(MarikoMtcTable, trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_3), }; - for (uint32_t i = 0; i < sizeof(ddll_low)/sizeof(uint32_t); i++) + for (const auto &offset : ddll_low) { - uint32_t *ddll = reinterpret_cast(reinterpret_cast(target_table) + ddll_low[i]); - uint32_t *ddll_ref = reinterpret_cast(reinterpret_cast(ref_table) + ddll_low[i]); - uint16_t adjusted_ddll = ADJUST_BIT(*ddll, *ddll_ref, 10,0) & ((1 << 10) - 1); + u32 *ddll = reinterpret_cast(reinterpret_cast(table) + offset); + u32 *ddll_ref = reinterpret_cast(reinterpret_cast(ref) + offset); + u16 adjusted_ddll = ADJUST_BIT(*ddll, *ddll_ref, 10,0) & ((1 << 10) - 1); CLEAR_BIT(*ddll, 10,0) *ddll |= adjusted_ddll; } @@ -534,7 +529,7 @@ namespace ams::ldr { /* External Memory Arbitration Configuration */ /* BIT 20:16 - EXTRA_TICKS_PER_UPDATE: 0 */ /* BIT 8:0 - CYCLES_PER_UPDATE: 12(1600MHz), 10(1331.2MHz) */ - ADJUST_PARAM_TABLE(target_table, ref_table, burst_mc_regs.mc_emem_arb_cfg); + ADJUST_PARAM_TABLE(table, burst_mc_regs.mc_emem_arb_cfg, ref); /* External Memory Arbitration Configuration: Direction Arbiter: Turns */ /* BIT 31:24 - W2R_TURN: approx. mc_emem_arb_timing_w2r */ @@ -542,11 +537,9 @@ namespace ams::ldr { /* BIT 15:8 - W2W_TURN: 0 */ /* BIT 7:0 - R2R_TURN: 0 */ { - uint32_t param_1600 = target_table->burst_mc_regs.mc_emem_arb_da_turns; - uint32_t param_1331 = ref_table->burst_mc_regs.mc_emem_arb_da_turns; - uint8_t w2r_turn = ADJUST_BIT(param_1600, param_1331, 31,24); - uint8_t r2w_turn = ADJUST_BIT(param_1600, param_1331, 23,16); - target_table->burst_mc_regs.mc_emem_arb_da_turns = w2r_turn << 24 | r2w_turn << 16; + u8 w2r_turn = table->burst_mc_regs.mc_emem_arb_timing_w2r; + u8 r2w_turn = table->burst_mc_regs.mc_emem_arb_timing_r2w; + table->burst_mc_regs.mc_emem_arb_da_turns = w2r_turn << 24 | r2w_turn << 16; } /* External Memory Arbitration Configuration: Direction Arbiter: Covers */ @@ -554,12 +547,12 @@ namespace ams::ldr { /* BIT 15:8 - RCD_R_COVER: 8(1600MHz), 7(1331.2MHz) */ /* BIT 7:0 - RC_COVER: approx. mc_emem_arb_timing_rc, 12(1600MHz), 9(1331.2MHz) */ { - uint32_t param_1600 = target_table->burst_mc_regs.mc_emem_arb_da_covers; - uint32_t param_1331 = ref_table->burst_mc_regs.mc_emem_arb_da_covers; - uint8_t rcd_w_cover = ADJUST_BIT(param_1600, param_1331, 23,16); - uint8_t rcd_r_cover = ADJUST_BIT(param_1600, param_1331, 15,8); - uint8_t rc_cover = ADJUST_BIT(param_1600, param_1331, 7,0); - target_table->burst_mc_regs.mc_emem_arb_da_covers = rcd_w_cover << 16 | rcd_r_cover << 8 | rc_cover; + u32 param_max = table->burst_mc_regs.mc_emem_arb_da_covers; + u32 param_ref = ref->burst_mc_regs.mc_emem_arb_da_covers; + u8 rcd_w_cover = ADJUST_BIT(param_max, param_ref, 23,16); + u8 rcd_r_cover = (ADJUST_BIT(param_max, param_ref, 23,16) + 3) / 2; + u8 rc_cover = table->burst_mc_regs.mc_emem_arb_timing_rc; + table->burst_mc_regs.mc_emem_arb_da_covers = rcd_w_cover << 16 | rcd_r_cover << 8 | rc_cover; } /* External Memory Arbitration Configuration: Miscellaneous Thresholds (0) */ @@ -567,15 +560,15 @@ namespace ams::ldr { /* BIT 14:8 - PRIORITY_INVERSION_THRESHOLD: 36(1600MHz), 30(1331.2MHz) */ /* BIT 7:0 - BC2AA_HOLDOFF_THRESHOLD: set to mc_emem_arb_timing_rc */ { - uint32_t param_1600 = target_table->burst_mc_regs.mc_emem_arb_misc0; - uint32_t param_1331 = ref_table->burst_mc_regs.mc_emem_arb_misc0; - uint8_t priority_inversion_iso_threshold = ADJUST_BIT(param_1600, param_1331, 20,16); - uint8_t priority_inversion_threshold = ADJUST_BIT(param_1600, param_1331, 14,8); - uint8_t bc2aa_holdoff_threshold = target_table->burst_mc_regs.mc_emem_arb_timing_rc; - CLEAR_BIT(target_table->burst_mc_regs.mc_emem_arb_misc0, 20,16) - CLEAR_BIT(target_table->burst_mc_regs.mc_emem_arb_misc0, 14,8) - CLEAR_BIT(target_table->burst_mc_regs.mc_emem_arb_misc0, 7,0) - target_table->burst_mc_regs.mc_emem_arb_misc0 |= + u32 param_max = table->burst_mc_regs.mc_emem_arb_misc0; + u32 param_ref = ref->burst_mc_regs.mc_emem_arb_misc0; + u8 priority_inversion_iso_threshold = ADJUST_BIT(param_max, param_ref, 20,16); + u8 priority_inversion_threshold = 3 * ADJUST_BIT(param_max, param_ref, 20,16); + u8 bc2aa_holdoff_threshold = table->burst_mc_regs.mc_emem_arb_timing_rc; + CLEAR_BIT(table->burst_mc_regs.mc_emem_arb_misc0, 20,16) + CLEAR_BIT(table->burst_mc_regs.mc_emem_arb_misc0, 14,8) + CLEAR_BIT(table->burst_mc_regs.mc_emem_arb_misc0, 7,0) + table->burst_mc_regs.mc_emem_arb_misc0 |= (priority_inversion_iso_threshold << 16 | priority_inversion_threshold << 8 | bc2aa_holdoff_threshold); } @@ -649,7 +642,7 @@ namespace ams::ldr { * * No need to care about this if Spread Spectrum (SS) is disabled */ - // Disable PLL Spread Spectrum Control + // Disable PLL Spread Spectrum Control (degrades performance) table->pll_en_ssc = 0; table->pllm_ss_cfg = 1 << 30; } @@ -784,7 +777,7 @@ namespace ams::ldr { return ResultFailure(); } - Result PcvMemHandler(uintptr_t ptr, bool isMariko) { + Result PcvMemMaxClockHandler(uintptr_t ptr, bool isMariko, uintptr_t *buffer_ptr) { if (isMariko) { // Mariko have 3 mtc tables (204/1331/1600 MHz), only these 3 frequencies could be set. @@ -792,28 +785,40 @@ namespace ams::ldr { u32 value_next = *(reinterpret_cast(ptr) + 1); u32 value_next2 = *(reinterpret_cast(ptr) + 2); - constexpr u32 mtc_min_volt = 1100; - constexpr u32 dvb_entry_volt = 675; - constexpr u32 mtc_table_rev = 3; - constexpr u32 mem_1331_khz = 1331'200; + constexpr u32 mtc_mariko_min_volt = 1100; + constexpr u32 mtc_erista_min_volt_max = 887; + constexpr u32 mtc_erista_min_volt_alt = 850; + constexpr u32 dvb_entry_volt = 675; + constexpr u32 mtc_mariko_rev = 3; - if (value_next == mtc_min_volt) + if (value_next == mtc_erista_min_volt_max && !(*buffer_ptr)) { - uintptr_t offset_new = ptr - offsetof(MarikoMtcTable, rate_khz); - uintptr_t offset_old = offset_new - sizeof(MarikoMtcTable); - - MarikoMtcTable* const mtc_table_new = reinterpret_cast(offset_new); - MarikoMtcTable* const mtc_table_old = reinterpret_cast(offset_old); - if ( mtc_table_new->rev != mtc_table_rev - || mtc_table_old->rev != mtc_table_rev - || mtc_table_old->rate_khz != mem_1331_khz ) + EristaMtcTable* const mtc_table_max = reinterpret_cast(ptr - offsetof(EristaMtcTable, rate_khz)); + EristaMtcTable* const mtc_table_alt = mtc_table_max - 1; + if (mtc_table_alt->rate_khz == 1331'200 && mtc_table_alt->min_volt == mtc_erista_min_volt_alt) + { + *buffer_ptr = reinterpret_cast(mtc_table_max); + return ResultSuccess(); + } + } + else if (value_next == mtc_mariko_min_volt) + { + MarikoMtcTable* const mtc_table_max = reinterpret_cast(ptr - offsetof(MarikoMtcTable, rate_khz)); + MarikoMtcTable* const mtc_table_alt = mtc_table_max - 1; + if ( mtc_table_max->rev != mtc_mariko_rev + || mtc_table_alt->rev != mtc_mariko_rev + || mtc_table_alt->rate_khz != MemClkOSAlt ) return ResultFailure(); - std::memcpy(reinterpret_cast(mtc_table_old), reinterpret_cast(mtc_table_new), sizeof(MarikoMtcTable)); + if (*buffer_ptr) + std::memcpy(reinterpret_cast(*buffer_ptr), reinterpret_cast(mtc_table_max), sizeof(MarikoMtcTable)); + else + std::memcpy(reinterpret_cast(mtc_table_alt), reinterpret_cast(mtc_table_max), sizeof(MarikoMtcTable)); - // Adjust params for Max MHz - // [!TODO] ref table is identical to new table, leaving some params unchanged - AdjustMtcTable(mtc_table_new, mtc_table_old); + AdjustMtcTable(mtc_table_max, mtc_table_alt); + + if (*buffer_ptr) + std::memcpy(reinterpret_cast(mtc_table_alt), reinterpret_cast(*buffer_ptr), sizeof(MarikoMtcTable)); } else if (value_next2 == dvb_entry_volt) { @@ -821,7 +826,7 @@ namespace ams::ldr { emc_dvb_dvfs_table_t* dvb_1331_entry = dvb_max_entry - 1; u32* dvb_1331_offset = reinterpret_cast(dvb_1331_entry); - if (*(dvb_1331_offset) != mem_1331_khz) + if (*(dvb_1331_offset) != MemClkOSAlt) return ResultFailure(); PatchOffset(dvb_1331_offset, MemClkOSLimit); @@ -836,6 +841,11 @@ namespace ams::ldr { /* Abort immediately once something goes wrong */ bool isMariko = (spl::GetSocType() == spl::SocType_Mariko); + // Use erista mtc tables in pcv module as tmp buffer for further mariko mtc table copies. + // Erista mtc tables appear earlier than Mariko ones, no need to search for them beforehand. + static_assert(sizeof(MarikoMtcTable) < sizeof(EristaMtcTable)); + uintptr_t mtcBuffer {}; + u8 cpuClockVddMariko {}; u8 cpuTableMariko {}; u8 gpuTableMariko {}; @@ -882,7 +892,7 @@ namespace ams::ldr { if (value == MemClkOSLimit) { - if (R_FAILED(PcvMemHandler(ptr, isMariko))) + if (R_FAILED(PcvMemMaxClockHandler(ptr, isMariko, &mtcBuffer))) AMS_ABORT(); } @@ -929,6 +939,8 @@ namespace ams::ldr { perf_conf_entry* confTable = 0; constexpr u32 entryCnt = 16; constexpr u32 memPtmLimit = MemClkOSLimit * 1000; + constexpr u32 memPtmAlt = MemClkOSAlt * 1000; + constexpr u32 memPtmClamp = MemClkOSClampDn * 1000; constexpr u32 memPtmMax = EmcClock * 1000; uintptr_t ptr = mapped_nso; @@ -964,8 +976,8 @@ namespace ams::ldr { PatchOffset(std::addressof(entry_current->emc_freq_1), memPtmMax); PatchOffset(std::addressof(entry_current->emc_freq_2), memPtmMax); break; - case 1331'200'000: - case 1065'600'000: + case memPtmAlt: + case memPtmClamp: PatchOffset(std::addressof(entry_current->emc_freq_1), memPtmLimit); PatchOffset(std::addressof(entry_current->emc_freq_2), memPtmLimit); break; diff --git a/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp b/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp index e5fbff0e..a96413d1 100644 --- a/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp +++ b/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp @@ -1112,4 +1112,1262 @@ struct MarikoMtcTable { uint32_t pllm_misc1_0_pllm_clamp_ph90; }; -static_assert(sizeof(MarikoMtcTable) == 0x10CC); \ No newline at end of file +static_assert(sizeof(MarikoMtcTable) == 0x10CC); + +struct EristaMtcTable { + uint32_t rev; + char dvfs_ver[60]; + uint32_t rate_khz; + uint32_t min_volt; + uint32_t gpu_min_volt; + char clock_src[32]; + uint32_t clk_src_emc; + uint32_t needs_training; + uint32_t training_pattern; + uint32_t trained; + + uint32_t periodic_training; + uint32_t trained_dram_clktree_c0d0u0; + uint32_t trained_dram_clktree_c0d0u1; + uint32_t trained_dram_clktree_c0d1u0; + uint32_t trained_dram_clktree_c0d1u1; + uint32_t trained_dram_clktree_c1d0u0; + uint32_t trained_dram_clktree_c1d0u1; + uint32_t trained_dram_clktree_c1d1u0; + uint32_t trained_dram_clktree_c1d1u1; + uint32_t current_dram_clktree_c0d0u0; + uint32_t current_dram_clktree_c0d0u1; + uint32_t current_dram_clktree_c0d1u0; + uint32_t current_dram_clktree_c0d1u1; + uint32_t current_dram_clktree_c1d0u0; + uint32_t current_dram_clktree_c1d0u1; + uint32_t current_dram_clktree_c1d1u0; + uint32_t current_dram_clktree_c1d1u1; + uint32_t run_clocks; + uint32_t tree_margin; + + uint32_t num_burst; + uint32_t num_burst_per_ch; + uint32_t num_trim; + uint32_t num_trim_per_ch; + uint32_t num_mc_regs; + uint32_t num_up_down; + uint32_t vref_num; + uint32_t training_mod_num; + uint32_t dram_timing_num; + + uint32_t ptfv_dqsosc_movavg_c0d0u0; + uint32_t ptfv_dqsosc_movavg_c0d0u1; + uint32_t ptfv_dqsosc_movavg_c0d1u0; + uint32_t ptfv_dqsosc_movavg_c0d1u1; + uint32_t ptfv_dqsosc_movavg_c1d0u0; + uint32_t ptfv_dqsosc_movavg_c1d0u1; + uint32_t ptfv_dqsosc_movavg_c1d1u0; + uint32_t ptfv_dqsosc_movavg_c1d1u1; + uint32_t ptfv_write_samples; + uint32_t ptfv_dvfs_samples; + uint32_t ptfv_movavg_weight; + uint32_t ptfv_config_ctrl; + + struct { + uint32_t emc_rc; + uint32_t emc_rfc; + uint32_t emc_rfcpb; + uint32_t emc_refctrl2; + uint32_t emc_rfc_slr; + uint32_t emc_ras; + uint32_t emc_rp; + uint32_t emc_r2w; + uint32_t emc_w2r; + uint32_t emc_r2p; + uint32_t emc_w2p; + uint32_t emc_r2r; + uint32_t emc_tppd; + uint32_t emc_ccdmw; + uint32_t emc_rd_rcd; + uint32_t emc_wr_rcd; + uint32_t emc_rrd; + uint32_t emc_rext; + uint32_t emc_wext; + uint32_t emc_wdv_chk; + uint32_t emc_wdv; + uint32_t emc_wsv; + uint32_t emc_wev; + uint32_t emc_wdv_mask; + uint32_t emc_ws_duration; + uint32_t emc_we_duration; + uint32_t emc_quse; + uint32_t emc_quse_width; + uint32_t emc_ibdly; + uint32_t emc_obdly; + uint32_t emc_einput; + uint32_t emc_mrw6; + uint32_t emc_einput_duration; + uint32_t emc_puterm_extra; + uint32_t emc_puterm_width; + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; + uint32_t emc_refresh; + uint32_t emc_burst_refresh_num; + uint32_t emc_pre_refresh_req_cnt; + uint32_t emc_pdex2wr; + uint32_t emc_pdex2rd; + uint32_t emc_pchg2pden; + uint32_t emc_act2pden; + uint32_t emc_ar2pden; + uint32_t emc_rw2pden; + uint32_t emc_cke2pden; + uint32_t emc_pdex2cke; + uint32_t emc_pdex2mrr; + uint32_t emc_txsr; + uint32_t emc_txsrdll; + uint32_t emc_tcke; + uint32_t emc_tckesr; + uint32_t emc_tpd; + uint32_t emc_tfaw; + uint32_t emc_trpab; + uint32_t emc_tclkstable; + uint32_t emc_tclkstop; + uint32_t emc_mrw7; + uint32_t emc_trefbw; + uint32_t emc_odt_write; + uint32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg7; + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_period; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe_1; + uint32_t emc_cfg_pipe_2; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + uint32_t emc_mrw8; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3; + uint32_t emc_txdsrvttgen; + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_fbio_spare; + uint32_t emc_zcal_interval; + uint32_t emc_zcal_wait_cnt; + uint32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt2; + uint32_t emc_auto_cal_channel; + uint32_t emc_dll_cfg_0; + uint32_t emc_dll_cfg_1; + uint32_t emc_pmacro_autocal_cfg_common; + uint32_t emc_pmacro_zctrl; + uint32_t emc_cfg; + uint32_t emc_cfg_pipe; + uint32_t emc_dyn_self_ref_control; + uint32_t emc_qpop; + uint32_t emc_dqs_brlshft_0; + uint32_t emc_dqs_brlshft_1; + uint32_t emc_cmd_brlshft_2; + uint32_t emc_cmd_brlshft_3; + uint32_t emc_pmacro_pad_cfg_ctrl; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_common_pad_tx_ctrl; + uint32_t emc_pmacro_vttgen_ctrl_0; + uint32_t emc_pmacro_vttgen_ctrl_1; + uint32_t emc_pmacro_vttgen_ctrl_2; + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl_0; + uint32_t emc_cfg_3; + uint32_t emc_pmacro_tx_pwrd_0; + uint32_t emc_pmacro_tx_pwrd_1; + uint32_t emc_pmacro_tx_pwrd_2; + uint32_t emc_pmacro_tx_pwrd_3; + uint32_t emc_pmacro_tx_pwrd_4; + uint32_t emc_pmacro_tx_pwrd_5; + uint32_t emc_config_sample_delay; + uint32_t emc_pmacro_tx_sel_clk_src_0; + uint32_t emc_pmacro_tx_sel_clk_src_1; + uint32_t emc_pmacro_tx_sel_clk_src_2; + uint32_t emc_pmacro_tx_sel_clk_src_3; + uint32_t emc_pmacro_tx_sel_clk_src_4; + uint32_t emc_pmacro_tx_sel_clk_src_5; + uint32_t emc_pmacro_ddll_bypass; + uint32_t emc_pmacro_ddll_pwrd_0; + uint32_t emc_pmacro_ddll_pwrd_1; + uint32_t emc_pmacro_ddll_pwrd_2; + uint32_t emc_pmacro_cmd_ctrl_0; + uint32_t emc_pmacro_cmd_ctrl_1; + uint32_t emc_pmacro_cmd_ctrl_2; + uint32_t emc_tr_timing_0; + uint32_t emc_tr_dvfs; + uint32_t emc_tr_ctrl_1; + uint32_t emc_tr_rdv; + uint32_t emc_tr_qpop; + uint32_t emc_tr_rdv_mask; + uint32_t emc_mrw14; + uint32_t emc_tr_qsafe; + uint32_t emc_tr_qrst; + uint32_t emc_training_ctrl; + uint32_t emc_training_settle; + uint32_t emc_training_vref_settle; + uint32_t emc_training_ca_fine_ctrl; + uint32_t emc_training_ca_ctrl_misc; + uint32_t emc_training_ca_ctrl_misc1; + uint32_t emc_training_ca_vref_ctrl; + uint32_t emc_training_quse_cors_ctrl; + uint32_t emc_training_quse_fine_ctrl; + uint32_t emc_training_quse_ctrl_misc; + uint32_t emc_training_quse_vref_ctrl; + uint32_t emc_training_read_fine_ctrl; + uint32_t emc_training_read_ctrl_misc; + uint32_t emc_training_read_vref_ctrl; + uint32_t emc_training_write_fine_ctrl; + uint32_t emc_training_write_ctrl_misc; + uint32_t emc_training_write_vref_ctrl; + uint32_t emc_training_mpc; + uint32_t emc_mrw15; + } + burst_regs; + + struct { + uint32_t emc0_mrw10; + uint32_t emc1_mrw10; + uint32_t emc0_mrw11; + uint32_t emc1_mrw11; + uint32_t emc0_mrw12; + uint32_t emc1_mrw12; + uint32_t emc0_mrw13; + uint32_t emc1_mrw13; + } + burst_perch_regs; + + struct { + uint32_t emc_rc; + uint32_t emc_rfc; + uint32_t emc_rfcpb; + uint32_t emc_refctrl2; + uint32_t emc_rfc_slr; + uint32_t emc_ras; + uint32_t emc_rp; + uint32_t emc_r2w; + uint32_t emc_w2r; + uint32_t emc_r2p; + uint32_t emc_w2p; + uint32_t emc_r2r; + uint32_t emc_tppd; + uint32_t emc_ccdmw; + uint32_t emc_rd_rcd; + uint32_t emc_wr_rcd; + uint32_t emc_rrd; + uint32_t emc_rext; + uint32_t emc_wext; + uint32_t emc_wdv_chk; + uint32_t emc_wdv; + uint32_t emc_wsv; + uint32_t emc_wev; + uint32_t emc_wdv_mask; + uint32_t emc_ws_duration; + uint32_t emc_we_duration; + uint32_t emc_quse; + uint32_t emc_quse_width; + uint32_t emc_ibdly; + uint32_t emc_obdly; + uint32_t emc_einput; + uint32_t emc_mrw6; + uint32_t emc_einput_duration; + uint32_t emc_puterm_extra; + uint32_t emc_puterm_width; + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; + uint32_t emc_refresh; + uint32_t emc_burst_refresh_num; + uint32_t emc_pre_refresh_req_cnt; + uint32_t emc_pdex2wr; + uint32_t emc_pdex2rd; + uint32_t emc_pchg2pden; + uint32_t emc_act2pden; + uint32_t emc_ar2pden; + uint32_t emc_rw2pden; + uint32_t emc_cke2pden; + uint32_t emc_pdex2cke; + uint32_t emc_pdex2mrr; + uint32_t emc_txsr; + uint32_t emc_txsrdll; + uint32_t emc_tcke; + uint32_t emc_tckesr; + uint32_t emc_tpd; + uint32_t emc_tfaw; + uint32_t emc_trpab; + uint32_t emc_tclkstable; + uint32_t emc_tclkstop; + uint32_t emc_mrw7; + uint32_t emc_trefbw; + uint32_t emc_odt_write; + uint32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg7; + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_period; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe_1; + uint32_t emc_cfg_pipe_2; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + uint32_t emc_mrw8; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3; + uint32_t emc_txdsrvttgen; + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_fbio_spare; + uint32_t emc_zcal_interval; + uint32_t emc_zcal_wait_cnt; + uint32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt2; + uint32_t emc_auto_cal_channel; + uint32_t emc_dll_cfg_0; + uint32_t emc_dll_cfg_1; + uint32_t emc_pmacro_autocal_cfg_common; + uint32_t emc_pmacro_zctrl; + uint32_t emc_cfg; + uint32_t emc_cfg_pipe; + uint32_t emc_dyn_self_ref_control; + uint32_t emc_qpop; + uint32_t emc_dqs_brlshft_0; + uint32_t emc_dqs_brlshft_1; + uint32_t emc_cmd_brlshft_2; + uint32_t emc_cmd_brlshft_3; + uint32_t emc_pmacro_pad_cfg_ctrl; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_common_pad_tx_ctrl; + uint32_t emc_pmacro_vttgen_ctrl_0; + uint32_t emc_pmacro_vttgen_ctrl_1; + uint32_t emc_pmacro_vttgen_ctrl_2; + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl_0; + uint32_t emc_cfg_3; + uint32_t emc_pmacro_tx_pwrd_0; + uint32_t emc_pmacro_tx_pwrd_1; + uint32_t emc_pmacro_tx_pwrd_2; + uint32_t emc_pmacro_tx_pwrd_3; + uint32_t emc_pmacro_tx_pwrd_4; + uint32_t emc_pmacro_tx_pwrd_5; + uint32_t emc_config_sample_delay; + uint32_t emc_pmacro_tx_sel_clk_src_0; + uint32_t emc_pmacro_tx_sel_clk_src_1; + uint32_t emc_pmacro_tx_sel_clk_src_2; + uint32_t emc_pmacro_tx_sel_clk_src_3; + uint32_t emc_pmacro_tx_sel_clk_src_4; + uint32_t emc_pmacro_tx_sel_clk_src_5; + uint32_t emc_pmacro_ddll_bypass; + uint32_t emc_pmacro_ddll_pwrd_0; + uint32_t emc_pmacro_ddll_pwrd_1; + uint32_t emc_pmacro_ddll_pwrd_2; + uint32_t emc_pmacro_cmd_ctrl_0; + uint32_t emc_pmacro_cmd_ctrl_1; + uint32_t emc_pmacro_cmd_ctrl_2; + uint32_t emc_tr_timing_0; + uint32_t emc_tr_dvfs; + uint32_t emc_tr_ctrl_1; + uint32_t emc_tr_rdv; + uint32_t emc_tr_qpop; + uint32_t emc_tr_rdv_mask; + uint32_t emc_mrw14; + uint32_t emc_tr_qsafe; + uint32_t emc_tr_qrst; + uint32_t emc_training_ctrl; + uint32_t emc_training_settle; + uint32_t emc_training_vref_settle; + uint32_t emc_training_ca_fine_ctrl; + uint32_t emc_training_ca_ctrl_misc; + uint32_t emc_training_ca_ctrl_misc1; + uint32_t emc_training_ca_vref_ctrl; + uint32_t emc_training_quse_cors_ctrl; + uint32_t emc_training_quse_fine_ctrl; + uint32_t emc_training_quse_ctrl_misc; + uint32_t emc_training_quse_vref_ctrl; + uint32_t emc_training_read_fine_ctrl; + uint32_t emc_training_read_ctrl_misc; + uint32_t emc_training_read_vref_ctrl; + uint32_t emc_training_write_fine_ctrl; + uint32_t emc_training_write_ctrl_misc; + uint32_t emc_training_write_vref_ctrl; + uint32_t emc_training_mpc; + uint32_t emc_mrw15; + } + shadow_regs_ca_train; + + struct { + uint32_t emc_rc; + uint32_t emc_rfc; + uint32_t emc_rfcpb; + uint32_t emc_refctrl2; + uint32_t emc_rfc_slr; + uint32_t emc_ras; + uint32_t emc_rp; + uint32_t emc_r2w; + uint32_t emc_w2r; + uint32_t emc_r2p; + uint32_t emc_w2p; + uint32_t emc_r2r; + uint32_t emc_tppd; + uint32_t emc_ccdmw; + uint32_t emc_rd_rcd; + uint32_t emc_wr_rcd; + uint32_t emc_rrd; + uint32_t emc_rext; + uint32_t emc_wext; + uint32_t emc_wdv_chk; + uint32_t emc_wdv; + uint32_t emc_wsv; + uint32_t emc_wev; + uint32_t emc_wdv_mask; + uint32_t emc_ws_duration; + uint32_t emc_we_duration; + uint32_t emc_quse; + uint32_t emc_quse_width; + uint32_t emc_ibdly; + uint32_t emc_obdly; + uint32_t emc_einput; + uint32_t emc_mrw6; + uint32_t emc_einput_duration; + uint32_t emc_puterm_extra; + uint32_t emc_puterm_width; + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; + uint32_t emc_refresh; + uint32_t emc_burst_refresh_num; + uint32_t emc_pre_refresh_req_cnt; + uint32_t emc_pdex2wr; + uint32_t emc_pdex2rd; + uint32_t emc_pchg2pden; + uint32_t emc_act2pden; + uint32_t emc_ar2pden; + uint32_t emc_rw2pden; + uint32_t emc_cke2pden; + uint32_t emc_pdex2cke; + uint32_t emc_pdex2mrr; + uint32_t emc_txsr; + uint32_t emc_txsrdll; + uint32_t emc_tcke; + uint32_t emc_tckesr; + uint32_t emc_tpd; + uint32_t emc_tfaw; + uint32_t emc_trpab; + uint32_t emc_tclkstable; + uint32_t emc_tclkstop; + uint32_t emc_mrw7; + uint32_t emc_trefbw; + uint32_t emc_odt_write; + uint32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg7; + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_period; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe_1; + uint32_t emc_cfg_pipe_2; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + uint32_t emc_mrw8; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3; + uint32_t emc_txdsrvttgen; + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_fbio_spare; + uint32_t emc_zcal_interval; + uint32_t emc_zcal_wait_cnt; + uint32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt2; + uint32_t emc_auto_cal_channel; + uint32_t emc_dll_cfg_0; + uint32_t emc_dll_cfg_1; + uint32_t emc_pmacro_autocal_cfg_common; + uint32_t emc_pmacro_zctrl; + uint32_t emc_cfg; + uint32_t emc_cfg_pipe; + uint32_t emc_dyn_self_ref_control; + uint32_t emc_qpop; + uint32_t emc_dqs_brlshft_0; + uint32_t emc_dqs_brlshft_1; + uint32_t emc_cmd_brlshft_2; + uint32_t emc_cmd_brlshft_3; + uint32_t emc_pmacro_pad_cfg_ctrl; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_common_pad_tx_ctrl; + uint32_t emc_pmacro_vttgen_ctrl_0; + uint32_t emc_pmacro_vttgen_ctrl_1; + uint32_t emc_pmacro_vttgen_ctrl_2; + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl_0; + uint32_t emc_cfg_3; + uint32_t emc_pmacro_tx_pwrd_0; + uint32_t emc_pmacro_tx_pwrd_1; + uint32_t emc_pmacro_tx_pwrd_2; + uint32_t emc_pmacro_tx_pwrd_3; + uint32_t emc_pmacro_tx_pwrd_4; + uint32_t emc_pmacro_tx_pwrd_5; + uint32_t emc_config_sample_delay; + uint32_t emc_pmacro_tx_sel_clk_src_0; + uint32_t emc_pmacro_tx_sel_clk_src_1; + uint32_t emc_pmacro_tx_sel_clk_src_2; + uint32_t emc_pmacro_tx_sel_clk_src_3; + uint32_t emc_pmacro_tx_sel_clk_src_4; + uint32_t emc_pmacro_tx_sel_clk_src_5; + uint32_t emc_pmacro_ddll_bypass; + uint32_t emc_pmacro_ddll_pwrd_0; + uint32_t emc_pmacro_ddll_pwrd_1; + uint32_t emc_pmacro_ddll_pwrd_2; + uint32_t emc_pmacro_cmd_ctrl_0; + uint32_t emc_pmacro_cmd_ctrl_1; + uint32_t emc_pmacro_cmd_ctrl_2; + uint32_t emc_tr_timing_0; + uint32_t emc_tr_dvfs; + uint32_t emc_tr_ctrl_1; + uint32_t emc_tr_rdv; + uint32_t emc_tr_qpop; + uint32_t emc_tr_rdv_mask; + uint32_t emc_mrw14; + uint32_t emc_tr_qsafe; + uint32_t emc_tr_qrst; + uint32_t emc_training_ctrl; + uint32_t emc_training_settle; + uint32_t emc_training_vref_settle; + uint32_t emc_training_ca_fine_ctrl; + uint32_t emc_training_ca_ctrl_misc; + uint32_t emc_training_ca_ctrl_misc1; + uint32_t emc_training_ca_vref_ctrl; + uint32_t emc_training_quse_cors_ctrl; + uint32_t emc_training_quse_fine_ctrl; + uint32_t emc_training_quse_ctrl_misc; + uint32_t emc_training_quse_vref_ctrl; + uint32_t emc_training_read_fine_ctrl; + uint32_t emc_training_read_ctrl_misc; + uint32_t emc_training_read_vref_ctrl; + uint32_t emc_training_write_fine_ctrl; + uint32_t emc_training_write_ctrl_misc; + uint32_t emc_training_write_vref_ctrl; + uint32_t emc_training_mpc; + uint32_t emc_mrw15; + } + shadow_regs_quse_train; + + struct { + uint32_t emc_rc; + uint32_t emc_rfc; + uint32_t emc_rfcpb; + uint32_t emc_refctrl2; + uint32_t emc_rfc_slr; + uint32_t emc_ras; + uint32_t emc_rp; + uint32_t emc_r2w; + uint32_t emc_w2r; + uint32_t emc_r2p; + uint32_t emc_w2p; + uint32_t emc_r2r; + uint32_t emc_tppd; + uint32_t emc_ccdmw; + uint32_t emc_rd_rcd; + uint32_t emc_wr_rcd; + uint32_t emc_rrd; + uint32_t emc_rext; + uint32_t emc_wext; + uint32_t emc_wdv_chk; + uint32_t emc_wdv; + uint32_t emc_wsv; + uint32_t emc_wev; + uint32_t emc_wdv_mask; + uint32_t emc_ws_duration; + uint32_t emc_we_duration; + uint32_t emc_quse; + uint32_t emc_quse_width; + uint32_t emc_ibdly; + uint32_t emc_obdly; + uint32_t emc_einput; + uint32_t emc_mrw6; + uint32_t emc_einput_duration; + uint32_t emc_puterm_extra; + uint32_t emc_puterm_width; + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; + uint32_t emc_refresh; + uint32_t emc_burst_refresh_num; + uint32_t emc_pre_refresh_req_cnt; + uint32_t emc_pdex2wr; + uint32_t emc_pdex2rd; + uint32_t emc_pchg2pden; + uint32_t emc_act2pden; + uint32_t emc_ar2pden; + uint32_t emc_rw2pden; + uint32_t emc_cke2pden; + uint32_t emc_pdex2cke; + uint32_t emc_pdex2mrr; + uint32_t emc_txsr; + uint32_t emc_txsrdll; + uint32_t emc_tcke; + uint32_t emc_tckesr; + uint32_t emc_tpd; + uint32_t emc_tfaw; + uint32_t emc_trpab; + uint32_t emc_tclkstable; + uint32_t emc_tclkstop; + uint32_t emc_mrw7; + uint32_t emc_trefbw; + uint32_t emc_odt_write; + uint32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg7; + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_period; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe_1; + uint32_t emc_cfg_pipe_2; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + uint32_t emc_mrw8; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3; + uint32_t emc_txdsrvttgen; + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_fbio_spare; + uint32_t emc_zcal_interval; + uint32_t emc_zcal_wait_cnt; + uint32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt2; + uint32_t emc_auto_cal_channel; + uint32_t emc_dll_cfg_0; + uint32_t emc_dll_cfg_1; + uint32_t emc_pmacro_autocal_cfg_common; + uint32_t emc_pmacro_zctrl; + uint32_t emc_cfg; + uint32_t emc_cfg_pipe; + uint32_t emc_dyn_self_ref_control; + uint32_t emc_qpop; + uint32_t emc_dqs_brlshft_0; + uint32_t emc_dqs_brlshft_1; + uint32_t emc_cmd_brlshft_2; + uint32_t emc_cmd_brlshft_3; + uint32_t emc_pmacro_pad_cfg_ctrl; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_common_pad_tx_ctrl; + uint32_t emc_pmacro_vttgen_ctrl_0; + uint32_t emc_pmacro_vttgen_ctrl_1; + uint32_t emc_pmacro_vttgen_ctrl_2; + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl_0; + uint32_t emc_cfg_3; + uint32_t emc_pmacro_tx_pwrd_0; + uint32_t emc_pmacro_tx_pwrd_1; + uint32_t emc_pmacro_tx_pwrd_2; + uint32_t emc_pmacro_tx_pwrd_3; + uint32_t emc_pmacro_tx_pwrd_4; + uint32_t emc_pmacro_tx_pwrd_5; + uint32_t emc_config_sample_delay; + uint32_t emc_pmacro_tx_sel_clk_src_0; + uint32_t emc_pmacro_tx_sel_clk_src_1; + uint32_t emc_pmacro_tx_sel_clk_src_2; + uint32_t emc_pmacro_tx_sel_clk_src_3; + uint32_t emc_pmacro_tx_sel_clk_src_4; + uint32_t emc_pmacro_tx_sel_clk_src_5; + uint32_t emc_pmacro_ddll_bypass; + uint32_t emc_pmacro_ddll_pwrd_0; + uint32_t emc_pmacro_ddll_pwrd_1; + uint32_t emc_pmacro_ddll_pwrd_2; + uint32_t emc_pmacro_cmd_ctrl_0; + uint32_t emc_pmacro_cmd_ctrl_1; + uint32_t emc_pmacro_cmd_ctrl_2; + uint32_t emc_tr_timing_0; + uint32_t emc_tr_dvfs; + uint32_t emc_tr_ctrl_1; + uint32_t emc_tr_rdv; + uint32_t emc_tr_qpop; + uint32_t emc_tr_rdv_mask; + uint32_t emc_mrw14; + uint32_t emc_tr_qsafe; + uint32_t emc_tr_qrst; + uint32_t emc_training_ctrl; + uint32_t emc_training_settle; + uint32_t emc_training_vref_settle; + uint32_t emc_training_ca_fine_ctrl; + uint32_t emc_training_ca_ctrl_misc; + uint32_t emc_training_ca_ctrl_misc1; + uint32_t emc_training_ca_vref_ctrl; + uint32_t emc_training_quse_cors_ctrl; + uint32_t emc_training_quse_fine_ctrl; + uint32_t emc_training_quse_ctrl_misc; + uint32_t emc_training_quse_vref_ctrl; + uint32_t emc_training_read_fine_ctrl; + uint32_t emc_training_read_ctrl_misc; + uint32_t emc_training_read_vref_ctrl; + uint32_t emc_training_write_fine_ctrl; + uint32_t emc_training_write_ctrl_misc; + uint32_t emc_training_write_vref_ctrl; + uint32_t emc_training_mpc; + uint32_t emc_mrw15; + } + shadow_regs_rdwr_train; + + struct { + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_2; + uint32_t emc_pmacro_ib_vref_dqs_0; + uint32_t emc_pmacro_ib_vref_dqs_1; + uint32_t emc_pmacro_ib_vref_dq_0; + uint32_t emc_pmacro_ib_vref_dq_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_2; + uint32_t emc_pmacro_quse_ddll_rank0_0; + uint32_t emc_pmacro_quse_ddll_rank0_1; + uint32_t emc_pmacro_quse_ddll_rank0_2; + uint32_t emc_pmacro_quse_ddll_rank0_3; + uint32_t emc_pmacro_quse_ddll_rank1_0; + uint32_t emc_pmacro_quse_ddll_rank1_1; + uint32_t emc_pmacro_quse_ddll_rank1_2; + uint32_t emc_pmacro_quse_ddll_rank1_3; + } + trim_regs; + + struct { + uint32_t emc0_cmd_brlshft_0; + uint32_t emc1_cmd_brlshft_1; + uint32_t emc0_data_brlshft_0; + uint32_t emc1_data_brlshft_0; + uint32_t emc0_data_brlshft_1; + uint32_t emc1_data_brlshft_1; + uint32_t emc0_quse_brlshft_0; + uint32_t emc1_quse_brlshft_1; + uint32_t emc0_quse_brlshft_2; + uint32_t emc1_quse_brlshft_3; + } + trim_perch_regs; + + struct { + uint32_t emc0_training_opt_dqs_ib_vref_rank0; + uint32_t emc1_training_opt_dqs_ib_vref_rank0; + uint32_t emc0_training_opt_dqs_ib_vref_rank1; + uint32_t emc1_training_opt_dqs_ib_vref_rank1; + } + vref_perch_regs; + + struct { + uint32_t t_rp; + uint32_t t_fc_lpddr4; + uint32_t t_rfc; + uint32_t t_pdex; + uint32_t rl; + } + dram_timings; + + struct { + uint32_t emc0_training_rw_offset_ib_byte0; + uint32_t emc1_training_rw_offset_ib_byte0; + uint32_t emc0_training_rw_offset_ib_byte1; + uint32_t emc1_training_rw_offset_ib_byte1; + uint32_t emc0_training_rw_offset_ib_byte2; + uint32_t emc1_training_rw_offset_ib_byte2; + uint32_t emc0_training_rw_offset_ib_byte3; + uint32_t emc1_training_rw_offset_ib_byte3; + uint32_t emc0_training_rw_offset_ib_misc; + uint32_t emc1_training_rw_offset_ib_misc; + uint32_t emc0_training_rw_offset_ob_byte0; + uint32_t emc1_training_rw_offset_ob_byte0; + uint32_t emc0_training_rw_offset_ob_byte1; + uint32_t emc1_training_rw_offset_ob_byte1; + uint32_t emc0_training_rw_offset_ob_byte2; + uint32_t emc1_training_rw_offset_ob_byte2; + uint32_t emc0_training_rw_offset_ob_byte3; + uint32_t emc1_training_rw_offset_ob_byte3; + uint32_t emc0_training_rw_offset_ob_misc; + uint32_t emc1_training_rw_offset_ob_misc; + } + training_mod_regs; + + uint32_t save_restore_mod_regs[12]; + + struct { + uint32_t mc_emem_arb_cfg; + uint32_t mc_emem_arb_outstanding_req; + uint32_t mc_emem_arb_refpb_hp_ctrl; + uint32_t mc_emem_arb_refpb_bank_ctrl; + uint32_t mc_emem_arb_timing_rcd; + uint32_t mc_emem_arb_timing_rp; + uint32_t mc_emem_arb_timing_rc; + uint32_t mc_emem_arb_timing_ras; + uint32_t mc_emem_arb_timing_faw; + uint32_t mc_emem_arb_timing_rrd; + uint32_t mc_emem_arb_timing_rap2pre; + uint32_t mc_emem_arb_timing_wap2pre; + uint32_t mc_emem_arb_timing_r2r; + uint32_t mc_emem_arb_timing_w2w; + uint32_t mc_emem_arb_timing_r2w; + uint32_t mc_emem_arb_timing_ccdmw; + uint32_t mc_emem_arb_timing_w2r; + uint32_t mc_emem_arb_timing_rfcpb; + uint32_t mc_emem_arb_da_turns; + uint32_t mc_emem_arb_da_covers; + uint32_t mc_emem_arb_misc0; + uint32_t mc_emem_arb_misc1; + uint32_t mc_emem_arb_misc2; + uint32_t mc_emem_arb_ring1_throttle; + uint32_t mc_emem_arb_dhyst_ctrl; + uint32_t mc_emem_arb_dhyst_timeout_util_0; + uint32_t mc_emem_arb_dhyst_timeout_util_1; + uint32_t mc_emem_arb_dhyst_timeout_util_2; + uint32_t mc_emem_arb_dhyst_timeout_util_3; + uint32_t mc_emem_arb_dhyst_timeout_util_4; + uint32_t mc_emem_arb_dhyst_timeout_util_5; + uint32_t mc_emem_arb_dhyst_timeout_util_6; + uint32_t mc_emem_arb_dhyst_timeout_util_7; + } + burst_mc_regs; + + struct { + uint32_t mc_mll_mpcorer_ptsa_rate; + uint32_t mc_ftop_ptsa_rate; + uint32_t mc_ptsa_grant_decrement; + uint32_t mc_latency_allowance_xusb_0; + uint32_t mc_latency_allowance_xusb_1; + uint32_t mc_latency_allowance_tsec_0; + uint32_t mc_latency_allowance_sdmmca_0; + uint32_t mc_latency_allowance_sdmmcaa_0; + uint32_t mc_latency_allowance_sdmmc_0; + uint32_t mc_latency_allowance_sdmmcab_0; + uint32_t mc_latency_allowance_ppcs_0; + uint32_t mc_latency_allowance_ppcs_1; + uint32_t mc_latency_allowance_mpcore_0; + uint32_t mc_latency_allowance_hc_0; + uint32_t mc_latency_allowance_hc_1; + uint32_t mc_latency_allowance_avpc_0; + uint32_t mc_latency_allowance_gpu_0; + uint32_t mc_latency_allowance_gpu2_0; + uint32_t mc_latency_allowance_nvenc_0; + uint32_t mc_latency_allowance_nvdec_0; + uint32_t mc_latency_allowance_vic_0; + uint32_t mc_latency_allowance_vi2_0; + uint32_t mc_latency_allowance_isp2_0; + uint32_t mc_latency_allowance_isp2_1; + } + la_scale_regs; + + uint32_t min_mrs_wait; + uint32_t emc_mrw; + uint32_t emc_mrw2; + uint32_t emc_mrw3; + uint32_t emc_mrw4; + uint32_t emc_mrw9; + uint32_t emc_mrs; + uint32_t emc_emrs; + uint32_t emc_emrs2; + uint32_t emc_auto_cal_config; + uint32_t emc_auto_cal_config2; + uint32_t emc_auto_cal_config3; + uint32_t emc_auto_cal_config4; + uint32_t emc_auto_cal_config5; + uint32_t emc_auto_cal_config6; + uint32_t emc_auto_cal_config7; + uint32_t emc_auto_cal_config8; + uint32_t emc_cfg_2; + uint32_t emc_sel_dpd_ctrl; + uint32_t emc_fdpd_ctrl_cmd_no_ramp; + uint32_t dll_clk_src; + uint32_t clk_out_enb_x_0_clk_enb_emc_dll; + uint32_t latency; +}; + +static_assert(sizeof(EristaMtcTable) == 0x1340); \ No newline at end of file