diff --git a/Source/sys-clk/common/include/fuse.h b/Source/sys-clk/common/include/fuse.h
new file mode 100644
index 00000000..107cebd2
--- /dev/null
+++ b/Source/sys-clk/common/include/fuse.h
@@ -0,0 +1,314 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018 shuffle2
+ * Copyright (c) 2018 balika011
+ * Copyright (c) 2019-2025 CTCaer
+ * Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+#ifndef BIT
+#define BIT(n) (1U<<(n))
+#endif
+
+/*! Fuse registers. */
+#define FUSE_CTRL 0x0
+#define FUSE_ADDR 0x4
+#define FUSE_RDATA 0x8
+#define FUSE_WDATA 0xC
+#define FUSE_TIME_RD1 0x10
+#define FUSE_TIME_RD2 0x14
+#define FUSE_TIME_PGM1 0x18
+#define FUSE_TIME_PGM2 0x1C
+#define FUSE_PRIV2INTFC 0x20
+#define FUSE_PRIV2INTFC_START_DATA BIT(0)
+#define FUSE_PRIV2INTFC_SKIP_RECORDS BIT(1)
+#define FUSE_FUSEBYPASS 0x24
+#define FUSE_PRIVATEKEYDISABLE 0x28
+#define FUSE_PRIVKEY_DISABLE BIT(0)
+#define FUSE_PRIVKEY_TZ_STICKY_BIT BIT(4)
+#define FUSE_DISABLEREGPROGRAM 0x2C
+#define FUSE_WRITE_ACCESS_SW 0x30
+#define FUSE_PWR_GOOD_SW 0x34
+#define FUSE_PRIV2RESHIFT 0x3C
+#define FUSE_FUSETIME_RD0 0x40
+#define FUSE_FUSETIME_RD1 0x44
+#define FUSE_FUSETIME_RD2 0x48
+#define FUSE_FUSETIME_RD3 0x4C
+#define FUSE_PRIVATE_KEY0_NONZERO 0x80
+#define FUSE_PRIVATE_KEY1_NONZERO 0x84
+#define FUSE_PRIVATE_KEY2_NONZERO 0x88
+#define FUSE_PRIVATE_KEY3_NONZERO 0x8C
+#define FUSE_PRIVATE_KEY4_NONZERO 0x90
+
+/*! Fuse Cached registers */
+#define FUSE_RESERVED_ODM8_B01 0x98 // FUSE_READ_TZ Group 0.
+#define FUSE_RESERVED_ODM9_B01 0x9C // FUSE_READ_TZ Group 0.
+#define FUSE_RESERVED_ODM10_B01 0xA0 // FUSE_READ_TZ Group 0.
+#define FUSE_RESERVED_ODM11_B01 0xA4 // FUSE_READ_TZ Group 0.
+#define FUSE_RESERVED_ODM12_B01 0xA8 // FUSE_READ_TZ Group 1? Is value -1?
+#define FUSE_RESERVED_ODM13_B01 0xAC // FUSE_READ_TZ Group 1? Is value -1?
+#define FUSE_RESERVED_ODM14_B01 0xB0 // FUSE_READ_TZ Group 1? Is value -1?
+#define FUSE_RESERVED_ODM15_B01 0xB4 // FUSE_READ_TZ Group 1? Is value -1?
+#define FUSE_RESERVED_ODM16_B01 0xB8 // FUSE_READ_TZ Group 2? Is value -1?
+#define FUSE_RESERVED_ODM17_B01 0xBC // FUSE_READ_TZ Group 2? Is value -1?
+#define FUSE_RESERVED_ODM18_B01 0xC0 // FUSE_READ_TZ Group 2.
+#define FUSE_RESERVED_ODM19_B01 0xC4 // FUSE_READ_TZ Group 2.
+#define FUSE_RESERVED_ODM20_B01 0xC8 // FUSE_READ_TZ Group 3.
+#define FUSE_RESERVED_ODM21_B01 0xCC // FUSE_READ_TZ Group 3.
+#define FUSE_KEK00_B01 0xD0
+#define FUSE_KEK01_B01 0xD4
+#define FUSE_KEK02_B01 0xD8
+#define FUSE_KEK03_B01 0xDC
+#define FUSE_BEK00_B01 0xE0
+#define FUSE_BEK01_B01 0xE4
+#define FUSE_BEK02_B01 0xE8
+#define FUSE_BEK03_B01 0xEC
+#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4SVT_B01 0xF0
+#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4SVT_B01 0xF4
+#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4SVT_B01 0xF8
+#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4SVT_B01 0xFC
+
+#define FUSE_PRODUCTION_MODE 0x100
+#define FUSE_JTAG_SECUREID_VALID 0x104
+#define FUSE_ODM_LOCK 0x108
+#define FUSE_OPT_OPENGL_EN 0x10C
+#define FUSE_SKU_INFO 0x110
+#define FUSE_CPU_SPEEDO_0_CALIB 0x114
+#define FUSE_CPU_IDDQ_CALIB 0x118
+
+#define FUSE_RESERVED_ODM22_B01 0x11C // FUSE_READ_TZ Group 3.
+#define FUSE_RESERVED_ODM23_B01 0x120 // FUSE_READ_TZ Group 3.
+#define FUSE_RESERVED_ODM24_B01 0x124 // FUSE_READ_TZ Group 4.
+
+#define FUSE_OPT_FT_REV 0x128
+#define FUSE_CPU_SPEEDO_1_CALIB 0x12C
+#define FUSE_CPU_SPEEDO_2_CALIB 0x130
+#define FUSE_SOC_SPEEDO_0_CALIB 0x134
+#define FUSE_SOC_SPEEDO_1_CALIB 0x138
+#define FUSE_SOC_SPEEDO_2_CALIB 0x13C
+#define FUSE_SOC_IDDQ_CALIB 0x140
+
+#define FUSE_RESERVED_ODM25_B01 0x144 // FUSE_READ_TZ Group 4.
+
+#define FUSE_FA 0x148
+#define FUSE_RESERVED_PRODUCTION 0x14C
+#define FUSE_HDMI_LANE0_CALIB 0x150
+#define FUSE_HDMI_LANE1_CALIB 0x154
+#define FUSE_HDMI_LANE2_CALIB 0x158
+#define FUSE_HDMI_LANE3_CALIB 0x15C
+#define FUSE_ENCRYPTION_RATE 0x160
+#define FUSE_PUBLIC_KEY0 0x164
+#define FUSE_PUBLIC_KEY1 0x168
+#define FUSE_PUBLIC_KEY2 0x16C
+#define FUSE_PUBLIC_KEY3 0x170
+#define FUSE_PUBLIC_KEY4 0x174
+#define FUSE_PUBLIC_KEY5 0x178
+#define FUSE_PUBLIC_KEY6 0x17C
+#define FUSE_PUBLIC_KEY7 0x180
+#define FUSE_TSENSOR1_CALIB 0x184 // CPU1.
+#define FUSE_TSENSOR2_CALIB 0x188 // CPU2.
+
+#define FUSE_OPT_SECURE_SCC_DIS_B01 0x18C
+
+#define FUSE_OPT_CP_REV 0x190 // FUSE style revision - ATE. 0x101 0x100
+#define FUSE_OPT_PFG 0x194
+#define FUSE_TSENSOR0_CALIB 0x198 // CPU0.
+#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19C
+#define FUSE_SECURITY_MODE 0x1A0
+#define FUSE_PRIVATE_KEY0 0x1A4
+#define FUSE_PRIVATE_KEY1 0x1A8
+#define FUSE_PRIVATE_KEY2 0x1AC
+#define FUSE_PRIVATE_KEY3 0x1B0
+#define FUSE_PRIVATE_KEY4 0x1B4
+#define FUSE_ARM_JTAG_DIS 0x1B8
+#define FUSE_BOOT_DEVICE_INFO 0x1BC
+#define FUSE_RESERVED_SW 0x1C0
+#define FUSE_OPT_VP9_DISABLE 0x1C4
+
+#define FUSE_RESERVED_ODM0 0x1C8
+#define FUSE_RESERVED_ODM1 0x1CC
+#define FUSE_RESERVED_ODM2 0x1D0
+#define FUSE_RESERVED_ODM3 0x1D4
+#define FUSE_RESERVED_ODM4 0x1D8
+#define FUSE_RESERVED_ODM5 0x1DC
+#define FUSE_RESERVED_ODM6 0x1E0
+#define FUSE_RESERVED_ODM7 0x1E4
+
+#define FUSE_OBS_DIS 0x1E8
+
+#define FUSE_OPT_NVJTAG_PROTECTION_ENABLE_B01 0x1EC
+
+#define FUSE_USB_CALIB 0x1F0
+#define FUSE_SKU_DIRECT_CONFIG 0x1F4
+#define FUSE_KFUSE_PRIVKEY_CTRL 0x1F8
+#define FUSE_PACKAGE_INFO 0x1FC // 1: MID, 2: DSC.
+#define FUSE_OPT_VENDOR_CODE 0x200
+#define FUSE_OPT_FAB_CODE 0x204
+#define FUSE_OPT_LOT_CODE_0 0x208
+#define FUSE_OPT_LOT_CODE_1 0x20C
+#define FUSE_OPT_WAFER_ID 0x210
+#define FUSE_OPT_X_COORDINATE 0x214
+#define FUSE_OPT_Y_COORDINATE 0x218
+#define FUSE_OPT_SEC_DEBUG_EN 0x21C
+#define FUSE_OPT_OPS_RESERVED 0x220
+#define FUSE_SATA_CALIB 0x224
+
+#define FUSE_SPARE_REGISTER_ODM_B01 0x224
+
+#define FUSE_GPU_IDDQ_CALIB 0x228
+#define FUSE_TSENSOR3_CALIB 0x22C // CPU3.
+#define FUSE_CLOCK_BONDOUT0 0x230
+#define FUSE_CLOCK_BONDOUT1 0x234
+
+#define FUSE_RESERVED_ODM26_B01 0x238 // FUSE_READ_TZ Group 4.
+#define FUSE_RESERVED_ODM27_B01 0x23C // FUSE_READ_TZ Group 4.
+#define FUSE_RESERVED_ODM28_B01 0x240 // MAX77812 phase configuration. FUSE_READ_TZ Group 5.
+
+#define FUSE_OPT_SAMPLE_TYPE 0x244
+#define FUSE_OPT_SUBREVISION 0x248 // "", "p", "q", "r". e.g: A01p.
+#define FUSE_OPT_SW_RESERVED_0 0x24C
+#define FUSE_OPT_SW_RESERVED_1 0x250
+#define FUSE_TSENSOR4_CALIB 0x254 // GPU.
+#define FUSE_TSENSOR5_CALIB 0x258 // MEM0.
+#define FUSE_TSENSOR6_CALIB 0x25C // MEM1.
+#define FUSE_TSENSOR7_CALIB 0x260 // PLLX.
+#define FUSE_OPT_PRIV_SEC_DIS 0x264
+#define FUSE_PKC_DISABLE 0x268
+
+#define FUSE_BOOT_SECURITY_INFO_B01 0x268
+#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4HVT_B01 0x26C
+#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4HVT_B01 0x270
+#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4HVT_B01 0x274
+#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4HVT_B01 0x278
+
+#define FUSE_FUSE2TSEC_DEBUG_DISABLE 0x27C
+#define FUSE_TSENSOR_COMMON 0x280
+#define FUSE_OPT_CP_BIN 0x284
+#define FUSE_OPT_GPU_DISABLE 0x288
+#define FUSE_OPT_FT_BIN 0x28C
+#define FUSE_OPT_DONE_MAP 0x290
+
+#define FUSE_RESERVED_ODM29_B01 0x294 // FUSE_READ_TZ Group 5? Is value -1?
+
+#define FUSE_APB2JTAG_DISABLE 0x298
+#define FUSE_ODM_INFO 0x29C // Debug features disable.
+#define FUSE_ARM_CRYPT_DE_FEATURE 0x2A8
+
+#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4SVT_B01 0x2B0
+#define FUSE_OPT_RAM_RCT_TSMCDP_PO4SVT_B01 0x2B4
+#define FUSE_OPT_RAM_WCT_TSMCDP_PO4SVT_B01 0x2B8
+#define FUSE_OPT_RAM_KP_TSMCDP_PO4SVT_B01 0x2BC
+
+#define FUSE_WOA_SKU_FLAG 0x2C0
+#define FUSE_ECO_RESERVE_1 0x2C4
+#define FUSE_GCPLEX_CONFIG_FUSE 0x2C8
+#define FUSE_GPU_VPR_AUTO_FETCH_DIS BIT(0)
+#define FUSE_GPU_VPR_ENABLED BIT(1)
+#define FUSE_GPU_WPR_ENABLED BIT(2)
+#define FUSE_PRODUCTION_MONTH 0x2CC
+#define FUSE_RAM_REPAIR_INDICATOR 0x2D0
+#define FUSE_TSENSOR9_CALIB 0x2D4 // AOTAG.
+#define FUSE_VMIN_CALIBRATION 0x2DC
+#define FUSE_AGING_SENSOR_CALIBRATION 0x2E0
+#define FUSE_DEBUG_AUTHENTICATION 0x2E4
+#define FUSE_SECURE_PROVISION_INDEX 0x2E8
+#define FUSE_SECURE_PROVISION_INFO 0x2EC
+#define FUSE_OPT_GPU_DISABLE_CP1 0x2F0
+#define FUSE_SPARE_ENDIS 0x2F4
+#define FUSE_ECO_RESERVE_0 0x2F8 // AID.
+#define FUSE_RESERVED_CALIB0 0x304 // GPCPLL ADC Calibration.
+#define FUSE_RESERVED_CALIB1 0x308
+#define FUSE_OPT_GPU_TPC0_DISABLE 0x30C
+#define FUSE_OPT_GPU_TPC0_DISABLE_CP1 0x310
+#define FUSE_OPT_CPU_DISABLE 0x314
+#define FUSE_OPT_CPU_DISABLE_CP1 0x318
+#define FUSE_TSENSOR10_CALIB 0x31C
+#define FUSE_TSENSOR10_CALIB_AUX 0x320
+#define FUSE_OPT_RAM_SVOP_DP 0x324
+#define FUSE_OPT_RAM_SVOP_PDP 0x328
+#define FUSE_OPT_RAM_SVOP_REG 0x32C
+#define FUSE_OPT_RAM_SVOP_SP 0x330
+#define FUSE_OPT_RAM_SVOP_SMPDP 0x334
+
+#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4HVT_B01 0x324
+#define FUSE_OPT_RAM_RCT_TSMCDP_PO4HVT_B01 0x328
+#define FUSE_OPT_RAM_WCT_TSMCDP_PO4HVT_B01 0x32c
+#define FUSE_OPT_RAM_KP_TSMCDP_PO4HVT_B01 0x330
+#define FUSE_OPT_RAM_SVOP_SP_B01 0x334
+
+#define FUSE_OPT_GPU_TPC0_DISABLE_CP2 0x338
+#define FUSE_OPT_GPU_TPC1_DISABLE 0x33C
+#define FUSE_OPT_GPU_TPC1_DISABLE_CP1 0x340
+#define FUSE_OPT_GPU_TPC1_DISABLE_CP2 0x344
+#define FUSE_OPT_CPU_DISABLE_CP2 0x348
+#define FUSE_OPT_GPU_DISABLE_CP2 0x34C
+#define FUSE_USB_CALIB_EXT 0x350
+#define FUSE_RESERVED_FIELD 0x354 // RMA.
+#define FUSE_SPARE_REALIGNMENT_REG 0x37C
+#define FUSE_SPARE_BIT_0 0x380
+//...
+#define FUSE_SPARE_BIT_31 0x3FC
+
+/*! Fuse commands. */
+#define FUSE_IDLE 0x0
+#define FUSE_READ 0x1
+#define FUSE_WRITE 0x2
+#define FUSE_SENSE 0x3
+#define FUSE_CMD_MASK 0x3
+
+/*! Fuse status. */
+#define FUSE_STATUS_RESET 0
+#define FUSE_STATUS_POST_RESET 1
+#define FUSE_STATUS_LOAD_ROW0 2
+#define FUSE_STATUS_LOAD_ROW1 3
+#define FUSE_STATUS_IDLE 4
+#define FUSE_STATUS_READ_SETUP 5
+#define FUSE_STATUS_READ_STROBE 6
+#define FUSE_STATUS_SAMPLE_FUSES 7
+#define FUSE_STATUS_READ_HOLD 8
+#define FUSE_STATUS_FUSE_SRC_SETUP 9
+#define FUSE_STATUS_WRITE_SETUP 10
+#define FUSE_STATUS_WRITE_ADDR_SETUP 11
+#define FUSE_STATUS_WRITE_PROGRAM 12
+#define FUSE_STATUS_WRITE_ADDR_HOLD 13
+#define FUSE_STATUS_FUSE_SRC_HOLD 14
+#define FUSE_STATUS_LOAD_RIR 15
+#define FUSE_STATUS_READ_BEFORE_WRITE_SETUP 16
+#define FUSE_STATUS_READ_DEASSERT_PD 17
+
+/*! Fuse cache registers. */
+#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))
+
+#define FUSE_ARRAY_WORDS_NUM 192
+#define FUSE_ARRAY_WORDS_NUM_B01 256
+
+enum
+{
+ FUSE_NX_HW_TYPE_ICOSA,
+ FUSE_NX_HW_TYPE_IOWA,
+ FUSE_NX_HW_TYPE_HOAG,
+ FUSE_NX_HW_TYPE_AULA
+};
+
+enum
+{
+ FUSE_NX_HW_STATE_PROD,
+ FUSE_NX_HW_STATE_DEV
+};
+
+#endif
diff --git a/Source/sys-clk/common/include/sysclk/clock_manager.h b/Source/sys-clk/common/include/sysclk/clock_manager.h
index 9660eabf..a24a0e48 100644
--- a/Source/sys-clk/common/include/sysclk/clock_manager.h
+++ b/Source/sys-clk/common/include/sysclk/clock_manager.h
@@ -43,7 +43,9 @@ typedef struct
uint32_t voltages[HocClkVoltage_EnumMax];
u16 speedos[HorizonOCSpeedo_EnumMax];
u16 iddq[HorizonOCSpeedo_EnumMax];
-
+ u16 waferX;
+ u16 waferY;
+
// Misc stuff
GpuSchedulingMode gpuSchedulingMode;
bool isSysDockInstalled;
diff --git a/Source/sys-clk/overlay/src/ui/gui/about_gui.cpp b/Source/sys-clk/overlay/src/ui/gui/about_gui.cpp
index bb0c935a..59b80d9c 100644
--- a/Source/sys-clk/overlay/src/ui/gui/about_gui.cpp
+++ b/Source/sys-clk/overlay/src/ui/gui/about_gui.cpp
@@ -28,6 +28,7 @@ tsl::elm::ListItem* DramModule = NULL;
tsl::elm::ListItem* sysdockStatusItem = NULL;
tsl::elm::ListItem* saltyNXStatusItem = NULL;
tsl::elm::ListItem* RETROStatusItem = NULL;
+tsl::elm::ListItem* waferCordsItem = NULL;
ImageElement* CatImage = NULL;
HideableCategoryHeader* CatHeader = NULL;
@@ -61,9 +62,11 @@ void AboutGui::listUI()
new tsl::elm::ListItem("Module: ");
this->listElement->addItem(DramModule);
- sysdockStatusItem =
- new tsl::elm::ListItem("sys-dock status:");
- this->listElement->addItem(sysdockStatusItem);
+ if(!IsHoag()) {
+ sysdockStatusItem =
+ new tsl::elm::ListItem("sys-dock status:");
+ this->listElement->addItem(sysdockStatusItem);
+ }
saltyNXStatusItem =
new tsl::elm::ListItem("SaltyNX status:");
@@ -75,6 +78,10 @@ void AboutGui::listUI()
this->listElement->addItem(RETROStatusItem);
}
+ waferCordsItem =
+ new tsl::elm::ListItem("Wafer Position:");
+ this->listElement->addItem(waferCordsItem);
+
this->listElement->addItem(
new tsl::elm::CategoryHeader("Credits")
);
@@ -279,18 +286,24 @@ void AboutGui::update()
void AboutGui::refresh()
{
BaseMenuGui::refresh();
- std::string ramModule = formatRamModule();
if (!this->context)
return;
// Format strings once per refresh
sprintf(strings[0], "%u/%u/%u", this->context->speedos[HorizonOCSpeedo_CPU], this->context->speedos[HorizonOCSpeedo_GPU], this->context->speedos[HorizonOCSpeedo_SOC]);
+ // This is how hekate does it
sprintf(strings[1], "%u/%u/%u", this->context->iddq[HorizonOCSpeedo_CPU], this->context->iddq[HorizonOCSpeedo_GPU], this->context->iddq[HorizonOCSpeedo_SOC]);
SpeedoItem->setValue(strings[0]);
IddqItem->setValue(strings[1]);
DramModule->setValue(formatRamModule());
- sysdockStatusItem->setValue(this->context->isSysDockInstalled ? "Installed" : "Not Installed");
+ if(!IsHoag())
+ sysdockStatusItem->setValue(this->context->isSysDockInstalled ? "Installed" : "Not Installed");
+
saltyNXStatusItem->setValue(this->context->isSaltyNXInstalled ? "Installed" : "Not Installed");
+
if(IsHoag())
RETROStatusItem->setValue(this->context->isUsingRetroSuper ? "Installed" : "Not Installed");
+
+ sprintf(strings[2], "X: %u Y: %u", this->context->waferX, this->context->waferY);
+ waferCordsItem->setValue(strings[2]);
}
diff --git a/Source/sys-clk/sysmodule/src/board.cpp b/Source/sys-clk/sysmodule/src/board.cpp
index 433fff12..70b9caa0 100644
--- a/Source/sys-clk/sysmodule/src/board.cpp
+++ b/Source/sys-clk/sysmodule/src/board.cpp
@@ -42,6 +42,7 @@
#include
#include
#include
+#include
#define MAX(A, B) std::max(A, B)
#define MIN(A, B) std::min(A, B)
@@ -49,19 +50,6 @@
#define FLOOR(A) std::floor(A)
#define ROUND(A) std::lround(A)
-
-#define FUSE_CPU_SPEEDO_0_CALIB 0x114
-//#define FUSE_CPU_SPEEDO_1_CALIB 0x12C
-#define FUSE_CPU_SPEEDO_2_CALIB 0x130
-
-#define FUSE_SOC_SPEEDO_0_CALIB 0x134
-//#define FUSE_SOC_SPEEDO_1_CALIB 0x138
-//#define FUSE_SOC_SPEEDO_2_CALIB 0x13C
-
-#define FUSE_CPU_IDDQ_CALIB 0x118
-#define FUSE_SOC_IDDQ_CALIB 0x140
-#define FUSE_GPU_IDDQ_CALIB 0x228
-
#define HOSSVC_HAS_CLKRST (hosversionAtLeast(8,0,0))
#define HOSSVC_HAS_TC (hosversionAtLeast(5,0,0))
#define NVGPU_GPU_IOCTL_PMU_GET_GPU_LOAD 0x80044715
@@ -104,6 +92,7 @@ u32 cpu0, cpu1, cpu2, cpu3, cpuAvg;
u16 cpuSpeedo0, cpuSpeedo2, socSpeedo0; // CPU, GPU, SOC
u32 speedoBracket;
u16 cpuIDDQ, gpuIDDQ, socIDDQ;
+u16 BwaferX, BwaferY;
u8 g_dramID = 0;
u64 cldvfs, cldvfs_temp;
u32 cachedEristaUvLowTune0 = 0, cachedEristaUvLowTune1 = 0, cachedMarikoUvHighTune0 = 0;
@@ -314,6 +303,11 @@ bool Board::IsUsingRetroSuperDisplay() {
return isRetro;
}
+void Board::GetWaferPosition(u16* x, u16* y) {
+ *x = BwaferX;
+ *y = BwaferY;
+}
+
void Board::fuseReadSpeedos() {
u64 pid = 0;
@@ -352,9 +346,11 @@ void Board::fuseReadSpeedos() {
cpuSpeedo0 = *reinterpret_cast(dump + FUSE_CPU_SPEEDO_0_CALIB);
cpuSpeedo2 = *reinterpret_cast(dump + FUSE_CPU_SPEEDO_2_CALIB);
socSpeedo0 = *reinterpret_cast(dump + FUSE_SOC_SPEEDO_0_CALIB);
- cpuIDDQ = *reinterpret_cast(dump + FUSE_CPU_IDDQ_CALIB);
- gpuIDDQ = *reinterpret_cast(dump + FUSE_SOC_IDDQ_CALIB);
- socIDDQ = *reinterpret_cast(dump + FUSE_GPU_IDDQ_CALIB);
+ cpuIDDQ = *reinterpret_cast(dump + FUSE_CPU_IDDQ_CALIB) * 4;
+ socIDDQ = *reinterpret_cast(dump + FUSE_GPU_IDDQ_CALIB) * 5;
+ gpuIDDQ = *reinterpret_cast(dump + FUSE_SOC_IDDQ_CALIB) * 4;
+ BwaferX = *reinterpret_cast(dump + FUSE_OPT_X_COORDINATE);
+ BwaferY = *reinterpret_cast(dump + FUSE_OPT_Y_COORDINATE);
svcCloseHandle(debug);
return;
diff --git a/Source/sys-clk/sysmodule/src/board.h b/Source/sys-clk/sysmodule/src/board.h
index c29e53ae..d40e604a 100644
--- a/Source/sys-clk/sysmodule/src/board.h
+++ b/Source/sys-clk/sysmodule/src/board.h
@@ -49,6 +49,7 @@ class Board
static void ResetToStockMem();
static void ResetToStockGpu();
static void ResetToStockDisplay();
+ static void GetWaferPosition(u16* x, u16* y);
static u8 GetHighestDockedDisplayRate();
static SysClkProfile GetProfile();
static void SetHz(SysClkModule module, std::uint32_t hz);
diff --git a/Source/sys-clk/sysmodule/src/clock_manager.cpp b/Source/sys-clk/sysmodule/src/clock_manager.cpp
index 9386ba51..cc5872c4 100644
--- a/Source/sys-clk/sysmodule/src/clock_manager.cpp
+++ b/Source/sys-clk/sysmodule/src/clock_manager.cpp
@@ -154,7 +154,7 @@ ClockManager::ClockManager()
}
this->context->isUsingRetroSuper = Board::IsUsingRetroSuperDisplay();
-
+ Board::GetWaferPosition(&this->context->waferX, &this->context->waferY);
threadStart(&cpuGovernorTHREAD);
threadStart(&gpuGovernorTHREAD);
threadStart(&vrrTHREAD);