refactore readme; add more ram clocks and remove arbitrary 1731.2 MHz; rename sys-clk to sys-clk-OC and add its source directly for easier maintenance

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KazushiM

2021-08-29 14:54:43 +08:00

parent 566a7254e5

commit 958de01e00

9 changed files with 74 additions and 1121 deletions

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Source/sys-clk-OC Submodule

Submodule Source/sys-clk-OC added at d036afacf5