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loader: fix mariko cpu unsafe freqs

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This commit is contained in:
souldbminersmwc
2025-10-02 12:10:42 -04:00
parent 83924f8c73
commit 923dc00b53
3 changed files with 519 additions and 454 deletions
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18
Source/Atmosphere/stratosphere/loader/source/oc/customize.cpp
View File

@@ -422,14 +422,14 @@ volatile CustomizeTable C = {
},
.marikoCpuDvfsTableUnsafeFreqs = {
{ 204000, { 732856, -17335, 113 }, { 1120000 } },
{ 306000, { 760024, -18195, 113 }, { 1120000 } },
{ 408000, { 789258, -19055, 113 }, { 1120000 } },
{ 510000, { 789258, -19055, 113 }, { 1120000 } },
{ 612000, { 853926, -20775, 113 }, { 1120000 } },
{ 714000, { 889361, -21625, 113 }, { 1120000 } },
{ 816000, { 926862, -22485, 113 }, { 1120000 } },
{ 918000, { 966431, -23345, 113 }, { 1120000 } },
// { 204000, { 732856, -17335, 113 }, {} }, // Unneeded, made to make room for new freqs
// { 306000, { 760024, -18195, 113 }, {} },
{ 408000, { 789258, -19055, 113 }, {} },
{ 510000, { 789258, -19055, 113 }, {} },
{ 612000, { 853926, -20775, 113 }, {} },
{ 714000, { 889361, -21625, 113 }, {} },
{ 816000, { 926862, -22485, 113 }, {} },
{ 918000, { 966431, -23345, 113 }, {} },
{ 1020000, { 1008066, -24205, 113 }, { 1120000 } },
{ 1122000, { 1051768, -25065, 113 }, { 1120000 } },
{ 1224000, { 1097537, -25925, 113 }, { 1120000 } },
@@ -450,7 +450,7 @@ volatile CustomizeTable C = {
{ 2703000, { 1857394, -37019, 113 }, { 1235000 } },
{ 2805000, { 1908891, -37707, 113 }, { 1235000 } },
{ 2907000, { 1960388, -38395, 113 }, { 1235000 } },
},
},
.eristaCpuDvfsTableUnsafeFreqs = {
{ 204000, { 721094 }, {} },
{ 306000, { 754040 }, {} },

1
Source/Atmosphere/stratosphere/loader/source/oc/oc_test.cpp
View File

@@ -76,6 +76,7 @@ Result Test_PcvDvfsTable() {
cvb_entry_t last_mariko_cpu_cvb_entry_default = { 1963500, { 1675751, -38635, 27 }, { 1120000 } };
assert(memcmp(GetDvfsTableLastEntry((cvb_entry_t *)(&mariko::CpuCvbTableDefault)), (void *)&last_mariko_cpu_cvb_entry_default, sizeof(last_mariko_cpu_cvb_entry_default)) == 0);
assert(GetDvfsTableLastEntry((cvb_entry_t *)(&erista::GpuCvbTableDefault))->freq == 921600);
assert(GetDvfsTableEntryCount((cvb_entry_t *)(&ams::ldr::oc::C.marikoCpuDvfsTableSLT)) == 25);
// Customized table default
assert(GetDvfsTableEntryCount((cvb_entry_t *)(&ams::ldr::oc::C.eristaCpuDvfsTable)) == 19);

334
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp
View File

@@ -18,51 +18,62 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "pcv.hpp"
#include "../mtc_timing_value.hpp"
#include "pcv.hpp"
#include "../mtc_timing_value.hpp"
namespace ams::ldr::oc::pcv::mariko {
Result GpuVmin(u32 *ptr)
namespace ams::ldr::oc::pcv::mariko
{
Result GpuVmin(u32 *ptr)
{
if (!C.marikoGpuVmin)
R_SKIP();
PATCH_OFFSET(ptr, (int)C.marikoGpuVmin);
R_SUCCEED();
}
}
Result GpuVmax(u32 *ptr)
{
Result GpuVmax(u32 *ptr)
{
if (!C.marikoGpuVmax)
R_SKIP();
PATCH_OFFSET(ptr, (int)C.marikoGpuVmax);
R_SUCCEED();
}
}
Result CpuFreqVdd(u32* ptr) {
dvfs_rail* entry = reinterpret_cast<dvfs_rail *>(reinterpret_cast<u8 *>(ptr) - offsetof(dvfs_rail, freq));
Result CpuFreqVdd(u32 *ptr)
{
dvfs_rail *entry = reinterpret_cast<dvfs_rail *>(reinterpret_cast<u8 *>(ptr) - offsetof(dvfs_rail, freq));
R_UNLESS(entry->id == 1, ldr::ResultInvalidCpuFreqVddEntry());
R_UNLESS(entry->min_mv == 250'000, ldr::ResultInvalidCpuFreqVddEntry());
R_UNLESS(entry->step_mv == 5000, ldr::ResultInvalidCpuFreqVddEntry());
R_UNLESS(entry->max_mv == 1525'000, ldr::ResultInvalidCpuFreqVddEntry());
if (C.marikoCpuUV) {
if(!C.enableMarikoCpuUnsafeFreqs) {
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.marikoCpuDvfsTableSLT)->freq);
} else {
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.marikoCpuDvfsTableUnsafeFreqs)->freq);
}
} else {
if (C.enableMarikoCpuUnsafeFreqs)
{
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.marikoCpuDvfsTable)->freq);
}
else
{
if (C.marikoCpuUV)
{
if (!C.enableMarikoCpuUnsafeFreqs)
{
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.marikoCpuDvfsTableSLT)->freq);
}
else
{
PATCH_OFFSET(ptr, GetDvfsTableLastEntry(C.marikoCpuDvfsTableUnsafeFreqs)->freq);
}
}
}
R_SUCCEED();
}
}
Result CpuVoltRange(u32* ptr) {
Result CpuVoltRange(u32 *ptr)
{
u32 min_volt_got = *(ptr - 1);
for (const auto& mv : CpuMinVolts) {
for (const auto &mv : CpuMinVolts)
{
if (min_volt_got != mv)
continue;
@@ -71,32 +82,36 @@ Result CpuVoltRange(u32* ptr) {
PATCH_OFFSET(ptr, C.marikoCpuMaxVolt);
// Patch vmin for slt
if (C.marikoCpuUV) {
if (*(ptr-5) == 620) {
PATCH_OFFSET((ptr-5), C.marikoCpuVmin);
if (C.marikoCpuUV)
{
if (*(ptr - 5) == 620)
{
PATCH_OFFSET((ptr - 5), C.marikoCpuVmin);
}
if (*(ptr-1) == 620) {
PATCH_OFFSET((ptr-1), 600);
if (*(ptr - 1) == 620)
{
PATCH_OFFSET((ptr - 1), 600);
}
}
R_SUCCEED();
}
R_THROW(ldr::ResultInvalidCpuMinVolt());
}
}
Result CpuVoltDfll(u32* ptr) {
Result CpuVoltDfll(u32 *ptr)
{
cvb_cpu_dfll_data *entry = reinterpret_cast<cvb_cpu_dfll_data *>(ptr);
R_UNLESS(entry->tune0_low == 0x0000FFCF, ldr::ResultInvalidCpuVoltDfllEntry());
R_UNLESS(entry->tune0_high == 0x00000000, ldr::ResultInvalidCpuVoltDfllEntry());
R_UNLESS(entry->tune1_low == 0x012207FF, ldr::ResultInvalidCpuVoltDfllEntry());
R_UNLESS(entry->tune1_high == 0x03FFF7FF, ldr::ResultInvalidCpuVoltDfllEntry());
switch(C.marikoCpuUV) {
switch (C.marikoCpuUV)
{
case 0:
break;
case 1:
PATCH_OFFSET(&(entry->tune0_low), 0x0000FF88); //process_id 0 // EOS UV1
PATCH_OFFSET(&(entry->tune0_low), 0x0000FF88); // process_id 0 // EOS UV1
PATCH_OFFSET(&(entry->tune0_high), 0x0000FFFF);
PATCH_OFFSET(&(entry->tune1_low), 0x021107FF);
PATCH_OFFSET(&(entry->tune1_high), 0x00000000);
@@ -147,9 +162,10 @@ Result CpuVoltDfll(u32* ptr) {
break;
}
R_SUCCEED();
}
}
Result GpuFreqMaxAsm(u32* ptr32) {
Result GpuFreqMaxAsm(u32 *ptr32)
{
// Check if both two instructions match the pattern
u32 ins1 = *ptr32, ins2 = *(ptr32 + 1);
if (!(asm_compare_no_rd(ins1, asm_pattern[0]) && asm_compare_no_rd(ins2, asm_pattern[1])))
@@ -161,7 +177,8 @@ Result GpuFreqMaxAsm(u32* ptr32) {
R_THROW(ldr::ResultInvalidGpuFreqMaxPattern());
u32 max_clock;
switch(C.marikoGpuUV) {
switch (C.marikoGpuUV)
{
case 0:
max_clock = GetDvfsTableLastEntry(C.marikoGpuDvfsTable)->freq;
break;
@@ -172,7 +189,7 @@ Result GpuFreqMaxAsm(u32* ptr32) {
max_clock = GetDvfsTableLastEntry(C.marikoGpuDvfsTableHiOPT)->freq;
break;
case 3:
if(C.enableMarikoGpuUnsafeFreqs)
if (C.enableMarikoGpuUnsafeFreqs)
{
max_clock = GetDvfsTableLastEntry(C.marikoGpuDvfsTableUv3UnsafeFreqs)->freq;
}
@@ -187,19 +204,20 @@ Result GpuFreqMaxAsm(u32* ptr32) {
}
u32 asm_patch[2] = {
asm_set_rd(asm_set_imm16(asm_pattern[0], max_clock), rd),
asm_set_rd(asm_set_imm16(asm_pattern[1], max_clock >> 16), rd)
};
asm_set_rd(asm_set_imm16(asm_pattern[1], max_clock >> 16), rd)};
PATCH_OFFSET(ptr32, asm_patch[0]);
PATCH_OFFSET(ptr32 + 1, asm_patch[1]);
R_SUCCEED();
}
}
Result GpuFreqPllLimit(u32* ptr) {
clk_pll_param* entry = reinterpret_cast<clk_pll_param *>(ptr);
Result GpuFreqPllLimit(u32 *ptr)
{
clk_pll_param *entry = reinterpret_cast<clk_pll_param *>(ptr);
// All zero except for freq
for (size_t i = 1; i < sizeof(clk_pll_param) / sizeof(u32); i++) {
for (size_t i = 1; i < sizeof(clk_pll_param) / sizeof(u32); i++)
{
R_UNLESS(*(ptr + i) == 0, ldr::ResultInvalidGpuPllEntry());
}
@@ -207,27 +225,35 @@ Result GpuFreqPllLimit(u32* ptr) {
u32 max_clk = entry->freq * 2;
entry->freq = max_clk;
R_SUCCEED();
}
}
/* Get RAM vendor data, ty b0rd2death! */
/* Note: I know this is horrible but I don't care atm. */
bool IsMicron() {
/* Get RAM vendor data, ty b0rd2death! */
/* Note: I know this is horrible but I don't care atm. */
bool IsMicron()
{
u64 packed_version;
splGetConfig((SplConfigItem)2, &packed_version);
switch (packed_version) {
case 11: case 15:
case 25: case 26: case 27:
case 32: case 33: case 34:
switch (packed_version)
{
case 11:
case 15:
case 25:
case 26:
case 27:
case 32:
case 33:
case 34:
/* RAM is Micron. */
return true;
default:
/* Not Micron. */
return false;
}
}
}
void MemMtcTableAutoAdjust(MarikoMtcTable* table) {
void MemMtcTableAutoAdjust(MarikoMtcTable *table)
{
/* Official Tegra X1 TRM, sign up for nvidia developer program (free) to download:
* https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual
* Section 18.11: MC Registers
@@ -245,20 +271,21 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table) {
* you'd better calculate timings yourself rather than relying on following algorithm.
*/
if (C.mtcConf != AUTO_ADJ) {
if (C.mtcConf != AUTO_ADJ)
{
return;
}
#define WRITE_PARAM_BURST_REG(TABLE, PARAM, VALUE) TABLE->burst_regs.PARAM = VALUE;
#define WRITE_PARAM_CA_TRAIN_REG(TABLE, PARAM, VALUE) TABLE->shadow_regs_ca_train.PARAM = VALUE;
#define WRITE_PARAM_RDWR_TRAIN_REG(TABLE, PARAM, VALUE) TABLE->shadow_regs_rdwr_train.PARAM = VALUE;
#define WRITE_PARAM_BURST_REG(TABLE, PARAM, VALUE) TABLE->burst_regs.PARAM = VALUE;
#define WRITE_PARAM_CA_TRAIN_REG(TABLE, PARAM, VALUE) TABLE->shadow_regs_ca_train.PARAM = VALUE;
#define WRITE_PARAM_RDWR_TRAIN_REG(TABLE, PARAM, VALUE) TABLE->shadow_regs_rdwr_train.PARAM = VALUE;
#define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \
#define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \
WRITE_PARAM_BURST_REG(TABLE, PARAM, VALUE) \
WRITE_PARAM_CA_TRAIN_REG(TABLE, PARAM, VALUE) \
WRITE_PARAM_RDWR_TRAIN_REG(TABLE, PARAM, VALUE)
#define GET_CYCLE_CEIL(PARAM) u32(CEIL(double(PARAM) / tCK_avg))
#define GET_CYCLE_CEIL(PARAM) u32(CEIL(double(PARAM) / tCK_avg))
WRITE_PARAM_ALL_REG(table, emc_rc, GET_CYCLE_CEIL(tRC));
WRITE_PARAM_ALL_REG(table, emc_rfc, GET_CYCLE_CEIL(tRFCab));
@@ -277,7 +304,8 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table) {
WRITE_PARAM_ALL_REG(table, emc_w2p, WTP);
/* May or may not have to be patched in Micron; let's skip for now. */
if (!IsMicron()) {
if (!IsMicron())
{
WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tXP));
WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tXP));
}
@@ -289,47 +317,50 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table) {
WRITE_PARAM_ALL_REG(table, emc_trpab, GET_CYCLE_CEIL(tRPab));
WRITE_PARAM_ALL_REG(table, emc_trefbw, REFBW);
/* Worth replacing with l4t dumps at some point. */
// Burst MC Regs
#define WRITE_PARAM_BURST_MC_REG(TABLE, PARAM, VALUE) TABLE->burst_mc_regs.PARAM = VALUE;
/* Worth replacing with l4t dumps at some point. */
// Burst MC Regs
#define WRITE_PARAM_BURST_MC_REG(TABLE, PARAM, VALUE) TABLE->burst_mc_regs.PARAM = VALUE;
constexpr u32 MC_ARB_DIV = 4;
constexpr u32 MC_ARB_SFA = 2;
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_cfg, C.marikoEmcMaxClock / (33.3 * 1000) / MC_ARB_DIV); //CYCLES_PER_UPDATE: The number of mcclk cycles per deadline timer update
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_cfg, C.marikoEmcMaxClock / (33.3 * 1000) / MC_ARB_DIV); //CYCLES_PER_UPDATE: The number of mcclk cycles per deadline timer update
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rcd, CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV) - 2)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rp, CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rc, CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV) - 1)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_ras, CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_faw, CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rrd, CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1)
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rap2pre, CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV))
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_wap2pre, CEIL((WTP) / MC_ARB_DIV))
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2r, CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA)
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2w, CEIL((R2W) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_w2r, CEIL((W2R) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rap2pre, CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV))
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_wap2pre, CEIL((WTP) / MC_ARB_DIV))
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2r, CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA)
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2w, CEIL((R2W) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
// WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_w2r, CEIL((W2R) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rfcpb, CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV))
}
}
void MemMtcPllmbDivisor(MarikoMtcTable* table) {
void MemMtcPllmbDivisor(MarikoMtcTable *table)
{
// Calculate DIVM and DIVN (clock divisors)
// Common PLL oscillator is 38.4 MHz
// PLLMB_OUT = 38.4 MHz / PLLLMB_DIVM * PLLMB_DIVN
typedef struct {
typedef struct
{
u8 numerator : 4;
u8 denominator : 4;
} pllmb_div;
constexpr pllmb_div div[] = {
{3, 4}, {2, 3}, {1, 2}, {1, 3}, {1, 4}, {0, 2}
};
{3, 4}, {2, 3}, {1, 2}, {1, 3}, {1, 4}, {0, 2}};
constexpr u32 pll_osc_in = 38'400;
u32 divm {}, divn {};
u32 divm{}, divn{};
const u32 remainder = C.marikoEmcMaxClock % pll_osc_in;
for (const auto &index : div) {
for (const auto &index : div)
{
// Round down
if (remainder >= pll_osc_in * index.numerator / index.denominator) {
if (remainder >= pll_osc_in * index.numerator / index.denominator)
{
divm = index.denominator;
divn = C.marikoEmcMaxClock / pll_osc_in * divm + index.numerator;
break;
@@ -338,16 +369,18 @@ void MemMtcPllmbDivisor(MarikoMtcTable* table) {
table->pllmb_divm = divm;
table->pllmb_divn = divn;
}
}
Result MemFreqMtcTable(u32* ptr) {
u32 khz_list[] = { 1600000, 1331200, 204000 };
Result MemFreqMtcTable(u32 *ptr)
{
u32 khz_list[] = {1600000, 1331200, 204000};
u32 khz_list_size = sizeof(khz_list) / sizeof(u32);
// Generate list for mtc table pointers
MarikoMtcTable* table_list[khz_list_size];
for (u32 i = 0; i < khz_list_size; i++) {
u8* table = reinterpret_cast<u8 *>(ptr) - offsetof(MarikoMtcTable, rate_khz) - i * sizeof(MarikoMtcTable);
MarikoMtcTable *table_list[khz_list_size];
for (u32 i = 0; i < khz_list_size; i++)
{
u8 *table = reinterpret_cast<u8 *>(ptr) - offsetof(MarikoMtcTable, rate_khz) - i * sizeof(MarikoMtcTable);
table_list[i] = reinterpret_cast<MarikoMtcTable *>(table);
R_UNLESS(table_list[i]->rate_khz == khz_list[i], ldr::ResultInvalidMtcTable());
R_UNLESS(table_list[i]->rev == MTC_TABLE_REV, ldr::ResultInvalidMtcTable());
@@ -372,48 +405,70 @@ Result MemFreqMtcTable(u32* ptr) {
PATCH_OFFSET(ptr, C.marikoEmcMaxClock);
// Handle customize table replacement
//if (C.mtcConf == CUSTOMIZED_ALL) {
// if (C.mtcConf == CUSTOMIZED_ALL) {
// MemMtcCustomizeTable(table_list[0], reinterpret_cast<MarikoMtcTable *>(reinterpret_cast<u8 *>(C.marikoMtcTable)));
// }
R_SUCCEED();
}
}
Result MemFreqDvbTable(u32* ptr) {
emc_dvb_dvfs_table_t* default_end = reinterpret_cast<emc_dvb_dvfs_table_t *>(ptr);
emc_dvb_dvfs_table_t* new_start = default_end + 1;
Result MemFreqDvbTable(u32 *ptr)
{
emc_dvb_dvfs_table_t *default_end = reinterpret_cast<emc_dvb_dvfs_table_t *>(ptr);
emc_dvb_dvfs_table_t *new_start = default_end + 1;
// Validate existing table
void* mem_dvb_table_head = reinterpret_cast<u8 *>(new_start) - sizeof(EmcDvbTableDefault);
void *mem_dvb_table_head = reinterpret_cast<u8 *>(new_start) - sizeof(EmcDvbTableDefault);
bool validated = std::memcmp(mem_dvb_table_head, EmcDvbTableDefault, sizeof(EmcDvbTableDefault)) == 0;
R_UNLESS(validated, ldr::ResultInvalidDvbTable());
if (C.marikoEmcMaxClock <= EmcClkOSLimit)
R_SKIP();
int32_t voltAdd = 25*C.marikoEmcDvbShift;
int32_t voltAdd = 25 * C.marikoEmcDvbShift;
#define DVB_VOLT(zero, one, two) std::min(zero+voltAdd, 1050), std::min(one+voltAdd, 1025), std::min(two+voltAdd, 1000),
#define DVB_VOLT(zero, one, two) std::min(zero + voltAdd, 1050), std::min(one + voltAdd, 1025), std::min(two + voltAdd, 1000),
if (C.marikoEmcMaxClock < 1862400) {
if (C.marikoEmcMaxClock < 1862400)
{
std::memcpy(new_start, default_end, sizeof(emc_dvb_dvfs_table_t));
} else if (C.marikoEmcMaxClock < 2131200){
emc_dvb_dvfs_table_t oc_table = { 1862400, { 700, 675, 650, } };
}
else if (C.marikoEmcMaxClock < 2131200)
{
emc_dvb_dvfs_table_t oc_table = {1862400, {
700,
675,
650,
}};
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
} else if (C.marikoEmcMaxClock < 2400000){
emc_dvb_dvfs_table_t oc_table = { 2131200, { 725, 700, 675, } };
}
else if (C.marikoEmcMaxClock < 2400000)
{
emc_dvb_dvfs_table_t oc_table = {2131200, {
725,
700,
675,
}};
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
} else if (C.marikoEmcMaxClock < 2665600){
emc_dvb_dvfs_table_t oc_table = { 2400000, { DVB_VOLT(750, 725, 700) } };
}
else if (C.marikoEmcMaxClock < 2665600)
{
emc_dvb_dvfs_table_t oc_table = {2400000, {DVB_VOLT(750, 725, 700)}};
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
} else if (C.marikoEmcMaxClock < 2931200){
emc_dvb_dvfs_table_t oc_table = { 2665600, { DVB_VOLT(775, 750, 725) } };
}
else if (C.marikoEmcMaxClock < 2931200)
{
emc_dvb_dvfs_table_t oc_table = {2665600, {DVB_VOLT(775, 750, 725)}};
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
} else if (C.marikoEmcMaxClock < 3200000){
emc_dvb_dvfs_table_t oc_table = { 2931200, { DVB_VOLT(800, 775, 750) } };
}
else if (C.marikoEmcMaxClock < 3200000)
{
emc_dvb_dvfs_table_t oc_table = {2931200, {DVB_VOLT(800, 775, 750)}};
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
} else {
emc_dvb_dvfs_table_t oc_table = { 3200000, { DVB_VOLT(800, 800, 775) } };
}
else
{
emc_dvb_dvfs_table_t oc_table = {3200000, {DVB_VOLT(800, 800, 775)}};
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
}
new_start->freq = C.marikoEmcMaxClock;
@@ -422,18 +477,21 @@ Result MemFreqDvbTable(u32* ptr) {
*/
R_SUCCEED();
}
}
Result MemFreqMax(u32* ptr) {
Result MemFreqMax(u32 *ptr)
{
if (C.marikoEmcMaxClock <= EmcClkOSLimit)
R_SKIP();
PATCH_OFFSET(ptr, C.marikoEmcMaxClock);
R_SUCCEED();
}
}
Result I2cSet_U8(I2cDevice dev, u8 reg, u8 val) {
struct {
Result I2cSet_U8(I2cDevice dev, u8 reg, u8 val)
{
struct
{
u8 reg;
u8 val;
} __attribute__((packed)) cmd;
@@ -448,15 +506,17 @@ Result I2cSet_U8(I2cDevice dev, u8 reg, u8 val) {
res = i2csessionSendAuto(&_session, &cmd, sizeof(cmd), I2cTransactionOption_All);
i2csessionClose(&_session);
return res;
}
}
Result EmcVddqVolt(u32* ptr) {
regulator* entry = reinterpret_cast<regulator *>(reinterpret_cast<u8 *>(ptr) - offsetof(regulator, type_2_3.default_uv));
Result EmcVddqVolt(u32 *ptr)
{
regulator *entry = reinterpret_cast<regulator *>(reinterpret_cast<u8 *>(ptr) - offsetof(regulator, type_2_3.default_uv));
constexpr u32 uv_step = 5'000;
constexpr u32 uv_min = 250'000;
auto validator = [entry]() {
auto validator = [entry]()
{
R_UNLESS(entry->id == 2, ldr::ResultInvalidRegulatorEntry());
R_UNLESS(entry->type == 3, ldr::ResultInvalidRegulatorEntry());
R_UNLESS(entry->type_2_3.step_uv == uv_step, ldr::ResultInvalidRegulatorEntry());
@@ -480,45 +540,49 @@ Result EmcVddqVolt(u32* ptr) {
i2cExit();
R_SUCCEED();
}
}
void Patch(uintptr_t mapped_nso, size_t nso_size) {
void Patch(uintptr_t mapped_nso, size_t nso_size)
{
u32 CpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(CpuCvbTableDefault)->freq);
u32 GpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(GpuCvbTableDefault)->freq);
PatcherEntry<u32> patches[] = {
{ "CPU Freq Vdd", &CpuFreqVdd, 1, nullptr, CpuClkOSLimit },
{ "CPU Freq Table", CpuFreqCvbTable<true>, 1, nullptr, CpuCvbDefaultMaxFreq },
{ "CPU Volt Limit", &CpuVoltRange, 13, nullptr, CpuVoltOfficial },
{ "CPU Volt Dfll", &CpuVoltDfll, 1, nullptr, 0x0000FFCF },
{ "GPU Freq Table", GpuFreqCvbTable<true>, 1, nullptr, GpuCvbDefaultMaxFreq },
{ "GPU Freq Asm", &GpuFreqMaxAsm, 2, &GpuMaxClockPatternFn },
{ "GPU Freq PLL", &GpuFreqPllLimit, 1, nullptr, GpuClkPllLimit },
{ "MEM Freq Mtc", &MemFreqMtcTable, 0, nullptr, EmcClkOSLimit },
{ "MEM Freq Dvb", &MemFreqDvbTable, 1, nullptr, EmcClkOSLimit },
{ "MEM Freq Max", &MemFreqMax, 0, nullptr, EmcClkOSLimit },
{ "MEM Freq PLLM", &MemFreqPllmLimit, 2, nullptr, EmcClkPllmLimit },
{ "MEM Vddq", &EmcVddqVolt, 2, nullptr, EmcVddqDefault },
{ "MEM Vdd2", &MemVoltHandler, 2, nullptr, MemVdd2Default },
{ "GPU Vmin", &GpuVmin, 0, nullptr, gpuVmin},
{ "GPU Vmax", &GpuVmax, 0, nullptr, gpuVmax},
{"CPU Freq Vdd", &CpuFreqVdd, 1, nullptr, CpuClkOSLimit},
{"CPU Freq Table", CpuFreqCvbTable<true>, 1, nullptr, CpuCvbDefaultMaxFreq},
{"CPU Volt Limit", &CpuVoltRange, 13, nullptr, CpuVoltOfficial},
{"CPU Volt Dfll", &CpuVoltDfll, 1, nullptr, 0x0000FFCF},
{"GPU Freq Table", GpuFreqCvbTable<true>, 1, nullptr, GpuCvbDefaultMaxFreq},
{"GPU Freq Asm", &GpuFreqMaxAsm, 2, &GpuMaxClockPatternFn},
{"GPU Freq PLL", &GpuFreqPllLimit, 1, nullptr, GpuClkPllLimit},
{"MEM Freq Mtc", &MemFreqMtcTable, 0, nullptr, EmcClkOSLimit},
{"MEM Freq Dvb", &MemFreqDvbTable, 1, nullptr, EmcClkOSLimit},
{"MEM Freq Max", &MemFreqMax, 0, nullptr, EmcClkOSLimit},
{"MEM Freq PLLM", &MemFreqPllmLimit, 2, nullptr, EmcClkPllmLimit},
{"MEM Vddq", &EmcVddqVolt, 2, nullptr, EmcVddqDefault},
{"MEM Vdd2", &MemVoltHandler, 2, nullptr, MemVdd2Default},
{"GPU Vmin", &GpuVmin, 0, nullptr, gpuVmin},
{"GPU Vmax", &GpuVmax, 0, nullptr, gpuVmax},
};
for (uintptr_t ptr = mapped_nso;
ptr <= mapped_nso + nso_size - sizeof(MarikoMtcTable);
ptr += sizeof(u32)) {
u32* ptr32 = reinterpret_cast<u32 *>(ptr);
for (auto& entry : patches) {
ptr += sizeof(u32))
{
u32 *ptr32 = reinterpret_cast<u32 *>(ptr);
for (auto &entry : patches)
{
if (R_SUCCEEDED(entry.SearchAndApply(ptr32)))
break;
}
}
for (auto& entry : patches) {
for (auto &entry : patches)
{
LOGGING("%s Count: %zu", entry.description, entry.patched_count);
if (R_FAILED(entry.CheckResult()))
CRASH(entry.description);
}
}
}
}