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ldr: use DvbMeta struct

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Lightos1
2026-05-12 20:05:02 +02:00
parent 1b07df5f08
commit 7384404ac1
5 changed files with 77 additions and 66 deletions
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2
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_common.hpp
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@@ -125,7 +125,7 @@ namespace ams::ldr::hoc::pcv {
u32 unkStepMaybe; u32 unkStepMaybe;
u32 vmin; u32 vmin;
u32 unkZero4[3]; u32 unkZero4[3];
u32 pllMinMilliVoltsMaybe; u32 pllMinMilliVolts;
u32 vmax; u32 vmax;
u32 unkScale2; u32 unkScale2;
u32 speedoScale; u32 speedoScale;

11
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.cpp
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@@ -67,6 +67,7 @@ namespace ams::ldr::hoc::pcv::erista {
Result CpuVoltDfll(u32* ptr) { Result CpuVoltDfll(u32* ptr) {
CvbCpuDfllData *entry = reinterpret_cast<CvbCpuDfllData *>(ptr); CvbCpuDfllData *entry = reinterpret_cast<CvbCpuDfllData *>(ptr);
R_UNLESS(entry->tune0_low == 0xFFEAD0FF, ldr::ResultInvalidCpuVoltDfllEntry()); R_UNLESS(entry->tune0_low == 0xFFEAD0FF, ldr::ResultInvalidCpuVoltDfllEntry());
R_UNLESS(entry->tune0_high == 0x0, ldr::ResultInvalidCpuVoltDfllEntry()); R_UNLESS(entry->tune0_high == 0x0, ldr::ResultInvalidCpuVoltDfllEntry());
R_UNLESS(entry->tune1_low == 0x0, ldr::ResultInvalidCpuVoltDfllEntry()); R_UNLESS(entry->tune1_low == 0x0, ldr::ResultInvalidCpuVoltDfllEntry());
@@ -100,6 +101,7 @@ namespace ams::ldr::hoc::pcv::erista {
default: default:
break; break;
} }
R_SUCCEED(); R_SUCCEED();
} }
@@ -165,7 +167,9 @@ namespace ams::ldr::hoc::pcv::erista {
} }
u32 asm_patch[2] = { u32 asm_patch[2] = {
asm_set_rd(asm_set_imm16(GpuAsmPattern[0], max_clock), rd), asm_set_rd(asm_set_imm16(GpuAsmPattern[0], max_clock), rd),
asm_set_rd(asm_set_imm16(GpuAsmPattern[1], max_clock >> 16), rd)}; asm_set_rd(asm_set_imm16(GpuAsmPattern[1], max_clock >> 16), rd)
};
PATCH_OFFSET(ptr32, asm_patch[0]); PATCH_OFFSET(ptr32, asm_patch[0]);
PATCH_OFFSET(ptr32 + 1, asm_patch[1]); PATCH_OFFSET(ptr32 + 1, asm_patch[1]);
@@ -212,6 +216,8 @@ namespace ams::ldr::hoc::pcv::erista {
u32 trefbw = refresh_raw + 0x40; u32 trefbw = refresh_raw + 0x40;
trefbw = MIN(trefbw, static_cast<u32>(0x3FFF)); trefbw = MIN(trefbw, static_cast<u32>(0x3FFF));
const u32 dyn_self_ref_control = (static_cast<u32>(7605.0 / tCK_avg) + 260) | (table->burst_regs.emc_dyn_self_ref_control & 0xffff0000);
CalculateTimings(tCK_avg); CalculateTimings(tCK_avg);
WRITE_PARAM_ALL_REG(table, emc_rd_rcd, GET_CYCLE_CEIL(tRCD)); WRITE_PARAM_ALL_REG(table, emc_rd_rcd, GET_CYCLE_CEIL(tRCD));
@@ -239,7 +245,6 @@ namespace ams::ldr::hoc::pcv::erista {
WRITE_PARAM_ALL_REG(table, emc_refresh, refresh_raw); WRITE_PARAM_ALL_REG(table, emc_refresh, refresh_raw);
WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, refresh_raw / 4); WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, refresh_raw / 4);
WRITE_PARAM_ALL_REG(table, emc_trefbw, trefbw); WRITE_PARAM_ALL_REG(table, emc_trefbw, trefbw);
const u32 dyn_self_ref_control = (static_cast<u32>(7605.0 / tCK_avg) + 260) | (table->burst_regs.emc_dyn_self_ref_control & 0xffff0000);
WRITE_PARAM_ALL_REG(table, emc_dyn_self_ref_control, dyn_self_ref_control); WRITE_PARAM_ALL_REG(table, emc_dyn_self_ref_control, dyn_self_ref_control);
WRITE_PARAM_ALL_REG(table, emc_pdex2wr, pdex2rw); WRITE_PARAM_ALL_REG(table, emc_pdex2wr, pdex2rw);
WRITE_PARAM_ALL_REG(table, emc_pdex2rd, pdex2rw); WRITE_PARAM_ALL_REG(table, emc_pdex2rd, pdex2rw);
@@ -357,7 +362,7 @@ namespace ams::ldr::hoc::pcv::erista {
table->dram_timings.t_rp = tRFCpb; table->dram_timings.t_rp = tRFCpb;
table->dram_timings.t_rfc = tRFCab; table->dram_timings.t_rfc = tRFCab;
table->emc_cfg_2 = 0x11083D; table->emc_cfg_2 = 0x11083D;
table->min_volt = (u32)std::min(static_cast<s32>(1050), 900 + C.emcDvbShift * 25); table->min_volt = std::clamp(900 + (C.emcDvbShift * 25), 900, 1050);
} }
/* Probably more intuitive to point to 40800 rather than 1600000, but oh well. */ /* Probably more intuitive to point to 40800 rather than 1600000, but oh well. */

2
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_erista.hpp
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@@ -140,7 +140,7 @@ namespace ams::ldr::hoc::pcv::erista {
MtcTableIndex index; MtcTableIndex index;
}; };
constexpr MtcDramIndex mtcIndexTable[] = { const inline MtcDramIndex mtcIndexTable[] = {
{ ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH, T210SdevEmcDvfsTableS4gb01, }, { ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH, T210SdevEmcDvfsTableS4gb01, },
{ ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WTC, T210SdevEmcDvfsTableS4gb01, }, { ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WTC, T210SdevEmcDvfsTableS4gb01, },
{ ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH, T210SdevEmcDvfsTableS6gb01, }, { ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH, T210SdevEmcDvfsTableS6gb01, },

24
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp
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@@ -94,25 +94,31 @@ namespace ams::ldr::hoc::pcv::mariko {
} }
Result CpuVoltDVFS(u32 *ptr) { Result CpuVoltDVFS(u32 *ptr) {
if (MatchesPattern(ptr, cpuVoltagePatchOffsets, cpuVoltagePatchValues)) { CvbMeta *cpuCvbMeta = reinterpret_cast<CvbMeta *>(reinterpret_cast<u8 *>(ptr) - offsetof(CvbMeta, vmin));
R_UNLESS(cpuCvbMeta->highVmin == CpuHighVminOfficial, ldr::ResultInvalidCpuMinVolt());
R_UNLESS(cpuCvbMeta->unkStepMaybe == 38, ldr::ResultInvalidCpuMinVolt());
R_UNLESS(cpuCvbMeta->vmax == CpuVoltOfficial, ldr::ResultInvalidCpuMinVolt());
R_UNLESS(cpuCvbMeta->unkScale2 == 1000, ldr::ResultInvalidCpuMinVolt());
R_UNLESS(cpuCvbMeta->speedoScale == 100, ldr::ResultInvalidCpuMinVolt());
R_UNLESS(cpuCvbMeta->voltageScale == 1000, ldr::ResultInvalidCpuMinVolt());
R_UNLESS(cpuCvbMeta->unkZero5 == 0, ldr::ResultInvalidCpuMinVolt());
if (C.marikoCpuLowVmin) { if (C.marikoCpuLowVmin) {
PATCH_OFFSET(ptr, C.marikoCpuLowVmin); PATCH_OFFSET(&(cpuCvbMeta->vmin), C.marikoCpuLowVmin);
} }
if (C.marikoCpuHighVmin) { if (C.marikoCpuHighVmin) {
PATCH_OFFSET(ptr - 2, C.marikoCpuHighVmin); PATCH_OFFSET(&(cpuCvbMeta->highVmin), C.marikoCpuHighVmin);
} }
if (C.marikoCpuMaxVolt) { if (C.marikoCpuMaxVolt) {
PATCH_OFFSET(ptr + 5, C.marikoCpuMaxVolt); PATCH_OFFSET(&(cpuCvbMeta->vmax), C.marikoCpuMaxVolt);
} }
R_SUCCEED(); R_SUCCEED();
} }
R_THROW(ldr::ResultInvalidCpuMinVolt());
}
Result CpuVoltThermals(u32 *ptr) { Result CpuVoltThermals(u32 *ptr) {
if (std::memcmp(ptr, cpuVoltThermalData, sizeof(cpuVoltThermalData))) { if (std::memcmp(ptr, cpuVoltThermalData, sizeof(cpuVoltThermalData))) {
R_THROW(ldr::ResultInvalidCpuMinVolt()); R_THROW(ldr::ResultInvalidCpuMinVolt());
@@ -146,7 +152,7 @@ namespace ams::ldr::hoc::pcv::mariko {
PATCH_OFFSET(&(entry->tune0_low), 0xffa0); PATCH_OFFSET(&(entry->tune0_low), 0xffa0);
PATCH_OFFSET(&(entry->tune0_high), 0xffff); PATCH_OFFSET(&(entry->tune0_high), 0xffff);
PATCH_OFFSET(&(entry->tune1_low), 0x21107ff); PATCH_OFFSET(&(entry->tune1_low), 0x21107ff);
PATCH_OFFSET(&(entry->tune1_high), 0); PATCH_OFFSET(&(entry->tune1_high), 0x0);
break; break;
case 2: case 2:
PATCH_OFFSET(&(entry->tune0_high), 0xffdf); PATCH_OFFSET(&(entry->tune0_high), 0xffdf);
@@ -216,7 +222,7 @@ namespace ams::ldr::hoc::pcv::mariko {
switch (C.marikoCpuUVHigh) { switch (C.marikoCpuUVHigh) {
case 1: case 1:
PATCH_OFFSET(&(entry->tune1_high), 0); PATCH_OFFSET(&(entry->tune1_high), 0x0);
PATCH_OFFSET(&(entry->tune0_high), 0xffff); PATCH_OFFSET(&(entry->tune0_high), 0xffff);
break; break;
case 2: case 2:

4
Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.hpp
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@@ -50,8 +50,8 @@ namespace ams::ldr::hoc::pcv::mariko {
constexpr u32 CpuClkOfficial = 1963'500; constexpr u32 CpuClkOfficial = 1963'500;
constexpr u32 CpuVoltOfficial = 1120; constexpr u32 CpuVoltOfficial = 1120;
constexpr u32 CpuHighVminOfficial = 850;
constexpr u32 CpuVminOfficial = 620; constexpr u32 CpuVminOfficial = 620;
constexpr u32 CpuTune0Low = 0xFFCF; constexpr u32 CpuTune0Low = 0xFFCF;
static const u32 cpuVoltagePatchValues[] = { 850, 38, 1120, 1000, 100, 1000, 0 }; static const u32 cpuVoltagePatchValues[] = { 850, 38, 1120, 1000, 100, 1000, 0 };
@@ -230,7 +230,7 @@ namespace ams::ldr::hoc::pcv::mariko {
MtcTableIndex index; MtcTableIndex index;
}; };
constexpr MtcDramIndex mtcIndexTable[] = { const inline MtcDramIndex mtcIndexTable[] = {
{ HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, T210b0SdevEmcDvfsTableH1y4gb01, }, { HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, T210b0SdevEmcDvfsTableH1y4gb01, },
{ AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, T210b0SdevEmcDvfsTableH1y4gb01, }, { AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, T210b0SdevEmcDvfsTableH1y4gb01, },
{ IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, T210b0SdevEmcDvfsTableH1y4gb01, }, { IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, T210b0SdevEmcDvfsTableH1y4gb01, },