diff --git a/README.md b/README.md index 8bfa5750..bba0b0a4 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ # Switch OC Suite -Overclocking suite for Switch **(Mariko Only)** running on Atmosphere CFW. Support Horizon OS 11.0.0-13.1.0. +Overclocking suite for Switch **(Mariko Only)** running on Atmosphere CFW. Support Horizon OS 11.0.0-13.2.0. diff --git a/SdOut/atmosphere/1.2.4_loader_1795.2.kip b/SdOut/atmosphere/1.2.4_loader_1795.2.kip deleted file mode 100644 index 04081865..00000000 Binary files a/SdOut/atmosphere/1.2.4_loader_1795.2.kip and /dev/null differ diff --git a/SdOut/atmosphere/1.2.4_loader_2064.0.kip b/SdOut/atmosphere/1.2.4_loader_2064.0.kip deleted file mode 100644 index f381caaf..00000000 Binary files a/SdOut/atmosphere/1.2.4_loader_2064.0.kip and /dev/null differ diff --git a/SdOut/atmosphere/1.2.4_loader_2131.2.kip b/SdOut/atmosphere/1.2.4_loader_2131.2.kip deleted file mode 100644 index 530ac8e0..00000000 Binary files a/SdOut/atmosphere/1.2.4_loader_2131.2.kip and /dev/null differ diff --git a/SdOut/atmosphere/1.2.4_loader_1996.8.kip b/SdOut/atmosphere/1.2.5_loader_1795.2.kip similarity index 63% rename from SdOut/atmosphere/1.2.4_loader_1996.8.kip rename to SdOut/atmosphere/1.2.5_loader_1795.2.kip index 813445bf..27c69a23 100644 Binary files a/SdOut/atmosphere/1.2.4_loader_1996.8.kip and b/SdOut/atmosphere/1.2.5_loader_1795.2.kip differ diff --git a/SdOut/atmosphere/1.2.4_loader_1894.4.kip b/SdOut/atmosphere/1.2.5_loader_1862.4.kip similarity index 52% rename from SdOut/atmosphere/1.2.4_loader_1894.4.kip rename to SdOut/atmosphere/1.2.5_loader_1862.4.kip index 769f1b2c..dbfe5e35 100644 Binary files a/SdOut/atmosphere/1.2.4_loader_1894.4.kip and b/SdOut/atmosphere/1.2.5_loader_1862.4.kip differ diff --git a/SdOut/atmosphere/1.2.4_loader_1932.8.kip b/SdOut/atmosphere/1.2.5_loader_1996.8.kip similarity index 52% rename from SdOut/atmosphere/1.2.4_loader_1932.8.kip rename to SdOut/atmosphere/1.2.5_loader_1996.8.kip index c3cdd672..854e11c9 100644 Binary files a/SdOut/atmosphere/1.2.4_loader_1932.8.kip and b/SdOut/atmosphere/1.2.5_loader_1996.8.kip differ diff --git a/SdOut/atmosphere/1.2.4_loader_1862.4.kip b/SdOut/atmosphere/1.2.5_loader_2064.0.kip similarity index 63% rename from SdOut/atmosphere/1.2.4_loader_1862.4.kip rename to SdOut/atmosphere/1.2.5_loader_2064.0.kip index 6396ef1a..9ec399b8 100644 Binary files a/SdOut/atmosphere/1.2.4_loader_1862.4.kip and b/SdOut/atmosphere/1.2.5_loader_2064.0.kip differ diff --git a/Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp b/Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp index c803616b..41d1aa57 100644 --- a/Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp +++ b/Source/Atmosphere/stratosphere/loader/source/ldr_oc_patch.hpp @@ -2,12 +2,12 @@ constexpr ro::ModuleId PcvModuleId[] = { ParseModuleId("91D61D59D7002378E35584FC0B38C7693A3ABAB5"), //11.0.0 ParseModuleId("C503E96550F302E121873136B814A529863D949B"), //12.x - ParseModuleId("2058C97C551571506656AA04EC85E2B1B01B155C"), //13.0.0-13.1.0 + ParseModuleId("2058C97C551571506656AA04EC85E2B1B01B155C"), //13.0.0-13.2.0 }; constexpr ro::ModuleId PtmModuleId[] = { ParseModuleId("A79706954C6C45568B0FFE610627E2E89D8FB0D4"), //12.x - ParseModuleId("2CA78D4066C1C11317CC2705EBADA9A51D3AC981"), //13.0.0-13.1.0 + ParseModuleId("2CA78D4066C1C11317CC2705EBADA9A51D3AC981"), //13.0.0-13.2.0 }; namespace pcv { @@ -253,6 +253,16 @@ namespace pcv { { 0xE1810, 0xE6530, 0xE6580, 0xE6AB0, 0xE6AB8, 0xE6AC0, 0xE6AC8, 0xE6AD0, 0xE6AD8, 0xE6AE0, 0xE6AE8, 0xE6AF0, 0xE6AF8, 0xF0650, 0xFDDF0, 0x1012C8, 0x10D0D4, 0x119154, 0x11C62C, 0x11F890, 0x122AF4, 0x125D58, 0x128FBC, 0x12C220, 0x12F484, 0x1326E8, 0x13594C, 0x138BB0, 0x13BE14, 0x13F078, }, { 0xE1860, 0xE6580, 0xE65D0, 0xE6B00, 0xE6B08, 0xE6B10, 0xE6B18, 0xE6B20, 0xE6B28, 0xE6B30, 0xE6B38, 0xE6B40, 0xE6B48, 0xF06A0, 0xFDE40, 0x101318, 0x10D124, 0x1191A4, 0x11C67C, 0x11F8E0, 0x122B44, 0x125DA8, 0x12900C, 0x12C270, 0x12F4D4, 0x132738, 0x13599C, 0x138C00, 0x13BE64, 0x13F0C8, }, }; + + // Mariko mtc tables starting from rev, see mtc_timing_table.hpp for parameters. + // All mariko mtc tables will be patched to simplify the procedure. + constexpr u32 MtcTable_1600[13] = { + 0x1012D8, 0x11C63C, 0x11F8A0, 0x122B04, 0x125D68, 0x128FCC, 0x12C230, 0x12F494, 0x1326F8, 0x13595C, 0x138BC0, 0x13BE24, 0x13F088 + }; + + constexpr u32 MtcTableOffset = 0x10CC; + + #include "mtc_timing_table.hpp" } namespace ptm { diff --git a/Source/Atmosphere/stratosphere/loader/source/ldr_patcher.cpp b/Source/Atmosphere/stratosphere/loader/source/ldr_patcher.cpp index 191b2568..c341698c 100644 --- a/Source/Atmosphere/stratosphere/loader/source/ldr_patcher.cpp +++ b/Source/Atmosphere/stratosphere/loader/source/ldr_patcher.cpp @@ -15,6 +15,7 @@ */ #include #include "ldr_patcher.hpp" +//#define ADJUST_TIMING namespace ams::ldr { @@ -182,6 +183,108 @@ namespace ams::ldr { for (u32 j = 0; j < sizeof(pcv::EmcFreqOffsets[i])/sizeof(u32); j++) { std::memcpy(reinterpret_cast(mapped_nso + pcv::EmcFreqOffsets[i][j]), &EmcClock, sizeof(EmcClock)); } + + #ifdef ADJUST_TIMING + /* Adjust timing parameters in 1600MHz mtc tables */ + u32 param_1331, param_1600; + #define ADJUST_PROPORTIONAL(TARGET_TABLE, REF_TABLE, PARAM) \ + param_1331 = REF_TABLE->PARAM; \ + param_1600 = TARGET_TABLE->PARAM; \ + TARGET_TABLE->PARAM = param_1331 + ((GetEmcClock()-1331200)*(param_1600-param_1331))/(1600000-1331200); + + #define ADJUST_PROP_WITHIN_ALL_REG(TARGET_TABLE, REF_TABLE, PARAM) \ + ADJUST_PROPORTIONAL(TARGET_TABLE, REF_TABLE, burst_regs.PARAM) \ + ADJUST_PROPORTIONAL(TARGET_TABLE, REF_TABLE, shadow_regs_ca_train.PARAM) \ + ADJUST_PROPORTIONAL(TARGET_TABLE, REF_TABLE, shadow_regs_rdwr_train.PARAM) + + /* Calculate DIVM and DIVN */ + /* Assume oscillator (PLLMB_IN) is 38.4 MHz */ + /* PLLMB_OUT = PLLMB_IN / DIVM * DIVN */ + u32 divn = GetEmcClock() / 38400; + u32 divm = 1; + if (GetEmcClock() - divn * 38400 >= 38400 / 2) { + divm = 2; + divn = divn * 2 + 1; + } + + if (i == 2) { + for (u32 j = 0; j < sizeof(pcv::MtcTable_1600)/sizeof(u32); j++) { + pcv::MarikoMtcTable* mtc_table_1600 = reinterpret_cast(mapped_nso + pcv::MtcTable_1600[j]); + pcv::MarikoMtcTable* mtc_table_1331 = reinterpret_cast(mapped_nso + pcv::MtcTable_1600[j] - pcv::MtcTableOffset); + + /* Normal and reasonable values */ + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rc); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rfc); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rfcpb); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_ras); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rp); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_w2r); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_r2p); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_w2p); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_trtm); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_twtm); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tratm); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_twatm); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rd_rcd); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_wr_rcd); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rrd); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_wdv); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_wsv); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_wev); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_wdv_mask); //? + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_quse); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_quse_width); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_einput); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_einput_duration); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_qsafe); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rdv); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rdv_mask); //? + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rdv_early); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rdv_early_mask); //? + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_refresh); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_pre_refresh_req_cnt); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_pdex2wr); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_pdex2rd); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_act2pden); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_rw2pden); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_cke2pden); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_pdex2mrr); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_txsr); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_txsrdll); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tcke); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tckesr); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tpd); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tfaw); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_trpab); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tclkstop); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_trefbw); + //ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_pmacro_ddll_long_cmd_4); //? + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_pmacro_dll_cfg_2); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_qpop); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tr_rdv); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tr_qpop); + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tr_rdv_mask); //? + ADJUST_PROP_WITHIN_ALL_REG(mtc_table_1600, mtc_table_1331, emc_tr_qsafe); + + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, dram_timings.rl); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, burst_mc_regs.mc_emem_arb_timing_rcd); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, burst_mc_regs.mc_emem_arb_timing_rp); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, burst_mc_regs.mc_emem_arb_timing_rc); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, burst_mc_regs.mc_emem_arb_timing_ras); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, burst_mc_regs.mc_emem_arb_timing_faw); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, burst_mc_regs.mc_emem_arb_timing_wap2pre); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, burst_mc_regs.mc_emem_arb_timing_r2w); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, burst_mc_regs.mc_emem_arb_timing_w2r); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, burst_mc_regs.mc_emem_arb_timing_rfcpb); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, la_scale_regs.mc_mll_mpcorer_ptsa_rate); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, min_mrs_wait); + ADJUST_PROPORTIONAL(mtc_table_1600, mtc_table_1331, latency); + + mtc_table_1600->pllmb_divm = divm; + mtc_table_1600->pllmb_divn = divn; + } + } + #endif } } diff --git a/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp b/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp new file mode 100644 index 00000000..e5fbff0e --- /dev/null +++ b/Source/Atmosphere/stratosphere/loader/source/mtc_timing_table.hpp @@ -0,0 +1,1115 @@ +/* + * Copyright (c) Atmosphère-NX + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + * from GCC preprocessor output + */ + +struct MarikoMtcTable { + uint32_t rev; + char dvfs_ver[60]; + uint32_t rate_khz; + uint32_t min_volt; + uint32_t gpu_min_volt; + char clock_src[32]; + uint32_t clk_src_emc; + uint32_t pll_en_ssc; + uint32_t needs_training; + uint32_t training_pattern; + uint32_t trained; + + uint32_t periodic_training; + uint32_t trained_dram_clktree_c0d0u0; + uint32_t trained_dram_clktree_c0d0u1; + uint32_t trained_dram_clktree_c0d1u0; + uint32_t trained_dram_clktree_c0d1u1; + uint32_t trained_dram_clktree_c1d0u0; + uint32_t trained_dram_clktree_c1d0u1; + uint32_t trained_dram_clktree_c1d1u0; + uint32_t trained_dram_clktree_c1d1u1; + uint32_t current_dram_clktree_c0d0u0; + uint32_t current_dram_clktree_c0d0u1; + uint32_t current_dram_clktree_c0d1u0; + uint32_t current_dram_clktree_c0d1u1; + uint32_t current_dram_clktree_c1d0u0; + uint32_t current_dram_clktree_c1d0u1; + uint32_t current_dram_clktree_c1d1u0; + uint32_t current_dram_clktree_c1d1u1; + uint32_t emc_fbio_cfg7; + uint32_t run_clocks; + uint32_t tree_margin; + + uint32_t num_burst; + uint32_t num_burst_per_ch; + uint32_t num_trim; + uint32_t num_trim_per_ch; + uint32_t num_mc_regs; + uint32_t num_up_down; + uint32_t vref_num; + uint32_t training_mod_num; + uint32_t dram_timing_num; + + uint32_t ptfv_dqsosc_movavg_c0d0u0; + uint32_t ptfv_dqsosc_movavg_c0d0u1; + uint32_t ptfv_dqsosc_movavg_c0d1u0; + uint32_t ptfv_dqsosc_movavg_c0d1u1; + uint32_t ptfv_dqsosc_movavg_c1d0u0; + uint32_t ptfv_dqsosc_movavg_c1d0u1; + uint32_t ptfv_dqsosc_movavg_c1d1u0; + uint32_t ptfv_dqsosc_movavg_c1d1u1; + uint32_t ptfv_write_samples; + uint32_t ptfv_dvfs_samples; + uint32_t ptfv_movavg_weight; + uint32_t ptfv_config_ctrl; + + struct { + uint32_t emc_rc; + uint32_t emc_rfc; + uint32_t emc_rfcpb; + uint32_t emc_refctrl2; + uint32_t emc_rfc_slr; + uint32_t emc_ras; + uint32_t emc_rp; + uint32_t emc_r2w; + uint32_t emc_w2r; + uint32_t emc_r2p; + uint32_t emc_w2p; + uint32_t emc_r2r; + uint32_t emc_tppd; + uint32_t emc_trtm; + uint32_t emc_twtm; + uint32_t emc_tratm; + uint32_t emc_twatm; + uint32_t emc_tr2ref; + uint32_t emc_ccdmw; + uint32_t emc_rd_rcd; + uint32_t emc_wr_rcd; + uint32_t emc_rrd; + uint32_t emc_rext; + uint32_t emc_wext; + uint32_t emc_wdv_chk; + uint32_t emc_wdv; + uint32_t emc_wsv; + uint32_t emc_wev; + uint32_t emc_wdv_mask; + uint32_t emc_ws_duration; + uint32_t emc_we_duration; + uint32_t emc_quse; + uint32_t emc_quse_width; + uint32_t emc_ibdly; + uint32_t emc_obdly; + uint32_t emc_einput; + uint32_t emc_mrw6; + uint32_t emc_einput_duration; + uint32_t emc_puterm_extra; + uint32_t emc_puterm_width; + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; + uint32_t emc_refresh; + uint32_t emc_burst_refresh_num; + uint32_t emc_pre_refresh_req_cnt; + uint32_t emc_pdex2wr; + uint32_t emc_pdex2rd; + uint32_t emc_pchg2pden; + uint32_t emc_act2pden; + uint32_t emc_ar2pden; + uint32_t emc_rw2pden; + uint32_t emc_cke2pden; + uint32_t emc_pdex2cke; + uint32_t emc_pdex2mrr; + uint32_t emc_txsr; + uint32_t emc_txsrdll; + uint32_t emc_tcke; + uint32_t emc_tckesr; + uint32_t emc_tpd; + uint32_t emc_tfaw; + uint32_t emc_trpab; + uint32_t emc_tclkstable; + uint32_t emc_tclkstop; + uint32_t emc_mrw7; + uint32_t emc_trefbw; + uint32_t emc_odt_write; + uint32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg7; + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_period; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe_1; + uint32_t emc_cfg_pipe_2; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + uint32_t emc_mrw8; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3; + uint32_t emc_txdsrvttgen; + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_fbio_spare; + uint32_t emc_zcal_interval; + uint32_t emc_zcal_wait_cnt; + uint32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt2; + uint32_t emc_auto_cal_channel; + uint32_t emc_pmacro_dll_cfg_0; + uint32_t emc_pmacro_dll_cfg_1; + uint32_t emc_pmacro_dll_cfg_2; + uint32_t emc_pmacro_autocal_cfg_common; + uint32_t emc_pmacro_zctrl; + uint32_t emc_cfg; + uint32_t emc_cfg_pipe; + uint32_t emc_dyn_self_ref_control; + uint32_t emc_qpop; + uint32_t emc_dqs_brlshft_0; + uint32_t emc_dqs_brlshft_1; + uint32_t emc_cmd_brlshft_2; + uint32_t emc_cmd_brlshft_3; + uint32_t emc_pmacro_pad_cfg_ctrl; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_vttgen_ctrl_0; + uint32_t emc_pmacro_vttgen_ctrl_1; + uint32_t emc_pmacro_vttgen_ctrl_2; + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl_0; + uint32_t emc_cfg_3; + uint32_t emc_pmacro_tx_pwrd_0; + uint32_t emc_pmacro_tx_pwrd_1; + uint32_t emc_pmacro_tx_pwrd_2; + uint32_t emc_pmacro_tx_pwrd_3; + uint32_t emc_pmacro_tx_pwrd_4; + uint32_t emc_pmacro_tx_pwrd_5; + uint32_t emc_config_sample_delay; + uint32_t emc_pmacro_tx_sel_clk_src_0; + uint32_t emc_pmacro_tx_sel_clk_src_1; + uint32_t emc_pmacro_tx_sel_clk_src_2; + uint32_t emc_pmacro_tx_sel_clk_src_3; + uint32_t emc_pmacro_tx_sel_clk_src_4; + uint32_t emc_pmacro_tx_sel_clk_src_5; + uint32_t emc_pmacro_ddll_bypass; + uint32_t emc_pmacro_ddll_pwrd_0; + uint32_t emc_pmacro_ddll_pwrd_1; + uint32_t emc_pmacro_ddll_pwrd_2; + uint32_t emc_pmacro_cmd_ctrl_0; + uint32_t emc_pmacro_cmd_ctrl_1; + uint32_t emc_pmacro_cmd_ctrl_2; + uint32_t emc_pmacro_data_pi_ctrl; + uint32_t emc_pmacro_cmd_pi_ctrl; + uint32_t emc_tr_timing_0; + uint32_t emc_tr_dvfs; + uint32_t emc_tr_ctrl_1; + uint32_t emc_tr_rdv; + uint32_t emc_tr_qpop; + uint32_t emc_tr_rdv_mask; + uint32_t emc_mrw14; + uint32_t emc_tr_qsafe; + uint32_t emc_tr_qrst; + uint32_t emc_training_ctrl; + uint32_t emc_training_settle; + uint32_t emc_training_vref_settle; + uint32_t emc_training_ca_fine_ctrl; + uint32_t emc_training_ca_ctrl_misc; + uint32_t emc_training_ca_ctrl_misc1; + uint32_t emc_training_ca_vref_ctrl; + uint32_t emc_training_quse_cors_ctrl; + uint32_t emc_training_quse_fine_ctrl; + uint32_t emc_training_quse_ctrl_misc; + uint32_t emc_training_quse_vref_ctrl; + uint32_t emc_training_read_fine_ctrl; + uint32_t emc_training_read_ctrl_misc; + uint32_t emc_training_read_vref_ctrl; + uint32_t emc_training_write_fine_ctrl; + uint32_t emc_training_write_ctrl_misc; + uint32_t emc_training_write_vref_ctrl; + uint32_t emc_training_mpc; + uint32_t emc_mrw15; + } + burst_regs; + + struct { + uint32_t emc0_mrw10; + uint32_t emc1_mrw10; + uint32_t emc0_mrw11; + uint32_t emc1_mrw11; + uint32_t emc0_mrw12; + uint32_t emc1_mrw12; + uint32_t emc0_mrw13; + uint32_t emc1_mrw13; + } + burst_perch_regs; + + struct { + uint32_t emc_rc; + uint32_t emc_rfc; + uint32_t emc_rfcpb; + uint32_t emc_refctrl2; + uint32_t emc_rfc_slr; + uint32_t emc_ras; + uint32_t emc_rp; + uint32_t emc_r2w; + uint32_t emc_w2r; + uint32_t emc_r2p; + uint32_t emc_w2p; + uint32_t emc_r2r; + uint32_t emc_tppd; + uint32_t emc_trtm; + uint32_t emc_twtm; + uint32_t emc_tratm; + uint32_t emc_twatm; + uint32_t emc_tr2ref; + uint32_t emc_ccdmw; + uint32_t emc_rd_rcd; + uint32_t emc_wr_rcd; + uint32_t emc_rrd; + uint32_t emc_rext; + uint32_t emc_wext; + uint32_t emc_wdv_chk; + uint32_t emc_wdv; + uint32_t emc_wsv; + uint32_t emc_wev; + uint32_t emc_wdv_mask; + uint32_t emc_ws_duration; + uint32_t emc_we_duration; + uint32_t emc_quse; + uint32_t emc_quse_width; + uint32_t emc_ibdly; + uint32_t emc_obdly; + uint32_t emc_einput; + uint32_t emc_mrw6; + uint32_t emc_einput_duration; + uint32_t emc_puterm_extra; + uint32_t emc_puterm_width; + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; + uint32_t emc_refresh; + uint32_t emc_burst_refresh_num; + uint32_t emc_pre_refresh_req_cnt; + uint32_t emc_pdex2wr; + uint32_t emc_pdex2rd; + uint32_t emc_pchg2pden; + uint32_t emc_act2pden; + uint32_t emc_ar2pden; + uint32_t emc_rw2pden; + uint32_t emc_cke2pden; + uint32_t emc_pdex2cke; + uint32_t emc_pdex2mrr; + uint32_t emc_txsr; + uint32_t emc_txsrdll; + uint32_t emc_tcke; + uint32_t emc_tckesr; + uint32_t emc_tpd; + uint32_t emc_tfaw; + uint32_t emc_trpab; + uint32_t emc_tclkstable; + uint32_t emc_tclkstop; + uint32_t emc_mrw7; + uint32_t emc_trefbw; + uint32_t emc_odt_write; + uint32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg7; + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_period; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe_1; + uint32_t emc_cfg_pipe_2; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + uint32_t emc_mrw8; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3; + uint32_t emc_txdsrvttgen; + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_fbio_spare; + uint32_t emc_zcal_interval; + uint32_t emc_zcal_wait_cnt; + uint32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt2; + uint32_t emc_auto_cal_channel; + uint32_t emc_pmacro_dll_cfg_0; + uint32_t emc_pmacro_dll_cfg_1; + uint32_t emc_pmacro_dll_cfg_2; + uint32_t emc_pmacro_autocal_cfg_common; + uint32_t emc_pmacro_zctrl; + uint32_t emc_cfg; + uint32_t emc_cfg_pipe; + uint32_t emc_dyn_self_ref_control; + uint32_t emc_qpop; + uint32_t emc_dqs_brlshft_0; + uint32_t emc_dqs_brlshft_1; + uint32_t emc_cmd_brlshft_2; + uint32_t emc_cmd_brlshft_3; + uint32_t emc_pmacro_pad_cfg_ctrl; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_vttgen_ctrl_0; + uint32_t emc_pmacro_vttgen_ctrl_1; + uint32_t emc_pmacro_vttgen_ctrl_2; + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl_0; + uint32_t emc_cfg_3; + uint32_t emc_pmacro_tx_pwrd_0; + uint32_t emc_pmacro_tx_pwrd_1; + uint32_t emc_pmacro_tx_pwrd_2; + uint32_t emc_pmacro_tx_pwrd_3; + uint32_t emc_pmacro_tx_pwrd_4; + uint32_t emc_pmacro_tx_pwrd_5; + uint32_t emc_config_sample_delay; + uint32_t emc_pmacro_tx_sel_clk_src_0; + uint32_t emc_pmacro_tx_sel_clk_src_1; + uint32_t emc_pmacro_tx_sel_clk_src_2; + uint32_t emc_pmacro_tx_sel_clk_src_3; + uint32_t emc_pmacro_tx_sel_clk_src_4; + uint32_t emc_pmacro_tx_sel_clk_src_5; + uint32_t emc_pmacro_ddll_bypass; + uint32_t emc_pmacro_ddll_pwrd_0; + uint32_t emc_pmacro_ddll_pwrd_1; + uint32_t emc_pmacro_ddll_pwrd_2; + uint32_t emc_pmacro_cmd_ctrl_0; + uint32_t emc_pmacro_cmd_ctrl_1; + uint32_t emc_pmacro_cmd_ctrl_2; + uint32_t emc_pmacro_data_pi_ctrl; + uint32_t emc_pmacro_cmd_pi_ctrl; + uint32_t emc_tr_timing_0; + uint32_t emc_tr_dvfs; + uint32_t emc_tr_ctrl_1; + uint32_t emc_tr_rdv; + uint32_t emc_tr_qpop; + uint32_t emc_tr_rdv_mask; + uint32_t emc_mrw14; + uint32_t emc_tr_qsafe; + uint32_t emc_tr_qrst; + uint32_t emc_training_ctrl; + uint32_t emc_training_settle; + uint32_t emc_training_vref_settle; + uint32_t emc_training_ca_fine_ctrl; + uint32_t emc_training_ca_ctrl_misc; + uint32_t emc_training_ca_ctrl_misc1; + uint32_t emc_training_ca_vref_ctrl; + uint32_t emc_training_quse_cors_ctrl; + uint32_t emc_training_quse_fine_ctrl; + uint32_t emc_training_quse_ctrl_misc; + uint32_t emc_training_quse_vref_ctrl; + uint32_t emc_training_read_fine_ctrl; + uint32_t emc_training_read_ctrl_misc; + uint32_t emc_training_read_vref_ctrl; + uint32_t emc_training_write_fine_ctrl; + uint32_t emc_training_write_ctrl_misc; + uint32_t emc_training_write_vref_ctrl; + uint32_t emc_training_mpc; + uint32_t emc_mrw15; + } + shadow_regs_ca_train; + + struct { + uint32_t emc_rc; + uint32_t emc_rfc; + uint32_t emc_rfcpb; + uint32_t emc_refctrl2; + uint32_t emc_rfc_slr; + uint32_t emc_ras; + uint32_t emc_rp; + uint32_t emc_r2w; + uint32_t emc_w2r; + uint32_t emc_r2p; + uint32_t emc_w2p; + uint32_t emc_r2r; + uint32_t emc_tppd; + uint32_t emc_trtm; + uint32_t emc_twtm; + uint32_t emc_tratm; + uint32_t emc_twatm; + uint32_t emc_tr2ref; + uint32_t emc_ccdmw; + uint32_t emc_rd_rcd; + uint32_t emc_wr_rcd; + uint32_t emc_rrd; + uint32_t emc_rext; + uint32_t emc_wext; + uint32_t emc_wdv_chk; + uint32_t emc_wdv; + uint32_t emc_wsv; + uint32_t emc_wev; + uint32_t emc_wdv_mask; + uint32_t emc_ws_duration; + uint32_t emc_we_duration; + uint32_t emc_quse; + uint32_t emc_quse_width; + uint32_t emc_ibdly; + uint32_t emc_obdly; + uint32_t emc_einput; + uint32_t emc_mrw6; + uint32_t emc_einput_duration; + uint32_t emc_puterm_extra; + uint32_t emc_puterm_width; + uint32_t emc_qrst; + uint32_t emc_qsafe; + uint32_t emc_rdv; + uint32_t emc_rdv_mask; + uint32_t emc_rdv_early; + uint32_t emc_rdv_early_mask; + uint32_t emc_refresh; + uint32_t emc_burst_refresh_num; + uint32_t emc_pre_refresh_req_cnt; + uint32_t emc_pdex2wr; + uint32_t emc_pdex2rd; + uint32_t emc_pchg2pden; + uint32_t emc_act2pden; + uint32_t emc_ar2pden; + uint32_t emc_rw2pden; + uint32_t emc_cke2pden; + uint32_t emc_pdex2cke; + uint32_t emc_pdex2mrr; + uint32_t emc_txsr; + uint32_t emc_txsrdll; + uint32_t emc_tcke; + uint32_t emc_tckesr; + uint32_t emc_tpd; + uint32_t emc_tfaw; + uint32_t emc_trpab; + uint32_t emc_tclkstable; + uint32_t emc_tclkstop; + uint32_t emc_mrw7; + uint32_t emc_trefbw; + uint32_t emc_odt_write; + uint32_t emc_fbio_cfg5; + uint32_t emc_fbio_cfg7; + uint32_t emc_cfg_dig_dll; + uint32_t emc_cfg_dig_dll_period; + uint32_t emc_pmacro_ib_rxrt; + uint32_t emc_cfg_pipe_1; + uint32_t emc_cfg_pipe_2; + uint32_t emc_pmacro_quse_ddll_rank0_4; + uint32_t emc_pmacro_quse_ddll_rank0_5; + uint32_t emc_pmacro_quse_ddll_rank1_4; + uint32_t emc_pmacro_quse_ddll_rank1_5; + uint32_t emc_mrw8; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_4; + uint32_t emc_pmacro_ob_ddll_long_dqs_rank1_5; + uint32_t emc_pmacro_ddll_long_cmd_0; + uint32_t emc_pmacro_ddll_long_cmd_1; + uint32_t emc_pmacro_ddll_long_cmd_2; + uint32_t emc_pmacro_ddll_long_cmd_3; + uint32_t emc_pmacro_ddll_long_cmd_4; + uint32_t emc_pmacro_ddll_short_cmd_0; + uint32_t emc_pmacro_ddll_short_cmd_1; + uint32_t emc_pmacro_ddll_short_cmd_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3; + uint32_t emc_txdsrvttgen; + uint32_t emc_fdpd_ctrl_dq; + uint32_t emc_fdpd_ctrl_cmd; + uint32_t emc_fbio_spare; + uint32_t emc_zcal_interval; + uint32_t emc_zcal_wait_cnt; + uint32_t emc_mrs_wait_cnt; + uint32_t emc_mrs_wait_cnt2; + uint32_t emc_auto_cal_channel; + uint32_t emc_pmacro_dll_cfg_0; + uint32_t emc_pmacro_dll_cfg_1; + uint32_t emc_pmacro_dll_cfg_2; + uint32_t emc_pmacro_autocal_cfg_common; + uint32_t emc_pmacro_zctrl; + uint32_t emc_cfg; + uint32_t emc_cfg_pipe; + uint32_t emc_dyn_self_ref_control; + uint32_t emc_qpop; + uint32_t emc_dqs_brlshft_0; + uint32_t emc_dqs_brlshft_1; + uint32_t emc_cmd_brlshft_2; + uint32_t emc_cmd_brlshft_3; + uint32_t emc_pmacro_pad_cfg_ctrl; + uint32_t emc_pmacro_data_pad_rx_ctrl; + uint32_t emc_pmacro_cmd_pad_rx_ctrl; + uint32_t emc_pmacro_data_rx_term_mode; + uint32_t emc_pmacro_cmd_rx_term_mode; + uint32_t emc_pmacro_cmd_pad_tx_ctrl; + uint32_t emc_pmacro_data_pad_tx_ctrl; + uint32_t emc_pmacro_vttgen_ctrl_0; + uint32_t emc_pmacro_vttgen_ctrl_1; + uint32_t emc_pmacro_vttgen_ctrl_2; + uint32_t emc_pmacro_brick_ctrl_rfu1; + uint32_t emc_pmacro_cmd_brick_ctrl_fdpd; + uint32_t emc_pmacro_brick_ctrl_rfu2; + uint32_t emc_pmacro_data_brick_ctrl_fdpd; + uint32_t emc_pmacro_bg_bias_ctrl_0; + uint32_t emc_cfg_3; + uint32_t emc_pmacro_tx_pwrd_0; + uint32_t emc_pmacro_tx_pwrd_1; + uint32_t emc_pmacro_tx_pwrd_2; + uint32_t emc_pmacro_tx_pwrd_3; + uint32_t emc_pmacro_tx_pwrd_4; + uint32_t emc_pmacro_tx_pwrd_5; + uint32_t emc_config_sample_delay; + uint32_t emc_pmacro_tx_sel_clk_src_0; + uint32_t emc_pmacro_tx_sel_clk_src_1; + uint32_t emc_pmacro_tx_sel_clk_src_2; + uint32_t emc_pmacro_tx_sel_clk_src_3; + uint32_t emc_pmacro_tx_sel_clk_src_4; + uint32_t emc_pmacro_tx_sel_clk_src_5; + uint32_t emc_pmacro_ddll_bypass; + uint32_t emc_pmacro_ddll_pwrd_0; + uint32_t emc_pmacro_ddll_pwrd_1; + uint32_t emc_pmacro_ddll_pwrd_2; + uint32_t emc_pmacro_cmd_ctrl_0; + uint32_t emc_pmacro_cmd_ctrl_1; + uint32_t emc_pmacro_cmd_ctrl_2; + uint32_t emc_pmacro_data_pi_ctrl; + uint32_t emc_pmacro_cmd_pi_ctrl; + uint32_t emc_tr_timing_0; + uint32_t emc_tr_dvfs; + uint32_t emc_tr_ctrl_1; + uint32_t emc_tr_rdv; + uint32_t emc_tr_qpop; + uint32_t emc_tr_rdv_mask; + uint32_t emc_mrw14; + uint32_t emc_tr_qsafe; + uint32_t emc_tr_qrst; + uint32_t emc_training_ctrl; + uint32_t emc_training_settle; + uint32_t emc_training_vref_settle; + uint32_t emc_training_ca_fine_ctrl; + uint32_t emc_training_ca_ctrl_misc; + uint32_t emc_training_ca_ctrl_misc1; + uint32_t emc_training_ca_vref_ctrl; + uint32_t emc_training_quse_cors_ctrl; + uint32_t emc_training_quse_fine_ctrl; + uint32_t emc_training_quse_ctrl_misc; + uint32_t emc_training_quse_vref_ctrl; + uint32_t emc_training_read_fine_ctrl; + uint32_t emc_training_read_ctrl_misc; + uint32_t emc_training_read_vref_ctrl; + uint32_t emc_training_write_fine_ctrl; + uint32_t emc_training_write_ctrl_misc; + uint32_t emc_training_write_vref_ctrl; + uint32_t emc_training_mpc; + uint32_t emc_mrw15; + } + shadow_regs_rdwr_train; + + struct { + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank0_3; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_0; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_1; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_2; + uint32_t emc_pmacro_ib_ddll_long_dqs_rank1_3; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte0_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte1_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte2_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte3_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte4_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte5_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte6_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank0_byte7_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte0_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte1_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte2_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte3_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte4_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte5_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte6_2; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_0; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_1; + uint32_t emc_pmacro_ib_ddll_short_dq_rank1_byte7_2; + uint32_t emc_pmacro_ib_vref_dqs_0; + uint32_t emc_pmacro_ib_vref_dqs_1; + uint32_t emc_pmacro_ib_vref_dq_0; + uint32_t emc_pmacro_ib_vref_dq_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_3; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_4; + uint32_t emc_pmacro_ob_ddll_long_dq_rank0_5; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_0; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_1; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_2; + uint32_t emc_pmacro_ob_ddll_long_dq_rank1_3; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte4_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte5_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte6_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_byte7_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte0_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte1_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte2_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte3_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte4_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte5_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte6_2; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_0; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_1; + uint32_t emc_pmacro_ob_ddll_short_dq_rank1_byte7_2; + uint32_t emc_pmacro_quse_ddll_rank0_0; + uint32_t emc_pmacro_quse_ddll_rank0_1; + uint32_t emc_pmacro_quse_ddll_rank0_2; + uint32_t emc_pmacro_quse_ddll_rank0_3; + uint32_t emc_pmacro_quse_ddll_rank1_0; + uint32_t emc_pmacro_quse_ddll_rank1_1; + uint32_t emc_pmacro_quse_ddll_rank1_2; + uint32_t emc_pmacro_quse_ddll_rank1_3; + } + trim_regs; + + struct { + uint32_t emc0_cmd_brlshft_0; + uint32_t emc1_cmd_brlshft_1; + uint32_t emc0_data_brlshft_0; + uint32_t emc1_data_brlshft_0; + uint32_t emc0_data_brlshft_1; + uint32_t emc1_data_brlshft_1; + uint32_t emc0_quse_brlshft_0; + uint32_t emc1_quse_brlshft_1; + uint32_t emc0_quse_brlshft_2; + uint32_t emc1_quse_brlshft_3; + } + trim_perch_regs; + + struct { + uint32_t emc0_training_opt_dqs_ib_vref_rank0; + uint32_t emc1_training_opt_dqs_ib_vref_rank0; + uint32_t emc0_training_opt_dqs_ib_vref_rank1; + uint32_t emc1_training_opt_dqs_ib_vref_rank1; + } + vref_perch_regs; + + struct { + uint32_t t_rp; + uint32_t t_fc_lpddr4; + uint32_t t_rfc; + uint32_t t_pdex; + uint32_t rl; + } + dram_timings; + + uint32_t zq_op_cc_long_zcal; + uint32_t zq_op_cc_short_zcal; + uint32_t zcal_wait_time_ps_cc_long_zcal; + uint32_t zcal_wait_time_ps_cc_short_zcal; + uint32_t tZQCAL_lpddr4; + uint32_t zqcal_before_cc_cutoff; + uint32_t opt_cc_short_zcal; + uint32_t opt_short_zcal; + uint32_t opt_do_sw_qrst; + uint32_t save_restore_clkstop_pd; + uint32_t opt_E90; + uint32_t cya_allow_ref_cc; + uint32_t ref_b4_sref_en; + uint32_t cya_issue_pc_ref; + + struct { + uint32_t emc0_training_rw_offset_ib_byte0; + uint32_t emc1_training_rw_offset_ib_byte0; + uint32_t emc0_training_rw_offset_ib_byte1; + uint32_t emc1_training_rw_offset_ib_byte1; + uint32_t emc0_training_rw_offset_ib_byte2; + uint32_t emc1_training_rw_offset_ib_byte2; + uint32_t emc0_training_rw_offset_ib_byte3; + uint32_t emc1_training_rw_offset_ib_byte3; + uint32_t emc0_training_rw_offset_ib_misc; + uint32_t emc1_training_rw_offset_ib_misc; + uint32_t emc0_training_rw_offset_ob_byte0; + uint32_t emc1_training_rw_offset_ob_byte0; + uint32_t emc0_training_rw_offset_ob_byte1; + uint32_t emc1_training_rw_offset_ob_byte1; + uint32_t emc0_training_rw_offset_ob_byte2; + uint32_t emc1_training_rw_offset_ob_byte2; + uint32_t emc0_training_rw_offset_ob_byte3; + uint32_t emc1_training_rw_offset_ob_byte3; + uint32_t emc0_training_rw_offset_ob_misc; + uint32_t emc1_training_rw_offset_ob_misc; + } + training_mod_regs; + + uint32_t save_restore_mod_regs[12]; + + struct { + uint32_t mc_emem_arb_cfg; + uint32_t mc_emem_arb_outstanding_req; + uint32_t mc_emem_arb_refpb_hp_ctrl; + uint32_t mc_emem_arb_refpb_bank_ctrl; + uint32_t mc_emem_arb_timing_rcd; + uint32_t mc_emem_arb_timing_rp; + uint32_t mc_emem_arb_timing_rc; + uint32_t mc_emem_arb_timing_ras; + uint32_t mc_emem_arb_timing_faw; + uint32_t mc_emem_arb_timing_rrd; + uint32_t mc_emem_arb_timing_rap2pre; + uint32_t mc_emem_arb_timing_wap2pre; + uint32_t mc_emem_arb_timing_r2r; + uint32_t mc_emem_arb_timing_w2w; + uint32_t mc_emem_arb_timing_r2w; + uint32_t mc_emem_arb_timing_ccdmw; + uint32_t mc_emem_arb_timing_w2r; + uint32_t mc_emem_arb_timing_rfcpb; + uint32_t mc_emem_arb_da_turns; + uint32_t mc_emem_arb_da_covers; + uint32_t mc_emem_arb_misc0; + uint32_t mc_emem_arb_misc1; + uint32_t mc_emem_arb_misc2; + uint32_t mc_emem_arb_ring1_throttle; + uint32_t mc_emem_arb_dhyst_ctrl; + uint32_t mc_emem_arb_dhyst_timeout_util_0; + uint32_t mc_emem_arb_dhyst_timeout_util_1; + uint32_t mc_emem_arb_dhyst_timeout_util_2; + uint32_t mc_emem_arb_dhyst_timeout_util_3; + uint32_t mc_emem_arb_dhyst_timeout_util_4; + uint32_t mc_emem_arb_dhyst_timeout_util_5; + uint32_t mc_emem_arb_dhyst_timeout_util_6; + uint32_t mc_emem_arb_dhyst_timeout_util_7; + } + burst_mc_regs; + + struct { + uint32_t mc_mll_mpcorer_ptsa_rate; + uint32_t mc_ftop_ptsa_rate; + uint32_t mc_ptsa_grant_decrement; + uint32_t mc_latency_allowance_xusb_0; + uint32_t mc_latency_allowance_xusb_1; + uint32_t mc_latency_allowance_tsec_0; + uint32_t mc_latency_allowance_sdmmca_0; + uint32_t mc_latency_allowance_sdmmcaa_0; + uint32_t mc_latency_allowance_sdmmc_0; + uint32_t mc_latency_allowance_sdmmcab_0; + uint32_t mc_latency_allowance_ppcs_0; + uint32_t mc_latency_allowance_ppcs_1; + uint32_t mc_latency_allowance_mpcore_0; + uint32_t mc_latency_allowance_hc_0; + uint32_t mc_latency_allowance_hc_1; + uint32_t mc_latency_allowance_avpc_0; + uint32_t mc_latency_allowance_gpu_0; + uint32_t mc_latency_allowance_gpu2_0; + uint32_t mc_latency_allowance_nvenc_0; + uint32_t mc_latency_allowance_nvdec_0; + uint32_t mc_latency_allowance_vic_0; + uint32_t mc_latency_allowance_vi2_0; + uint32_t mc_latency_allowance_isp2_0; + uint32_t mc_latency_allowance_isp2_1; + } + la_scale_regs; + + uint32_t unk_0; + uint32_t vtt_vdda_ctrl_0; + uint32_t src_clock_div; + uint32_t vtt_vdda_dual_channel; + uint32_t vtt_vdda_ctrl_1; + uint32_t vtt_vdda_ctrl_2; + uint32_t vtt_vdda_ctrl_3; + uint32_t vtt_vdda_ctrl_4; + uint32_t misc_cfg_0; + uint32_t misc_cfg_1; + uint32_t misc_cfg_2; + uint32_t unk_1; + uint32_t unk_2; + uint32_t pipe_clk_delay; + uint32_t clkchange_delay; + uint32_t pllm_ss_cfg; + uint32_t pllm_ss_ctrl1; + uint32_t pllm_ss_ctrl2; + uint32_t pllmb_ss_cfg; + uint32_t pllmb_ss_ctrl1; + uint32_t pllmb_ss_ctrl2; + uint32_t pllmb_divm; + uint32_t pllmb_divn; + uint32_t pllmb_divp; + uint32_t min_mrs_wait; + uint32_t ramp_wait; + uint32_t emc_mrw; + uint32_t emc_mrw2; + uint32_t emc_mrw3; + uint32_t emc_mrw4; + uint32_t emc_mrw9; + uint32_t emc_mrs; + uint32_t emc_emrs; + uint32_t emc_emrs2; + uint32_t emc_auto_cal_config; + uint32_t emc_auto_cal_config2; + uint32_t emc_auto_cal_config3; + uint32_t emc_auto_cal_config4; + uint32_t emc_auto_cal_config5; + uint32_t emc_auto_cal_config6; + uint32_t emc_auto_cal_config7; + uint32_t emc_auto_cal_config8; + uint32_t emc_cfg_2; + uint32_t emc_sel_dpd_ctrl; + uint32_t emc_fdpd_ctrl_cmd_no_ramp; + uint32_t emc_tr_ctrl_0; + uint32_t dll_clk_src; + uint32_t clk_out_enb_x_0_clk_enb_emc_dll; + uint32_t latency; + uint32_t pllm_misc1_0_pllm_clamp_ph90; +}; + +static_assert(sizeof(MarikoMtcTable) == 0x10CC); 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