diff --git a/Source/hoc-clk/sysmodule/src/soc/gm20b.cpp b/Source/hoc-clk/sysmodule/src/soc/gm20b.cpp
index e2a4e158..9bf3a7e5 100644
--- a/Source/hoc-clk/sysmodule/src/soc/gm20b.cpp
+++ b/Source/hoc-clk/sysmodule/src/soc/gm20b.cpp
@@ -27,12 +27,12 @@ namespace gm20b {
 #define GPU_SIZE 0x1000000
 #define GPU_TRIM_SYS_GPCPLL_CFG 0x00
 #define GPU_TRIM_SYS_GPCPLL_COEFF 0x04
-#define GPU_TRIM_SYS_GPCPLL_CFG2 0x08
-#define GPU_TRIM_SYS_GPCPLL_CFG3 0x0C
+#define GPU_TRIM_SYS_GPCPLL_CFG2 0x0C
+#define GPU_TRIM_SYS_GPCPLL_CFG3 0x18
 #define GPU_TRIM_SYS_GPCPLL_DVFS0 0x10
 #define GPU_TRIM_SYS_GPCPLL_DVFS1 0x14
 #define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x1C
-#define GPU_TRIM_SYS_SEL_VCO 0x2C
+#define GPU_TRIM_SYS_SEL_VCO 0x100
 #define GPU_TRIM_SYS_GPC2CLK_OUT 0x250
 
 #define GPC_BCAST(x) (*(volatile u32 *)(gpu_base + 0x132800ul + (x)))
@@ -47,7 +47,7 @@ namespace gm20b {
 #define GPCPLL_CFG_LOCK BIT(17)
 
 #define GPCPLL_CFG2_SDM_DIN_MASK 0x000000FFu
-#define GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x007FFF00u
+#define GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x0000FF00u
 #define GPCPLL_CFG2_STEPA_SHIFT 24
 #define GPCPLL_CFG2_STEPA_MASK 0xFF000000u
 
@@ -57,7 +57,7 @@ namespace gm20b {
 #define GPCPLL_DVFS0_DFS_COEFF_MASK 0x0000007Fu
 
 #define NDIV_SLOWDOWN_SLOWDOWN_USING_PLL BIT(22)
-#define NDIV_SLOWDOWN_EN_DYNRAMP BIT(23)
+#define NDIV_SLOWDOWN_EN_DYNRAMP BIT(31)
 
 #define DYNRAMP_DONE_SYNCED BIT(24)