diff --git a/Source/hoc-clk/sysmodule/src/soc/registers.h b/Source/hoc-clk/sysmodule/src/soc/registers.h index f6f11b06..8e2be21d 100644 --- a/Source/hoc-clk/sysmodule/src/soc/registers.h +++ b/Source/hoc-clk/sysmodule/src/soc/registers.h @@ -545,4 +545,3458 @@ #define PLLA1_BASE 0x6a4 #define PLLDP_BASE 0x590 -#define OSC_HZ 38400000ULL \ No newline at end of file +#define OSC_HZ 38400000ULL + +#define GPU_BUS_BAR0_WINDOW 0x00001700 +#define GPU_BUS_BAR0_WINDOW_BASE_SHIFT 0x00000000 +#define GPU_BUS_BAR0_WINDOW_BASE_FIELDMASK 0x00ffffff +#define GPU_BUS_BAR0_WINDOW_TARGET_VID_MEM_F 0x00000000 +#define GPU_BUS_BAR0_WINDOW_TARGET_SYS_MEM_COHERENT_F 0x02000000 +#define GPU_BUS_BAR0_WINDOW_TARGET_SYS_MEM_NONCOHERENT_F 0x03000000 +#define GPU_BUS_BAR0_WINDOW_TARGET_BAR0_WINDOW_BASE_SHIFT_V 0x00000010 +#define GPU_BUS_BAR1_BLOCK 0x00001704 +#define GPU_BUS_BAR1_BLOCK_PTR_SHIFT 0x00000000 +#define GPU_BUS_BAR1_BLOCK_PTR_FIELDMASK 0x0fffffff +#define GPU_BUS_BAR1_BLOCK_TARGET_VID_MEM_F 0x00000000 +#define GPU_BUS_BAR1_BLOCK_TARGET_SYS_MEM_COH_F 0x20000000 +#define GPU_BUS_BAR1_BLOCK_TARGET_SYS_MEM_NCOH_F 0x30000000 +#define GPU_BUS_BAR1_BLOCK_MODE_VIRTUAL_F 0x80000000 +#define GPU_BUS_BAR2_BLOCK 0x00001714 +#define GPU_BUS_BAR2_BLOCK_PTR_SHIFT 0x00000000 +#define GPU_BUS_BAR2_BLOCK_PTR_FIELDMASK 0x0fffffff +#define GPU_BUS_BAR2_BLOCK_TARGET_VID_MEM_F 0x00000000 +#define GPU_BUS_BAR2_BLOCK_TARGET_SYS_MEM_COH_F 0x20000000 +#define GPU_BUS_BAR2_BLOCK_TARGET_SYS_MEM_NCOH_F 0x30000000 +#define GPU_BUS_BAR2_BLOCK_MODE_VIRTUAL_F 0x80000000 +#define GPU_BUS_BAR1_BLOCK_PTR_SHIFT_V 0x0000000c +#define GPU_BUS_BAR2_BLOCK_PTR_SHIFT_V 0x0000000c +#define GPU_BUS_BIND_STATUS 0x00001710 +#define GPU_BUS_BIND_STATUS_BAR1_PENDING_SHIFT 0x00000000 +#define GPU_BUS_BIND_STATUS_BAR1_PENDING_FIELDMASK 0x00000001 +#define GPU_BUS_BIND_STATUS_BAR1_PENDING_EMPTY_F 0x00000000 +#define GPU_BUS_BIND_STATUS_BAR1_PENDING_BUSY_F 0x00000001 +#define GPU_BUS_BIND_STATUS_BAR1_OUTSTANDING_SHIFT 0x00000001 +#define GPU_BUS_BIND_STATUS_BAR1_OUTSTANDING_FIELDMASK 0x00000001 +#define GPU_BUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE_F 0x00000000 +#define GPU_BUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE_F 0x00000002 +#define GPU_BUS_BIND_STATUS_BAR2_PENDING_SHIFT 0x00000002 +#define GPU_BUS_BIND_STATUS_BAR2_PENDING_FIELDMASK 0x00000001 +#define GPU_BUS_BIND_STATUS_BAR2_PENDING_EMPTY_F 0x00000000 +#define GPU_BUS_BIND_STATUS_BAR2_PENDING_BUSY_F 0x00000004 +#define GPU_BUS_BIND_STATUS_BAR2_OUTSTANDING_SHIFT 0x00000003 +#define GPU_BUS_BIND_STATUS_BAR2_OUTSTANDING_FIELDMASK 0x00000001 +#define GPU_BUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE_F 0x00000000 +#define GPU_BUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE_F 0x00000008 +#define GPU_BUS_INTR_0 0x00001100 +#define GPU_BUS_INTR_0_PRI_SQUASH_MASK 0x00000002 +#define GPU_BUS_INTR_0_PRI_SQUASH_SHIFT 0x00000001 +#define GPU_BUS_INTR_0_PRI_SQUASH_FIELDMASK 0x00000001 +#define GPU_BUS_INTR_0_PRI_FECSERR_MASK 0x00000004 +#define GPU_BUS_INTR_0_PRI_FECSERR_SHIFT 0x00000002 +#define GPU_BUS_INTR_0_PRI_FECSERR_FIELDMASK 0x00000001 +#define GPU_BUS_INTR_0_PRI_TIMEOUT_MASK 0x00000008 +#define GPU_BUS_INTR_0_PRI_TIMEOUT_SHIFT 0x00000003 +#define GPU_BUS_INTR_0_PRI_TIMEOUT_FIELDMASK 0x00000001 +#define GPU_BUS_INTR_EN_0 0x00001140 +#define GPU_BUS_INTR_EN_0_PRI_SQUASH_MASK 0x00000002 +#define GPU_BUS_INTR_EN_0_PRI_SQUASH_SHIFT 0x00000001 +#define GPU_BUS_INTR_EN_0_PRI_SQUASH_FIELDMASK 0x00000001 +#define GPU_BUS_INTR_EN_0_PRI_FECSERR_MASK 0x00000004 +#define GPU_BUS_INTR_EN_0_PRI_FECSERR_SHIFT 0x00000002 +#define GPU_BUS_INTR_EN_0_PRI_FECSERR_FIELDMASK 0x00000001 +#define GPU_BUS_INTR_EN_0_PRI_TIMEOUT_MASK 0x00000008 +#define GPU_BUS_INTR_EN_0_PRI_TIMEOUT_SHIFT 0x00000003 +#define GPU_BUS_INTR_EN_0_PRI_TIMEOUT_FIELDMASK 0x00000001 + +#define GPU_CCSR_CHANNEL_INST__BASE 0x00800000 +#define GPU_CCSR_CHANNEL_INST__STRIDE 0x00000008 +#define GPU_CCSR_CHANNEL_INST(i) (0x00800000 + (i) * 0x00000008) +#define GPU_CCSR_CHANNEL_INST__SIZE_1_V 0x00000200 +#define GPU_CCSR_CHANNEL_INST_PTR_SHIFT 0x00000000 +#define GPU_CCSR_CHANNEL_INST_PTR_FIELDMASK 0x0fffffff +#define GPU_CCSR_CHANNEL_INST_TARGET_VID_MEM_F 0x00000000 +#define GPU_CCSR_CHANNEL_INST_TARGET_SYS_MEM_COH_F 0x20000000 +#define GPU_CCSR_CHANNEL_INST_TARGET_SYS_MEM_NCOH_F 0x30000000 +#define GPU_CCSR_CHANNEL_INST_BIND_FALSE_F 0x00000000 +#define GPU_CCSR_CHANNEL_INST_BIND_TRUE_F 0x80000000 +#define GPU_CCSR_CHANNEL__BASE 0x00800004 +#define GPU_CCSR_CHANNEL__STRIDE 0x00000008 +#define GPU_CCSR_CHANNEL(i) (0x00800004 + (i) * 0x00000008) +#define GPU_CCSR_CHANNEL__SIZE_1_V 0x00000200 +#define GPU_CCSR_CHANNEL_ENABLE_SHIFT 0x00000000 +#define GPU_CCSR_CHANNEL_ENABLE_FIELDMASK 0x00000001 +#define GPU_CCSR_CHANNEL_ENABLE_SET_SHIFT 0x0000000a +#define GPU_CCSR_CHANNEL_ENABLE_SET_FIELDMASK 0x00000001 +#define GPU_CCSR_CHANNEL_ENABLE_SET_TRUE_F 0x00000400 +#define GPU_CCSR_CHANNEL_ENABLE_CLR_TRUE_F 0x00000800 +#define GPU_CCSR_CHANNEL_STATUS_SHIFT 0x00000018 +#define GPU_CCSR_CHANNEL_STATUS_FIELDMASK 0x0000000f +#define GPU_CCSR_CHANNEL_BUSY_SHIFT 0x0000001c +#define GPU_CCSR_CHANNEL_BUSY_FIELDMASK 0x00000001 + +#define GPU_CE2_INTR_STATUS 0x00106908 +#define GPU_CE2_INTR_STATUS_BLOCKPIPE_PENDING_F 0x00000001 +#define GPU_CE2_INTR_STATUS_BLOCKPIPE_RESET_F 0x00000001 +#define GPU_CE2_INTR_STATUS_NONBLOCKPIPE_PENDING_F 0x00000002 +#define GPU_CE2_INTR_STATUS_NONBLOCKPIPE_RESET_F 0x00000002 +#define GPU_CE2_INTR_STATUS_LAUNCHERR_PENDING_F 0x00000004 +#define GPU_CE2_INTR_STATUS_LAUNCHERR_RESET_F 0x00000004 + +#define GPU_CTXSW_PROG_FECS_HEADER_V 0x00000100 +#define GPU_CTXSW_PROG_MAIN_IMAGE_NUM_GPCS_O 0x00000008 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CTL_O 0x0000000c +#define GPU_CTXSW_PROG_MAIN_IMAGE_CTL_CDE_ENABLED_F 0x00000400 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CTL_CDE_DISABLED_F 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PATCH_COUNT_O 0x00000010 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_ID_O 0x000000f0 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PATCH_ADR_LO_O 0x00000014 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PATCH_ADR_HI_O 0x00000018 +#define GPU_CTXSW_PROG_MAIN_IMAGE_ZCULL_O 0x0000001c +#define GPU_CTXSW_PROG_MAIN_IMAGE_ZCULL_MODE_NO_CTXSW_V 0x00000001 +#define GPU_CTXSW_PROG_MAIN_IMAGE_ZCULL_MODE_SEPARATE_BUFFER_V 0x00000002 +#define GPU_CTXSW_PROG_MAIN_IMAGE_ZCULL_PTR_O 0x00000020 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_O 0x00000028 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_MODE_MASK 0x00000007 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_MODE_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_MODE_FIELDMASK 0x00000007 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_MODE_NO_CTXSW_F 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_SMPC_MODE_MASK 0x00000038 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_SMPC_MODE_SHIFT 0x00000003 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_SMPC_MODE_FIELDMASK 0x00000007 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_SMPC_MODE_CTXSW_F 0x00000008 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_SMPC_MODE_NO_CTXSW_F 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_PC_SAMPLING_SHIFT 0x00000006 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_PC_SAMPLING_FIELDMASK 0x00000001 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_PC_SAMPLING_MASK 0x00000040 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PM_PTR_O 0x0000002c +#define GPU_CTXSW_PROG_MAIN_IMAGE_NUM_SAVE_OPS_O 0x000000f4 +#define GPU_CTXSW_PROG_MAIN_IMAGE_NUM_RESTORE_OPS_O 0x000000f8 +#define GPU_CTXSW_PROG_MAIN_IMAGE_MAGIC_VALUE_O 0x000000fc +#define GPU_CTXSW_PROG_MAIN_IMAGE_MAGIC_VALUE_V_VALUE_V 0x600dc0de +#define GPU_CTXSW_PROG_LOCAL_PRIV_REGISTER_CTL_O 0x0000000c +#define GPU_CTXSW_PROG_LOCAL_PRIV_REGISTER_CTL_OFFSET_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_LOCAL_PRIV_REGISTER_CTL_OFFSET_FIELDMASK 0x0000ffff +#define GPU_CTXSW_PROG_LOCAL_IMAGE_PPC_INFO_O 0x000000f4 +#define GPU_CTXSW_PROG_LOCAL_IMAGE_PPC_INFO_NUM_PPCS_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_LOCAL_IMAGE_PPC_INFO_NUM_PPCS_FIELDMASK 0x0000ffff +#define GPU_CTXSW_PROG_LOCAL_IMAGE_PPC_INFO_PPC_MASK_SHIFT 0x00000010 +#define GPU_CTXSW_PROG_LOCAL_IMAGE_PPC_INFO_PPC_MASK_FIELDMASK 0x0000ffff +#define GPU_CTXSW_PROG_LOCAL_IMAGE_NUM_TPCS_O 0x000000f8 +#define GPU_CTXSW_PROG_LOCAL_MAGIC_VALUE_O 0x000000fc +#define GPU_CTXSW_PROG_LOCAL_MAGIC_VALUE_V_VALUE_V 0xad0becab +#define GPU_CTXSW_PROG_MAIN_EXTENDED_BUFFER_CTL_O 0x000000ec +#define GPU_CTXSW_PROG_MAIN_EXTENDED_BUFFER_CTL_OFFSET_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_MAIN_EXTENDED_BUFFER_CTL_OFFSET_FIELDMASK 0x0000ffff +#define GPU_CTXSW_PROG_MAIN_EXTENDED_BUFFER_CTL_SIZE_SHIFT 0x00000010 +#define GPU_CTXSW_PROG_MAIN_EXTENDED_BUFFER_CTL_SIZE_FIELDMASK 0x000000ff +#define GPU_CTXSW_PROG_EXTENDED_BUFFER_SEGMENTS_SIZE_IN_BYTES_V 0x00000100 +#define GPU_CTXSW_PROG_EXTENDED_MARKER_SIZE_IN_BYTES_V 0x00000004 +#define GPU_CTXSW_PROG_EXTENDED_SM_DSM_PERF_COUNTER_REGISTER_STRIDE_V 0x00000000 +#define GPU_CTXSW_PROG_EXTENDED_SM_DSM_PERF_COUNTER_CONTROL_REGISTER_STRIDE_V 0x00000002 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_O 0x000000a0 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_SIZE 0x00000002 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_FIELDMASK 0x00000003 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_MASK 0x00000003 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_ALLOW_ALL_F 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PRIV_ACCESS_MAP_CONFIG_MODE_USE_MAP_F 0x00000002 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_LO_O 0x000000a4 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PRIV_ACCESS_MAP_ADDR_HI_O 0x000000a8 +#define GPU_CTXSW_PROG_MAIN_IMAGE_MISC_OPTIONS_O 0x0000003c +#define GPU_CTXSW_PROG_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES_MASK 0x00000008 +#define GPU_CTXSW_PROG_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES_SHIFT 0x00000003 +#define GPU_CTXSW_PROG_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES_FIELDMASK 0x00000001 +#define GPU_CTXSW_PROG_MAIN_IMAGE_MISC_OPTIONS_VERIF_FEATURES_DISABLED_F 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_CONTROL_O 0x000000ac +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_CONTROL_NUM_RECORDS_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_CONTROL_NUM_RECORDS_FIELDMASK 0x0000ffff +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_O 0x000000b0 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_V_MASK 0x0fffffff +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_V_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_V_FIELDMASK 0x0fffffff +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_TARGET_MASK 0x30000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_TARGET_SHIFT 0x0000001c +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_TARGET_FIELDMASK 0x00000003 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_TARGET_VID_MEM_F 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_TARGET_SYS_MEM_COHERENT_F 0x20000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_HI_TARGET_SYS_MEM_NONCOHERENT_F 0x30000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_O 0x000000b4 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_V_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_CONTEXT_TIMESTAMP_BUFFER_PTR_V_FIELDMASK 0xffffffff +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_RECORD_SIZE_IN_BYTES_V 0x00000080 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_RECORD_SIZE_IN_WORDS_V 0x00000020 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_MAGIC_VALUE_LO_O 0x00000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_MAGIC_VALUE_LO_V_VALUE_V 0x00000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_MAGIC_VALUE_HI_O 0x00000004 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_MAGIC_VALUE_HI_V_VALUE_V 0x600dbeef +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_CONTEXT_ID_O 0x00000008 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_CONTEXT_PTR_O 0x0000000c +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_NEW_CONTEXT_ID_O 0x00000010 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_NEW_CONTEXT_PTR_O 0x00000014 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_LO_O 0x00000018 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_O 0x0000001c +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_V_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_V_FIELDMASK 0x00ffffff +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_SHIFT 0x00000018 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FIELDMASK 0x000000ff +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_MASK 0xff000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_CTXSW_REQ_BY_HOST_V 0x00000001 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_CTXSW_REQ_BY_HOST_F 0x01000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_V 0x00000002 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_F 0x02000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_WFI_V 0x0000000a +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_WFI_F 0x0a000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_GFXP_V 0x0000000b +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_GFXP_F 0x0b000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_CTAP_V 0x0000000c +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_CTAP_F 0x0c000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_CILP_V 0x0000000d +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_FE_ACK_CILP_F 0x0d000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_SAVE_END_V 0x00000003 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_SAVE_END_F 0x03000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_RESTORE_START_V 0x00000004 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_RESTORE_START_F 0x04000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_CONTEXT_START_V 0x00000005 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_CONTEXT_START_F 0x05000000 +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_INVALID_TIMESTAMP_V 0x000000ff +#define GPU_CTXSW_PROG_RECORD_TIMESTAMP_TIMESTAMP_HI_TAG_INVALID_TIMESTAMP_F 0xff000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PREEMPTION_OPTIONS_O 0x00000060 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL_SHIFT 0x00000000 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL_FIELDMASK 0x00000003 +#define GPU_CTXSW_PROG_MAIN_IMAGE_PREEMPTION_OPTIONS_CONTROL_CTA_ENABLED_F 0x00000001 + +#define GPU_FB_FBHUB_NUM_ACTIVE_LTCS 0x00100800 +#define GPU_FB_MMU_CTRL 0x00100c80 +#define GPU_FB_MMU_CTRL_VM_PG_SIZE_SHIFT 0x00000000 +#define GPU_FB_MMU_CTRL_VM_PG_SIZE_FIELDMASK 0x00000001 +#define GPU_FB_MMU_CTRL_VM_PG_SIZE_128KB_F 0x00000000 +#define GPU_FB_MMU_CTRL_VM_PG_SIZE_64KB_F 0x00000001 +#define GPU_FB_MMU_CTRL_PRI_FIFO_EMPTY_SHIFT 0x0000000f +#define GPU_FB_MMU_CTRL_PRI_FIFO_EMPTY_FIELDMASK 0x00000001 +#define GPU_FB_MMU_CTRL_PRI_FIFO_EMPTY_FALSE_F 0x00000000 +#define GPU_FB_MMU_CTRL_PRI_FIFO_SPACE_SHIFT 0x00000010 +#define GPU_FB_MMU_CTRL_PRI_FIFO_SPACE_FIELDMASK 0x000000ff +#define GPU_FB_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_SHIFT 0x0000000b +#define GPU_FB_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_FIELDMASK 0x00000001 +#define GPU_FB_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE_F 0x00000800 +#define GPU_FB_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE_F 0x00000000 +#define GPU_FB_MMU_CTRL_USE_FULL_COMP_TAG_LINE_SHIFT 0x0000000c +#define GPU_FB_MMU_CTRL_USE_FULL_COMP_TAG_LINE_FIELDMASK 0x00000001 +#define GPU_FB_MMU_CTRL_USE_FULL_COMP_TAG_LINE_TRUE_F 0x00001000 +#define GPU_FB_PRIV_MMU_PHY_SECURE 0x00100ce4 +#define GPU_FB_MMU_INVALIDATE_PDB 0x00100cb8 +#define GPU_FB_MMU_INVALIDATE_PDB_APERTURE_VID_MEM_F 0x00000000 +#define GPU_FB_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM_F 0x00000002 +#define GPU_FB_MMU_INVALIDATE_PDB_ADDR_SHIFT 0x00000004 +#define GPU_FB_MMU_INVALIDATE_PDB_ADDR_FIELDMASK 0x0fffffff +#define GPU_FB_MMU_INVALIDATE 0x00100cbc +#define GPU_FB_MMU_INVALIDATE_ALL_VA_TRUE_F 0x00000001 +#define GPU_FB_MMU_INVALIDATE_ALL_PDB_TRUE_F 0x00000002 +#define GPU_FB_MMU_INVALIDATE_TRIGGER_SIZE 0x00000001 +#define GPU_FB_MMU_INVALIDATE_TRIGGER_SHIFT 0x0000001f +#define GPU_FB_MMU_INVALIDATE_TRIGGER_FIELDMASK 0x00000001 +#define GPU_FB_MMU_INVALIDATE_TRIGGER_MASK 0x80000000 +#define GPU_FB_MMU_INVALIDATE_TRIGGER_TRUE_F 0x80000000 +#define GPU_FB_MMU_DEBUG_WR 0x00100cc8 +#define GPU_FB_MMU_DEBUG_WR_APERTURE_SIZE 0x00000002 +#define GPU_FB_MMU_DEBUG_WR_APERTURE_SHIFT 0x00000000 +#define GPU_FB_MMU_DEBUG_WR_APERTURE_FIELDMASK 0x00000003 +#define GPU_FB_MMU_DEBUG_WR_APERTURE_MASK 0x00000003 +#define GPU_FB_MMU_DEBUG_WR_APERTURE_VID_MEM_F 0x00000000 +#define GPU_FB_MMU_DEBUG_WR_APERTURE_SYS_MEM_COH_F 0x00000002 +#define GPU_FB_MMU_DEBUG_WR_APERTURE_SYS_MEM_NCOH_F 0x00000003 +#define GPU_FB_MMU_DEBUG_WR_VOL_FALSE_F 0x00000000 +#define GPU_FB_MMU_DEBUG_WR_VOL_TRUE_V 0x00000001 +#define GPU_FB_MMU_DEBUG_WR_VOL_TRUE_F 0x00000004 +#define GPU_FB_MMU_DEBUG_WR_ADDR_SHIFT 0x00000004 +#define GPU_FB_MMU_DEBUG_WR_ADDR_FIELDMASK 0x0fffffff +#define GPU_FB_MMU_DEBUG_WR_ADDR_ALIGNMENT_V 0x0000000c +#define GPU_FB_MMU_DEBUG_RD 0x00100ccc +#define GPU_FB_MMU_DEBUG_RD_APERTURE_VID_MEM_F 0x00000000 +#define GPU_FB_MMU_DEBUG_RD_APERTURE_SYS_MEM_COH_F 0x00000002 +#define GPU_FB_MMU_DEBUG_RD_APERTURE_SYS_MEM_NCOH_F 0x00000003 +#define GPU_FB_MMU_DEBUG_RD_VOL_FALSE_F 0x00000000 +#define GPU_FB_MMU_DEBUG_RD_ADDR_SHIFT 0x00000004 +#define GPU_FB_MMU_DEBUG_RD_ADDR_FIELDMASK 0x0fffffff +#define GPU_FB_MMU_DEBUG_RD_ADDR_ALIGNMENT_V 0x0000000c +#define GPU_FB_MMU_DEBUG_CTRL 0x00100cc4 +#define GPU_FB_MMU_DEBUG_CTRL_DEBUG_SHIFT 0x00000010 +#define GPU_FB_MMU_DEBUG_CTRL_DEBUG_FIELDMASK 0x00000001 +#define GPU_FB_MMU_DEBUG_CTRL_DEBUG_MASK 0x00010000 +#define GPU_FB_MMU_DEBUG_CTRL_DEBUG_ENABLED_V 0x00000001 +#define GPU_FB_MMU_DEBUG_CTRL_DEBUG_ENABLED_F 0x00010000 +#define GPU_FB_MMU_DEBUG_CTRL_DEBUG_DISABLED_V 0x00000000 +#define GPU_FB_MMU_DEBUG_CTRL_DEBUG_DISABLED_F 0x00000000 +#define GPU_FB_MMU_VPR_INFO 0x00100cd0 +#define GPU_FB_MMU_VPR_INFO_INDEX_SHIFT 0x00000000 +#define GPU_FB_MMU_VPR_INFO_INDEX_FIELDMASK 0x00000003 +#define GPU_FB_MMU_VPR_INFO_INDEX_ADDR_LO_V 0x00000000 +#define GPU_FB_MMU_VPR_INFO_INDEX_ADDR_HI_V 0x00000001 +#define GPU_FB_MMU_VPR_INFO_INDEX_CYA_LO_V 0x00000002 +#define GPU_FB_MMU_VPR_INFO_INDEX_CYA_HI_V 0x00000003 +#define GPU_FB_MMU_VPR_INFO_FETCH_SHIFT 0x00000002 +#define GPU_FB_MMU_VPR_INFO_FETCH_FIELDMASK 0x00000001 +#define GPU_FB_MMU_VPR_INFO_FETCH_FALSE_V 0x00000000 +#define GPU_FB_MMU_VPR_INFO_FETCH_TRUE_V 0x00000001 +#define GPU_FB_MMU_WPR_INFO 0x00100cd4 +#define GPU_FB_MMU_WPR_INFO_INDEX_SHIFT 0x00000000 +#define GPU_FB_MMU_WPR_INFO_INDEX_FIELDMASK 0x0000000f +#define GPU_FB_MMU_WPR_INFO_INDEX_ALLOW_READ_V 0x00000000 +#define GPU_FB_MMU_WPR_INFO_INDEX_ALLOW_WRITE_V 0x00000001 +#define GPU_FB_MMU_WPR_INFO_INDEX_WPR1_ADDR_LO_V 0x00000002 +#define GPU_FB_MMU_WPR_INFO_INDEX_WPR1_ADDR_HI_V 0x00000003 +#define GPU_FB_MMU_WPR_INFO_INDEX_WPR2_ADDR_LO_V 0x00000004 +#define GPU_FB_MMU_WPR_INFO_INDEX_WPR2_ADDR_HI_V 0x00000005 + +#define GPU_FIFO_BAR1_BASE 0x00002254 +#define GPU_FIFO_BAR1_BASE_PTR_SHIFT 0x00000000 +#define GPU_FIFO_BAR1_BASE_PTR_FIELDMASK 0x0fffffff +#define GPU_FIFO_BAR1_BASE_PTR_ALIGN_SHIFT_V 0x0000000c +#define GPU_FIFO_BAR1_BASE_VALID_FALSE_F 0x00000000 +#define GPU_FIFO_BAR1_BASE_VALID_TRUE_F 0x10000000 +#define GPU_FIFO_RUNLIST_BASE 0x00002270 +#define GPU_FIFO_RUNLIST_BASE_PTR_SHIFT 0x00000000 +#define GPU_FIFO_RUNLIST_BASE_PTR_FIELDMASK 0x0fffffff +#define GPU_FIFO_RUNLIST_BASE_TARGET_VID_MEM_F 0x00000000 +#define GPU_FIFO_RUNLIST_BASE_TARGET_SYS_MEM_COH_F 0x20000000 +#define GPU_FIFO_RUNLIST_BASE_TARGET_SYS_MEM_NCOH_F 0x30000000 +#define GPU_FIFO_RUNLIST 0x00002274 +#define GPU_FIFO_RUNLIST_ENGINE_SHIFT 0x00000014 +#define GPU_FIFO_RUNLIST_ENGINE_FIELDMASK 0x0000000f +#define GPU_FIFO_ENG_RUNLIST_BASE__BASE 0x00002280 +#define GPU_FIFO_ENG_RUNLIST_BASE__STRIDE 0x00000008 +#define GPU_FIFO_ENG_RUNLIST_BASE(i) (0x00002280 + (i) * 0x00000008) +#define GPU_FIFO_ENG_RUNLIST_BASE__SIZE_1_V 0x00000001 +#define GPU_FIFO_ENG_RUNLIST__BASE 0x00002284 +#define GPU_FIFO_ENG_RUNLIST__STRIDE 0x00000008 +#define GPU_FIFO_ENG_RUNLIST(i) (0x00002284 + (i) * 0x00000008) +#define GPU_FIFO_ENG_RUNLIST__SIZE_1_V 0x00000001 +#define GPU_FIFO_ENG_RUNLIST_LENGTH_SHIFT 0x00000000 +#define GPU_FIFO_ENG_RUNLIST_LENGTH_FIELDMASK 0x0000ffff +#define GPU_FIFO_ENG_RUNLIST_LENGTH_MAX_V 0x0000ffff +#define GPU_FIFO_ENG_RUNLIST_PENDING_TRUE_F 0x00100000 +#define GPU_FIFO_PB_TIMESLICE__BASE 0x00002350 +#define GPU_FIFO_PB_TIMESLICE__STRIDE 0x00000004 +#define GPU_FIFO_PB_TIMESLICE(i) (0x00002350 + (i) * 0x00000004) +#define GPU_FIFO_PB_TIMESLICE_TIMEOUT_16_F 0x00000010 +#define GPU_FIFO_PB_TIMESLICE_TIMESCALE_0_F 0x00000000 +#define GPU_FIFO_PB_TIMESLICE_ENABLE_TRUE_F 0x10000000 +#define GPU_FIFO_PBDMA_MAP__BASE 0x00002390 +#define GPU_FIFO_PBDMA_MAP__STRIDE 0x00000004 +#define GPU_FIFO_PBDMA_MAP(i) (0x00002390 + (i) * 0x00000004) +#define GPU_FIFO_INTR_0 0x00002100 +#define GPU_FIFO_INTR_0_BIND_ERROR_PENDING_F 0x00000001 +#define GPU_FIFO_INTR_0_BIND_ERROR_RESET_F 0x00000001 +#define GPU_FIFO_INTR_0_SCHED_ERROR_PENDING_F 0x00000100 +#define GPU_FIFO_INTR_0_SCHED_ERROR_RESET_F 0x00000100 +#define GPU_FIFO_INTR_0_CHSW_ERROR_PENDING_F 0x00010000 +#define GPU_FIFO_INTR_0_CHSW_ERROR_RESET_F 0x00010000 +#define GPU_FIFO_INTR_0_FB_FLUSH_TIMEOUT_PENDING_F 0x00800000 +#define GPU_FIFO_INTR_0_FB_FLUSH_TIMEOUT_RESET_F 0x00800000 +#define GPU_FIFO_INTR_0_LB_ERROR_PENDING_F 0x01000000 +#define GPU_FIFO_INTR_0_LB_ERROR_RESET_F 0x01000000 +#define GPU_FIFO_INTR_0_DROPPED_MMU_FAULT_PENDING_F 0x08000000 +#define GPU_FIFO_INTR_0_DROPPED_MMU_FAULT_RESET_F 0x08000000 +#define GPU_FIFO_INTR_0_MMU_FAULT_PENDING_F 0x10000000 +#define GPU_FIFO_INTR_0_PBDMA_INTR_PENDING_F 0x20000000 +#define GPU_FIFO_INTR_0_RUNLIST_EVENT_PENDING_F 0x40000000 +#define GPU_FIFO_INTR_0_CHANNEL_INTR_PENDING_F 0x80000000 +#define GPU_FIFO_INTR_EN_0 0x00002140 +#define GPU_FIFO_INTR_EN_0_SCHED_ERROR_SHIFT 0x00000008 +#define GPU_FIFO_INTR_EN_0_SCHED_ERROR_FIELDMASK 0x00000001 +#define GPU_FIFO_INTR_EN_0_SCHED_ERROR_MASK 0x00000100 +#define GPU_FIFO_INTR_EN_0_MMU_FAULT_SHIFT 0x0000001c +#define GPU_FIFO_INTR_EN_0_MMU_FAULT_FIELDMASK 0x00000001 +#define GPU_FIFO_INTR_EN_0_MMU_FAULT_MASK 0x10000000 +#define GPU_FIFO_INTR_EN_1 0x00002528 +#define GPU_FIFO_INTR_BIND_ERROR 0x0000252c +#define GPU_FIFO_INTR_SCHED_ERROR 0x0000254c +#define GPU_FIFO_INTR_SCHED_ERROR_CODE_SHIFT 0x00000000 +#define GPU_FIFO_INTR_SCHED_ERROR_CODE_FIELDMASK 0x000000ff +#define GPU_FIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT_V 0x0000000a +#define GPU_FIFO_INTR_CHSW_ERROR 0x0000256c +#define GPU_FIFO_INTR_MMU_FAULT_ID 0x0000259c +#define GPU_FIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS_V 0x00000000 +#define GPU_FIFO_INTR_MMU_FAULT_ENG_ID_GRAPHICS_F 0x00000000 +#define GPU_FIFO_INTR_MMU_FAULT_INST__BASE 0x00002800 +#define GPU_FIFO_INTR_MMU_FAULT_INST__STRIDE 0x00000010 +#define GPU_FIFO_INTR_MMU_FAULT_INST(i) (0x00002800 + (i) * 0x00000010) +#define GPU_FIFO_INTR_MMU_FAULT_INST_PTR_SHIFT 0x00000000 +#define GPU_FIFO_INTR_MMU_FAULT_INST_PTR_FIELDMASK 0x0fffffff +#define GPU_FIFO_INTR_MMU_FAULT_INST_PTR_ALIGN_SHIFT_V 0x0000000c +#define GPU_FIFO_INTR_MMU_FAULT_LO__BASE 0x00002804 +#define GPU_FIFO_INTR_MMU_FAULT_LO__STRIDE 0x00000010 +#define GPU_FIFO_INTR_MMU_FAULT_LO(i) (0x00002804 + (i) * 0x00000010) +#define GPU_FIFO_INTR_MMU_FAULT_HI__BASE 0x00002808 +#define GPU_FIFO_INTR_MMU_FAULT_HI__STRIDE 0x00000010 +#define GPU_FIFO_INTR_MMU_FAULT_HI(i) (0x00002808 + (i) * 0x00000010) +#define GPU_FIFO_INTR_MMU_FAULT_INFO__BASE 0x0000280c +#define GPU_FIFO_INTR_MMU_FAULT_INFO__STRIDE 0x00000010 +#define GPU_FIFO_INTR_MMU_FAULT_INFO(i) (0x0000280c + (i) * 0x00000010) +#define GPU_FIFO_INTR_MMU_FAULT_INFO_TYPE_SHIFT 0x00000000 +#define GPU_FIFO_INTR_MMU_FAULT_INFO_TYPE_FIELDMASK 0x0000000f +#define GPU_FIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_SHIFT 0x00000006 +#define GPU_FIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_FIELDMASK 0x00000001 +#define GPU_FIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_GPC_V 0x00000000 +#define GPU_FIFO_INTR_MMU_FAULT_INFO_ENGINE_SUBID_HUB_V 0x00000001 +#define GPU_FIFO_INTR_MMU_FAULT_INFO_CLIENT_SHIFT 0x00000008 +#define GPU_FIFO_INTR_MMU_FAULT_INFO_CLIENT_FIELDMASK 0x0000003f +#define GPU_FIFO_INTR_PBDMA_ID 0x000025a0 +#define GPU_FIFO_INTR_PBDMA_ID_STATUS_FIELDMASK 0x00000001 +#define GPU_FIFO_INTR_PBDMA_ID_STATUS__SHIFT_BASE 0x00000000 +#define GPU_FIFO_INTR_PBDMA_ID_STATUS__SHIFT_STRIDE 0x00000001 +#define GPU_FIFO_INTR_PBDMA_ID_STATUS__SHIFT_I(i) (0 + (i) * 1) +#define GPU_FIFO_INTR_PBDMA_ID_STATUS__SIZE_1_V 0x00000001 +#define GPU_FIFO_INTR_RUNLIST 0x00002a00 +#define GPU_FIFO_FB_TIMEOUT 0x00002a04 +#define GPU_FIFO_FB_TIMEOUT_PERIOD_MASK 0x3fffffff +#define GPU_FIFO_FB_TIMEOUT_PERIOD_SHIFT 0x00000000 +#define GPU_FIFO_FB_TIMEOUT_PERIOD_FIELDMASK 0x3fffffff +#define GPU_FIFO_FB_TIMEOUT_PERIOD_MAX_F 0x3fffffff +#define GPU_FIFO_ERROR_SCHED_DISABLE 0x0000262c +#define GPU_FIFO_SCHED_DISABLE 0x00002630 +#define GPU_FIFO_SCHED_DISABLE_RUNLIST_FIELDMASK 0x00000001 +#define GPU_FIFO_SCHED_DISABLE_RUNLIST__SHIFT_BASE 0x00000000 +#define GPU_FIFO_SCHED_DISABLE_RUNLIST__SHIFT_STRIDE 0x00000001 +#define GPU_FIFO_SCHED_DISABLE_RUNLIST__SHIFT_I(i) (0 + (i) * 1) +#define GPU_FIFO_SCHED_DISABLE_TRUE_V 0x00000001 +#define GPU_FIFO_PREEMPT 0x00002634 +#define GPU_FIFO_PREEMPT_PENDING_TRUE_F 0x00100000 +#define GPU_FIFO_PREEMPT_TYPE_CHANNEL_F 0x00000000 +#define GPU_FIFO_PREEMPT_TYPE_TSG_F 0x01000000 +#define GPU_FIFO_PREEMPT_CHID_SHIFT 0x00000000 +#define GPU_FIFO_PREEMPT_CHID_FIELDMASK 0x00000fff +#define GPU_FIFO_PREEMPT_ID_SHIFT 0x00000000 +#define GPU_FIFO_PREEMPT_ID_FIELDMASK 0x00000fff +#define GPU_FIFO_TRIGGER_MMU_FAULT__BASE 0x00002a30 +#define GPU_FIFO_TRIGGER_MMU_FAULT__STRIDE 0x00000004 +#define GPU_FIFO_TRIGGER_MMU_FAULT(i) (0x00002a30 + (i) * 0x00000004) +#define GPU_FIFO_TRIGGER_MMU_FAULT_ID_SHIFT 0x00000000 +#define GPU_FIFO_TRIGGER_MMU_FAULT_ID_FIELDMASK 0x0000001f +#define GPU_FIFO_TRIGGER_MMU_FAULT_ENABLE_SHIFT 0x00000008 +#define GPU_FIFO_TRIGGER_MMU_FAULT_ENABLE_FIELDMASK 0x00000001 +#define GPU_FIFO_ENGINE_STATUS__BASE 0x00002640 +#define GPU_FIFO_ENGINE_STATUS__STRIDE 0x00000008 +#define GPU_FIFO_ENGINE_STATUS(i) (0x00002640 + (i) * 0x00000008) +#define GPU_FIFO_ENGINE_STATUS__SIZE_1_V 0x00000002 +#define GPU_FIFO_ENGINE_STATUS_ID_SHIFT 0x00000000 +#define GPU_FIFO_ENGINE_STATUS_ID_FIELDMASK 0x00000fff +#define GPU_FIFO_ENGINE_STATUS_ID_TYPE_SHIFT 0x0000000c +#define GPU_FIFO_ENGINE_STATUS_ID_TYPE_FIELDMASK 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_ID_TYPE_CHID_V 0x00000000 +#define GPU_FIFO_ENGINE_STATUS_ID_TYPE_TSGID_V 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_CTX_STATUS_SHIFT 0x0000000d +#define GPU_FIFO_ENGINE_STATUS_CTX_STATUS_FIELDMASK 0x00000007 +#define GPU_FIFO_ENGINE_STATUS_CTX_STATUS_INVALID_V 0x00000000 +#define GPU_FIFO_ENGINE_STATUS_CTX_STATUS_VALID_V 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD_V 0x00000005 +#define GPU_FIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE_V 0x00000006 +#define GPU_FIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH_V 0x00000007 +#define GPU_FIFO_ENGINE_STATUS_NEXT_ID_SHIFT 0x00000010 +#define GPU_FIFO_ENGINE_STATUS_NEXT_ID_FIELDMASK 0x00000fff +#define GPU_FIFO_ENGINE_STATUS_NEXT_ID_TYPE_SHIFT 0x0000001c +#define GPU_FIFO_ENGINE_STATUS_NEXT_ID_TYPE_FIELDMASK 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID_V 0x00000000 +#define GPU_FIFO_ENGINE_STATUS_FAULTED_SHIFT 0x0000001e +#define GPU_FIFO_ENGINE_STATUS_FAULTED_FIELDMASK 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_FAULTED_TRUE_V 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_ENGINE_SHIFT 0x0000001f +#define GPU_FIFO_ENGINE_STATUS_ENGINE_FIELDMASK 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_ENGINE_IDLE_V 0x00000000 +#define GPU_FIFO_ENGINE_STATUS_ENGINE_BUSY_V 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_CTXSW_SHIFT 0x0000000f +#define GPU_FIFO_ENGINE_STATUS_CTXSW_FIELDMASK 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS_V 0x00000001 +#define GPU_FIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS_F 0x00008000 +#define GPU_FIFO_PBDMA_STATUS__BASE 0x00003080 +#define GPU_FIFO_PBDMA_STATUS__STRIDE 0x00000004 +#define GPU_FIFO_PBDMA_STATUS(i) (0x00003080 + (i) * 0x00000004) +#define GPU_FIFO_PBDMA_STATUS__SIZE_1_V 0x00000001 +#define GPU_FIFO_PBDMA_STATUS_ID_SHIFT 0x00000000 +#define GPU_FIFO_PBDMA_STATUS_ID_FIELDMASK 0x00000fff +#define GPU_FIFO_PBDMA_STATUS_ID_TYPE_SHIFT 0x0000000c +#define GPU_FIFO_PBDMA_STATUS_ID_TYPE_FIELDMASK 0x00000001 +#define GPU_FIFO_PBDMA_STATUS_ID_TYPE_CHID_V 0x00000000 +#define GPU_FIFO_PBDMA_STATUS_ID_TYPE_TSGID_V 0x00000001 +#define GPU_FIFO_PBDMA_STATUS_CHAN_STATUS_SHIFT 0x0000000d +#define GPU_FIFO_PBDMA_STATUS_CHAN_STATUS_FIELDMASK 0x00000007 +#define GPU_FIFO_PBDMA_STATUS_CHAN_STATUS_VALID_V 0x00000001 +#define GPU_FIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD_V 0x00000005 +#define GPU_FIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE_V 0x00000006 +#define GPU_FIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH_V 0x00000007 +#define GPU_FIFO_PBDMA_STATUS_NEXT_ID_SHIFT 0x00000010 +#define GPU_FIFO_PBDMA_STATUS_NEXT_ID_FIELDMASK 0x00000fff +#define GPU_FIFO_PBDMA_STATUS_NEXT_ID_TYPE_SHIFT 0x0000001c +#define GPU_FIFO_PBDMA_STATUS_NEXT_ID_TYPE_FIELDMASK 0x00000001 +#define GPU_FIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID_V 0x00000000 +#define GPU_FIFO_PBDMA_STATUS_CHSW_SHIFT 0x0000000f +#define GPU_FIFO_PBDMA_STATUS_CHSW_FIELDMASK 0x00000001 +#define GPU_FIFO_PBDMA_STATUS_CHSW_IN_PROGRESS_V 0x00000001 + +#define GPU_FLUSH_L2_SYSTEM_INVALIDATE 0x00070004 +#define GPU_FLUSH_L2_SYSTEM_INVALIDATE_PENDING_SHIFT 0x00000000 +#define GPU_FLUSH_L2_SYSTEM_INVALIDATE_PENDING_FIELDMASK 0x00000001 +#define GPU_FLUSH_L2_SYSTEM_INVALIDATE_PENDING_BUSY_V 0x00000001 +#define GPU_FLUSH_L2_SYSTEM_INVALIDATE_PENDING_BUSY_F 0x00000001 +#define GPU_FLUSH_L2_SYSTEM_INVALIDATE_OUTSTANDING_SHIFT 0x00000001 +#define GPU_FLUSH_L2_SYSTEM_INVALIDATE_OUTSTANDING_FIELDMASK 0x00000001 +#define GPU_FLUSH_L2_SYSTEM_INVALIDATE_OUTSTANDING_TRUE_V 0x00000001 +#define GPU_FLUSH_L2_FLUSH_DIRTY 0x00070010 +#define GPU_FLUSH_L2_FLUSH_DIRTY_PENDING_SHIFT 0x00000000 +#define GPU_FLUSH_L2_FLUSH_DIRTY_PENDING_FIELDMASK 0x00000001 +#define GPU_FLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY_V 0x00000000 +#define GPU_FLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY_F 0x00000000 +#define GPU_FLUSH_L2_FLUSH_DIRTY_PENDING_BUSY_V 0x00000001 +#define GPU_FLUSH_L2_FLUSH_DIRTY_PENDING_BUSY_F 0x00000001 +#define GPU_FLUSH_L2_FLUSH_DIRTY_OUTSTANDING_SHIFT 0x00000001 +#define GPU_FLUSH_L2_FLUSH_DIRTY_OUTSTANDING_FIELDMASK 0x00000001 +#define GPU_FLUSH_L2_FLUSH_DIRTY_OUTSTANDING_FALSE_V 0x00000000 +#define GPU_FLUSH_L2_FLUSH_DIRTY_OUTSTANDING_FALSE_F 0x00000000 +#define GPU_FLUSH_L2_FLUSH_DIRTY_OUTSTANDING_TRUE_V 0x00000001 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS 0x0007000c +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_PENDING_SHIFT 0x00000000 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_PENDING_FIELDMASK 0x00000001 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_PENDING_EMPTY_V 0x00000000 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_PENDING_EMPTY_F 0x00000000 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_PENDING_BUSY_V 0x00000001 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_PENDING_BUSY_F 0x00000001 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_SHIFT 0x00000001 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_FIELDMASK 0x00000001 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_FALSE_V 0x00000000 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_FALSE_F 0x00000000 +#define GPU_FLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_TRUE_V 0x00000001 +#define GPU_FLUSH_FB_FLUSH 0x00070000 +#define GPU_FLUSH_FB_FLUSH_PENDING_SHIFT 0x00000000 +#define GPU_FLUSH_FB_FLUSH_PENDING_FIELDMASK 0x00000001 +#define GPU_FLUSH_FB_FLUSH_PENDING_BUSY_V 0x00000001 +#define GPU_FLUSH_FB_FLUSH_PENDING_BUSY_F 0x00000001 +#define GPU_FLUSH_FB_FLUSH_OUTSTANDING_SHIFT 0x00000001 +#define GPU_FLUSH_FB_FLUSH_OUTSTANDING_FIELDMASK 0x00000001 +#define GPU_FLUSH_FB_FLUSH_OUTSTANDING_TRUE_V 0x00000001 + +#define GPU_FUSE_STATUS_OPT_TPC_GPC__BASE 0x00021c38 +#define GPU_FUSE_STATUS_OPT_TPC_GPC__STRIDE 0x00000004 +#define GPU_FUSE_STATUS_OPT_TPC_GPC(i) (0x00021c38 + (i) * 0x00000004) +#define GPU_FUSE_CTRL_OPT_TPC_GPC__BASE 0x00021838 +#define GPU_FUSE_CTRL_OPT_TPC_GPC__STRIDE 0x00000004 +#define GPU_FUSE_CTRL_OPT_TPC_GPC(i) (0x00021838 + (i) * 0x00000004) +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP 0x00021944 +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP_DATA_SHIFT 0x00000000 +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP_DATA_FIELDMASK 0x00000003 +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP_DATA_MASK 0x00000003 +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE 0x00021948 +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA_SHIFT 0x00000000 +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA_FIELDMASK 0x00000001 +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA_MASK 0x00000001 +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA_YES_F 0x00000001 +#define GPU_FUSE_CTRL_OPT_RAM_SVOP_PDP_OVERRIDE_DATA_NO_F 0x00000000 +#define GPU_FUSE_STATUS_OPT_FBIO 0x00021c14 +#define GPU_FUSE_STATUS_OPT_FBIO_DATA_SHIFT 0x00000000 +#define GPU_FUSE_STATUS_OPT_FBIO_DATA_FIELDMASK 0x0000ffff +#define GPU_FUSE_STATUS_OPT_FBIO_DATA_MASK 0x0000ffff +#define GPU_FUSE_STATUS_OPT_ROP_L2_FBP__BASE 0x00021d70 +#define GPU_FUSE_STATUS_OPT_ROP_L2_FBP__STRIDE 0x00000004 +#define GPU_FUSE_STATUS_OPT_ROP_L2_FBP(i) (0x00021d70 + (i) * 0x00000004) +#define GPU_FUSE_STATUS_OPT_FBP 0x00021d38 +#define GPU_FUSE_STATUS_OPT_FBP_IDX_FIELDMASK 0x00000001 +#define GPU_FUSE_STATUS_OPT_FBP_IDX__SHIFT_BASE 0x00000000 +#define GPU_FUSE_STATUS_OPT_FBP_IDX__SHIFT_STRIDE 0x00000000 +#define GPU_FUSE_STATUS_OPT_FBP_IDX__SHIFT_I(i) (0 + (i) * 0) +#define GPU_FUSE_OPT_SEC_DEBUG_EN 0x00021218 +#define GPU_FUSE_OPT_PRIV_SEC_EN 0x00021434 + +#define GPU_GMMU_PDE_APERTURE_BIG_W 0x00000000 +#define GPU_GMMU_PDE_APERTURE_BIG_INVALID_F 0x00000000 +#define GPU_GMMU_PDE_APERTURE_BIG_VIDEO_MEMORY_F 0x00000001 +#define GPU_GMMU_PDE_APERTURE_BIG_SYS_MEM_COH_F 0x00000002 +#define GPU_GMMU_PDE_APERTURE_BIG_SYS_MEM_NCOH_F 0x00000003 +#define GPU_GMMU_PDE_SIZE_W 0x00000000 +#define GPU_GMMU_PDE_SIZE_FULL_F 0x00000000 +#define GPU_GMMU_PDE_ADDRESS_BIG_SYS_SHIFT 0x00000004 +#define GPU_GMMU_PDE_ADDRESS_BIG_SYS_FIELDMASK 0x0fffffff +#define GPU_GMMU_PDE_ADDRESS_BIG_SYS_W 0x00000000 +#define GPU_GMMU_PDE_APERTURE_SMALL_W 0x00000001 +#define GPU_GMMU_PDE_APERTURE_SMALL_INVALID_F 0x00000000 +#define GPU_GMMU_PDE_APERTURE_SMALL_VIDEO_MEMORY_F 0x00000001 +#define GPU_GMMU_PDE_APERTURE_SMALL_SYS_MEM_COH_F 0x00000002 +#define GPU_GMMU_PDE_APERTURE_SMALL_SYS_MEM_NCOH_F 0x00000003 +#define GPU_GMMU_PDE_VOL_SMALL_W 0x00000001 +#define GPU_GMMU_PDE_VOL_SMALL_TRUE_F 0x00000004 +#define GPU_GMMU_PDE_VOL_SMALL_FALSE_F 0x00000000 +#define GPU_GMMU_PDE_VOL_BIG_W 0x00000001 +#define GPU_GMMU_PDE_VOL_BIG_TRUE_F 0x00000008 +#define GPU_GMMU_PDE_VOL_BIG_FALSE_F 0x00000000 +#define GPU_GMMU_PDE_ADDRESS_SMALL_SYS_SHIFT 0x00000004 +#define GPU_GMMU_PDE_ADDRESS_SMALL_SYS_FIELDMASK 0x0fffffff +#define GPU_GMMU_PDE_ADDRESS_SMALL_SYS_W 0x00000001 +#define GPU_GMMU_PDE_ADDRESS_SHIFT_V 0x0000000c +#define GPU_GMMU_PDE__SIZE_V 0x00000008 +#define GPU_GMMU_PTE__SIZE_V 0x00000008 +#define GPU_GMMU_PTE_VALID_W 0x00000000 +#define GPU_GMMU_PTE_VALID_TRUE_F 0x00000001 +#define GPU_GMMU_PTE_VALID_FALSE_F 0x00000000 +#define GPU_GMMU_PTE_PRIVILEGE_W 0x00000000 +#define GPU_GMMU_PTE_PRIVILEGE_TRUE_F 0x00000002 +#define GPU_GMMU_PTE_PRIVILEGE_FALSE_F 0x00000000 +#define GPU_GMMU_PTE_ADDRESS_SYS_SHIFT 0x00000004 +#define GPU_GMMU_PTE_ADDRESS_SYS_FIELDMASK 0x0fffffff +#define GPU_GMMU_PTE_ADDRESS_SYS_W 0x00000000 +#define GPU_GMMU_PTE_VOL_W 0x00000001 +#define GPU_GMMU_PTE_VOL_TRUE_F 0x00000001 +#define GPU_GMMU_PTE_VOL_FALSE_F 0x00000000 +#define GPU_GMMU_PTE_APERTURE_W 0x00000001 +#define GPU_GMMU_PTE_APERTURE_VIDEO_MEMORY_F 0x00000000 +#define GPU_GMMU_PTE_APERTURE_SYS_MEM_COH_F 0x00000004 +#define GPU_GMMU_PTE_APERTURE_SYS_MEM_NCOH_F 0x00000006 +#define GPU_GMMU_PTE_READ_ONLY_W 0x00000000 +#define GPU_GMMU_PTE_READ_ONLY_TRUE_F 0x00000004 +#define GPU_GMMU_PTE_WRITE_DISABLE_W 0x00000001 +#define GPU_GMMU_PTE_WRITE_DISABLE_TRUE_F 0x80000000 +#define GPU_GMMU_PTE_READ_DISABLE_W 0x00000001 +#define GPU_GMMU_PTE_READ_DISABLE_TRUE_F 0x40000000 +#define GPU_GMMU_PTE_COMPTAGLINE_SIZE 0x00000011 +#define GPU_GMMU_PTE_COMPTAGLINE_SHIFT 0x0000000c +#define GPU_GMMU_PTE_COMPTAGLINE_FIELDMASK 0x0001ffff +#define GPU_GMMU_PTE_COMPTAGLINE_W 0x00000001 +#define GPU_GMMU_PTE_ADDRESS_SHIFT_V 0x0000000c +#define GPU_GMMU_PTE_KIND_SHIFT 0x00000004 +#define GPU_GMMU_PTE_KIND_FIELDMASK 0x000000ff +#define GPU_GMMU_PTE_KIND_W 0x00000001 +#define GPU_GMMU_PTE_KIND_INVALID_V 0x000000ff +#define GPU_GMMU_PTE_KIND_PITCH_V 0x00000000 +#define GPU_GMMU_PTE_KIND_Z16_V 0x00000001 +#define GPU_GMMU_PTE_KIND_Z16_2C_V 0x00000002 +#define GPU_GMMU_PTE_KIND_Z16_MS2_2C_V 0x00000003 +#define GPU_GMMU_PTE_KIND_Z16_MS4_2C_V 0x00000004 +#define GPU_GMMU_PTE_KIND_Z16_MS8_2C_V 0x00000005 +#define GPU_GMMU_PTE_KIND_Z16_MS16_2C_V 0x00000006 +#define GPU_GMMU_PTE_KIND_Z16_2Z_V 0x00000007 +#define GPU_GMMU_PTE_KIND_Z16_MS2_2Z_V 0x00000008 +#define GPU_GMMU_PTE_KIND_Z16_MS4_2Z_V 0x00000009 +#define GPU_GMMU_PTE_KIND_Z16_MS8_2Z_V 0x0000000a +#define GPU_GMMU_PTE_KIND_Z16_MS16_2Z_V 0x0000000b +#define GPU_GMMU_PTE_KIND_Z16_4CZ_V 0x0000000c +#define GPU_GMMU_PTE_KIND_Z16_MS2_4CZ_V 0x0000000d +#define GPU_GMMU_PTE_KIND_Z16_MS4_4CZ_V 0x0000000e +#define GPU_GMMU_PTE_KIND_Z16_MS8_4CZ_V 0x0000000f +#define GPU_GMMU_PTE_KIND_Z16_MS16_4CZ_V 0x00000010 +#define GPU_GMMU_PTE_KIND_S8Z24_V 0x00000011 +#define GPU_GMMU_PTE_KIND_S8Z24_1Z_V 0x00000012 +#define GPU_GMMU_PTE_KIND_S8Z24_MS2_1Z_V 0x00000013 +#define GPU_GMMU_PTE_KIND_S8Z24_MS4_1Z_V 0x00000014 +#define GPU_GMMU_PTE_KIND_S8Z24_MS8_1Z_V 0x00000015 +#define GPU_GMMU_PTE_KIND_S8Z24_MS16_1Z_V 0x00000016 +#define GPU_GMMU_PTE_KIND_S8Z24_2CZ_V 0x00000017 +#define GPU_GMMU_PTE_KIND_S8Z24_MS2_2CZ_V 0x00000018 +#define GPU_GMMU_PTE_KIND_S8Z24_MS4_2CZ_V 0x00000019 +#define GPU_GMMU_PTE_KIND_S8Z24_MS8_2CZ_V 0x0000001a +#define GPU_GMMU_PTE_KIND_S8Z24_MS16_2CZ_V 0x0000001b +#define GPU_GMMU_PTE_KIND_S8Z24_2CS_V 0x0000001c +#define GPU_GMMU_PTE_KIND_S8Z24_MS2_2CS_V 0x0000001d +#define GPU_GMMU_PTE_KIND_S8Z24_MS4_2CS_V 0x0000001e +#define GPU_GMMU_PTE_KIND_S8Z24_MS8_2CS_V 0x0000001f +#define GPU_GMMU_PTE_KIND_S8Z24_MS16_2CS_V 0x00000020 +#define GPU_GMMU_PTE_KIND_S8Z24_4CSZV_V 0x00000021 +#define GPU_GMMU_PTE_KIND_S8Z24_MS2_4CSZV_V 0x00000022 +#define GPU_GMMU_PTE_KIND_S8Z24_MS4_4CSZV_V 0x00000023 +#define GPU_GMMU_PTE_KIND_S8Z24_MS8_4CSZV_V 0x00000024 +#define GPU_GMMU_PTE_KIND_S8Z24_MS16_4CSZV_V 0x00000025 +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC12_V 0x00000026 +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC4_V 0x00000027 +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC8_V 0x00000028 +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC24_V 0x00000029 +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC12_1ZV_V 0x0000002e +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC4_1ZV_V 0x0000002f +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC8_1ZV_V 0x00000030 +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC24_1ZV_V 0x00000031 +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC12_2CS_V 0x00000032 +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC4_2CS_V 0x00000033 +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC8_2CS_V 0x00000034 +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC24_2CS_V 0x00000035 +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC12_2CZV_V 0x0000003a +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC4_2CZV_V 0x0000003b +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC8_2CZV_V 0x0000003c +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC24_2CZV_V 0x0000003d +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC12_2ZV_V 0x0000003e +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC4_2ZV_V 0x0000003f +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC8_2ZV_V 0x00000040 +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC24_2ZV_V 0x00000041 +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV_V 0x00000042 +#define GPU_GMMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV_V 0x00000043 +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV_V 0x00000044 +#define GPU_GMMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV_V 0x00000045 +#define GPU_GMMU_PTE_KIND_Z24S8_V 0x00000046 +#define GPU_GMMU_PTE_KIND_Z24S8_1Z_V 0x00000047 +#define GPU_GMMU_PTE_KIND_Z24S8_MS2_1Z_V 0x00000048 +#define GPU_GMMU_PTE_KIND_Z24S8_MS4_1Z_V 0x00000049 +#define GPU_GMMU_PTE_KIND_Z24S8_MS8_1Z_V 0x0000004a +#define GPU_GMMU_PTE_KIND_Z24S8_MS16_1Z_V 0x0000004b +#define GPU_GMMU_PTE_KIND_Z24S8_2CS_V 0x0000004c +#define GPU_GMMU_PTE_KIND_Z24S8_MS2_2CS_V 0x0000004d +#define GPU_GMMU_PTE_KIND_Z24S8_MS4_2CS_V 0x0000004e +#define GPU_GMMU_PTE_KIND_Z24S8_MS8_2CS_V 0x0000004f +#define GPU_GMMU_PTE_KIND_Z24S8_MS16_2CS_V 0x00000050 +#define GPU_GMMU_PTE_KIND_Z24S8_2CZ_V 0x00000051 +#define GPU_GMMU_PTE_KIND_Z24S8_MS2_2CZ_V 0x00000052 +#define GPU_GMMU_PTE_KIND_Z24S8_MS4_2CZ_V 0x00000053 +#define GPU_GMMU_PTE_KIND_Z24S8_MS8_2CZ_V 0x00000054 +#define GPU_GMMU_PTE_KIND_Z24S8_MS16_2CZ_V 0x00000055 +#define GPU_GMMU_PTE_KIND_Z24S8_4CSZV_V 0x00000056 +#define GPU_GMMU_PTE_KIND_Z24S8_MS2_4CSZV_V 0x00000057 +#define GPU_GMMU_PTE_KIND_Z24S8_MS4_4CSZV_V 0x00000058 +#define GPU_GMMU_PTE_KIND_Z24S8_MS8_4CSZV_V 0x00000059 +#define GPU_GMMU_PTE_KIND_Z24S8_MS16_4CSZV_V 0x0000005a +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC12_V 0x0000005b +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC4_V 0x0000005c +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC8_V 0x0000005d +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC24_V 0x0000005e +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC12_1ZV_V 0x00000063 +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC4_1ZV_V 0x00000064 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC8_1ZV_V 0x00000065 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC24_1ZV_V 0x00000066 +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC12_2CS_V 0x00000067 +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC4_2CS_V 0x00000068 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC8_2CS_V 0x00000069 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC24_2CS_V 0x0000006a +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC12_2CZV_V 0x0000006f +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC4_2CZV_V 0x00000070 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC8_2CZV_V 0x00000071 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC24_2CZV_V 0x00000072 +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC12_2ZV_V 0x00000073 +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC4_2ZV_V 0x00000074 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC8_2ZV_V 0x00000075 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC24_2ZV_V 0x00000076 +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV_V 0x00000077 +#define GPU_GMMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV_V 0x00000078 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV_V 0x00000079 +#define GPU_GMMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV_V 0x0000007a +#define GPU_GMMU_PTE_KIND_ZF32_V 0x0000007b +#define GPU_GMMU_PTE_KIND_ZF32_1Z_V 0x0000007c +#define GPU_GMMU_PTE_KIND_ZF32_MS2_1Z_V 0x0000007d +#define GPU_GMMU_PTE_KIND_ZF32_MS4_1Z_V 0x0000007e +#define GPU_GMMU_PTE_KIND_ZF32_MS8_1Z_V 0x0000007f +#define GPU_GMMU_PTE_KIND_ZF32_MS16_1Z_V 0x00000080 +#define GPU_GMMU_PTE_KIND_ZF32_2CS_V 0x00000081 +#define GPU_GMMU_PTE_KIND_ZF32_MS2_2CS_V 0x00000082 +#define GPU_GMMU_PTE_KIND_ZF32_MS4_2CS_V 0x00000083 +#define GPU_GMMU_PTE_KIND_ZF32_MS8_2CS_V 0x00000084 +#define GPU_GMMU_PTE_KIND_ZF32_MS16_2CS_V 0x00000085 +#define GPU_GMMU_PTE_KIND_ZF32_2CZ_V 0x00000086 +#define GPU_GMMU_PTE_KIND_ZF32_MS2_2CZ_V 0x00000087 +#define GPU_GMMU_PTE_KIND_ZF32_MS4_2CZ_V 0x00000088 +#define GPU_GMMU_PTE_KIND_ZF32_MS8_2CZ_V 0x00000089 +#define GPU_GMMU_PTE_KIND_ZF32_MS16_2CZ_V 0x0000008a +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_V 0x0000008b +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_V 0x0000008c +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_V 0x0000008d +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_V 0x0000008e +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS_V 0x0000008f +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS_V 0x00000090 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS_V 0x00000091 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS_V 0x00000092 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV_V 0x00000097 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV_V 0x00000098 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV_V 0x00000099 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV_V 0x0000009a +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV_V 0x0000009b +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV_V 0x0000009c +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV_V 0x0000009d +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV_V 0x0000009e +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS_V 0x0000009f +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS_V 0x000000a0 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS_V 0x000000a1 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS_V 0x000000a2 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV_V 0x000000a3 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV_V 0x000000a4 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV_V 0x000000a5 +#define GPU_GMMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV_V 0x000000a6 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_V 0x000000a7 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_V 0x000000a8 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_V 0x000000a9 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_V 0x000000aa +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS_V 0x000000ab +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS_V 0x000000ac +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS_V 0x000000ad +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS_V 0x000000ae +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV_V 0x000000b3 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV_V 0x000000b4 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV_V 0x000000b5 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV_V 0x000000b6 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV_V 0x000000b7 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV_V 0x000000b8 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV_V 0x000000b9 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV_V 0x000000ba +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS_V 0x000000bb +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS_V 0x000000bc +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS_V 0x000000bd +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS_V 0x000000be +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV_V 0x000000bf +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV_V 0x000000c0 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV_V 0x000000c1 +#define GPU_GMMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV_V 0x000000c2 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_V 0x000000c3 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_1CS_V 0x000000c4 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS2_1CS_V 0x000000c5 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS4_1CS_V 0x000000c6 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS8_1CS_V 0x000000c7 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS16_1CS_V 0x000000c8 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_2CSZV_V 0x000000ce +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV_V 0x000000cf +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV_V 0x000000d0 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV_V 0x000000d1 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV_V 0x000000d2 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_2CS_V 0x000000d3 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS2_2CS_V 0x000000d4 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS4_2CS_V 0x000000d5 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS8_2CS_V 0x000000d6 +#define GPU_GMMU_PTE_KIND_ZF32_X24S8_MS16_2CS_V 0x000000d7 +#define GPU_GMMU_PTE_KIND_GENERIC_16BX2_V 0x000000fe +#define GPU_GMMU_PTE_KIND_C32_2C_V 0x000000d8 +#define GPU_GMMU_PTE_KIND_C32_2CBR_V 0x000000d9 +#define GPU_GMMU_PTE_KIND_C32_2CBA_V 0x000000da +#define GPU_GMMU_PTE_KIND_C32_2CRA_V 0x000000db +#define GPU_GMMU_PTE_KIND_C32_2BRA_V 0x000000dc +#define GPU_GMMU_PTE_KIND_C32_MS2_2C_V 0x000000dd +#define GPU_GMMU_PTE_KIND_C32_MS2_2CBR_V 0x000000de +#define GPU_GMMU_PTE_KIND_C32_MS2_2CRA_V 0x000000cc +#define GPU_GMMU_PTE_KIND_C32_MS4_2C_V 0x000000df +#define GPU_GMMU_PTE_KIND_C32_MS4_2CBR_V 0x000000e0 +#define GPU_GMMU_PTE_KIND_C32_MS4_2CBA_V 0x000000e1 +#define GPU_GMMU_PTE_KIND_C32_MS4_2CRA_V 0x000000e2 +#define GPU_GMMU_PTE_KIND_C32_MS4_2BRA_V 0x000000e3 +#define GPU_GMMU_PTE_KIND_C32_MS8_MS16_2C_V 0x000000e4 +#define GPU_GMMU_PTE_KIND_C32_MS8_MS16_2CRA_V 0x000000e5 +#define GPU_GMMU_PTE_KIND_C64_2C_V 0x000000e6 +#define GPU_GMMU_PTE_KIND_C64_2CBR_V 0x000000e7 +#define GPU_GMMU_PTE_KIND_C64_2CBA_V 0x000000e8 +#define GPU_GMMU_PTE_KIND_C64_2CRA_V 0x000000e9 +#define GPU_GMMU_PTE_KIND_C64_2BRA_V 0x000000ea +#define GPU_GMMU_PTE_KIND_C64_MS2_2C_V 0x000000eb +#define GPU_GMMU_PTE_KIND_C64_MS2_2CBR_V 0x000000ec +#define GPU_GMMU_PTE_KIND_C64_MS2_2CRA_V 0x000000cd +#define GPU_GMMU_PTE_KIND_C64_MS4_2C_V 0x000000ed +#define GPU_GMMU_PTE_KIND_C64_MS4_2CBR_V 0x000000ee +#define GPU_GMMU_PTE_KIND_C64_MS4_2CBA_V 0x000000ef +#define GPU_GMMU_PTE_KIND_C64_MS4_2CRA_V 0x000000f0 +#define GPU_GMMU_PTE_KIND_C64_MS4_2BRA_V 0x000000f1 +#define GPU_GMMU_PTE_KIND_C64_MS8_MS16_2C_V 0x000000f2 +#define GPU_GMMU_PTE_KIND_C64_MS8_MS16_2CRA_V 0x000000f3 +#define GPU_GMMU_PTE_KIND_C128_2C_V 0x000000f4 +#define GPU_GMMU_PTE_KIND_C128_2CR_V 0x000000f5 +#define GPU_GMMU_PTE_KIND_C128_MS2_2C_V 0x000000f6 +#define GPU_GMMU_PTE_KIND_C128_MS2_2CR_V 0x000000f7 +#define GPU_GMMU_PTE_KIND_C128_MS4_2C_V 0x000000f8 +#define GPU_GMMU_PTE_KIND_C128_MS4_2CR_V 0x000000f9 +#define GPU_GMMU_PTE_KIND_C128_MS8_MS16_2C_V 0x000000fa +#define GPU_GMMU_PTE_KIND_C128_MS8_MS16_2CR_V 0x000000fb +#define GPU_GMMU_PTE_KIND_X8C24_V 0x000000fc +#define GPU_GMMU_PTE_KIND_PITCH_NO_SWIZZLE_V 0x000000fd +#define GPU_GMMU_PTE_KIND_SMSKED_MESSAGE_V 0x000000ca +#define GPU_GMMU_PTE_KIND_SMHOST_MESSAGE_V 0x000000cb +#define GPU_GMMU_PTE_KIND_S8_V 0x0000002a +#define GPU_GMMU_PTE_KIND_S8_2S_V 0x0000002b + +#define GPU_GR_INTR 0x00400100 +#define GPU_GR_INTR_NOTIFY_PENDING_F 0x00000001 +#define GPU_GR_INTR_NOTIFY_RESET_F 0x00000001 +#define GPU_GR_INTR_SEMAPHORE_PENDING_F 0x00000002 +#define GPU_GR_INTR_SEMAPHORE_RESET_F 0x00000002 +#define GPU_GR_INTR_ILLEGAL_METHOD_PENDING_F 0x00000010 +#define GPU_GR_INTR_ILLEGAL_METHOD_RESET_F 0x00000010 +#define GPU_GR_INTR_ILLEGAL_NOTIFY_PENDING_F 0x00000040 +#define GPU_GR_INTR_ILLEGAL_NOTIFY_RESET_F 0x00000040 +#define GPU_GR_INTR_FIRMWARE_METHOD_SHIFT 0x00000008 +#define GPU_GR_INTR_FIRMWARE_METHOD_FIELDMASK 0x00000001 +#define GPU_GR_INTR_FIRMWARE_METHOD_PENDING_F 0x00000100 +#define GPU_GR_INTR_FIRMWARE_METHOD_RESET_F 0x00000100 +#define GPU_GR_INTR_ILLEGAL_CLASS_PENDING_F 0x00000020 +#define GPU_GR_INTR_ILLEGAL_CLASS_RESET_F 0x00000020 +#define GPU_GR_INTR_FECS_ERROR_PENDING_F 0x00080000 +#define GPU_GR_INTR_FECS_ERROR_RESET_F 0x00080000 +#define GPU_GR_INTR_CLASS_ERROR_PENDING_F 0x00100000 +#define GPU_GR_INTR_CLASS_ERROR_RESET_F 0x00100000 +#define GPU_GR_INTR_EXCEPTION_PENDING_F 0x00200000 +#define GPU_GR_INTR_EXCEPTION_RESET_F 0x00200000 +#define GPU_GR_FECS_INTR 0x00400144 +#define GPU_GR_CLASS_ERROR 0x00400110 +#define GPU_GR_CLASS_ERROR_CODE_SHIFT 0x00000000 +#define GPU_GR_CLASS_ERROR_CODE_FIELDMASK 0x0000ffff +#define GPU_GR_INTR_NONSTALL 0x00400120 +#define GPU_GR_INTR_NONSTALL_TRAP_PENDING_F 0x00000002 +#define GPU_GR_INTR_EN 0x0040013c +#define GPU_GR_EXCEPTION 0x00400108 +#define GPU_GR_EXCEPTION_FE_MASK 0x00000001 +#define GPU_GR_EXCEPTION_FE_SHIFT 0x00000000 +#define GPU_GR_EXCEPTION_FE_FIELDMASK 0x00000001 +#define GPU_GR_EXCEPTION_GPC_MASK 0x01000000 +#define GPU_GR_EXCEPTION_GPC_SHIFT 0x00000018 +#define GPU_GR_EXCEPTION_GPC_FIELDMASK 0x00000001 +#define GPU_GR_EXCEPTION_MEMFMT_MASK 0x00000002 +#define GPU_GR_EXCEPTION_MEMFMT_SHIFT 0x00000001 +#define GPU_GR_EXCEPTION_MEMFMT_FIELDMASK 0x00000001 +#define GPU_GR_EXCEPTION_DS_MASK 0x00000010 +#define GPU_GR_EXCEPTION_DS_SHIFT 0x00000004 +#define GPU_GR_EXCEPTION_DS_FIELDMASK 0x00000001 +#define GPU_GR_EXCEPTION1 0x00400118 +#define GPU_GR_EXCEPTION1_GPC_0_PENDING_F 0x00000001 +#define GPU_GR_EXCEPTION2 0x0040011c +#define GPU_GR_EXCEPTION_EN 0x00400138 +#define GPU_GR_EXCEPTION_EN_FE_MASK 0x00000001 +#define GPU_GR_EXCEPTION_EN_FE_SHIFT 0x00000000 +#define GPU_GR_EXCEPTION_EN_FE_FIELDMASK 0x00000001 +#define GPU_GR_EXCEPTION1_EN 0x00400130 +#define GPU_GR_EXCEPTION2_EN 0x00400134 +#define GPU_GR_GPFIFO_CTL 0x00400500 +#define GPU_GR_GPFIFO_CTL_ACCESS_SHIFT 0x00000000 +#define GPU_GR_GPFIFO_CTL_ACCESS_FIELDMASK 0x00000001 +#define GPU_GR_GPFIFO_CTL_ACCESS_DISABLED_F 0x00000000 +#define GPU_GR_GPFIFO_CTL_ACCESS_ENABLED_F 0x00000001 +#define GPU_GR_GPFIFO_CTL_SEMAPHORE_ACCESS_SHIFT 0x00000010 +#define GPU_GR_GPFIFO_CTL_SEMAPHORE_ACCESS_FIELDMASK 0x00000001 +#define GPU_GR_GPFIFO_CTL_SEMAPHORE_ACCESS_ENABLED_V 0x00000001 +#define GPU_GR_GPFIFO_CTL_SEMAPHORE_ACCESS_ENABLED_F 0x00010000 +#define GPU_GR_GPFIFO_STATUS 0x00400504 +#define GPU_GR_TRAPPED_ADDR 0x00400704 +#define GPU_GR_TRAPPED_ADDR_MTHD_SHIFT 0x00000002 +#define GPU_GR_TRAPPED_ADDR_MTHD_FIELDMASK 0x00000fff +#define GPU_GR_TRAPPED_ADDR_SUBCH_SHIFT 0x00000010 +#define GPU_GR_TRAPPED_ADDR_SUBCH_FIELDMASK 0x00000007 +#define GPU_GR_TRAPPED_DATA_LO 0x00400708 +#define GPU_GR_TRAPPED_DATA_HI 0x0040070c +#define GPU_GR_STATUS 0x00400700 +#define GPU_GR_STATUS_FE_METHOD_UPPER_SHIFT 0x00000001 +#define GPU_GR_STATUS_FE_METHOD_UPPER_FIELDMASK 0x00000001 +#define GPU_GR_STATUS_FE_METHOD_LOWER_SHIFT 0x00000002 +#define GPU_GR_STATUS_FE_METHOD_LOWER_FIELDMASK 0x00000001 +#define GPU_GR_STATUS_FE_METHOD_LOWER_IDLE_V 0x00000000 +#define GPU_GR_STATUS_FE_GI_SHIFT 0x00000015 +#define GPU_GR_STATUS_FE_GI_FIELDMASK 0x00000001 +#define GPU_GR_STATUS_MASK 0x00400610 +#define GPU_GR_STATUS_1 0x00400604 +#define GPU_GR_STATUS_2 0x00400608 +#define GPU_GR_ENGINE_STATUS 0x0040060c +#define GPU_GR_ENGINE_STATUS_VALUE_BUSY_F 0x00000001 +#define GPU_GR_PRI_BE0_BECS_BE_EXCEPTION 0x00410204 +#define GPU_GR_PRI_BE0_BECS_BE_EXCEPTION_EN 0x00410208 +#define GPU_GR_PRI_GPC0_GPCCS_GPC_EXCEPTION 0x00502c90 +#define GPU_GR_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN 0x00502c94 +#define GPU_GR_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x00504508 +#define GPU_GR_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x0050450c +#define GPU_GR_ACTIVITY_0 0x00400380 +#define GPU_GR_ACTIVITY_1 0x00400384 +#define GPU_GR_ACTIVITY_2 0x00400388 +#define GPU_GR_ACTIVITY_4 0x00400390 +#define GPU_GR_PRI_GPC0_GCC_DBG 0x00501000 +#define GPU_GR_PRI_GPCS_GCC_DBG 0x00419000 +#define GPU_GR_PRI_GPCS_GCC_DBG_INVALIDATE_MASK 0x00000002 +#define GPU_GR_PRI_GPCS_GCC_DBG_INVALIDATE_SHIFT 0x00000001 +#define GPU_GR_PRI_GPCS_GCC_DBG_INVALIDATE_FIELDMASK 0x00000001 +#define GPU_GR_PRI_GPC0_TPC0_SM_CACHE_CONTROL 0x005046a4 +#define GPU_GR_PRI_GPCS_TPCS_SM_CACHE_CONTROL 0x00419ea4 +#define GPU_GR_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_CACHE_MASK 0x00000001 +#define GPU_GR_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_CACHE_SHIFT 0x00000000 +#define GPU_GR_PRI_GPCS_TPCS_SM_CACHE_CONTROL_INVALIDATE_CACHE_FIELDMASK 0x00000001 +#define GPU_GR_PRI_SKED_ACTIVITY 0x00407054 +#define GPU_GR_PRI_GPC0_GPCCS_GPC_ACTIVITY0 0x00502c80 +#define GPU_GR_PRI_GPC0_GPCCS_GPC_ACTIVITY1 0x00502c84 +#define GPU_GR_PRI_GPC0_GPCCS_GPC_ACTIVITY2 0x00502c88 +#define GPU_GR_PRI_GPC0_GPCCS_GPC_ACTIVITY3 0x00502c8c +#define GPU_GR_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY_0 0x00504500 +#define GPU_GR_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY_0 0x00504d00 +#define GPU_GR_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY_0 0x00501d00 +#define GPU_GR_PRI_GPCS_GPCCS_GPC_ACTIVITY_0 0x0041ac80 +#define GPU_GR_PRI_GPCS_GPCCS_GPC_ACTIVITY_1 0x0041ac84 +#define GPU_GR_PRI_GPCS_GPCCS_GPC_ACTIVITY_2 0x0041ac88 +#define GPU_GR_PRI_GPCS_GPCCS_GPC_ACTIVITY_3 0x0041ac8c +#define GPU_GR_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY_0 0x0041c500 +#define GPU_GR_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY_0 0x0041cd00 +#define GPU_GR_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY_0 0x00419d00 +#define GPU_GR_PRI_BE0_BECS_BE_ACTIVITY0 0x00410200 +#define GPU_GR_PRI_BE1_BECS_BE_ACTIVITY0 0x00410600 +#define GPU_GR_PRI_BES_BECS_BE_ACTIVITY0 0x00408a00 +#define GPU_GR_PRI_DS_MPIPE_STATUS 0x00405858 +#define GPU_GR_PRI_FE_GO_IDLE_ON_STATUS 0x00404150 +#define GPU_GR_PRI_FE_GO_IDLE_CHECK 0x00404158 +#define GPU_GR_PRI_FE_GO_IDLE_INFO 0x00404194 +#define GPU_GR_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS 0x00504238 +#define GPU_GR_PRI_BE0_CROP_STATUS1 0x00410134 +#define GPU_GR_PRI_BES_CROP_STATUS1 0x00408934 +#define GPU_GR_PRI_BE0_ZROP_STATUS 0x00410048 +#define GPU_GR_PRI_BE0_ZROP_STATUS2 0x0041004c +#define GPU_GR_PRI_BES_ZROP_STATUS 0x00408848 +#define GPU_GR_PRI_BES_ZROP_STATUS2 0x0040884c +#define GPU_GR_PIPE_BUNDLE_ADDRESS 0x00400200 +#define GPU_GR_PIPE_BUNDLE_ADDRESS_VALUE_SHIFT 0x00000000 +#define GPU_GR_PIPE_BUNDLE_ADDRESS_VALUE_FIELDMASK 0x0000ffff +#define GPU_GR_PIPE_BUNDLE_DATA 0x00400204 +#define GPU_GR_PIPE_BUNDLE_CONFIG 0x00400208 +#define GPU_GR_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE_DISABLED_F 0x00000000 +#define GPU_GR_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE_ENABLED_F 0x80000000 +#define GPU_GR_FE_HWW_ESR 0x00404000 +#define GPU_GR_FE_HWW_ESR_RESET_ACTIVE_F 0x40000000 +#define GPU_GR_FE_HWW_ESR_EN_ENABLE_F 0x80000000 +#define GPU_GR_FE_GO_IDLE_TIMEOUT 0x00404154 +#define GPU_GR_FE_GO_IDLE_TIMEOUT_COUNT_SHIFT 0x00000000 +#define GPU_GR_FE_GO_IDLE_TIMEOUT_COUNT_FIELDMASK 0xffffffff +#define GPU_GR_FE_GO_IDLE_TIMEOUT_COUNT_DISABLED_F 0x00000000 +#define GPU_GR_FE_GO_IDLE_TIMEOUT_COUNT_PROD_F 0x00000800 +#define GPU_GR_FE_OBJECT_TABLE__BASE 0x00404200 +#define GPU_GR_FE_OBJECT_TABLE__STRIDE 0x00000004 +#define GPU_GR_FE_OBJECT_TABLE(i) (0x00404200 + (i) * 0x00000004) +#define GPU_GR_FE_OBJECT_TABLE_NVCLASS_SHIFT 0x00000000 +#define GPU_GR_FE_OBJECT_TABLE_NVCLASS_FIELDMASK 0x0000ffff +#define GPU_GR_FE_TPC_FS 0x004041c4 +#define GPU_GR_PRI_MME_SHADOW_RAW_INDEX 0x00404488 +#define GPU_GR_PRI_MME_SHADOW_RAW_INDEX_WRITE_TRIGGER_F 0x80000000 +#define GPU_GR_PRI_MME_SHADOW_RAW_DATA 0x0040448c +#define GPU_GR_MME_HWW_ESR 0x00404490 +#define GPU_GR_MME_HWW_ESR_RESET_ACTIVE_F 0x40000000 +#define GPU_GR_MME_HWW_ESR_EN_ENABLE_F 0x80000000 +#define GPU_GR_MEMFMT_HWW_ESR 0x00404600 +#define GPU_GR_MEMFMT_HWW_ESR_RESET_ACTIVE_F 0x40000000 +#define GPU_GR_MEMFMT_HWW_ESR_EN_ENABLE_F 0x80000000 +#define GPU_GR_FECS_CPUCTL 0x00409100 +#define GPU_GR_FECS_CPUCTL_STARTCPU_SHIFT 0x00000001 +#define GPU_GR_FECS_CPUCTL_STARTCPU_FIELDMASK 0x00000001 +#define GPU_GR_FECS_CPUCTL_ALIAS 0x00409130 +#define GPU_GR_FECS_CPUCTL_ALIAS_STARTCPU_SHIFT 0x00000001 +#define GPU_GR_FECS_CPUCTL_ALIAS_STARTCPU_FIELDMASK 0x00000001 +#define GPU_GR_FECS_DMACTL 0x0040910c +#define GPU_GR_FECS_DMACTL_REQUIRE_CTX_SHIFT 0x00000000 +#define GPU_GR_FECS_DMACTL_REQUIRE_CTX_FIELDMASK 0x00000001 +#define GPU_GR_FECS_DMACTL_DMEM_SCRUBBING_MASK 0x00000002 +#define GPU_GR_FECS_DMACTL_DMEM_SCRUBBING_SHIFT 0x00000001 +#define GPU_GR_FECS_DMACTL_DMEM_SCRUBBING_FIELDMASK 0x00000001 +#define GPU_GR_FECS_DMACTL_IMEM_SCRUBBING_MASK 0x00000004 +#define GPU_GR_FECS_DMACTL_IMEM_SCRUBBING_SHIFT 0x00000002 +#define GPU_GR_FECS_DMACTL_IMEM_SCRUBBING_FIELDMASK 0x00000001 +#define GPU_GR_FECS_OS 0x00409080 +#define GPU_GR_FECS_IDLESTATE 0x0040904c +#define GPU_GR_FECS_MAILBOX0 0x00409040 +#define GPU_GR_FECS_MAILBOX1 0x00409044 +#define GPU_GR_FECS_IRQSTAT 0x00409008 +#define GPU_GR_FECS_IRQMODE 0x0040900c +#define GPU_GR_FECS_IRQMASK 0x00409018 +#define GPU_GR_FECS_IRQDEST 0x0040901c +#define GPU_GR_FECS_CURCTX 0x00409050 +#define GPU_GR_FECS_NXTCTX 0x00409054 +#define GPU_GR_FECS_ENGCTL 0x004090a4 +#define GPU_GR_FECS_DEBUG1 0x00409090 +#define GPU_GR_FECS_DEBUGINFO 0x00409094 +#define GPU_GR_FECS_ICD_CMD 0x00409200 +#define GPU_GR_FECS_ICD_CMD_OPC_SIZE 0x00000004 +#define GPU_GR_FECS_ICD_CMD_OPC_SHIFT 0x00000000 +#define GPU_GR_FECS_ICD_CMD_OPC_FIELDMASK 0x0000000f +#define GPU_GR_FECS_ICD_CMD_OPC_MASK 0x0000000f +#define GPU_GR_FECS_ICD_CMD_OPC_RREG_F 0x00000008 +#define GPU_GR_FECS_ICD_CMD_OPC_RSTAT_F 0x0000000e +#define GPU_GR_FECS_ICD_CMD_IDX_SHIFT 0x00000008 +#define GPU_GR_FECS_ICD_CMD_IDX_FIELDMASK 0x0000001f +#define GPU_GR_FECS_ICD_RDATA 0x0040920c +#define GPU_GR_FECS_IMEMC__BASE 0x00409180 +#define GPU_GR_FECS_IMEMC__STRIDE 0x00000010 +#define GPU_GR_FECS_IMEMC(i) (0x00409180 + (i) * 0x00000010) +#define GPU_GR_FECS_IMEMC_OFFS_SHIFT 0x00000002 +#define GPU_GR_FECS_IMEMC_OFFS_FIELDMASK 0x0000003f +#define GPU_GR_FECS_IMEMC_BLK_SHIFT 0x00000008 +#define GPU_GR_FECS_IMEMC_BLK_FIELDMASK 0x000000ff +#define GPU_GR_FECS_IMEMC_AINCW_SHIFT 0x00000018 +#define GPU_GR_FECS_IMEMC_AINCW_FIELDMASK 0x00000001 +#define GPU_GR_FECS_IMEMD__BASE 0x00409184 +#define GPU_GR_FECS_IMEMD__STRIDE 0x00000010 +#define GPU_GR_FECS_IMEMD(i) (0x00409184 + (i) * 0x00000010) +#define GPU_GR_FECS_IMEMT__BASE 0x00409188 +#define GPU_GR_FECS_IMEMT__STRIDE 0x00000010 +#define GPU_GR_FECS_IMEMT(i) (0x00409188 + (i) * 0x00000010) +#define GPU_GR_FECS_IMEMT_TAG_SHIFT 0x00000000 +#define GPU_GR_FECS_IMEMT_TAG_FIELDMASK 0x0000ffff +#define GPU_GR_FECS_DMEMC__BASE 0x004091c0 +#define GPU_GR_FECS_DMEMC__STRIDE 0x00000008 +#define GPU_GR_FECS_DMEMC(i) (0x004091c0 + (i) * 0x00000008) +#define GPU_GR_FECS_DMEMC_OFFS_SIZE 0x00000006 +#define GPU_GR_FECS_DMEMC_OFFS_SHIFT 0x00000002 +#define GPU_GR_FECS_DMEMC_OFFS_FIELDMASK 0x0000003f +#define GPU_GR_FECS_DMEMC_OFFS_MASK 0x000000fc +#define GPU_GR_FECS_DMEMC_BLK_SHIFT 0x00000008 +#define GPU_GR_FECS_DMEMC_BLK_FIELDMASK 0x000000ff +#define GPU_GR_FECS_DMEMC_AINCW_SHIFT 0x00000018 +#define GPU_GR_FECS_DMEMC_AINCW_FIELDMASK 0x00000001 +#define GPU_GR_FECS_DMEMD__BASE 0x004091c4 +#define GPU_GR_FECS_DMEMD__STRIDE 0x00000008 +#define GPU_GR_FECS_DMEMD(i) (0x004091c4 + (i) * 0x00000008) +#define GPU_GR_FECS_DMATRFBASE 0x00409110 +#define GPU_GR_FECS_DMATRFMOFFS 0x00409114 +#define GPU_GR_FECS_DMATRFFBOFFS 0x0040911c +#define GPU_GR_FECS_DMATRFCMD 0x00409118 +#define GPU_GR_FECS_DMATRFCMD_IMEM_SHIFT 0x00000004 +#define GPU_GR_FECS_DMATRFCMD_IMEM_FIELDMASK 0x00000001 +#define GPU_GR_FECS_DMATRFCMD_WRITE_SHIFT 0x00000005 +#define GPU_GR_FECS_DMATRFCMD_WRITE_FIELDMASK 0x00000001 +#define GPU_GR_FECS_DMATRFCMD_SIZE_SHIFT 0x00000008 +#define GPU_GR_FECS_DMATRFCMD_SIZE_FIELDMASK 0x00000007 +#define GPU_GR_FECS_DMATRFCMD_CTXDMA_SHIFT 0x0000000c +#define GPU_GR_FECS_DMATRFCMD_CTXDMA_FIELDMASK 0x00000007 +#define GPU_GR_FECS_BOOTVEC 0x00409104 +#define GPU_GR_FECS_BOOTVEC_VEC_SHIFT 0x00000000 +#define GPU_GR_FECS_BOOTVEC_VEC_FIELDMASK 0xffffffff +#define GPU_GR_FECS_FALCON_HWCFG 0x00409108 +#define GPU_GR_GPCS_GPCCS_FALCON_HWCFG 0x0041a108 +#define GPU_GR_FECS_FALCON_RM 0x00409084 +#define GPU_GR_FECS_CURRENT_CTX 0x00409b00 +#define GPU_GR_FECS_CURRENT_CTX_PTR_SHIFT 0x00000000 +#define GPU_GR_FECS_CURRENT_CTX_PTR_FIELDMASK 0x0fffffff +#define GPU_GR_FECS_CURRENT_CTX_TARGET_SIZE 0x00000002 +#define GPU_GR_FECS_CURRENT_CTX_TARGET_SHIFT 0x0000001c +#define GPU_GR_FECS_CURRENT_CTX_TARGET_FIELDMASK 0x00000003 +#define GPU_GR_FECS_CURRENT_CTX_TARGET_MASK 0x30000000 +#define GPU_GR_FECS_CURRENT_CTX_TARGET_VID_MEM_F 0x00000000 +#define GPU_GR_FECS_CURRENT_CTX_TARGET_SYS_MEM_COH_F 0x20000000 +#define GPU_GR_FECS_CURRENT_CTX_TARGET_SYS_MEM_NCOH_F 0x30000000 +#define GPU_GR_FECS_CURRENT_CTX_VALID_SIZE 0x00000001 +#define GPU_GR_FECS_CURRENT_CTX_VALID_SHIFT 0x0000001f +#define GPU_GR_FECS_CURRENT_CTX_VALID_FIELDMASK 0x00000001 +#define GPU_GR_FECS_CURRENT_CTX_VALID_MASK 0x80000000 +#define GPU_GR_FECS_CURRENT_CTX_VALID_FALSE_F 0x00000000 +#define GPU_GR_FECS_METHOD_DATA 0x00409500 +#define GPU_GR_FECS_METHOD_PUSH 0x00409504 +#define GPU_GR_FECS_METHOD_PUSH_ADR_SHIFT 0x00000000 +#define GPU_GR_FECS_METHOD_PUSH_ADR_FIELDMASK 0x00000fff +#define GPU_GR_FECS_METHOD_PUSH_ADR_BIND_POINTER_V 0x00000003 +#define GPU_GR_FECS_METHOD_PUSH_ADR_BIND_POINTER_F 0x00000003 +#define GPU_GR_FECS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE_V 0x00000010 +#define GPU_GR_FECS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE_V 0x00000009 +#define GPU_GR_FECS_METHOD_PUSH_ADR_RESTORE_GOLDEN_V 0x00000015 +#define GPU_GR_FECS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE_V 0x00000016 +#define GPU_GR_FECS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE_V 0x00000025 +#define GPU_GR_FECS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE_V 0x00000030 +#define GPU_GR_FECS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE_V 0x00000031 +#define GPU_GR_FECS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS_V 0x00000032 +#define GPU_GR_FECS_METHOD_PUSH_ADR_STOP_CTXSW_V 0x00000038 +#define GPU_GR_FECS_METHOD_PUSH_ADR_START_CTXSW_V 0x00000039 +#define GPU_GR_FECS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT_F 0x00000021 +#define GPU_GR_FECS_METHOD_PUSH_ADR_WRITE_TIMESTAMP_RECORD_V 0x0000003d +#define GPU_GR_FECS_METHOD_PUSH_ADR_HALT_PIPELINE_V 0x00000004 +#define GPU_GR_FECS_HOST_INT_STATUS 0x00409c18 +#define GPU_GR_FECS_HOST_INT_STATUS_FAULT_DURING_CTXSW_SHIFT 0x00000010 +#define GPU_GR_FECS_HOST_INT_STATUS_FAULT_DURING_CTXSW_FIELDMASK 0x00000001 +#define GPU_GR_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD_SHIFT 0x00000011 +#define GPU_GR_FECS_HOST_INT_STATUS_UMIMP_FIRMWARE_METHOD_FIELDMASK 0x00000001 +#define GPU_GR_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD_SHIFT 0x00000012 +#define GPU_GR_FECS_HOST_INT_STATUS_UMIMP_ILLEGAL_METHOD_FIELDMASK 0x00000001 +#define GPU_GR_FECS_HOST_INT_STATUS_CTXSW_INTR_SHIFT 0x00000000 +#define GPU_GR_FECS_HOST_INT_STATUS_CTXSW_INTR_FIELDMASK 0x0000ffff +#define GPU_GR_FECS_HOST_INT_CLEAR 0x00409c20 +#define GPU_GR_FECS_HOST_INT_CLEAR_CTXSW_INTR1_SHIFT 0x00000001 +#define GPU_GR_FECS_HOST_INT_CLEAR_CTXSW_INTR1_FIELDMASK 0x00000001 +#define GPU_GR_FECS_HOST_INT_CLEAR_CTXSW_INTR1_CLEAR_F 0x00000002 +#define GPU_GR_FECS_HOST_INT_ENABLE 0x00409c24 +#define GPU_GR_FECS_HOST_INT_ENABLE_CTXSW_INTR1_ENABLE_F 0x00000002 +#define GPU_GR_FECS_HOST_INT_ENABLE_FAULT_DURING_CTXSW_ENABLE_F 0x00010000 +#define GPU_GR_FECS_HOST_INT_ENABLE_UMIMP_FIRMWARE_METHOD_ENABLE_F 0x00020000 +#define GPU_GR_FECS_HOST_INT_ENABLE_UMIMP_ILLEGAL_METHOD_ENABLE_F 0x00040000 +#define GPU_GR_FECS_HOST_INT_ENABLE_WATCHDOG_ENABLE_F 0x00080000 +#define GPU_GR_FECS_CTXSW_RESET_CTL 0x00409614 +#define GPU_GR_FECS_CTXSW_RESET_CTL_SYS_HALT_DISABLED_F 0x00000000 +#define GPU_GR_FECS_CTXSW_RESET_CTL_GPC_HALT_DISABLED_F 0x00000000 +#define GPU_GR_FECS_CTXSW_RESET_CTL_BE_HALT_DISABLED_F 0x00000000 +#define GPU_GR_FECS_CTXSW_RESET_CTL_SYS_ENGINE_RESET_DISABLED_F 0x00000010 +#define GPU_GR_FECS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED_F 0x00000020 +#define GPU_GR_FECS_CTXSW_RESET_CTL_BE_ENGINE_RESET_DISABLED_F 0x00000040 +#define GPU_GR_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_ENABLED_F 0x00000000 +#define GPU_GR_FECS_CTXSW_RESET_CTL_SYS_CONTEXT_RESET_DISABLED_F 0x00000100 +#define GPU_GR_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED_F 0x00000000 +#define GPU_GR_FECS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED_F 0x00000200 +#define GPU_GR_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_SIZE 0x00000001 +#define GPU_GR_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_SHIFT 0x0000000a +#define GPU_GR_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_FIELDMASK 0x00000001 +#define GPU_GR_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_MASK 0x00000400 +#define GPU_GR_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_ENABLED_F 0x00000000 +#define GPU_GR_FECS_CTXSW_RESET_CTL_BE_CONTEXT_RESET_DISABLED_F 0x00000400 +#define GPU_GR_FECS_CTX_STATE_STORE_MAJOR_REV_ID 0x0040960c +#define GPU_GR_FECS_CTXSW_MAILBOX__BASE 0x00409800 +#define GPU_GR_FECS_CTXSW_MAILBOX__STRIDE 0x00000004 +#define GPU_GR_FECS_CTXSW_MAILBOX(i) (0x00409800 + (i) * 0x00000004) +#define GPU_GR_FECS_CTXSW_MAILBOX__SIZE_1_V 0x00000010 +#define GPU_GR_FECS_CTXSW_MAILBOX_VALUE_SHIFT 0x00000000 +#define GPU_GR_FECS_CTXSW_MAILBOX_VALUE_FIELDMASK 0xffffffff +#define GPU_GR_FECS_CTXSW_MAILBOX_VALUE_PASS_V 0x00000001 +#define GPU_GR_FECS_CTXSW_MAILBOX_VALUE_FAIL_V 0x00000002 +#define GPU_GR_FECS_CTXSW_MAILBOX_SET__BASE 0x004098c0 +#define GPU_GR_FECS_CTXSW_MAILBOX_SET__STRIDE 0x00000004 +#define GPU_GR_FECS_CTXSW_MAILBOX_SET(i) (0x004098c0 + (i) * 0x00000004) +#define GPU_GR_FECS_CTXSW_MAILBOX_SET_VALUE_SHIFT 0x00000000 +#define GPU_GR_FECS_CTXSW_MAILBOX_SET_VALUE_FIELDMASK 0xffffffff +#define GPU_GR_FECS_CTXSW_MAILBOX_CLEAR__BASE 0x00409840 +#define GPU_GR_FECS_CTXSW_MAILBOX_CLEAR__STRIDE 0x00000004 +#define GPU_GR_FECS_CTXSW_MAILBOX_CLEAR(i) (0x00409840 + (i) * 0x00000004) +#define GPU_GR_FECS_CTXSW_MAILBOX_CLEAR_VALUE_SHIFT 0x00000000 +#define GPU_GR_FECS_CTXSW_MAILBOX_CLEAR_VALUE_FIELDMASK 0xffffffff +#define GPU_GR_FECS_FS 0x00409604 +#define GPU_GR_FECS_FS_NUM_AVAILABLE_GPCS_SIZE 0x00000005 +#define GPU_GR_FECS_FS_NUM_AVAILABLE_GPCS_SHIFT 0x00000000 +#define GPU_GR_FECS_FS_NUM_AVAILABLE_GPCS_FIELDMASK 0x0000001f +#define GPU_GR_FECS_FS_NUM_AVAILABLE_GPCS_MASK 0x0000001f +#define GPU_GR_FECS_FS_NUM_AVAILABLE_FBPS_SIZE 0x00000005 +#define GPU_GR_FECS_FS_NUM_AVAILABLE_FBPS_SHIFT 0x00000010 +#define GPU_GR_FECS_FS_NUM_AVAILABLE_FBPS_FIELDMASK 0x0000001f +#define GPU_GR_FECS_FS_NUM_AVAILABLE_FBPS_MASK 0x001f0000 +#define GPU_GR_FECS_CFG 0x00409620 +#define GPU_GR_FECS_CFG_IMEM_SZ_SHIFT 0x00000000 +#define GPU_GR_FECS_CFG_IMEM_SZ_FIELDMASK 0x000000ff +#define GPU_GR_FECS_RC_LANES 0x00409880 +#define GPU_GR_FECS_RC_LANES_NUM_CHAINS_SIZE 0x00000006 +#define GPU_GR_FECS_RC_LANES_NUM_CHAINS_SHIFT 0x00000000 +#define GPU_GR_FECS_RC_LANES_NUM_CHAINS_FIELDMASK 0x0000003f +#define GPU_GR_FECS_RC_LANES_NUM_CHAINS_MASK 0x0000003f +#define GPU_GR_FECS_CTXSW_STATUS_1 0x00409400 +#define GPU_GR_FECS_CTXSW_STATUS_1_ARB_BUSY_SIZE 0x00000001 +#define GPU_GR_FECS_CTXSW_STATUS_1_ARB_BUSY_SHIFT 0x0000000c +#define GPU_GR_FECS_CTXSW_STATUS_1_ARB_BUSY_FIELDMASK 0x00000001 +#define GPU_GR_FECS_CTXSW_STATUS_1_ARB_BUSY_MASK 0x00001000 +#define GPU_GR_FECS_ARB_CTX_ADR 0x00409a24 +#define GPU_GR_FECS_NEW_CTX 0x00409b04 +#define GPU_GR_FECS_NEW_CTX_PTR_SIZE 0x0000001c +#define GPU_GR_FECS_NEW_CTX_PTR_SHIFT 0x00000000 +#define GPU_GR_FECS_NEW_CTX_PTR_FIELDMASK 0x0fffffff +#define GPU_GR_FECS_NEW_CTX_PTR_MASK 0x0fffffff +#define GPU_GR_FECS_NEW_CTX_TARGET_SIZE 0x00000002 +#define GPU_GR_FECS_NEW_CTX_TARGET_SHIFT 0x0000001c +#define GPU_GR_FECS_NEW_CTX_TARGET_FIELDMASK 0x00000003 +#define GPU_GR_FECS_NEW_CTX_TARGET_MASK 0x30000000 +#define GPU_GR_FECS_NEW_CTX_TARGET_VID_MEM_F 0x00000000 +#define GPU_GR_FECS_NEW_CTX_TARGET_SYS_MEM_NCOH_F 0x30000000 +#define GPU_GR_FECS_NEW_CTX_VALID_SIZE 0x00000001 +#define GPU_GR_FECS_NEW_CTX_VALID_SHIFT 0x0000001f +#define GPU_GR_FECS_NEW_CTX_VALID_FIELDMASK 0x00000001 +#define GPU_GR_FECS_NEW_CTX_VALID_MASK 0x80000000 +#define GPU_GR_FECS_ARB_CTX_PTR 0x00409a0c +#define GPU_GR_FECS_ARB_CTX_PTR_PTR_SIZE 0x0000001c +#define GPU_GR_FECS_ARB_CTX_PTR_PTR_SHIFT 0x00000000 +#define GPU_GR_FECS_ARB_CTX_PTR_PTR_FIELDMASK 0x0fffffff +#define GPU_GR_FECS_ARB_CTX_PTR_PTR_MASK 0x0fffffff +#define GPU_GR_FECS_ARB_CTX_PTR_TARGET_SIZE 0x00000002 +#define GPU_GR_FECS_ARB_CTX_PTR_TARGET_SHIFT 0x0000001c +#define GPU_GR_FECS_ARB_CTX_PTR_TARGET_FIELDMASK 0x00000003 +#define GPU_GR_FECS_ARB_CTX_PTR_TARGET_MASK 0x30000000 +#define GPU_GR_FECS_ARB_CTX_PTR_TARGET_VID_MEM_F 0x00000000 +#define GPU_GR_FECS_ARB_CTX_PTR_TARGET_SYS_MEM_NCOH_F 0x30000000 +#define GPU_GR_FECS_ARB_CTX_CMD 0x00409a10 +#define GPU_GR_FECS_ARB_CTX_CMD_CMD_SIZE 0x00000005 +#define GPU_GR_FECS_ARB_CTX_CMD_CMD_SHIFT 0x00000000 +#define GPU_GR_FECS_ARB_CTX_CMD_CMD_FIELDMASK 0x0000001f +#define GPU_GR_FECS_ARB_CTX_CMD_CMD_MASK 0x0000001f +#define GPU_GR_FECS_CTXSW_STATUS_FE_0 0x00409c00 +#define GPU_GR_GPC0_GPCCS_CTXSW_STATUS_GPC_0 0x00502c04 +#define GPU_GR_GPC0_GPCCS_CTXSW_STATUS_1 0x00502400 +#define GPU_GR_FECS_CTXSW_IDLESTATE 0x00409420 +#define GPU_GR_GPC0_GPCCS_CTXSW_IDLESTATE 0x00502420 +#define GPU_GR_RSTR2D_GPC_MAP0 0x0040780c +#define GPU_GR_RSTR2D_GPC_MAP1 0x00407810 +#define GPU_GR_RSTR2D_GPC_MAP2 0x00407814 +#define GPU_GR_RSTR2D_GPC_MAP3 0x00407818 +#define GPU_GR_RSTR2D_GPC_MAP4 0x0040781c +#define GPU_GR_RSTR2D_GPC_MAP5 0x00407820 +#define GPU_GR_RSTR2D_MAP_TABLE_CFG 0x004078bc +#define GPU_GR_RSTR2D_MAP_TABLE_CFG_ROW_OFFSET_SHIFT 0x00000000 +#define GPU_GR_RSTR2D_MAP_TABLE_CFG_ROW_OFFSET_FIELDMASK 0x000000ff +#define GPU_GR_RSTR2D_MAP_TABLE_CFG_NUM_ENTRIES_SHIFT 0x00000008 +#define GPU_GR_RSTR2D_MAP_TABLE_CFG_NUM_ENTRIES_FIELDMASK 0x000000ff +#define GPU_GR_PD_HWW_ESR 0x00406018 +#define GPU_GR_PD_HWW_ESR_RESET_ACTIVE_F 0x40000000 +#define GPU_GR_PD_HWW_ESR_EN_ENABLE_F 0x80000000 +#define GPU_GR_PD_NUM_TPC_PER_GPC__BASE 0x00406028 +#define GPU_GR_PD_NUM_TPC_PER_GPC__STRIDE 0x00000004 +#define GPU_GR_PD_NUM_TPC_PER_GPC(i) (0x00406028 + (i) * 0x00000004) +#define GPU_GR_PD_NUM_TPC_PER_GPC__SIZE_1_V 0x00000004 +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT0_SHIFT 0x00000000 +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT0_FIELDMASK 0x0000000f +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT1_SHIFT 0x00000004 +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT1_FIELDMASK 0x0000000f +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT2_SHIFT 0x00000008 +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT2_FIELDMASK 0x0000000f +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT3_SHIFT 0x0000000c +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT3_FIELDMASK 0x0000000f +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT4_SHIFT 0x00000010 +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT4_FIELDMASK 0x0000000f +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT5_SHIFT 0x00000014 +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT5_FIELDMASK 0x0000000f +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT6_SHIFT 0x00000018 +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT6_FIELDMASK 0x0000000f +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT7_SHIFT 0x0000001c +#define GPU_GR_PD_NUM_TPC_PER_GPC_COUNT7_FIELDMASK 0x0000000f +#define GPU_GR_PD_AB_DIST_CFG0 0x004064c0 +#define GPU_GR_PD_AB_DIST_CFG0_TIMESLICE_ENABLE_EN_F 0x80000000 +#define GPU_GR_PD_AB_DIST_CFG0_TIMESLICE_ENABLE_DIS_F 0x00000000 +#define GPU_GR_PD_AB_DIST_CFG1 0x004064c4 +#define GPU_GR_PD_AB_DIST_CFG1_MAX_BATCHES_INIT_F 0x0000ffff +#define GPU_GR_PD_AB_DIST_CFG1_MAX_OUTPUT_SHIFT 0x00000010 +#define GPU_GR_PD_AB_DIST_CFG1_MAX_OUTPUT_FIELDMASK 0x0000ffff +#define GPU_GR_PD_AB_DIST_CFG1_MAX_OUTPUT_GRANULARITY_V 0x00000080 +#define GPU_GR_PD_AB_DIST_CFG2 0x004064c8 +#define GPU_GR_PD_AB_DIST_CFG2_TOKEN_LIMIT_SHIFT 0x00000000 +#define GPU_GR_PD_AB_DIST_CFG2_TOKEN_LIMIT_FIELDMASK 0x00000fff +#define GPU_GR_PD_AB_DIST_CFG2_TOKEN_LIMIT_INIT_V 0x000001c0 +#define GPU_GR_PD_AB_DIST_CFG2_STATE_LIMIT_SHIFT 0x00000010 +#define GPU_GR_PD_AB_DIST_CFG2_STATE_LIMIT_FIELDMASK 0x00000fff +#define GPU_GR_PD_AB_DIST_CFG2_STATE_LIMIT_SCC_BUNDLE_GRANULARITY_V 0x00000020 +#define GPU_GR_PD_AB_DIST_CFG2_STATE_LIMIT_MIN_GPM_FIFO_DEPTHS_V 0x00000182 +#define GPU_GR_PD_PAGEPOOL 0x004064cc +#define GPU_GR_PD_PAGEPOOL_TOTAL_PAGES_SHIFT 0x00000000 +#define GPU_GR_PD_PAGEPOOL_TOTAL_PAGES_FIELDMASK 0x000000ff +#define GPU_GR_PD_PAGEPOOL_VALID_TRUE_F 0x80000000 +#define GPU_GR_PD_DIST_SKIP_TABLE__BASE 0x004064d0 +#define GPU_GR_PD_DIST_SKIP_TABLE__STRIDE 0x00000004 +#define GPU_GR_PD_DIST_SKIP_TABLE(i) (0x004064d0 + (i) * 0x00000004) +#define GPU_GR_PD_DIST_SKIP_TABLE__SIZE_1_V 0x00000008 +#define GPU_GR_PD_DIST_SKIP_TABLE_GPC_4N0_MASK_SHIFT 0x00000000 +#define GPU_GR_PD_DIST_SKIP_TABLE_GPC_4N0_MASK_FIELDMASK 0x000000ff +#define GPU_GR_PD_DIST_SKIP_TABLE_GPC_4N1_MASK_SHIFT 0x00000008 +#define GPU_GR_PD_DIST_SKIP_TABLE_GPC_4N1_MASK_FIELDMASK 0x000000ff +#define GPU_GR_PD_DIST_SKIP_TABLE_GPC_4N2_MASK_SHIFT 0x00000010 +#define GPU_GR_PD_DIST_SKIP_TABLE_GPC_4N2_MASK_FIELDMASK 0x000000ff +#define GPU_GR_PD_DIST_SKIP_TABLE_GPC_4N3_MASK_SHIFT 0x00000018 +#define GPU_GR_PD_DIST_SKIP_TABLE_GPC_4N3_MASK_FIELDMASK 0x000000ff +#define GPU_GR_DS_DEBUG 0x00405800 +#define GPU_GR_DS_DEBUG_TIMESLICE_MODE_DISABLE_F 0x00000000 +#define GPU_GR_DS_DEBUG_TIMESLICE_MODE_ENABLE_F 0x08000000 +#define GPU_GR_DS_ZBC_COLOR_R 0x00405804 +#define GPU_GR_DS_ZBC_COLOR_R_VAL_SHIFT 0x00000000 +#define GPU_GR_DS_ZBC_COLOR_R_VAL_FIELDMASK 0xffffffff +#define GPU_GR_DS_ZBC_COLOR_G 0x00405808 +#define GPU_GR_DS_ZBC_COLOR_G_VAL_SHIFT 0x00000000 +#define GPU_GR_DS_ZBC_COLOR_G_VAL_FIELDMASK 0xffffffff +#define GPU_GR_DS_ZBC_COLOR_B 0x0040580c +#define GPU_GR_DS_ZBC_COLOR_B_VAL_SHIFT 0x00000000 +#define GPU_GR_DS_ZBC_COLOR_B_VAL_FIELDMASK 0xffffffff +#define GPU_GR_DS_ZBC_COLOR_A 0x00405810 +#define GPU_GR_DS_ZBC_COLOR_A_VAL_SHIFT 0x00000000 +#define GPU_GR_DS_ZBC_COLOR_A_VAL_FIELDMASK 0xffffffff +#define GPU_GR_DS_ZBC_COLOR_FMT 0x00405814 +#define GPU_GR_DS_ZBC_COLOR_FMT_VAL_SHIFT 0x00000000 +#define GPU_GR_DS_ZBC_COLOR_FMT_VAL_FIELDMASK 0x0000007f +#define GPU_GR_DS_ZBC_COLOR_FMT_VAL_INVALID_F 0x00000000 +#define GPU_GR_DS_ZBC_COLOR_FMT_VAL_ZERO_V 0x00000001 +#define GPU_GR_DS_ZBC_COLOR_FMT_VAL_UNORM_ONE_V 0x00000002 +#define GPU_GR_DS_ZBC_COLOR_FMT_VAL_RF32_GF32_BF32_AF32_V 0x00000004 +#define GPU_GR_DS_ZBC_COLOR_FMT_VAL_A8_B8_G8_R8_V 0x00000028 +#define GPU_GR_DS_ZBC_Z 0x00405818 +#define GPU_GR_DS_ZBC_Z_VAL_SIZE 0x00000020 +#define GPU_GR_DS_ZBC_Z_VAL_SHIFT 0x00000000 +#define GPU_GR_DS_ZBC_Z_VAL_FIELDMASK 0xffffffff +#define GPU_GR_DS_ZBC_Z_VAL_MASK 0xffffffff +#define GPU_GR_DS_ZBC_Z_VAL__INIT_V 0x00000000 +#define GPU_GR_DS_ZBC_Z_VAL__INIT_F 0x00000000 +#define GPU_GR_DS_ZBC_Z_FMT 0x0040581c +#define GPU_GR_DS_ZBC_Z_FMT_VAL_SHIFT 0x00000000 +#define GPU_GR_DS_ZBC_Z_FMT_VAL_FIELDMASK 0x00000001 +#define GPU_GR_DS_ZBC_Z_FMT_VAL_INVALID_F 0x00000000 +#define GPU_GR_DS_ZBC_Z_FMT_VAL_FP32_V 0x00000001 +#define GPU_GR_DS_ZBC_TBL_INDEX 0x00405820 +#define GPU_GR_DS_ZBC_TBL_INDEX_VAL_SHIFT 0x00000000 +#define GPU_GR_DS_ZBC_TBL_INDEX_VAL_FIELDMASK 0x0000000f +#define GPU_GR_DS_ZBC_TBL_LD 0x00405824 +#define GPU_GR_DS_ZBC_TBL_LD_SELECT_C_F 0x00000000 +#define GPU_GR_DS_ZBC_TBL_LD_SELECT_Z_F 0x00000001 +#define GPU_GR_DS_ZBC_TBL_LD_ACTION_WRITE_F 0x00000000 +#define GPU_GR_DS_ZBC_TBL_LD_TRIGGER_ACTIVE_F 0x00000004 +#define GPU_GR_DS_TGA_CONSTRAINTLOGIC 0x00405830 +#define GPU_GR_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE_SHIFT 0x00000010 +#define GPU_GR_DS_TGA_CONSTRAINTLOGIC_BETA_CBSIZE_FIELDMASK 0x0000ffff +#define GPU_GR_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE_SHIFT 0x00000000 +#define GPU_GR_DS_TGA_CONSTRAINTLOGIC_ALPHA_CBSIZE_FIELDMASK 0x0000ffff +#define GPU_GR_DS_HWW_ESR 0x00405840 +#define GPU_GR_DS_HWW_ESR_RESET_SIZE 0x00000001 +#define GPU_GR_DS_HWW_ESR_RESET_SHIFT 0x0000001e +#define GPU_GR_DS_HWW_ESR_RESET_FIELDMASK 0x00000001 +#define GPU_GR_DS_HWW_ESR_RESET_MASK 0x40000000 +#define GPU_GR_DS_HWW_ESR_RESET_TASK_V 0x00000001 +#define GPU_GR_DS_HWW_ESR_RESET_TASK_F 0x40000000 +#define GPU_GR_DS_HWW_ESR_EN_ENABLED_F 0x80000000 +#define GPU_GR_DS_HWW_ESR_2 0x00405848 +#define GPU_GR_DS_HWW_ESR_2_RESET_SIZE 0x00000001 +#define GPU_GR_DS_HWW_ESR_2_RESET_SHIFT 0x0000001e +#define GPU_GR_DS_HWW_ESR_2_RESET_FIELDMASK 0x00000001 +#define GPU_GR_DS_HWW_ESR_2_RESET_MASK 0x40000000 +#define GPU_GR_DS_HWW_ESR_2_RESET_TASK_V 0x00000001 +#define GPU_GR_DS_HWW_ESR_2_RESET_TASK_F 0x40000000 +#define GPU_GR_DS_HWW_ESR_2_EN_ENABLED_F 0x80000000 +#define GPU_GR_DS_HWW_REPORT_MASK 0x00405844 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH0_ERR_REPORT_F 0x00000001 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH1_ERR_REPORT_F 0x00000002 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH2_ERR_REPORT_F 0x00000004 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH3_ERR_REPORT_F 0x00000008 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH4_ERR_REPORT_F 0x00000010 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH5_ERR_REPORT_F 0x00000020 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH6_ERR_REPORT_F 0x00000040 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH7_ERR_REPORT_F 0x00000080 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH8_ERR_REPORT_F 0x00000100 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH9_ERR_REPORT_F 0x00000200 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH10_ERR_REPORT_F 0x00000400 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH11_ERR_REPORT_F 0x00000800 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH12_ERR_REPORT_F 0x00001000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH13_ERR_REPORT_F 0x00002000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH14_ERR_REPORT_F 0x00004000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH15_ERR_REPORT_F 0x00008000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH16_ERR_REPORT_F 0x00010000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH17_ERR_REPORT_F 0x00020000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH18_ERR_REPORT_F 0x00040000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH19_ERR_REPORT_F 0x00080000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH20_ERR_REPORT_F 0x00100000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH21_ERR_REPORT_F 0x00200000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH22_ERR_REPORT_F 0x00400000 +#define GPU_GR_DS_HWW_REPORT_MASK_SPH23_ERR_REPORT_F 0x00800000 +#define GPU_GR_DS_HWW_REPORT_MASK_2 0x0040584c +#define GPU_GR_DS_HWW_REPORT_MASK_2_SPH24_ERR_REPORT_F 0x00000001 +#define GPU_GR_DS_NUM_TPC_PER_GPC__BASE 0x00405870 +#define GPU_GR_DS_NUM_TPC_PER_GPC__STRIDE 0x00000004 +#define GPU_GR_DS_NUM_TPC_PER_GPC(i) (0x00405870 + (i) * 0x00000004) +#define GPU_GR_SCC_BUNDLE_CB_BASE 0x00408004 +#define GPU_GR_SCC_BUNDLE_CB_BASE_ADDR_39_8_SHIFT 0x00000000 +#define GPU_GR_SCC_BUNDLE_CB_BASE_ADDR_39_8_FIELDMASK 0xffffffff +#define GPU_GR_SCC_BUNDLE_CB_BASE_ADDR_39_8_ALIGN_BITS_V 0x00000008 +#define GPU_GR_SCC_BUNDLE_CB_SIZE 0x00408008 +#define GPU_GR_SCC_BUNDLE_CB_SIZE_DIV_256B_SHIFT 0x00000000 +#define GPU_GR_SCC_BUNDLE_CB_SIZE_DIV_256B_FIELDMASK 0x000007ff +#define GPU_GR_SCC_BUNDLE_CB_SIZE_DIV_256B__PROD_V 0x00000018 +#define GPU_GR_SCC_BUNDLE_CB_SIZE_DIV_256B_BYTE_GRANULARITY_V 0x00000100 +#define GPU_GR_SCC_BUNDLE_CB_SIZE_VALID_FALSE_V 0x00000000 +#define GPU_GR_SCC_BUNDLE_CB_SIZE_VALID_FALSE_F 0x00000000 +#define GPU_GR_SCC_BUNDLE_CB_SIZE_VALID_TRUE_F 0x80000000 +#define GPU_GR_SCC_PAGEPOOL_BASE 0x0040800c +#define GPU_GR_SCC_PAGEPOOL_BASE_ADDR_39_8_SHIFT 0x00000000 +#define GPU_GR_SCC_PAGEPOOL_BASE_ADDR_39_8_FIELDMASK 0xffffffff +#define GPU_GR_SCC_PAGEPOOL_BASE_ADDR_39_8_ALIGN_BITS_V 0x00000008 +#define GPU_GR_SCC_PAGEPOOL 0x00408010 +#define GPU_GR_SCC_PAGEPOOL_TOTAL_PAGES_SHIFT 0x00000000 +#define GPU_GR_SCC_PAGEPOOL_TOTAL_PAGES_FIELDMASK 0x000000ff +#define GPU_GR_SCC_PAGEPOOL_TOTAL_PAGES_HWMAX_V 0x00000000 +#define GPU_GR_SCC_PAGEPOOL_TOTAL_PAGES_HWMAX_VALUE_V 0x00000080 +#define GPU_GR_SCC_PAGEPOOL_TOTAL_PAGES_BYTE_GRANULARITY_V 0x00000100 +#define GPU_GR_SCC_PAGEPOOL_MAX_VALID_PAGES_SIZE 0x00000008 +#define GPU_GR_SCC_PAGEPOOL_MAX_VALID_PAGES_SHIFT 0x00000008 +#define GPU_GR_SCC_PAGEPOOL_MAX_VALID_PAGES_FIELDMASK 0x000000ff +#define GPU_GR_SCC_PAGEPOOL_MAX_VALID_PAGES_MASK 0x0000ff00 +#define GPU_GR_SCC_PAGEPOOL_VALID_TRUE_F 0x80000000 +#define GPU_GR_SCC_INIT 0x0040802c +#define GPU_GR_SCC_INIT_RAM_TRIGGER_F 0x00000001 +#define GPU_GR_SCC_HWW_ESR 0x00408030 +#define GPU_GR_SCC_HWW_ESR_RESET_ACTIVE_F 0x40000000 +#define GPU_GR_SCC_HWW_ESR_EN_ENABLE_F 0x80000000 +#define GPU_GR_SKED_HWW_ESR 0x00407020 +#define GPU_GR_SKED_HWW_ESR_RESET_ACTIVE_F 0x40000000 +#define GPU_GR_CWD_FS 0x00405b00 +#define GPU_GR_CWD_FS_NUM_GPCS_SHIFT 0x00000000 +#define GPU_GR_CWD_FS_NUM_GPCS_FIELDMASK 0x000000ff +#define GPU_GR_CWD_FS_NUM_TPCS_SHIFT 0x00000008 +#define GPU_GR_CWD_FS_NUM_TPCS_FIELDMASK 0x000000ff +#define GPU_GR_CWD_GPC_TPC_ID__BASE 0x00405b60 +#define GPU_GR_CWD_GPC_TPC_ID__STRIDE 0x00000004 +#define GPU_GR_CWD_GPC_TPC_ID(i) (0x00405b60 + (i) * 0x00000004) +#define GPU_GR_CWD_GPC_TPC_ID_TPC0_SIZE 0x00000004 +#define GPU_GR_CWD_GPC_TPC_ID_TPC0_SHIFT 0x00000000 +#define GPU_GR_CWD_GPC_TPC_ID_TPC0_FIELDMASK 0x0000000f +#define GPU_GR_CWD_GPC_TPC_ID_GPC0_SIZE 0x00000004 +#define GPU_GR_CWD_GPC_TPC_ID_GPC0_SHIFT 0x00000004 +#define GPU_GR_CWD_GPC_TPC_ID_GPC0_FIELDMASK 0x0000000f +#define GPU_GR_CWD_GPC_TPC_ID_TPC1_SHIFT 0x00000008 +#define GPU_GR_CWD_GPC_TPC_ID_TPC1_FIELDMASK 0x0000000f +#define GPU_GR_CWD_SM_ID__BASE 0x00405ba0 +#define GPU_GR_CWD_SM_ID__STRIDE 0x00000004 +#define GPU_GR_CWD_SM_ID(i) (0x00405ba0 + (i) * 0x00000004) +#define GPU_GR_CWD_SM_ID__SIZE_1_V 0x00000006 +#define GPU_GR_CWD_SM_ID_TPC0_SHIFT 0x00000000 +#define GPU_GR_CWD_SM_ID_TPC0_FIELDMASK 0x000000ff +#define GPU_GR_CWD_SM_ID_TPC1_SHIFT 0x00000008 +#define GPU_GR_CWD_SM_ID_TPC1_FIELDMASK 0x000000ff +#define GPU_GR_GPC0_FS_GPC 0x00502608 +#define GPU_GR_GPC0_FS_GPC_NUM_AVAILABLE_TPCS_SHIFT 0x00000000 +#define GPU_GR_GPC0_FS_GPC_NUM_AVAILABLE_TPCS_FIELDMASK 0x0000001f +#define GPU_GR_GPC0_FS_GPC_NUM_AVAILABLE_ZCULLS_SHIFT 0x00000010 +#define GPU_GR_GPC0_FS_GPC_NUM_AVAILABLE_ZCULLS_FIELDMASK 0x0000001f +#define GPU_GR_GPC0_CFG 0x00502620 +#define GPU_GR_GPC0_CFG_IMEM_SZ_SHIFT 0x00000000 +#define GPU_GR_GPC0_CFG_IMEM_SZ_FIELDMASK 0x000000ff +#define GPU_GR_GPCCS_RC_LANES 0x00502880 +#define GPU_GR_GPCCS_RC_LANES_NUM_CHAINS_SIZE 0x00000006 +#define GPU_GR_GPCCS_RC_LANES_NUM_CHAINS_SHIFT 0x00000000 +#define GPU_GR_GPCCS_RC_LANES_NUM_CHAINS_FIELDMASK 0x0000003f +#define GPU_GR_GPCCS_RC_LANES_NUM_CHAINS_MASK 0x0000003f +#define GPU_GR_GPCCS_RC_LANE_SIZE__BASE 0x00502910 +#define GPU_GR_GPCCS_RC_LANE_SIZE__STRIDE 0x00000000 +#define GPU_GR_GPCCS_RC_LANE_SIZE(i) (0x00502910 + (i) * 0x00000000) +#define GPU_GR_GPCCS_RC_LANE_SIZE__SIZE_1_V 0x00000010 +#define GPU_GR_GPCCS_RC_LANE_SIZE_V_SIZE 0x00000018 +#define GPU_GR_GPCCS_RC_LANE_SIZE_V_SHIFT 0x00000000 +#define GPU_GR_GPCCS_RC_LANE_SIZE_V_FIELDMASK 0x00ffffff +#define GPU_GR_GPCCS_RC_LANE_SIZE_V_MASK 0x00ffffff +#define GPU_GR_GPCCS_RC_LANE_SIZE_V_0_V 0x00000000 +#define GPU_GR_GPCCS_RC_LANE_SIZE_V_0_F 0x00000000 +#define GPU_GR_GPC0_ZCULL_FS 0x00500910 +#define GPU_GR_GPC0_ZCULL_FS_NUM_SMS_SHIFT 0x00000000 +#define GPU_GR_GPC0_ZCULL_FS_NUM_SMS_FIELDMASK 0x000001ff +#define GPU_GR_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS_SHIFT 0x00000010 +#define GPU_GR_GPC0_ZCULL_FS_NUM_ACTIVE_BANKS_FIELDMASK 0x0000000f +#define GPU_GR_GPC0_ZCULL_RAM_ADDR 0x00500914 +#define GPU_GR_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC_SHIFT 0x00000000 +#define GPU_GR_GPC0_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC_FIELDMASK 0x0000000f +#define GPU_GR_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET_SHIFT 0x00000008 +#define GPU_GR_GPC0_ZCULL_RAM_ADDR_ROW_OFFSET_FIELDMASK 0x0000000f +#define GPU_GR_GPC0_ZCULL_SM_NUM_RCP 0x00500918 +#define GPU_GR_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE_SHIFT 0x00000000 +#define GPU_GR_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE_FIELDMASK 0x00ffffff +#define GPU_GR_GPC0_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX_V 0x00800000 +#define GPU_GR_GPC0_ZCULL_TOTAL_RAM_SIZE 0x00500920 +#define GPU_GR_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS_SHIFT 0x00000000 +#define GPU_GR_GPC0_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS_FIELDMASK 0x0000ffff +#define GPU_GR_GPC0_ZCULL_ZCSIZE__BASE 0x00500a04 +#define GPU_GR_GPC0_ZCULL_ZCSIZE__STRIDE 0x00000020 +#define GPU_GR_GPC0_ZCULL_ZCSIZE(i) (0x00500a04 + (i) * 0x00000020) +#define GPU_GR_GPC0_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE_V 0x00000040 +#define GPU_GR_GPC0_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE_V 0x00000010 +#define GPU_GR_GPC0_GPM_PD_SM_ID__BASE 0x00500c10 +#define GPU_GR_GPC0_GPM_PD_SM_ID__STRIDE 0x00000004 +#define GPU_GR_GPC0_GPM_PD_SM_ID(i) (0x00500c10 + (i) * 0x00000004) +#define GPU_GR_GPC0_GPM_PD_SM_ID_ID_SHIFT 0x00000000 +#define GPU_GR_GPC0_GPM_PD_SM_ID_ID_FIELDMASK 0x000000ff +#define GPU_GR_GPC0_GPM_PD_PES_TPC_ID_MASK__BASE 0x00500c30 +#define GPU_GR_GPC0_GPM_PD_PES_TPC_ID_MASK__STRIDE 0x00000004 +#define GPU_GR_GPC0_GPM_PD_PES_TPC_ID_MASK(i) (0x00500c30 + (i) * 0x00000004) +#define GPU_GR_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK_SHIFT 0x00000000 +#define GPU_GR_GPC0_GPM_PD_PES_TPC_ID_MASK_MASK_FIELDMASK 0x000000ff +#define GPU_GR_GPC0_TPC0_PE_CFG_SMID 0x00504088 +#define GPU_GR_GPC0_TPC0_PE_CFG_SMID_VALUE_SHIFT 0x00000000 +#define GPU_GR_GPC0_TPC0_PE_CFG_SMID_VALUE_FIELDMASK 0x0000ffff +#define GPU_GR_GPC0_TPC0_SM_CFG 0x00504698 +#define GPU_GR_GPC0_TPC0_SM_CFG_SM_ID_SHIFT 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_CFG_SM_ID_FIELDMASK 0x0000ffff +#define GPU_GR_GPC0_TPC0_SM_ARCH 0x0050469c +#define GPU_GR_GPC0_TPC0_SM_ARCH_WARP_COUNT_SHIFT 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_ARCH_WARP_COUNT_FIELDMASK 0x000000ff +#define GPU_GR_GPC0_TPC0_SM_ARCH_SPA_VERSION_SHIFT 0x00000008 +#define GPU_GR_GPC0_TPC0_SM_ARCH_SPA_VERSION_FIELDMASK 0x00000fff +#define GPU_GR_GPC0_TPC0_SM_ARCH_SM_VERSION_SHIFT 0x00000014 +#define GPU_GR_GPC0_TPC0_SM_ARCH_SM_VERSION_FIELDMASK 0x00000fff +#define GPU_GR_GPC0_PPC0_PES_VSC_STREM 0x00503018 +#define GPU_GR_GPC0_PPC0_PES_VSC_STREM_MASTER_PE_MASK 0x00000001 +#define GPU_GR_GPC0_PPC0_PES_VSC_STREM_MASTER_PE_SHIFT 0x00000000 +#define GPU_GR_GPC0_PPC0_PES_VSC_STREM_MASTER_PE_FIELDMASK 0x00000001 +#define GPU_GR_GPC0_PPC0_PES_VSC_STREM_MASTER_PE_TRUE_F 0x00000001 +#define GPU_GR_GPC0_PPC0_CBM_BETA_CB_SIZE 0x005030c0 +#define GPU_GR_GPC0_PPC0_CBM_BETA_CB_SIZE_V_SHIFT 0x00000000 +#define GPU_GR_GPC0_PPC0_CBM_BETA_CB_SIZE_V_FIELDMASK 0x0000ffff +#define GPU_GR_GPC0_PPC0_CBM_BETA_CB_SIZE_V_MASK 0x0000ffff +#define GPU_GR_GPC0_PPC0_CBM_BETA_CB_SIZE_V_DEFAULT_V 0x00000400 +#define GPU_GR_GPC0_PPC0_CBM_BETA_CB_SIZE_V_GRANULARITY_V 0x00000020 +#define GPU_GR_GPC0_PPC0_CBM_BETA_CB_OFFSET 0x005030f4 +#define GPU_GR_GPC0_PPC0_CBM_ALPHA_CB_SIZE 0x005030e4 +#define GPU_GR_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_SHIFT 0x00000000 +#define GPU_GR_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_FIELDMASK 0x0000ffff +#define GPU_GR_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_MASK 0x0000ffff +#define GPU_GR_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_DEFAULT_V 0x00000800 +#define GPU_GR_GPC0_PPC0_CBM_ALPHA_CB_SIZE_V_GRANULARITY_V 0x00000020 +#define GPU_GR_GPC0_PPC0_CBM_ALPHA_CB_OFFSET 0x005030f8 +#define GPU_GR_GPCS_TPCS_TEX_M_DBG2 0x00419a3c +#define GPU_GR_GPCS_TPCS_TEX_M_DBG2_LG_RD_COALESCE_EN_SHIFT 0x00000002 +#define GPU_GR_GPCS_TPCS_TEX_M_DBG2_LG_RD_COALESCE_EN_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_TPCS_TEX_M_DBG2_LG_RD_COALESCE_EN_MASK 0x00000004 +#define GPU_GR_GPCS_TPCS_TEX_M_DBG2_SU_RD_COALESCE_EN_SHIFT 0x00000004 +#define GPU_GR_GPCS_TPCS_TEX_M_DBG2_SU_RD_COALESCE_EN_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_TPCS_TEX_M_DBG2_SU_RD_COALESCE_EN_MASK 0x00000010 +#define GPU_GR_GPCCS_FALCON_ADDR 0x0041a0ac +#define GPU_GR_GPCCS_FALCON_ADDR_LSB_SIZE 0x00000006 +#define GPU_GR_GPCCS_FALCON_ADDR_LSB_SHIFT 0x00000000 +#define GPU_GR_GPCCS_FALCON_ADDR_LSB_FIELDMASK 0x0000003f +#define GPU_GR_GPCCS_FALCON_ADDR_LSB_MASK 0x0000003f +#define GPU_GR_GPCCS_FALCON_ADDR_LSB_INIT_V 0x00000000 +#define GPU_GR_GPCCS_FALCON_ADDR_LSB_INIT_F 0x00000000 +#define GPU_GR_GPCCS_FALCON_ADDR_MSB_SIZE 0x00000006 +#define GPU_GR_GPCCS_FALCON_ADDR_MSB_SHIFT 0x00000006 +#define GPU_GR_GPCCS_FALCON_ADDR_MSB_FIELDMASK 0x0000003f +#define GPU_GR_GPCCS_FALCON_ADDR_MSB_MASK 0x00000fc0 +#define GPU_GR_GPCCS_FALCON_ADDR_MSB_INIT_V 0x00000000 +#define GPU_GR_GPCCS_FALCON_ADDR_MSB_INIT_F 0x00000000 +#define GPU_GR_GPCCS_FALCON_ADDR_EXT_SIZE 0x0000000c +#define GPU_GR_GPCCS_FALCON_ADDR_EXT_SHIFT 0x00000000 +#define GPU_GR_GPCCS_FALCON_ADDR_EXT_FIELDMASK 0x00000fff +#define GPU_GR_GPCCS_FALCON_ADDR_EXT_MASK 0x00000fff +#define GPU_GR_GPCCS_CPUCTL 0x0041a100 +#define GPU_GR_GPCCS_CPUCTL_STARTCPU_SHIFT 0x00000001 +#define GPU_GR_GPCCS_CPUCTL_STARTCPU_FIELDMASK 0x00000001 +#define GPU_GR_GPCCS_DMACTL 0x0041a10c +#define GPU_GR_GPCCS_DMACTL_REQUIRE_CTX_SHIFT 0x00000000 +#define GPU_GR_GPCCS_DMACTL_REQUIRE_CTX_FIELDMASK 0x00000001 +#define GPU_GR_GPCCS_DMACTL_DMEM_SCRUBBING_MASK 0x00000002 +#define GPU_GR_GPCCS_DMACTL_DMEM_SCRUBBING_SHIFT 0x00000001 +#define GPU_GR_GPCCS_DMACTL_DMEM_SCRUBBING_FIELDMASK 0x00000001 +#define GPU_GR_GPCCS_DMACTL_IMEM_SCRUBBING_MASK 0x00000004 +#define GPU_GR_GPCCS_DMACTL_IMEM_SCRUBBING_SHIFT 0x00000002 +#define GPU_GR_GPCCS_DMACTL_IMEM_SCRUBBING_FIELDMASK 0x00000001 +#define GPU_GR_GPCCS_IMEMC__BASE 0x0041a180 +#define GPU_GR_GPCCS_IMEMC__STRIDE 0x00000010 +#define GPU_GR_GPCCS_IMEMC(i) (0x0041a180 + (i) * 0x00000010) +#define GPU_GR_GPCCS_IMEMC_OFFS_SHIFT 0x00000002 +#define GPU_GR_GPCCS_IMEMC_OFFS_FIELDMASK 0x0000003f +#define GPU_GR_GPCCS_IMEMC_BLK_SHIFT 0x00000008 +#define GPU_GR_GPCCS_IMEMC_BLK_FIELDMASK 0x000000ff +#define GPU_GR_GPCCS_IMEMC_AINCW_SHIFT 0x00000018 +#define GPU_GR_GPCCS_IMEMC_AINCW_FIELDMASK 0x00000001 +#define GPU_GR_GPCCS_IMEMD__BASE 0x0041a184 +#define GPU_GR_GPCCS_IMEMD__STRIDE 0x00000010 +#define GPU_GR_GPCCS_IMEMD(i) (0x0041a184 + (i) * 0x00000010) +#define GPU_GR_GPCCS_IMEMT__BASE 0x0041a188 +#define GPU_GR_GPCCS_IMEMT__STRIDE 0x00000010 +#define GPU_GR_GPCCS_IMEMT(i) (0x0041a188 + (i) * 0x00000010) +#define GPU_GR_GPCCS_IMEMT__SIZE_1_V 0x00000004 +#define GPU_GR_GPCCS_IMEMT_TAG_SHIFT 0x00000000 +#define GPU_GR_GPCCS_IMEMT_TAG_FIELDMASK 0x0000ffff +#define GPU_GR_GPCCS_DMEMC__BASE 0x0041a1c0 +#define GPU_GR_GPCCS_DMEMC__STRIDE 0x00000008 +#define GPU_GR_GPCCS_DMEMC(i) (0x0041a1c0 + (i) * 0x00000008) +#define GPU_GR_GPCCS_DMEMC_OFFS_SHIFT 0x00000002 +#define GPU_GR_GPCCS_DMEMC_OFFS_FIELDMASK 0x0000003f +#define GPU_GR_GPCCS_DMEMC_BLK_SHIFT 0x00000008 +#define GPU_GR_GPCCS_DMEMC_BLK_FIELDMASK 0x000000ff +#define GPU_GR_GPCCS_DMEMC_AINCW_SHIFT 0x00000018 +#define GPU_GR_GPCCS_DMEMC_AINCW_FIELDMASK 0x00000001 +#define GPU_GR_GPCCS_DMEMD__BASE 0x0041a1c4 +#define GPU_GR_GPCCS_DMEMD__STRIDE 0x00000008 +#define GPU_GR_GPCCS_DMEMD(i) (0x0041a1c4 + (i) * 0x00000008) +#define GPU_GR_GPCCS_CTXSW_MAILBOX__BASE 0x0041a800 +#define GPU_GR_GPCCS_CTXSW_MAILBOX__STRIDE 0x00000004 +#define GPU_GR_GPCCS_CTXSW_MAILBOX(i) (0x0041a800 + (i) * 0x00000004) +#define GPU_GR_GPCCS_CTXSW_MAILBOX_VALUE_SHIFT 0x00000000 +#define GPU_GR_GPCCS_CTXSW_MAILBOX_VALUE_FIELDMASK 0xffffffff +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_BASE 0x00418e24 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_BASE_ADDR_39_8_SIZE 0x00000020 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_BASE_ADDR_39_8_SHIFT 0x00000000 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_BASE_ADDR_39_8_FIELDMASK 0xffffffff +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_BASE_ADDR_39_8_MASK 0xffffffff +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_BASE_ADDR_39_8_INIT_V 0x00000000 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_BASE_ADDR_39_8_INIT_F 0x00000000 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE 0x00418e28 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_DIV_256B_SIZE 0x0000000b +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_DIV_256B_SHIFT 0x00000000 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_DIV_256B_FIELDMASK 0x000007ff +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_DIV_256B_MASK 0x000007ff +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_DIV_256B_INIT_V 0x00000018 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_DIV_256B_INIT_F 0x00000018 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_VALID_SIZE 0x00000001 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_VALID_SHIFT 0x0000001f +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_VALID_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_VALID_MASK 0x80000000 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_VALID_FALSE_V 0x00000000 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_VALID_FALSE_F 0x00000000 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_VALID_TRUE_V 0x00000001 +#define GPU_GR_GPCS_SWDX_BUNDLE_CB_SIZE_VALID_TRUE_F 0x80000000 +#define GPU_GR_GPCS_SWDX_TC_BETA_CB_SIZE__BASE 0x00418ea0 +#define GPU_GR_GPCS_SWDX_TC_BETA_CB_SIZE__STRIDE 0x00000004 +#define GPU_GR_GPCS_SWDX_TC_BETA_CB_SIZE(i) (0x00418ea0 + (i) * 0x00000004) +#define GPU_GR_GPCS_SWDX_TC_BETA_CB_SIZE_V_SHIFT 0x00000000 +#define GPU_GR_GPCS_SWDX_TC_BETA_CB_SIZE_V_FIELDMASK 0x0000ffff +#define GPU_GR_GPCS_SWDX_TC_BETA_CB_SIZE_V_MASK 0x0000ffff +#define GPU_GR_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3_SHIFT 0x00000010 +#define GPU_GR_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3_FIELDMASK 0x0000ffff +#define GPU_GR_GPCS_SWDX_TC_BETA_CB_SIZE_DIV3_MASK 0xffff0000 +#define GPU_GR_GPCS_SWDX_RM_PAGEPOOL 0x00418e30 +#define GPU_GR_GPCS_SWDX_RM_PAGEPOOL_TOTAL_PAGES_SHIFT 0x00000000 +#define GPU_GR_GPCS_SWDX_RM_PAGEPOOL_TOTAL_PAGES_FIELDMASK 0x000000ff +#define GPU_GR_GPCS_SWDX_RM_PAGEPOOL_VALID_TRUE_F 0x80000000 +#define GPU_GR_GPCS_SETUP_ATTRIB_CB_BASE 0x00418810 +#define GPU_GR_GPCS_SETUP_ATTRIB_CB_BASE_ADDR_39_12_SHIFT 0x00000000 +#define GPU_GR_GPCS_SETUP_ATTRIB_CB_BASE_ADDR_39_12_FIELDMASK 0x0fffffff +#define GPU_GR_GPCS_SETUP_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS_V 0x0000000c +#define GPU_GR_GPCS_SETUP_ATTRIB_CB_BASE_VALID_TRUE_F 0x80000000 +#define GPU_GR_CRSTR_GPC_MAP0 0x00418b08 +#define GPU_GR_CRSTR_GPC_MAP0_TILE0_SHIFT 0x00000000 +#define GPU_GR_CRSTR_GPC_MAP0_TILE0_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP0_TILE1_SHIFT 0x00000005 +#define GPU_GR_CRSTR_GPC_MAP0_TILE1_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP0_TILE2_SHIFT 0x0000000a +#define GPU_GR_CRSTR_GPC_MAP0_TILE2_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP0_TILE3_SHIFT 0x0000000f +#define GPU_GR_CRSTR_GPC_MAP0_TILE3_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP0_TILE4_SHIFT 0x00000014 +#define GPU_GR_CRSTR_GPC_MAP0_TILE4_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP0_TILE5_SHIFT 0x00000019 +#define GPU_GR_CRSTR_GPC_MAP0_TILE5_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP1 0x00418b0c +#define GPU_GR_CRSTR_GPC_MAP1_TILE6_SHIFT 0x00000000 +#define GPU_GR_CRSTR_GPC_MAP1_TILE6_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP1_TILE7_SHIFT 0x00000005 +#define GPU_GR_CRSTR_GPC_MAP1_TILE7_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP1_TILE8_SHIFT 0x0000000a +#define GPU_GR_CRSTR_GPC_MAP1_TILE8_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP1_TILE9_SHIFT 0x0000000f +#define GPU_GR_CRSTR_GPC_MAP1_TILE9_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP1_TILE10_SHIFT 0x00000014 +#define GPU_GR_CRSTR_GPC_MAP1_TILE10_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP1_TILE11_SHIFT 0x00000019 +#define GPU_GR_CRSTR_GPC_MAP1_TILE11_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP2 0x00418b10 +#define GPU_GR_CRSTR_GPC_MAP2_TILE12_SHIFT 0x00000000 +#define GPU_GR_CRSTR_GPC_MAP2_TILE12_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP2_TILE13_SHIFT 0x00000005 +#define GPU_GR_CRSTR_GPC_MAP2_TILE13_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP2_TILE14_SHIFT 0x0000000a +#define GPU_GR_CRSTR_GPC_MAP2_TILE14_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP2_TILE15_SHIFT 0x0000000f +#define GPU_GR_CRSTR_GPC_MAP2_TILE15_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP2_TILE16_SHIFT 0x00000014 +#define GPU_GR_CRSTR_GPC_MAP2_TILE16_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP2_TILE17_SHIFT 0x00000019 +#define GPU_GR_CRSTR_GPC_MAP2_TILE17_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP3 0x00418b14 +#define GPU_GR_CRSTR_GPC_MAP3_TILE18_SHIFT 0x00000000 +#define GPU_GR_CRSTR_GPC_MAP3_TILE18_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP3_TILE19_SHIFT 0x00000005 +#define GPU_GR_CRSTR_GPC_MAP3_TILE19_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP3_TILE20_SHIFT 0x0000000a +#define GPU_GR_CRSTR_GPC_MAP3_TILE20_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP3_TILE21_SHIFT 0x0000000f +#define GPU_GR_CRSTR_GPC_MAP3_TILE21_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP3_TILE22_SHIFT 0x00000014 +#define GPU_GR_CRSTR_GPC_MAP3_TILE22_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP3_TILE23_SHIFT 0x00000019 +#define GPU_GR_CRSTR_GPC_MAP3_TILE23_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP4 0x00418b18 +#define GPU_GR_CRSTR_GPC_MAP4_TILE24_SHIFT 0x00000000 +#define GPU_GR_CRSTR_GPC_MAP4_TILE24_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP4_TILE25_SHIFT 0x00000005 +#define GPU_GR_CRSTR_GPC_MAP4_TILE25_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP4_TILE26_SHIFT 0x0000000a +#define GPU_GR_CRSTR_GPC_MAP4_TILE26_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP4_TILE27_SHIFT 0x0000000f +#define GPU_GR_CRSTR_GPC_MAP4_TILE27_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP4_TILE28_SHIFT 0x00000014 +#define GPU_GR_CRSTR_GPC_MAP4_TILE28_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP4_TILE29_SHIFT 0x00000019 +#define GPU_GR_CRSTR_GPC_MAP4_TILE29_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP5 0x00418b1c +#define GPU_GR_CRSTR_GPC_MAP5_TILE30_SHIFT 0x00000000 +#define GPU_GR_CRSTR_GPC_MAP5_TILE30_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP5_TILE31_SHIFT 0x00000005 +#define GPU_GR_CRSTR_GPC_MAP5_TILE31_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP5_TILE32_SHIFT 0x0000000a +#define GPU_GR_CRSTR_GPC_MAP5_TILE32_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP5_TILE33_SHIFT 0x0000000f +#define GPU_GR_CRSTR_GPC_MAP5_TILE33_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP5_TILE34_SHIFT 0x00000014 +#define GPU_GR_CRSTR_GPC_MAP5_TILE34_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_GPC_MAP5_TILE35_SHIFT 0x00000019 +#define GPU_GR_CRSTR_GPC_MAP5_TILE35_FIELDMASK 0x00000007 +#define GPU_GR_CRSTR_MAP_TABLE_CFG 0x00418bb8 +#define GPU_GR_CRSTR_MAP_TABLE_CFG_ROW_OFFSET_SHIFT 0x00000000 +#define GPU_GR_CRSTR_MAP_TABLE_CFG_ROW_OFFSET_FIELDMASK 0x000000ff +#define GPU_GR_CRSTR_MAP_TABLE_CFG_NUM_ENTRIES_SHIFT 0x00000008 +#define GPU_GR_CRSTR_MAP_TABLE_CFG_NUM_ENTRIES_FIELDMASK 0x000000ff +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0 0x00418980 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0_SHIFT 0x00000000 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_0_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1_SHIFT 0x00000004 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_1_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2_SHIFT 0x00000008 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_2_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3_SHIFT 0x0000000c +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_3_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4_SHIFT 0x00000010 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_4_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5_SHIFT 0x00000014 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_5_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6_SHIFT 0x00000018 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_6_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7_SHIFT 0x0000001c +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP0_TILE_7_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1 0x00418984 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8_SHIFT 0x00000000 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_8_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9_SHIFT 0x00000004 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_9_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10_SHIFT 0x00000008 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_10_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11_SHIFT 0x0000000c +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_11_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12_SHIFT 0x00000010 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_12_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13_SHIFT 0x00000014 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_13_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14_SHIFT 0x00000018 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_14_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15_SHIFT 0x0000001c +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP1_TILE_15_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2 0x00418988 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16_SHIFT 0x00000000 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_16_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17_SHIFT 0x00000004 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_17_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18_SHIFT 0x00000008 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_18_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19_SHIFT 0x0000000c +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_19_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20_SHIFT 0x00000010 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_20_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21_SHIFT 0x00000014 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_21_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22_SHIFT 0x00000018 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_22_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23_SIZE 0x00000003 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23_SHIFT 0x0000001c +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP2_TILE_23_MASK 0x70000000 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3 0x0041898c +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24_SHIFT 0x00000000 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_24_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25_SHIFT 0x00000004 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_25_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26_SHIFT 0x00000008 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_26_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27_SHIFT 0x0000000c +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_27_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28_SHIFT 0x00000010 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_28_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29_SHIFT 0x00000014 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_29_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30_SHIFT 0x00000018 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_30_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31_SHIFT 0x0000001c +#define GPU_GR_GPCS_ZCULL_SM_IN_GPC_NUMBER_MAP3_TILE_31_FIELDMASK 0x00000007 +#define GPU_GR_GPCS_GPM_PD_CFG 0x00418c6c +#define GPU_GR_GPCS_GPM_PD_CFG_TIMESLICE_MODE_DISABLE_F 0x00000000 +#define GPU_GR_GPCS_GPM_PD_CFG_TIMESLICE_MODE_ENABLE_F 0x00000001 +#define GPU_GR_GPCS_GCC_PAGEPOOL_BASE 0x00419004 +#define GPU_GR_GPCS_GCC_PAGEPOOL_BASE_ADDR_39_8_SHIFT 0x00000000 +#define GPU_GR_GPCS_GCC_PAGEPOOL_BASE_ADDR_39_8_FIELDMASK 0xffffffff +#define GPU_GR_GPCS_GCC_PAGEPOOL 0x00419008 +#define GPU_GR_GPCS_GCC_PAGEPOOL_TOTAL_PAGES_SHIFT 0x00000000 +#define GPU_GR_GPCS_GCC_PAGEPOOL_TOTAL_PAGES_FIELDMASK 0x000000ff +#define GPU_GR_GPCS_TPCS_PE_VAF 0x0041980c +#define GPU_GR_GPCS_TPCS_PE_VAF_FAST_MODE_SWITCH_TRUE_F 0x00000010 +#define GPU_GR_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR 0x00419848 +#define GPU_GR_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V_SHIFT 0x00000000 +#define GPU_GR_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_V_FIELDMASK 0x0fffffff +#define GPU_GR_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_SHIFT 0x0000001c +#define GPU_GR_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_TPCS_PE_PIN_CB_GLOBAL_BASE_ADDR_VALID_TRUE_F 0x10000000 +#define GPU_GR_GPCS_TPCS_MPC_VTG_DEBUG 0x00419c00 +#define GPU_GR_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE_DISABLED_F 0x00000000 +#define GPU_GR_GPCS_TPCS_MPC_VTG_DEBUG_TIMESLICE_MODE_ENABLED_F 0x00000008 +#define GPU_GR_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR 0x00419c2c +#define GPU_GR_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_V_SHIFT 0x00000000 +#define GPU_GR_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_V_FIELDMASK 0x0fffffff +#define GPU_GR_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID_SHIFT 0x0000001c +#define GPU_GR_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_TPCS_MPC_VTG_CB_GLOBAL_BASE_ADDR_VALID_TRUE_F 0x10000000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK 0x00419e44 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_ERROR_REPORT_F 0x00000002 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_API_STACK_ERROR_REPORT_F 0x00000004 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_RET_EMPTY_STACK_ERROR_REPORT_F 0x00000008 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_WRAP_REPORT_F 0x00000010 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_PC_REPORT_F 0x00000020 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_PC_OVERFLOW_REPORT_F 0x00000040 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_IMMC_ADDR_REPORT_F 0x00000080 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_REG_REPORT_F 0x00000100 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_ENCODING_REPORT_F 0x00000200 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_SPH_INSTR_COMBO_REPORT_F 0x00000400 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM_REPORT_F 0x00000800 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_REPORT_F 0x00001000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_REG_REPORT_F 0x00002000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_OOR_ADDR_REPORT_F 0x00004000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MISALIGNED_ADDR_REPORT_F 0x00008000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_ADDR_SPACE_REPORT_F 0x00010000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_ILLEGAL_INSTR_PARAM2_REPORT_F 0x00020000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_INVALID_CONST_ADDR_LDC_REPORT_F 0x00040000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_MMU_FAULT_REPORT_F 0x00800000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_STACK_OVERFLOW_REPORT_F 0x00400000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_GEOMETRY_SM_ERROR_REPORT_F 0x00080000 +#define GPU_GR_GPCS_TPCS_SM_HWW_WARP_ESR_REPORT_MASK_DIVERGENT_REPORT_F 0x00100000 +#define GPU_GR_GPC0_TPC0_SM_HWW_WARP_ESR_REPORT_MASK 0x00504644 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x00419e4c +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SM_TO_SM_FAULT_REPORT_F 0x00000001 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_L1_ERROR_REPORT_F 0x00000002 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_MULTIPLE_WARP_ERRORS_REPORT_F 0x00000004 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_PHYSICAL_STACK_OVERFLOW_ERROR_REPORT_F 0x00000008 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_INT_REPORT_F 0x00000010 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_BPT_PAUSE_REPORT_F 0x00000020 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_REPORT_MASK_SINGLE_STEP_COMPLETE_REPORT_F 0x00000040 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR_REPORT_MASK 0x0050464c +#define GPU_GR_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN 0x00419d0c +#define GPU_GR_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_SM_ENABLED_F 0x00000002 +#define GPU_GR_GPCS_TPCS_TPCCS_TPC_EXCEPTION_EN_TEX_ENABLED_F 0x00000001 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN 0x0050450c +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM_ENABLED_F 0x00000002 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM_SHIFT 0x00000001 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN_SM_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_GPCCS_GPC_EXCEPTION_EN 0x0041ac94 +#define GPU_GR_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC_SHIFT 0x00000010 +#define GPU_GR_GPCS_GPCCS_GPC_EXCEPTION_EN_TPC_FIELDMASK 0x000000ff +#define GPU_GR_GPC0_GPCCS_GPC_EXCEPTION 0x00502c90 +#define GPU_GR_GPC0_GPCCS_GPC_EXCEPTION_TPC_SHIFT 0x00000010 +#define GPU_GR_GPC0_GPCCS_GPC_EXCEPTION_TPC_FIELDMASK 0x000000ff +#define GPU_GR_GPC0_GPCCS_GPC_EXCEPTION_TPC_0_PENDING_V 0x00000001 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION 0x00504508 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_TEX_SHIFT 0x00000000 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_TEX_FIELDMASK 0x00000001 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_TEX_PENDING_V 0x00000001 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM_SHIFT 0x00000001 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM_FIELDMASK 0x00000001 +#define GPU_GR_GPC0_TPC0_TPCCS_TPC_EXCEPTION_SM_PENDING_V 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0 0x00504610 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_MASK 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_SHIFT 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_FIELDMASK 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON_V 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON_F 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF_V 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_DEBUGGER_MODE_OFF_F 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE_F 0x80000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE_F 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_SINGLE_STEP_MODE_ENABLE_F 0x00000008 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_SINGLE_STEP_MODE_DISABLE_F 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK_F 0x40000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_MASK 0x00000002 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_SHIFT 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_FIELDMASK 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_WARP_DISABLE_F 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_MASK 0x00000004 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_SHIFT 0x00000002 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_FIELDMASK 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_DISABLE_F 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_STOP_ON_ANY_WARP_DISABLE_V 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_CONTROL0_STOP_ON_ANY_SM_STOP_ON_ANY_SM_DISABLE_V 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_WARP_VALID_MASK 0x00504614 +#define GPU_GR_GPC0_TPC0_SM_WARP_VALID_MASK_1 0x00504618 +#define GPU_GR_GPC0_TPC0_SM_WARP_VALID_MASK_2 0x0050461c +#define GPU_GR_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK 0x00504624 +#define GPU_GR_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_1 0x00504628 +#define GPU_GR_GPC0_TPC0_SM_DBGR_BPT_PAUSE_MASK_2 0x00504750 +#define GPU_GR_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK 0x00504634 +#define GPU_GR_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_1 0x00504638 +#define GPU_GR_GPC0_TPC0_SM_DBGR_BPT_TRAP_MASK_2 0x00504758 +#define GPU_GR_GPCS_TPCS_SM_DBGR_BPT_PAUSE_MASK 0x00419e24 +#define GPU_GR_GPC0_TPC0_SM_DBGR_STATUS0 0x0050460c +#define GPU_GR_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE_SHIFT 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_DBGR_STATUS0_SM_IN_TRAP_MODE_FIELDMASK 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN_SHIFT 0x00000004 +#define GPU_GR_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN_FIELDMASK 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DBGR_STATUS0_LOCKED_DOWN_TRUE_V 0x00000001 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR 0x00419e50 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_INT_PENDING_F 0x00000010 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_BPT_PAUSE_PENDING_F 0x00000020 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_PENDING_F 0x00000040 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_SM_TO_SM_FAULT_PENDING_F 0x00000001 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_L1_ERROR_PENDING_F 0x00000002 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_PENDING_F 0x00000004 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_PHYSICAL_STACK_OVERFLOW_ERROR_PENDING_F 0x00000008 +#define GPU_GR_GPCS_TPCS_SM_HWW_GLOBAL_ESR_TIMEOUT_ERROR_PENDING_F 0x80000000 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR 0x00504650 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_INT_PENDING_F 0x00000010 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR_BPT_PAUSE_PENDING_F 0x00000020 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SINGLE_STEP_COMPLETE_PENDING_F 0x00000040 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR_SM_TO_SM_FAULT_PENDING_F 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR_L1_ERROR_PENDING_F 0x00000002 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR_MULTIPLE_WARP_ERRORS_PENDING_F 0x00000004 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR_PHYSICAL_STACK_OVERFLOW_ERROR_PENDING_F 0x00000008 +#define GPU_GR_GPC0_TPC0_SM_HWW_GLOBAL_ESR_TIMEOUT_ERROR_PENDING_F 0x80000000 +#define GPU_GR_GPC0_TPC0_TEX_M_HWW_ESR 0x00504224 +#define GPU_GR_GPC0_TPC0_TEX_M_HWW_ESR_INTR_PENDING_F 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_HWW_WARP_ESR 0x00504648 +#define GPU_GR_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_SHIFT 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_FIELDMASK 0x0000ffff +#define GPU_GR_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE_V 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_HWW_WARP_ESR_ERROR_NONE_F 0x00000000 +#define GPU_GR_GPC0_TPC0_SM_HWW_WARP_ESR_PC 0x00504654 +#define GPU_GR_GPC0_TPC0_SM_HALFCTL_CTRL 0x00504770 +#define GPU_GR_GPCS_TPCS_SM_HALFCTL_CTRL 0x00419f70 +#define GPU_GR_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_MASK 0x00000010 +#define GPU_GR_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_SHIFT 0x00000004 +#define GPU_GR_GPCS_TPCS_SM_HALFCTL_CTRL_SCTL_READ_QUAD_CTL_FIELDMASK 0x00000001 +#define GPU_GR_GPC0_TPC0_SM_DEBUG_SFE_CONTROL 0x0050477c +#define GPU_GR_GPCS_TPCS_SM_DEBUG_SFE_CONTROL 0x00419f7c +#define GPU_GR_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL_MASK 0x00000001 +#define GPU_GR_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL_SHIFT 0x00000000 +#define GPU_GR_GPCS_TPCS_SM_DEBUG_SFE_CONTROL_READ_HALF_CTL_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_TPCS_PES_VSC_VPC 0x0041be08 +#define GPU_GR_GPCS_TPCS_PES_VSC_VPC_FAST_MODE_SWITCH_TRUE_F 0x00000004 +#define GPU_GR_PPCS_WWDX_MAP_GPC_MAP0 0x0041bf00 +#define GPU_GR_PPCS_WWDX_MAP_GPC_MAP1 0x0041bf04 +#define GPU_GR_PPCS_WWDX_MAP_GPC_MAP2 0x0041bf08 +#define GPU_GR_PPCS_WWDX_MAP_GPC_MAP3 0x0041bf0c +#define GPU_GR_PPCS_WWDX_MAP_GPC_MAP4 0x0041bf10 +#define GPU_GR_PPCS_WWDX_MAP_GPC_MAP5 0x0041bf14 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG 0x0041bfd0 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_ROW_OFFSET_SHIFT 0x00000000 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_ROW_OFFSET_FIELDMASK 0x000000ff +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_NUM_ENTRIES_SHIFT 0x00000008 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_NUM_ENTRIES_FIELDMASK 0x000000ff +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_NORMALIZED_NUM_ENTRIES_SHIFT 0x00000010 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_NORMALIZED_NUM_ENTRIES_FIELDMASK 0x0000001f +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_NORMALIZED_SHIFT_VALUE_SHIFT 0x00000015 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_NORMALIZED_SHIFT_VALUE_FIELDMASK 0x00000007 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_COEFF5_MOD_VALUE_SHIFT 0x00000018 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG_COEFF5_MOD_VALUE_FIELDMASK 0x0000001f +#define GPU_GR_GPCS_PPCS_WWDX_SM_NUM_RCP 0x0041bfd4 +#define GPU_GR_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE_SHIFT 0x00000000 +#define GPU_GR_GPCS_PPCS_WWDX_SM_NUM_RCP_CONSERVATIVE_FIELDMASK 0x00ffffff +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2 0x0041bfe4 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF6_MOD_VALUE_SHIFT 0x00000000 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF6_MOD_VALUE_FIELDMASK 0x0000001f +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF7_MOD_VALUE_SHIFT 0x00000005 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF7_MOD_VALUE_FIELDMASK 0x0000001f +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF8_MOD_VALUE_SHIFT 0x0000000a +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF8_MOD_VALUE_FIELDMASK 0x0000001f +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF9_MOD_VALUE_SHIFT 0x0000000f +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF9_MOD_VALUE_FIELDMASK 0x0000001f +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF10_MOD_VALUE_SHIFT 0x00000014 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF10_MOD_VALUE_FIELDMASK 0x0000001f +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF11_MOD_VALUE_SHIFT 0x00000019 +#define GPU_GR_PPCS_WWDX_MAP_TABLE_CFG2_COEFF11_MOD_VALUE_FIELDMASK 0x0000001f +#define GPU_GR_BES_ZROP_SETTINGS 0x00408850 +#define GPU_GR_BES_ZROP_SETTINGS_NUM_ACTIVE_LTCS_SHIFT 0x00000000 +#define GPU_GR_BES_ZROP_SETTINGS_NUM_ACTIVE_LTCS_FIELDMASK 0x0000000f +#define GPU_GR_BE0_CROP_DEBUG3 0x00410108 +#define GPU_GR_BES_CROP_DEBUG3 0x00408908 +#define GPU_GR_BES_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_MASK 0x80000000 +#define GPU_GR_BES_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_SHIFT 0x0000001f +#define GPU_GR_BES_CROP_DEBUG3_COMP_VDC_4TO2_DISABLE_FIELDMASK 0x00000001 +#define GPU_GR_BES_CROP_SETTINGS 0x00408958 +#define GPU_GR_BES_CROP_SETTINGS_NUM_ACTIVE_LTCS_SHIFT 0x00000000 +#define GPU_GR_BES_CROP_SETTINGS_NUM_ACTIVE_LTCS_FIELDMASK 0x0000000f +#define GPU_GR_ZCULL_BYTES_PER_ALIQUOT_PER_GPU_V 0x00000020 +#define GPU_GR_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC_V 0x00000020 +#define GPU_GR_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC_V 0x000000c0 +#define GPU_GR_ZCULL_SUBREGION_QTY_V 0x00000010 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL0 0x00504604 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL_SEL1 0x00504608 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL0 0x0050465c +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL1 0x00504660 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL2 0x00504664 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL3 0x00504668 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL4 0x0050466c +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_CONTROL5 0x00504658 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_CONTROL 0x00504730 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_CONTROL 0x00504734 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_CONTROL 0x00504738 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_CONTROL 0x0050473c +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER4_CONTROL 0x00504740 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER5_CONTROL 0x00504744 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER6_CONTROL 0x00504748 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER7_CONTROL 0x0050474c +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS_S1 0x00504678 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER_STATUS1 0x00504694 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S0 0x005046f0 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER0_S1 0x00504700 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S0 0x005046f4 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER1_S1 0x00504704 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S0 0x005046f8 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER2_S1 0x00504708 +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S0 0x005046fc +#define GPU_GR_PRI_GPC0_TPC0_SM_DSM_PERF_COUNTER3_S1 0x0050470c +#define GPU_GR_FE_PWR_MODE 0x00404170 +#define GPU_GR_FE_PWR_MODE_MODE_AUTO_F 0x00000000 +#define GPU_GR_FE_PWR_MODE_MODE_FORCE_ON_F 0x00000002 +#define GPU_GR_FE_PWR_MODE_REQ_SHIFT 0x00000004 +#define GPU_GR_FE_PWR_MODE_REQ_FIELDMASK 0x00000001 +#define GPU_GR_FE_PWR_MODE_REQ_SEND_F 0x00000010 +#define GPU_GR_FE_PWR_MODE_REQ_DONE_V 0x00000000 +#define GPU_GR_GPCS_PRI_MMU_CTRL 0x00418880 +#define GPU_GR_GPCS_PRI_MMU_CTRL_VM_PG_SIZE_MASK 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_CTRL_VM_PG_SIZE_SHIFT 0x00000000 +#define GPU_GR_GPCS_PRI_MMU_CTRL_VM_PG_SIZE_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_MASK 0x00000800 +#define GPU_GR_GPCS_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_SHIFT 0x0000000b +#define GPU_GR_GPCS_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE_MASK 0x00001000 +#define GPU_GR_GPCS_PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE_SHIFT 0x0000000c +#define GPU_GR_GPCS_PRI_MMU_CTRL_USE_FULL_COMP_TAG_LINE_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_CTRL_VOL_FAULT_MASK 0x00000002 +#define GPU_GR_GPCS_PRI_MMU_CTRL_VOL_FAULT_SHIFT 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_CTRL_VOL_FAULT_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_CTRL_COMP_FAULT_MASK 0x00000004 +#define GPU_GR_GPCS_PRI_MMU_CTRL_COMP_FAULT_SHIFT 0x00000002 +#define GPU_GR_GPCS_PRI_MMU_CTRL_COMP_FAULT_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_CTRL_MISS_GRAN_MASK 0x00000018 +#define GPU_GR_GPCS_PRI_MMU_CTRL_MISS_GRAN_SHIFT 0x00000003 +#define GPU_GR_GPCS_PRI_MMU_CTRL_MISS_GRAN_FIELDMASK 0x00000003 +#define GPU_GR_GPCS_PRI_MMU_CTRL_CACHE_MODE_MASK 0x00000060 +#define GPU_GR_GPCS_PRI_MMU_CTRL_CACHE_MODE_SHIFT 0x00000005 +#define GPU_GR_GPCS_PRI_MMU_CTRL_CACHE_MODE_FIELDMASK 0x00000003 +#define GPU_GR_GPCS_PRI_MMU_CTRL_MMU_APERTURE_MASK 0x30000000 +#define GPU_GR_GPCS_PRI_MMU_CTRL_MMU_APERTURE_SHIFT 0x0000001c +#define GPU_GR_GPCS_PRI_MMU_CTRL_MMU_APERTURE_FIELDMASK 0x00000003 +#define GPU_GR_GPCS_PRI_MMU_CTRL_MMU_VOL_MASK 0x40000000 +#define GPU_GR_GPCS_PRI_MMU_CTRL_MMU_VOL_SHIFT 0x0000001e +#define GPU_GR_GPCS_PRI_MMU_CTRL_MMU_VOL_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_CTRL_MMU_DISABLE_MASK 0x80000000 +#define GPU_GR_GPCS_PRI_MMU_CTRL_MMU_DISABLE_SHIFT 0x0000001f +#define GPU_GR_GPCS_PRI_MMU_CTRL_MMU_DISABLE_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_PM_UNIT_MASK 0x00418890 +#define GPU_GR_GPCS_PRI_MMU_PM_REQ_MASK 0x00418894 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_CTRL 0x004188b0 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_CTRL_DEBUG_MASK 0x00010000 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_CTRL_DEBUG_SHIFT 0x00000010 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_CTRL_DEBUG_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED_V 0x00000001 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED_F 0x00010000 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED_V 0x00000000 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED_F 0x00000000 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_WR 0x004188b4 +#define GPU_GR_GPCS_PRI_MMU_DEBUG_RD 0x004188b8 +#define GPU_GR_GPCS_MMU_NUM_ACTIVE_LTCS 0x004188ac +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0 0x00419e10 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_SHIFT 0x00000000 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_DEBUGGER_MODE_ON_V 0x00000001 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_MASK 0x80000000 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_SHIFT 0x0000001f +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_ENABLE_F 0x80000000 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_STOP_TRIGGER_DISABLE_F 0x00000000 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_SINGLE_STEP_MODE_MASK 0x00000008 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_SINGLE_STEP_MODE_SHIFT 0x00000003 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_SINGLE_STEP_MODE_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_SINGLE_STEP_MODE_ENABLE_F 0x00000008 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_SINGLE_STEP_MODE_DISABLE_F 0x00000000 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_MASK 0x40000000 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_SHIFT 0x0000001e +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_FIELDMASK 0x00000001 +#define GPU_GR_GPCS_TPCS_SM_DBGR_CONTROL0_RUN_TRIGGER_TASK_F 0x40000000 + +#define GPU_LTC_PLTCG_BASE_V 0x00140000 +#define GPU_LTC_PLTCG_EXTENT_V 0x0017ffff +#define GPU_LTC_LTC0_LTSS_V 0x00140200 +#define GPU_LTC_LTC0_LTS0_V 0x00140400 +#define GPU_LTC_LTCS_LTSS_V 0x0017e200 +#define GPU_LTC_LTCS_LTS0_CBC_CTRL1 0x0014046c +#define GPU_LTC_LTC0_LTS0_DSTG_CFG0 0x00140518 +#define GPU_LTC_LTCS_LTSS_DSTG_CFG0 0x0017e318 +#define GPU_LTC_LTCS_LTSS_DSTG_CFG0_VDC_4TO2_DISABLE_MASK 0x00008000 +#define GPU_LTC_LTCS_LTSS_DSTG_CFG0_VDC_4TO2_DISABLE_SHIFT 0x0000000f +#define GPU_LTC_LTCS_LTSS_DSTG_CFG0_VDC_4TO2_DISABLE_FIELDMASK 0x00000001 +#define GPU_LTC_LTC0_LTS0_TSTG_CFG1 0x00140494 +#define GPU_LTC_LTC0_LTS0_TSTG_CFG1_ACTIVE_WAYS_SHIFT 0x00000000 +#define GPU_LTC_LTC0_LTS0_TSTG_CFG1_ACTIVE_WAYS_FIELDMASK 0x0000ffff +#define GPU_LTC_LTC0_LTS0_TSTG_CFG1_ACTIVE_SETS_SHIFT 0x00000010 +#define GPU_LTC_LTC0_LTS0_TSTG_CFG1_ACTIVE_SETS_FIELDMASK 0x00000003 +#define GPU_LTC_LTC0_LTS0_TSTG_CFG1_ACTIVE_SETS_ALL_V 0x00000000 +#define GPU_LTC_LTC0_LTS0_TSTG_CFG1_ACTIVE_SETS_HALF_V 0x00000001 +#define GPU_LTC_LTC0_LTS0_TSTG_CFG1_ACTIVE_SETS_QUARTER_V 0x00000002 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL1 0x0017e26c +#define GPU_LTC_LTCS_LTSS_CBC_CTRL1_CLEAN_ACTIVE_F 0x00000001 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL1_INVALIDATE_ACTIVE_F 0x00000002 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL1_CLEAR_SHIFT 0x00000002 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL1_CLEAR_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL1_CLEAR_ACTIVE_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL1_CLEAR_ACTIVE_F 0x00000004 +#define GPU_LTC_LTC0_LTS0_CBC_CTRL1 0x0014046c +#define GPU_LTC_LTCS_LTSS_CBC_CTRL2 0x0017e270 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL2_CLEAR_LOWER_BOUND_SHIFT 0x00000000 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL2_CLEAR_LOWER_BOUND_FIELDMASK 0x0001ffff +#define GPU_LTC_LTCS_LTSS_CBC_CTRL3 0x0017e274 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL3_CLEAR_UPPER_BOUND_SHIFT 0x00000000 +#define GPU_LTC_LTCS_LTSS_CBC_CTRL3_CLEAR_UPPER_BOUND_FIELDMASK 0x0001ffff +#define GPU_LTC_LTCS_LTSS_CBC_CTRL3_CLEAR_UPPER_BOUND_INIT_V 0x0001ffff +#define GPU_LTC_LTCS_LTSS_CBC_BASE 0x0017e278 +#define GPU_LTC_LTCS_LTSS_CBC_BASE_ALIGNMENT_SHIFT_V 0x0000000b +#define GPU_LTC_LTCS_LTSS_CBC_BASE_ADDRESS_SHIFT 0x00000000 +#define GPU_LTC_LTCS_LTSS_CBC_BASE_ADDRESS_FIELDMASK 0x03ffffff +#define GPU_LTC_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS 0x0017e27c +#define GPU_LTC_LTCS_MISC_LTC_NUM_ACTIVE_LTCS 0x0017e000 +#define GPU_LTC_LTCS_LTSS_CBC_PARAM 0x0017e280 +#define GPU_LTC_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE_SHIFT 0x00000000 +#define GPU_LTC_LTCS_LTSS_CBC_PARAM_COMPTAGS_PER_CACHE_LINE_FIELDMASK 0x0000ffff +#define GPU_LTC_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_SHIFT 0x00000018 +#define GPU_LTC_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_FIELDMASK 0x0000000f +#define GPU_LTC_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC_SHIFT 0x0000001c +#define GPU_LTC_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC_FIELDMASK 0x0000000f +#define GPU_LTC_LTCS_LTSS_TSTG_SET_MGMT 0x0017e2ac +#define GPU_LTC_LTCS_LTSS_TSTG_SET_MGMT_MAX_WAYS_EVICT_LAST_SHIFT 0x00000010 +#define GPU_LTC_LTCS_LTSS_TSTG_SET_MGMT_MAX_WAYS_EVICT_LAST_FIELDMASK 0x0000001f +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_INDEX 0x0017e338 +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS_SHIFT 0x00000000 +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS_FIELDMASK 0x0000000f +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__BASE 0x0017e33c +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__STRIDE 0x00000004 +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x0017e33c + (i) * 0x00000004) +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1_V 0x00000004 +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x0017e34c +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD_SIZE 0x00000020 +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD_SHIFT 0x00000000 +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD_FIELDMASK 0xffffffff +#define GPU_LTC_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD_MASK 0xffffffff +#define GPU_LTC_LTCS_LTSS_TSTG_SET_MGMT_2 0x0017e2b0 +#define GPU_LTC_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE_ENABLED_F 0x10000000 +#define GPU_LTC_LTCS_LTSS_G_ELPG 0x0017e214 +#define GPU_LTC_LTCS_LTSS_G_ELPG_FLUSH_SHIFT 0x00000000 +#define GPU_LTC_LTCS_LTSS_G_ELPG_FLUSH_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_G_ELPG_FLUSH_PENDING_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_G_ELPG_FLUSH_PENDING_F 0x00000001 +#define GPU_LTC_LTC0_LTSS_G_ELPG 0x00140214 +#define GPU_LTC_LTC0_LTSS_G_ELPG_FLUSH_SHIFT 0x00000000 +#define GPU_LTC_LTC0_LTSS_G_ELPG_FLUSH_FIELDMASK 0x00000001 +#define GPU_LTC_LTC0_LTSS_G_ELPG_FLUSH_PENDING_V 0x00000001 +#define GPU_LTC_LTC0_LTSS_G_ELPG_FLUSH_PENDING_F 0x00000001 +#define GPU_LTC_LTC1_LTSS_G_ELPG 0x00142214 +#define GPU_LTC_LTC1_LTSS_G_ELPG_FLUSH_SHIFT 0x00000000 +#define GPU_LTC_LTC1_LTSS_G_ELPG_FLUSH_FIELDMASK 0x00000001 +#define GPU_LTC_LTC1_LTSS_G_ELPG_FLUSH_PENDING_V 0x00000001 +#define GPU_LTC_LTC1_LTSS_G_ELPG_FLUSH_PENDING_F 0x00000001 +#define GPU_LTC_LTCS_LTSS_INTR 0x0017e20c +#define GPU_LTC_LTCS_LTSS_INTR_EN_EVICTED_CB_MASK 0x00100000 +#define GPU_LTC_LTCS_LTSS_INTR_EN_EVICTED_CB_SHIFT 0x00000014 +#define GPU_LTC_LTCS_LTSS_INTR_EN_EVICTED_CB_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS_MASK 0x40000000 +#define GPU_LTC_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS_SHIFT 0x0000001e +#define GPU_LTC_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_MASK 0x00200000 +#define GPU_LTC_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_SHIFT 0x00000015 +#define GPU_LTC_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_FIELDMASK 0x00000001 +#define GPU_LTC_LTC0_LTS0_INTR 0x0014040c +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0 0x0017e2a0 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_SHIFT 0x00000000 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_PENDING_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_PENDING_F 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_MAX_CYCLES_BETWEEN_INVALIDATES_SHIFT 0x00000008 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_MAX_CYCLES_BETWEEN_INVALIDATES_FIELDMASK 0x0000000f +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_MAX_CYCLES_BETWEEN_INVALIDATES_3_V 0x00000003 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_MAX_CYCLES_BETWEEN_INVALIDATES_3_F 0x00000300 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_LAST_CLASS_SHIFT 0x0000001c +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_LAST_CLASS_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_LAST_CLASS_TRUE_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_LAST_CLASS_TRUE_F 0x10000000 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_NORMAL_CLASS_SHIFT 0x0000001d +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_NORMAL_CLASS_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_NORMAL_CLASS_TRUE_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_NORMAL_CLASS_TRUE_F 0x20000000 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_FIRST_CLASS_SHIFT 0x0000001e +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_FIRST_CLASS_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_FIRST_CLASS_TRUE_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT0_INVALIDATE_EVICT_FIRST_CLASS_TRUE_F 0x40000000 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1 0x0017e2a4 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_SHIFT 0x00000000 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_PENDING_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_PENDING_F 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_MAX_CYCLES_BETWEEN_CLEANS_SHIFT 0x00000008 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_MAX_CYCLES_BETWEEN_CLEANS_FIELDMASK 0x0000000f +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_MAX_CYCLES_BETWEEN_CLEANS_3_V 0x00000003 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_MAX_CYCLES_BETWEEN_CLEANS_3_F 0x00000300 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_WAIT_FOR_FB_TO_PULL_SHIFT 0x00000010 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_WAIT_FOR_FB_TO_PULL_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_WAIT_FOR_FB_TO_PULL_TRUE_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_WAIT_FOR_FB_TO_PULL_TRUE_F 0x00010000 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_LAST_CLASS_SHIFT 0x0000001c +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_LAST_CLASS_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_LAST_CLASS_TRUE_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_LAST_CLASS_TRUE_F 0x10000000 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_NORMAL_CLASS_SHIFT 0x0000001d +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_NORMAL_CLASS_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_NORMAL_CLASS_TRUE_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_NORMAL_CLASS_TRUE_F 0x20000000 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_FIRST_CLASS_SHIFT 0x0000001e +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_FIRST_CLASS_FIELDMASK 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_FIRST_CLASS_TRUE_V 0x00000001 +#define GPU_LTC_LTCS_LTSS_TSTG_CMGMT1_CLEAN_EVICT_FIRST_CLASS_TRUE_F 0x40000000 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT0 0x001402a0 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT0_INVALIDATE_SHIFT 0x00000000 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT0_INVALIDATE_FIELDMASK 0x00000001 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT0_INVALIDATE_PENDING_V 0x00000001 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT0_INVALIDATE_PENDING_F 0x00000001 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT1 0x001402a4 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT1_CLEAN_SHIFT 0x00000000 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT1_CLEAN_FIELDMASK 0x00000001 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT1_CLEAN_PENDING_V 0x00000001 +#define GPU_LTC_LTC0_LTSS_TSTG_CMGMT1_CLEAN_PENDING_F 0x00000001 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT0 0x001422a0 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT0_INVALIDATE_SHIFT 0x00000000 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT0_INVALIDATE_FIELDMASK 0x00000001 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT0_INVALIDATE_PENDING_V 0x00000001 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT0_INVALIDATE_PENDING_F 0x00000001 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT1 0x001422a4 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT1_CLEAN_SHIFT 0x00000000 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT1_CLEAN_FIELDMASK 0x00000001 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT1_CLEAN_PENDING_V 0x00000001 +#define GPU_LTC_LTC1_LTSS_TSTG_CMGMT1_CLEAN_PENDING_F 0x00000001 + +#define GPU_MC_BOOT_0 0x00000000 +#define GPU_MC_BOOT_0_ARCHITECTURE_SHIFT 0x00000018 +#define GPU_MC_BOOT_0_ARCHITECTURE_FIELDMASK 0x0000001f +#define GPU_MC_BOOT_0_IMPLEMENTATION_SHIFT 0x00000014 +#define GPU_MC_BOOT_0_IMPLEMENTATION_FIELDMASK 0x0000000f +#define GPU_MC_BOOT_0_MAJOR_REVISION_SHIFT 0x00000004 +#define GPU_MC_BOOT_0_MAJOR_REVISION_FIELDMASK 0x0000000f +#define GPU_MC_BOOT_0_MINOR_REVISION_SHIFT 0x00000000 +#define GPU_MC_BOOT_0_MINOR_REVISION_FIELDMASK 0x0000000f +#define GPU_MC_INTR__BASE 0x00000100 +#define GPU_MC_INTR__STRIDE 0x00000004 +#define GPU_MC_INTR(i) (0x00000100 + (i) * 0x00000004) +#define GPU_MC_INTR_PFIFO_PENDING_F 0x00000100 +#define GPU_MC_INTR_PMU_PENDING_F 0x01000000 +#define GPU_MC_INTR_LTC_PENDING_F 0x02000000 +#define GPU_MC_INTR_PRIV_RING_PENDING_F 0x40000000 +#define GPU_MC_INTR_PBUS_PENDING_F 0x10000000 +#define GPU_MC_INTR_MASK_0 0x00000640 +#define GPU_MC_INTR_MASK_0_PMU_ENABLED_F 0x01000000 +#define GPU_MC_INTR_EN_0 0x00000140 +#define GPU_MC_INTR_EN_0_INTA_DISABLED_F 0x00000000 +#define GPU_MC_INTR_EN_0_INTA_HARDWARE_F 0x00000001 +#define GPU_MC_INTR_MASK_1 0x00000644 +#define GPU_MC_INTR_MASK_1_PMU_SIZE 0x00000001 +#define GPU_MC_INTR_MASK_1_PMU_SHIFT 0x00000018 +#define GPU_MC_INTR_MASK_1_PMU_FIELDMASK 0x00000001 +#define GPU_MC_INTR_MASK_1_PMU_MASK 0x01000000 +#define GPU_MC_INTR_MASK_1_PMU_ENABLED_F 0x01000000 +#define GPU_MC_INTR_EN_1 0x00000144 +#define GPU_MC_INTR_EN_1_INTA_DISABLED_F 0x00000000 +#define GPU_MC_INTR_EN_1_INTA_HARDWARE_F 0x00000001 +#define GPU_MC_ENABLE 0x00000200 +#define GPU_MC_ENABLE_XBAR_ENABLED_F 0x00000004 +#define GPU_MC_ENABLE_L2_ENABLED_F 0x00000008 +#define GPU_MC_ENABLE_PMEDIA_SIZE 0x00000001 +#define GPU_MC_ENABLE_PMEDIA_SHIFT 0x00000004 +#define GPU_MC_ENABLE_PMEDIA_FIELDMASK 0x00000001 +#define GPU_MC_ENABLE_PMEDIA_MASK 0x00000010 +#define GPU_MC_ENABLE_PRIV_RING_ENABLED_F 0x00000020 +#define GPU_MC_ENABLE_CE0_MASK 0x00000040 +#define GPU_MC_ENABLE_CE0_SHIFT 0x00000006 +#define GPU_MC_ENABLE_CE0_FIELDMASK 0x00000001 +#define GPU_MC_ENABLE_PFIFO_ENABLED_F 0x00000100 +#define GPU_MC_ENABLE_PGRAPH_ENABLED_F 0x00001000 +#define GPU_MC_ENABLE_PWR_SHIFT 0x0000000d +#define GPU_MC_ENABLE_PWR_FIELDMASK 0x00000001 +#define GPU_MC_ENABLE_PWR_DISABLED_V 0x00000000 +#define GPU_MC_ENABLE_PWR_ENABLED_F 0x00002000 +#define GPU_MC_ENABLE_PFB_ENABLED_F 0x00100000 +#define GPU_MC_ENABLE_CE2_MASK 0x00200000 +#define GPU_MC_ENABLE_CE2_SHIFT 0x00000015 +#define GPU_MC_ENABLE_CE2_FIELDMASK 0x00000001 +#define GPU_MC_ENABLE_CE2_ENABLED_F 0x00200000 +#define GPU_MC_ENABLE_BLG_ENABLED_F 0x08000000 +#define GPU_MC_ENABLE_PERFMON_ENABLED_F 0x10000000 +#define GPU_MC_ENABLE_HUB_ENABLED_F 0x20000000 +#define GPU_MC_INTR_LTC 0x0000017c +#define GPU_MC_ENABLE_PB 0x00000204 +#define GPU_MC_ENABLE_PB_0_SIZE 0x00000001 +#define GPU_MC_ENABLE_PB_0_SHIFT 0x00000000 +#define GPU_MC_ENABLE_PB_0_FIELDMASK 0x00000001 +#define GPU_MC_ENABLE_PB_0_MASK 0x00000001 +#define GPU_MC_ENABLE_PB_0_ENABLED_V 0x00000001 +#define GPU_MC_ENABLE_PB_SEL_FIELDMASK 0x00000001 +#define GPU_MC_ENABLE_PB_SEL__SHIFT_BASE 0x00000000 +#define GPU_MC_ENABLE_PB_SEL__SHIFT_STRIDE 0x00000001 +#define GPU_MC_ENABLE_PB_SEL__SHIFT_I(i) (0 + (i) * 1) +#define GPU_MC_ELPG_ENABLE 0x0000020c +#define GPU_MC_ELPG_ENABLE_XBAR_ENABLED_F 0x00000004 +#define GPU_MC_ELPG_ENABLE_PFB_ENABLED_F 0x00100000 +#define GPU_MC_ELPG_ENABLE_HUB_ENABLED_F 0x20000000 + +#define GPU_PBDMA_GP_ENTRY1 0x10000004 +#define GPU_PBDMA_GP_ENTRY1_GET_HI_SHIFT 0x00000000 +#define GPU_PBDMA_GP_ENTRY1_GET_HI_FIELDMASK 0x000000ff +#define GPU_PBDMA_GP_ENTRY1_LENGTH_SHIFT 0x0000000a +#define GPU_PBDMA_GP_ENTRY1_LENGTH_FIELDMASK 0x001fffff +#define GPU_PBDMA_GP_BASE__BASE 0x00040048 +#define GPU_PBDMA_GP_BASE__STRIDE 0x00002000 +#define GPU_PBDMA_GP_BASE(i) (0x00040048 + (i) * 0x00002000) +#define GPU_PBDMA_GP_BASE__SIZE_1_V 0x00000001 +#define GPU_PBDMA_GP_BASE_OFFSET_SHIFT 0x00000003 +#define GPU_PBDMA_GP_BASE_OFFSET_FIELDMASK 0x1fffffff +#define GPU_PBDMA_GP_BASE_RSVD_SIZE 0x00000003 +#define GPU_PBDMA_GP_BASE_HI__BASE 0x0004004c +#define GPU_PBDMA_GP_BASE_HI__STRIDE 0x00002000 +#define GPU_PBDMA_GP_BASE_HI(i) (0x0004004c + (i) * 0x00002000) +#define GPU_PBDMA_GP_BASE_HI_OFFSET_SHIFT 0x00000000 +#define GPU_PBDMA_GP_BASE_HI_OFFSET_FIELDMASK 0x000000ff +#define GPU_PBDMA_GP_BASE_HI_LIMIT2_SHIFT 0x00000010 +#define GPU_PBDMA_GP_BASE_HI_LIMIT2_FIELDMASK 0x0000001f +#define GPU_PBDMA_GP_FETCH__BASE 0x00040050 +#define GPU_PBDMA_GP_FETCH__STRIDE 0x00002000 +#define GPU_PBDMA_GP_FETCH(i) (0x00040050 + (i) * 0x00002000) +#define GPU_PBDMA_GP_GET__BASE 0x00040014 +#define GPU_PBDMA_GP_GET__STRIDE 0x00002000 +#define GPU_PBDMA_GP_GET(i) (0x00040014 + (i) * 0x00002000) +#define GPU_PBDMA_GP_PUT__BASE 0x00040000 +#define GPU_PBDMA_GP_PUT__STRIDE 0x00002000 +#define GPU_PBDMA_GP_PUT(i) (0x00040000 + (i) * 0x00002000) +#define GPU_PBDMA_PB_FETCH__BASE 0x00040054 +#define GPU_PBDMA_PB_FETCH__STRIDE 0x00002000 +#define GPU_PBDMA_PB_FETCH(i) (0x00040054 + (i) * 0x00002000) +#define GPU_PBDMA_PB_FETCH_HI__BASE 0x00040058 +#define GPU_PBDMA_PB_FETCH_HI__STRIDE 0x00002000 +#define GPU_PBDMA_PB_FETCH_HI(i) (0x00040058 + (i) * 0x00002000) +#define GPU_PBDMA_GET__BASE 0x00040018 +#define GPU_PBDMA_GET__STRIDE 0x00002000 +#define GPU_PBDMA_GET(i) (0x00040018 + (i) * 0x00002000) +#define GPU_PBDMA_GET_HI__BASE 0x0004001c +#define GPU_PBDMA_GET_HI__STRIDE 0x00002000 +#define GPU_PBDMA_GET_HI(i) (0x0004001c + (i) * 0x00002000) +#define GPU_PBDMA_PUT__BASE 0x0004005c +#define GPU_PBDMA_PUT__STRIDE 0x00002000 +#define GPU_PBDMA_PUT(i) (0x0004005c + (i) * 0x00002000) +#define GPU_PBDMA_PUT_HI__BASE 0x00040060 +#define GPU_PBDMA_PUT_HI__STRIDE 0x00002000 +#define GPU_PBDMA_PUT_HI(i) (0x00040060 + (i) * 0x00002000) +#define GPU_PBDMA_FORMATS__BASE 0x0004009c +#define GPU_PBDMA_FORMATS__STRIDE 0x00002000 +#define GPU_PBDMA_FORMATS(i) (0x0004009c + (i) * 0x00002000) +#define GPU_PBDMA_FORMATS_GP_FERMI0_F 0x00000000 +#define GPU_PBDMA_FORMATS_PB_FERMI1_F 0x00000100 +#define GPU_PBDMA_FORMATS_MP_FERMI0_F 0x00000000 +#define GPU_PBDMA_PB_HEADER__BASE 0x00040084 +#define GPU_PBDMA_PB_HEADER__STRIDE 0x00002000 +#define GPU_PBDMA_PB_HEADER(i) (0x00040084 + (i) * 0x00002000) +#define GPU_PBDMA_PB_HEADER_PRIV_USER_F 0x00000000 +#define GPU_PBDMA_PB_HEADER_METHOD_ZERO_F 0x00000000 +#define GPU_PBDMA_PB_HEADER_SUBCHANNEL_ZERO_F 0x00000000 +#define GPU_PBDMA_PB_HEADER_LEVEL_MAIN_F 0x00000000 +#define GPU_PBDMA_PB_HEADER_FIRST_TRUE_F 0x00400000 +#define GPU_PBDMA_PB_HEADER_TYPE_INC_F 0x20000000 +#define GPU_PBDMA_PB_HEADER_TYPE_NON_INC_F 0x60000000 +#define GPU_PBDMA_HDR_SHADOW__BASE 0x00040118 +#define GPU_PBDMA_HDR_SHADOW__STRIDE 0x00002000 +#define GPU_PBDMA_HDR_SHADOW(i) (0x00040118 + (i) * 0x00002000) +#define GPU_PBDMA_SUBDEVICE__BASE 0x00040094 +#define GPU_PBDMA_SUBDEVICE__STRIDE 0x00002000 +#define GPU_PBDMA_SUBDEVICE(i) (0x00040094 + (i) * 0x00002000) +#define GPU_PBDMA_SUBDEVICE_ID_SHIFT 0x00000000 +#define GPU_PBDMA_SUBDEVICE_ID_FIELDMASK 0x00000fff +#define GPU_PBDMA_SUBDEVICE_STATUS_ACTIVE_F 0x10000000 +#define GPU_PBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE_F 0x20000000 +#define GPU_PBDMA_METHOD0__BASE 0x000400c0 +#define GPU_PBDMA_METHOD0__STRIDE 0x00002000 +#define GPU_PBDMA_METHOD0(i) (0x000400c0 + (i) * 0x00002000) +#define GPU_PBDMA_METHOD0_FIFO_SIZE_V 0x00000004 +#define GPU_PBDMA_METHOD0_ADDR_SHIFT 0x00000002 +#define GPU_PBDMA_METHOD0_ADDR_FIELDMASK 0x00000fff +#define GPU_PBDMA_METHOD0_SUBCH_SHIFT 0x00000010 +#define GPU_PBDMA_METHOD0_SUBCH_FIELDMASK 0x00000007 +#define GPU_PBDMA_METHOD0_FIRST_TRUE_F 0x00400000 +#define GPU_PBDMA_METHOD0_VALID_TRUE_F 0x80000000 +#define GPU_PBDMA_METHOD1__BASE 0x000400c8 +#define GPU_PBDMA_METHOD1__STRIDE 0x00002000 +#define GPU_PBDMA_METHOD1(i) (0x000400c8 + (i) * 0x00002000) +#define GPU_PBDMA_METHOD2__BASE 0x000400d0 +#define GPU_PBDMA_METHOD2__STRIDE 0x00002000 +#define GPU_PBDMA_METHOD2(i) (0x000400d0 + (i) * 0x00002000) +#define GPU_PBDMA_METHOD3__BASE 0x000400d8 +#define GPU_PBDMA_METHOD3__STRIDE 0x00002000 +#define GPU_PBDMA_METHOD3(i) (0x000400d8 + (i) * 0x00002000) +#define GPU_PBDMA_DATA0__BASE 0x000400c4 +#define GPU_PBDMA_DATA0__STRIDE 0x00002000 +#define GPU_PBDMA_DATA0(i) (0x000400c4 + (i) * 0x00002000) +#define GPU_PBDMA_TARGET__BASE 0x000400ac +#define GPU_PBDMA_TARGET__STRIDE 0x00002000 +#define GPU_PBDMA_TARGET(i) (0x000400ac + (i) * 0x00002000) +#define GPU_PBDMA_TARGET_ENGINE_SW_F 0x0000001f +#define GPU_PBDMA_ACQUIRE__BASE 0x00040030 +#define GPU_PBDMA_ACQUIRE__STRIDE 0x00002000 +#define GPU_PBDMA_ACQUIRE(i) (0x00040030 + (i) * 0x00002000) +#define GPU_PBDMA_ACQUIRE_RETRY_MAN_2_F 0x00000002 +#define GPU_PBDMA_ACQUIRE_RETRY_EXP_2_F 0x00000100 +#define GPU_PBDMA_ACQUIRE_TIMEOUT_EXP_SHIFT 0x0000000b +#define GPU_PBDMA_ACQUIRE_TIMEOUT_EXP_FIELDMASK 0x0000000f +#define GPU_PBDMA_ACQUIRE_TIMEOUT_EXP_MAX_V 0x0000000f +#define GPU_PBDMA_ACQUIRE_TIMEOUT_EXP_MAX_F 0x00007800 +#define GPU_PBDMA_ACQUIRE_TIMEOUT_MAN_SHIFT 0x0000000f +#define GPU_PBDMA_ACQUIRE_TIMEOUT_MAN_FIELDMASK 0x0000ffff +#define GPU_PBDMA_ACQUIRE_TIMEOUT_MAN_MAX_V 0x0000ffff +#define GPU_PBDMA_ACQUIRE_TIMEOUT_MAN_MAX_F 0x7fff8000 +#define GPU_PBDMA_ACQUIRE_TIMEOUT_EN_ENABLE_F 0x80000000 +#define GPU_PBDMA_ACQUIRE_TIMEOUT_EN_DISABLE_F 0x00000000 +#define GPU_PBDMA_STATUS__BASE 0x00040100 +#define GPU_PBDMA_STATUS__STRIDE 0x00002000 +#define GPU_PBDMA_STATUS(i) (0x00040100 + (i) * 0x00002000) +#define GPU_PBDMA_CHANNEL__BASE 0x00040120 +#define GPU_PBDMA_CHANNEL__STRIDE 0x00002000 +#define GPU_PBDMA_CHANNEL(i) (0x00040120 + (i) * 0x00002000) +#define GPU_PBDMA_SIGNATURE__BASE 0x00040010 +#define GPU_PBDMA_SIGNATURE__STRIDE 0x00002000 +#define GPU_PBDMA_SIGNATURE(i) (0x00040010 + (i) * 0x00002000) +#define GPU_PBDMA_SIGNATURE_HW_VALID_F 0x0000face +#define GPU_PBDMA_SIGNATURE_SW_ZERO_F 0x00000000 +#define GPU_PBDMA_USERD__BASE 0x00040008 +#define GPU_PBDMA_USERD__STRIDE 0x00002000 +#define GPU_PBDMA_USERD(i) (0x00040008 + (i) * 0x00002000) +#define GPU_PBDMA_USERD_TARGET_VID_MEM_F 0x00000000 +#define GPU_PBDMA_USERD_TARGET_SYS_MEM_COH_F 0x00000002 +#define GPU_PBDMA_USERD_TARGET_SYS_MEM_NCOH_F 0x00000003 +#define GPU_PBDMA_USERD_ADDR_SHIFT 0x00000009 +#define GPU_PBDMA_USERD_ADDR_FIELDMASK 0x007fffff +#define GPU_PBDMA_USERD_HI__BASE 0x0004000c +#define GPU_PBDMA_USERD_HI__STRIDE 0x00002000 +#define GPU_PBDMA_USERD_HI(i) (0x0004000c + (i) * 0x00002000) +#define GPU_PBDMA_USERD_HI_ADDR_SHIFT 0x00000000 +#define GPU_PBDMA_USERD_HI_ADDR_FIELDMASK 0x000000ff +#define GPU_PBDMA_HCE_CTRL__BASE 0x000400e4 +#define GPU_PBDMA_HCE_CTRL__STRIDE 0x00002000 +#define GPU_PBDMA_HCE_CTRL(i) (0x000400e4 + (i) * 0x00002000) +#define GPU_PBDMA_HCE_CTRL_HCE_PRIV_MODE_YES_F 0x00000020 +#define GPU_PBDMA_INTR_0__BASE 0x00040108 +#define GPU_PBDMA_INTR_0__STRIDE 0x00002000 +#define GPU_PBDMA_INTR_0(i) (0x00040108 + (i) * 0x00002000) +#define GPU_PBDMA_INTR_0_MEMREQ_SHIFT 0x00000000 +#define GPU_PBDMA_INTR_0_MEMREQ_FIELDMASK 0x00000001 +#define GPU_PBDMA_INTR_0_MEMREQ_PENDING_F 0x00000001 +#define GPU_PBDMA_INTR_0_MEMACK_TIMEOUT_PENDING_F 0x00000002 +#define GPU_PBDMA_INTR_0_MEMACK_EXTRA_PENDING_F 0x00000004 +#define GPU_PBDMA_INTR_0_MEMDAT_TIMEOUT_PENDING_F 0x00000008 +#define GPU_PBDMA_INTR_0_MEMDAT_EXTRA_PENDING_F 0x00000010 +#define GPU_PBDMA_INTR_0_MEMFLUSH_PENDING_F 0x00000020 +#define GPU_PBDMA_INTR_0_MEMOP_PENDING_F 0x00000040 +#define GPU_PBDMA_INTR_0_LBCONNECT_PENDING_F 0x00000080 +#define GPU_PBDMA_INTR_0_LBREQ_PENDING_F 0x00000100 +#define GPU_PBDMA_INTR_0_LBACK_TIMEOUT_PENDING_F 0x00000200 +#define GPU_PBDMA_INTR_0_LBACK_EXTRA_PENDING_F 0x00000400 +#define GPU_PBDMA_INTR_0_LBDAT_TIMEOUT_PENDING_F 0x00000800 +#define GPU_PBDMA_INTR_0_LBDAT_EXTRA_PENDING_F 0x00001000 +#define GPU_PBDMA_INTR_0_GPFIFO_PENDING_F 0x00002000 +#define GPU_PBDMA_INTR_0_GPPTR_PENDING_F 0x00004000 +#define GPU_PBDMA_INTR_0_GPENTRY_PENDING_F 0x00008000 +#define GPU_PBDMA_INTR_0_GPCRC_PENDING_F 0x00010000 +#define GPU_PBDMA_INTR_0_PBPTR_PENDING_F 0x00020000 +#define GPU_PBDMA_INTR_0_PBENTRY_PENDING_F 0x00040000 +#define GPU_PBDMA_INTR_0_PBCRC_PENDING_F 0x00080000 +#define GPU_PBDMA_INTR_0_XBARCONNECT_PENDING_F 0x00100000 +#define GPU_PBDMA_INTR_0_METHOD_PENDING_F 0x00200000 +#define GPU_PBDMA_INTR_0_METHODCRC_PENDING_F 0x00400000 +#define GPU_PBDMA_INTR_0_DEVICE_PENDING_F 0x00800000 +#define GPU_PBDMA_INTR_0_SEMAPHORE_PENDING_F 0x02000000 +#define GPU_PBDMA_INTR_0_ACQUIRE_PENDING_F 0x04000000 +#define GPU_PBDMA_INTR_0_PRI_PENDING_F 0x08000000 +#define GPU_PBDMA_INTR_0_NO_CTXSW_SEG_PENDING_F 0x20000000 +#define GPU_PBDMA_INTR_0_PBSEG_PENDING_F 0x40000000 +#define GPU_PBDMA_INTR_0_SIGNATURE_PENDING_F 0x80000000 +#define GPU_PBDMA_INTR_1__BASE 0x00040148 +#define GPU_PBDMA_INTR_1__STRIDE 0x00002000 +#define GPU_PBDMA_INTR_1(i) (0x00040148 + (i) * 0x00002000) +#define GPU_PBDMA_INTR_EN_0__BASE 0x0004010c +#define GPU_PBDMA_INTR_EN_0__STRIDE 0x00002000 +#define GPU_PBDMA_INTR_EN_0(i) (0x0004010c + (i) * 0x00002000) +#define GPU_PBDMA_INTR_EN_0_LBREQ_ENABLED_F 0x00000100 +#define GPU_PBDMA_INTR_EN_1__BASE 0x0004014c +#define GPU_PBDMA_INTR_EN_1__STRIDE 0x00002000 +#define GPU_PBDMA_INTR_EN_1(i) (0x0004014c + (i) * 0x00002000) +#define GPU_PBDMA_INTR_STALL__BASE 0x0004013c +#define GPU_PBDMA_INTR_STALL__STRIDE 0x00002000 +#define GPU_PBDMA_INTR_STALL(i) (0x0004013c + (i) * 0x00002000) +#define GPU_PBDMA_INTR_STALL_LBREQ_ENABLED_F 0x00000100 +#define GPU_PBDMA_UDMA_NOP 0x00000008 +#define GPU_PBDMA_SYNCPOINTA__BASE 0x000400a4 +#define GPU_PBDMA_SYNCPOINTA__STRIDE 0x00002000 +#define GPU_PBDMA_SYNCPOINTA(i) (0x000400a4 + (i) * 0x00002000) +#define GPU_PBDMA_SYNCPOINTA_PAYLOAD_SHIFT 0x00000000 +#define GPU_PBDMA_SYNCPOINTA_PAYLOAD_FIELDMASK 0xffffffff +#define GPU_PBDMA_SYNCPOINTB__BASE 0x000400a8 +#define GPU_PBDMA_SYNCPOINTB__STRIDE 0x00002000 +#define GPU_PBDMA_SYNCPOINTB(i) (0x000400a8 + (i) * 0x00002000) +#define GPU_PBDMA_SYNCPOINTB_OP_SHIFT 0x00000000 +#define GPU_PBDMA_SYNCPOINTB_OP_FIELDMASK 0x00000003 +#define GPU_PBDMA_SYNCPOINTB_OP_WAIT_V 0x00000000 +#define GPU_PBDMA_SYNCPOINTB_WAIT_SWITCH_SHIFT 0x00000004 +#define GPU_PBDMA_SYNCPOINTB_WAIT_SWITCH_FIELDMASK 0x00000001 +#define GPU_PBDMA_SYNCPOINTB_WAIT_SWITCH_EN_V 0x00000001 +#define GPU_PBDMA_SYNCPOINTB_SYNCPT_INDEX_SHIFT 0x00000008 +#define GPU_PBDMA_SYNCPOINTB_SYNCPT_INDEX_FIELDMASK 0x000000ff +#define GPU_PBDMA_RUNLIST_TIMESLICE__BASE 0x000400f8 +#define GPU_PBDMA_RUNLIST_TIMESLICE__STRIDE 0x00002000 +#define GPU_PBDMA_RUNLIST_TIMESLICE(i) (0x000400f8 + (i) * 0x00002000) +#define GPU_PBDMA_RUNLIST_TIMESLICE_TIMEOUT_128_F 0x00000080 +#define GPU_PBDMA_RUNLIST_TIMESLICE_TIMESCALE_3_F 0x00003000 +#define GPU_PBDMA_RUNLIST_TIMESLICE_ENABLE_TRUE_F 0x10000000 + +#define GPU_PERF_PMASYS_CONTROL 0x001b4000 +#define GPU_PERF_PMASYS_CONTROL_MEMBUF_STATUS_SHIFT 0x00000004 +#define GPU_PERF_PMASYS_CONTROL_MEMBUF_STATUS_FIELDMASK 0x00000001 +#define GPU_PERF_PMASYS_CONTROL_MEMBUF_STATUS_OVERFLOWED_V 0x00000001 +#define GPU_PERF_PMASYS_CONTROL_MEMBUF_STATUS_OVERFLOWED_F 0x00000010 +#define GPU_PERF_PMASYS_CONTROL_MEMBUF_CLEAR_STATUS_SHIFT 0x00000005 +#define GPU_PERF_PMASYS_CONTROL_MEMBUF_CLEAR_STATUS_FIELDMASK 0x00000001 +#define GPU_PERF_PMASYS_CONTROL_MEMBUF_CLEAR_STATUS_DOIT_V 0x00000001 +#define GPU_PERF_PMASYS_CONTROL_MEMBUF_CLEAR_STATUS_DOIT_F 0x00000020 +#define GPU_PERF_PMASYS_MEM_BLOCK 0x001b4070 +#define GPU_PERF_PMASYS_MEM_BLOCK_BASE_SHIFT 0x00000000 +#define GPU_PERF_PMASYS_MEM_BLOCK_BASE_FIELDMASK 0x0fffffff +#define GPU_PERF_PMASYS_MEM_BLOCK_TARGET_SHIFT 0x0000001c +#define GPU_PERF_PMASYS_MEM_BLOCK_TARGET_FIELDMASK 0x00000003 +#define GPU_PERF_PMASYS_MEM_BLOCK_TARGET_LFB_V 0x00000000 +#define GPU_PERF_PMASYS_MEM_BLOCK_TARGET_LFB_F 0x00000000 +#define GPU_PERF_PMASYS_MEM_BLOCK_TARGET_SYS_COH_V 0x00000002 +#define GPU_PERF_PMASYS_MEM_BLOCK_TARGET_SYS_COH_F 0x20000000 +#define GPU_PERF_PMASYS_MEM_BLOCK_TARGET_SYS_NCOH_V 0x00000003 +#define GPU_PERF_PMASYS_MEM_BLOCK_TARGET_SYS_NCOH_F 0x30000000 +#define GPU_PERF_PMASYS_MEM_BLOCK_VALID_SHIFT 0x0000001f +#define GPU_PERF_PMASYS_MEM_BLOCK_VALID_FIELDMASK 0x00000001 +#define GPU_PERF_PMASYS_MEM_BLOCK_VALID_TRUE_V 0x00000001 +#define GPU_PERF_PMASYS_MEM_BLOCK_VALID_TRUE_F 0x80000000 +#define GPU_PERF_PMASYS_MEM_BLOCK_VALID_FALSE_V 0x00000000 +#define GPU_PERF_PMASYS_MEM_BLOCK_VALID_FALSE_F 0x00000000 +#define GPU_PERF_PMASYS_OUTBASE 0x001b4074 +#define GPU_PERF_PMASYS_OUTBASE_PTR_SHIFT 0x00000005 +#define GPU_PERF_PMASYS_OUTBASE_PTR_FIELDMASK 0x07ffffff +#define GPU_PERF_PMASYS_OUTBASEUPPER 0x001b4078 +#define GPU_PERF_PMASYS_OUTBASEUPPER_PTR_SHIFT 0x00000000 +#define GPU_PERF_PMASYS_OUTBASEUPPER_PTR_FIELDMASK 0x000000ff +#define GPU_PERF_PMASYS_OUTSIZE 0x001b407c +#define GPU_PERF_PMASYS_OUTSIZE_NUMBYTES_SHIFT 0x00000005 +#define GPU_PERF_PMASYS_OUTSIZE_NUMBYTES_FIELDMASK 0x07ffffff +#define GPU_PERF_PMASYS_MEM_BYTES 0x001b4084 +#define GPU_PERF_PMASYS_MEM_BYTES_NUMBYTES_SHIFT 0x00000004 +#define GPU_PERF_PMASYS_MEM_BYTES_NUMBYTES_FIELDMASK 0x0fffffff +#define GPU_PERF_PMASYS_MEM_BUMP 0x001b4088 +#define GPU_PERF_PMASYS_MEM_BUMP_NUMBYTES_SHIFT 0x00000004 +#define GPU_PERF_PMASYS_MEM_BUMP_NUMBYTES_FIELDMASK 0x0fffffff +#define GPU_PERF_PMASYS_ENGINESTATUS 0x001b40a4 +#define GPU_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_SHIFT 0x00000004 +#define GPU_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_FIELDMASK 0x00000001 +#define GPU_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_EMPTY_V 0x00000001 +#define GPU_PERF_PMASYS_ENGINESTATUS_RBUFEMPTY_EMPTY_F 0x00000010 + +#define GPU_PRAM_DATA032__BASE 0x00700000 +#define GPU_PRAM_DATA032__STRIDE 0x00000004 +#define GPU_PRAM_DATA032(i) (0x00700000 + (i) * 0x00000004) + +#define GPU_PRI_RINGMASTER_COMMAND 0x0012004c +#define GPU_PRI_RINGMASTER_COMMAND_CMD_MASK 0x0000003f +#define GPU_PRI_RINGMASTER_COMMAND_CMD_SHIFT 0x00000000 +#define GPU_PRI_RINGMASTER_COMMAND_CMD_FIELDMASK 0x0000003f +#define GPU_PRI_RINGMASTER_COMMAND_CMD_NO_CMD_V 0x00000000 +#define GPU_PRI_RINGMASTER_COMMAND_CMD_START_RING_F 0x00000001 +#define GPU_PRI_RINGMASTER_COMMAND_CMD_ACK_INTERRUPT_F 0x00000002 +#define GPU_PRI_RINGMASTER_COMMAND_CMD_ENUMERATE_STATIONS_F 0x00000003 +#define GPU_PRI_RINGMASTER_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL_F 0x00000000 +#define GPU_PRI_RINGMASTER_COMMAND_DATA 0x00120048 +#define GPU_PRI_RINGMASTER_START_RESULTS 0x00120050 +#define GPU_PRI_RINGMASTER_START_RESULTS_CONNECTIVITY_SHIFT 0x00000000 +#define GPU_PRI_RINGMASTER_START_RESULTS_CONNECTIVITY_FIELDMASK 0x00000001 +#define GPU_PRI_RINGMASTER_START_RESULTS_CONNECTIVITY_PASS_V 0x00000001 +#define GPU_PRI_RINGMASTER_INTR_STATUS0 0x00120058 +#define GPU_PRI_RINGMASTER_INTR_STATUS0_RING_START_CONN_FAULT_SHIFT 0x00000000 +#define GPU_PRI_RINGMASTER_INTR_STATUS0_RING_START_CONN_FAULT_FIELDMASK 0x00000001 +#define GPU_PRI_RINGMASTER_INTR_STATUS0_DISCONNECT_FAULT_SHIFT 0x00000001 +#define GPU_PRI_RINGMASTER_INTR_STATUS0_DISCONNECT_FAULT_FIELDMASK 0x00000001 +#define GPU_PRI_RINGMASTER_INTR_STATUS0_OVERFLOW_FAULT_SHIFT 0x00000002 +#define GPU_PRI_RINGMASTER_INTR_STATUS0_OVERFLOW_FAULT_FIELDMASK 0x00000001 +#define GPU_PRI_RINGMASTER_INTR_STATUS0_GBL_WRITE_ERROR_SYS_SHIFT 0x00000008 +#define GPU_PRI_RINGMASTER_INTR_STATUS0_GBL_WRITE_ERROR_SYS_FIELDMASK 0x00000001 +#define GPU_PRI_RINGMASTER_INTR_STATUS1 0x0012005c +#define GPU_PRI_RINGMASTER_GLOBAL_CTL 0x00120060 +#define GPU_PRI_RINGMASTER_GLOBAL_CTL_RING_RESET_ASSERTED_F 0x00000001 +#define GPU_PRI_RINGMASTER_GLOBAL_CTL_RING_RESET_DEASSERTED_F 0x00000000 +#define GPU_PRI_RINGMASTER_ENUM_FBP 0x00120074 +#define GPU_PRI_RINGMASTER_ENUM_FBP_COUNT_SHIFT 0x00000000 +#define GPU_PRI_RINGMASTER_ENUM_FBP_COUNT_FIELDMASK 0x0000001f +#define GPU_PRI_RINGMASTER_ENUM_GPC 0x00120078 +#define GPU_PRI_RINGMASTER_ENUM_GPC_COUNT_SHIFT 0x00000000 +#define GPU_PRI_RINGMASTER_ENUM_GPC_COUNT_FIELDMASK 0x0000001f +#define GPU_PRI_RINGMASTER_ENUM_LTC 0x0012006c +#define GPU_PRI_RINGMASTER_ENUM_LTC_COUNT_SHIFT 0x00000000 +#define GPU_PRI_RINGMASTER_ENUM_LTC_COUNT_FIELDMASK 0x0000001f + +#define GPU_PRI_RINGSTATION_GPC_MASTER_CONFIG__BASE 0x00128300 +#define GPU_PRI_RINGSTATION_GPC_MASTER_CONFIG__STRIDE 0x00000004 +#define GPU_PRI_RINGSTATION_GPC_MASTER_CONFIG(i) (0x00128300 + (i) * 0x00000004) +#define GPU_PRI_RINGSTATION_GPC_GPC0_PRIV_ERROR_ADR 0x00128120 +#define GPU_PRI_RINGSTATION_GPC_GPC0_PRIV_ERROR_WRDAT 0x00128124 +#define GPU_PRI_RINGSTATION_GPC_GPC0_PRIV_ERROR_INFO 0x00128128 +#define GPU_PRI_RINGSTATION_GPC_GPC0_PRIV_ERROR_CODE 0x0012812c + +#define GPU_PRI_RINGSTATION_SYS_MASTER_CONFIG__BASE 0x00122300 +#define GPU_PRI_RINGSTATION_SYS_MASTER_CONFIG__STRIDE 0x00000004 +#define GPU_PRI_RINGSTATION_SYS_MASTER_CONFIG(i) (0x00122300 + (i) * 0x00000004) +#define GPU_PRI_RINGSTATION_SYS_DECODE_CONFIG 0x00122204 +#define GPU_PRI_RINGSTATION_SYS_DECODE_CONFIG_RING_MASK 0x00000007 +#define GPU_PRI_RINGSTATION_SYS_DECODE_CONFIG_RING_SHIFT 0x00000000 +#define GPU_PRI_RINGSTATION_SYS_DECODE_CONFIG_RING_FIELDMASK 0x00000007 +#define GPU_PRI_RINGSTATION_SYS_DECODE_CONFIG_RING_DROP_ON_RING_NOT_STARTED_F 0x00000001 +#define GPU_PRI_RINGSTATION_SYS_PRIV_ERROR_ADR 0x00122120 +#define GPU_PRI_RINGSTATION_SYS_PRIV_ERROR_WRDAT 0x00122124 +#define GPU_PRI_RINGSTATION_SYS_PRIV_ERROR_INFO 0x00122128 +#define GPU_PRI_RINGSTATION_SYS_PRIV_ERROR_CODE 0x0012212c + +#define GPU_PROJ_GPC_BASE_V 0x00500000 +#define GPU_PROJ_GPC_SHARED_BASE_V 0x00418000 +#define GPU_PROJ_GPC_STRIDE_V 0x00008000 +#define GPU_PROJ_LTC_STRIDE_V 0x00002000 +#define GPU_PROJ_LTS_STRIDE_V 0x00000200 +#define GPU_PROJ_FBPA_STRIDE_V 0x00001000 +#define GPU_PROJ_PPC_IN_GPC_BASE_V 0x00003000 +#define GPU_PROJ_PPC_IN_GPC_SHARED_BASE_V 0x00003e00 +#define GPU_PROJ_PPC_IN_GPC_STRIDE_V 0x00000200 +#define GPU_PROJ_ROP_BASE_V 0x00410000 +#define GPU_PROJ_ROP_SHARED_BASE_V 0x00408800 +#define GPU_PROJ_ROP_STRIDE_V 0x00000400 +#define GPU_PROJ_TPC_IN_GPC_BASE_V 0x00004000 +#define GPU_PROJ_TPC_IN_GPC_STRIDE_V 0x00000800 +#define GPU_PROJ_TPC_IN_GPC_SHARED_BASE_V 0x00001800 +#define GPU_PROJ_HOST_NUM_ENGINES_V 0x00000002 +#define GPU_PROJ_HOST_NUM_PBDMA_V 0x00000001 +#define GPU_PROJ_SCAL_LITTER_NUM_TPC_PER_GPC_V 0x00000002 +#define GPU_PROJ_SCAL_LITTER_NUM_FBPS_V 0x00000001 +#define GPU_PROJ_SCAL_LITTER_NUM_FBPAS_V 0x00000001 +#define GPU_PROJ_SCAL_LITTER_NUM_GPCS_V 0x00000001 +#define GPU_PROJ_SCAL_LITTER_NUM_PES_PER_GPC_V 0x00000001 +#define GPU_PROJ_SCAL_LITTER_NUM_TPCS_PER_PES_V 0x00000002 +#define GPU_PROJ_SCAL_LITTER_NUM_ZCULL_BANKS_V 0x00000004 +#define GPU_PROJ_SCAL_MAX_GPCS_V 0x00000020 +#define GPU_PROJ_SCAL_MAX_TPC_PER_GPC_V 0x00000008 + +#define GPU_PWR_FALCON_IRQSSET 0x0010a000 +#define GPU_PWR_FALCON_IRQSSET_SWGEN0_SET_F 0x00000040 +#define GPU_PWR_FALCON_IRQSCLR 0x0010a004 +#define GPU_PWR_FALCON_IRQSTAT 0x0010a008 +#define GPU_PWR_FALCON_IRQSTAT_HALT_TRUE_F 0x00000010 +#define GPU_PWR_FALCON_IRQSTAT_EXTERR_TRUE_F 0x00000020 +#define GPU_PWR_FALCON_IRQSTAT_SWGEN0_TRUE_F 0x00000040 +#define GPU_PWR_FALCON_IRQMODE 0x0010a00c +#define GPU_PWR_FALCON_IRQMSET 0x0010a010 +#define GPU_PWR_FALCON_IRQMSET_GPTMR_SHIFT 0x00000000 +#define GPU_PWR_FALCON_IRQMSET_GPTMR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMSET_WDTMR_SHIFT 0x00000001 +#define GPU_PWR_FALCON_IRQMSET_WDTMR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMSET_MTHD_SHIFT 0x00000002 +#define GPU_PWR_FALCON_IRQMSET_MTHD_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMSET_CTXSW_SHIFT 0x00000003 +#define GPU_PWR_FALCON_IRQMSET_CTXSW_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMSET_HALT_SHIFT 0x00000004 +#define GPU_PWR_FALCON_IRQMSET_HALT_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMSET_EXTERR_SHIFT 0x00000005 +#define GPU_PWR_FALCON_IRQMSET_EXTERR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMSET_SWGEN0_SHIFT 0x00000006 +#define GPU_PWR_FALCON_IRQMSET_SWGEN0_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMSET_SWGEN1_SHIFT 0x00000007 +#define GPU_PWR_FALCON_IRQMSET_SWGEN1_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR 0x0010a014 +#define GPU_PWR_FALCON_IRQMCLR_GPTMR_SHIFT 0x00000000 +#define GPU_PWR_FALCON_IRQMCLR_GPTMR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR_WDTMR_SHIFT 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR_WDTMR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR_MTHD_SHIFT 0x00000002 +#define GPU_PWR_FALCON_IRQMCLR_MTHD_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR_CTXSW_SHIFT 0x00000003 +#define GPU_PWR_FALCON_IRQMCLR_CTXSW_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR_HALT_SHIFT 0x00000004 +#define GPU_PWR_FALCON_IRQMCLR_HALT_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR_EXTERR_SHIFT 0x00000005 +#define GPU_PWR_FALCON_IRQMCLR_EXTERR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR_SWGEN0_SHIFT 0x00000006 +#define GPU_PWR_FALCON_IRQMCLR_SWGEN0_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR_SWGEN1_SHIFT 0x00000007 +#define GPU_PWR_FALCON_IRQMCLR_SWGEN1_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQMCLR_EXT_SHIFT 0x00000008 +#define GPU_PWR_FALCON_IRQMCLR_EXT_FIELDMASK 0x000000ff +#define GPU_PWR_FALCON_IRQMASK 0x0010a018 +#define GPU_PWR_FALCON_IRQDEST 0x0010a01c +#define GPU_PWR_FALCON_IRQDEST_HOST_GPTMR_SHIFT 0x00000000 +#define GPU_PWR_FALCON_IRQDEST_HOST_GPTMR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_HOST_WDTMR_SHIFT 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_HOST_WDTMR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_HOST_MTHD_SHIFT 0x00000002 +#define GPU_PWR_FALCON_IRQDEST_HOST_MTHD_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_HOST_CTXSW_SHIFT 0x00000003 +#define GPU_PWR_FALCON_IRQDEST_HOST_CTXSW_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_HOST_HALT_SHIFT 0x00000004 +#define GPU_PWR_FALCON_IRQDEST_HOST_HALT_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_HOST_EXTERR_SHIFT 0x00000005 +#define GPU_PWR_FALCON_IRQDEST_HOST_EXTERR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_HOST_SWGEN0_SHIFT 0x00000006 +#define GPU_PWR_FALCON_IRQDEST_HOST_SWGEN0_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_HOST_SWGEN1_SHIFT 0x00000007 +#define GPU_PWR_FALCON_IRQDEST_HOST_SWGEN1_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_HOST_EXT_SHIFT 0x00000008 +#define GPU_PWR_FALCON_IRQDEST_HOST_EXT_FIELDMASK 0x000000ff +#define GPU_PWR_FALCON_IRQDEST_TARGET_GPTMR_SHIFT 0x00000010 +#define GPU_PWR_FALCON_IRQDEST_TARGET_GPTMR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_TARGET_WDTMR_SHIFT 0x00000011 +#define GPU_PWR_FALCON_IRQDEST_TARGET_WDTMR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_TARGET_MTHD_SHIFT 0x00000012 +#define GPU_PWR_FALCON_IRQDEST_TARGET_MTHD_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_TARGET_CTXSW_SHIFT 0x00000013 +#define GPU_PWR_FALCON_IRQDEST_TARGET_CTXSW_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_TARGET_HALT_SHIFT 0x00000014 +#define GPU_PWR_FALCON_IRQDEST_TARGET_HALT_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_TARGET_EXTERR_SHIFT 0x00000015 +#define GPU_PWR_FALCON_IRQDEST_TARGET_EXTERR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_TARGET_SWGEN0_SHIFT 0x00000016 +#define GPU_PWR_FALCON_IRQDEST_TARGET_SWGEN0_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_TARGET_SWGEN1_SHIFT 0x00000017 +#define GPU_PWR_FALCON_IRQDEST_TARGET_SWGEN1_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IRQDEST_TARGET_EXT_SHIFT 0x00000018 +#define GPU_PWR_FALCON_IRQDEST_TARGET_EXT_FIELDMASK 0x000000ff +#define GPU_PWR_FALCON_CURCTX 0x0010a050 +#define GPU_PWR_FALCON_NXTCTX 0x0010a054 +#define GPU_PWR_FALCON_MAILBOX0 0x0010a040 +#define GPU_PWR_FALCON_MAILBOX1 0x0010a044 +#define GPU_PWR_FALCON_ITFEN 0x0010a048 +#define GPU_PWR_FALCON_ITFEN_CTXEN_ENABLE_F 0x00000001 +#define GPU_PWR_FALCON_IDLESTATE 0x0010a04c +#define GPU_PWR_FALCON_IDLESTATE_FALCON_BUSY_SHIFT 0x00000000 +#define GPU_PWR_FALCON_IDLESTATE_FALCON_BUSY_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IDLESTATE_EXT_BUSY_SHIFT 0x00000001 +#define GPU_PWR_FALCON_IDLESTATE_EXT_BUSY_FIELDMASK 0x00007fff +#define GPU_PWR_FALCON_OS 0x0010a080 +#define GPU_PWR_FALCON_ENGCTL 0x0010a0a4 +#define GPU_PWR_FALCON_CPUCTL 0x0010a100 +#define GPU_PWR_FALCON_CPUCTL_STARTCPU_SHIFT 0x00000001 +#define GPU_PWR_FALCON_CPUCTL_STARTCPU_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_CPUCTL_HALT_INTR_SHIFT 0x00000004 +#define GPU_PWR_FALCON_CPUCTL_HALT_INTR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_CPUCTL_HALT_INTR_MASK 0x00000010 +#define GPU_PWR_FALCON_CPUCTL_CPUCTL_ALIAS_EN_SHIFT 0x00000006 +#define GPU_PWR_FALCON_CPUCTL_CPUCTL_ALIAS_EN_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_CPUCTL_CPUCTL_ALIAS_EN_MASK 0x00000040 +#define GPU_PWR_FALCON_CPUCTL_ALIAS 0x0010a130 +#define GPU_PWR_FALCON_CPUCTL_ALIAS_STARTCPU_SHIFT 0x00000001 +#define GPU_PWR_FALCON_CPUCTL_ALIAS_STARTCPU_FIELDMASK 0x00000001 +#define GPU_PWR_PMU_SCPCTL_STAT 0x0010ac08 +#define GPU_PWR_PMU_SCPCTL_STAT_DEBUG_MODE_SHIFT 0x00000014 +#define GPU_PWR_PMU_SCPCTL_STAT_DEBUG_MODE_FIELDMASK 0x00000001 +#define GPU_PWR_PMU_SCPCTL_STAT_DEBUG_MODE_MASK 0x00100000 +#define GPU_PWR_FALCON_IMEMC__BASE 0x0010a180 +#define GPU_PWR_FALCON_IMEMC__STRIDE 0x00000010 +#define GPU_PWR_FALCON_IMEMC(i) (0x0010a180 + (i) * 0x00000010) +#define GPU_PWR_FALCON_IMEMC_OFFS_SHIFT 0x00000002 +#define GPU_PWR_FALCON_IMEMC_OFFS_FIELDMASK 0x0000003f +#define GPU_PWR_FALCON_IMEMC_BLK_SHIFT 0x00000008 +#define GPU_PWR_FALCON_IMEMC_BLK_FIELDMASK 0x000000ff +#define GPU_PWR_FALCON_IMEMC_AINCW_SHIFT 0x00000018 +#define GPU_PWR_FALCON_IMEMC_AINCW_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_IMEMD__BASE 0x0010a184 +#define GPU_PWR_FALCON_IMEMD__STRIDE 0x00000010 +#define GPU_PWR_FALCON_IMEMD(i) (0x0010a184 + (i) * 0x00000010) +#define GPU_PWR_FALCON_IMEMT__BASE 0x0010a188 +#define GPU_PWR_FALCON_IMEMT__STRIDE 0x00000010 +#define GPU_PWR_FALCON_IMEMT(i) (0x0010a188 + (i) * 0x00000010) +#define GPU_PWR_FALCON_SCTL 0x0010a240 +#define GPU_PWR_FALCON_MMU_PHYS_SEC 0x00100ce4 +#define GPU_PWR_FALCON_BOOTVEC 0x0010a104 +#define GPU_PWR_FALCON_BOOTVEC_VEC_SHIFT 0x00000000 +#define GPU_PWR_FALCON_BOOTVEC_VEC_FIELDMASK 0xffffffff +#define GPU_PWR_FALCON_DMACTL 0x0010a10c +#define GPU_PWR_FALCON_DMACTL_DMEM_SCRUBBING_MASK 0x00000002 +#define GPU_PWR_FALCON_DMACTL_DMEM_SCRUBBING_SHIFT 0x00000001 +#define GPU_PWR_FALCON_DMACTL_DMEM_SCRUBBING_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_DMACTL_IMEM_SCRUBBING_MASK 0x00000004 +#define GPU_PWR_FALCON_DMACTL_IMEM_SCRUBBING_SHIFT 0x00000002 +#define GPU_PWR_FALCON_DMACTL_IMEM_SCRUBBING_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_HWCFG 0x0010a108 +#define GPU_PWR_FALCON_HWCFG_IMEM_SIZE_SHIFT 0x00000000 +#define GPU_PWR_FALCON_HWCFG_IMEM_SIZE_FIELDMASK 0x000001ff +#define GPU_PWR_FALCON_HWCFG_DMEM_SIZE_SHIFT 0x00000009 +#define GPU_PWR_FALCON_HWCFG_DMEM_SIZE_FIELDMASK 0x000001ff +#define GPU_PWR_FALCON_DMATRFBASE 0x0010a110 +#define GPU_PWR_FALCON_DMATRFMOFFS 0x0010a114 +#define GPU_PWR_FALCON_DMATRFCMD 0x0010a118 +#define GPU_PWR_FALCON_DMATRFCMD_IMEM_SHIFT 0x00000004 +#define GPU_PWR_FALCON_DMATRFCMD_IMEM_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_DMATRFCMD_WRITE_SHIFT 0x00000005 +#define GPU_PWR_FALCON_DMATRFCMD_WRITE_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_DMATRFCMD_SIZE_SHIFT 0x00000008 +#define GPU_PWR_FALCON_DMATRFCMD_SIZE_FIELDMASK 0x00000007 +#define GPU_PWR_FALCON_DMATRFCMD_CTXDMA_SHIFT 0x0000000c +#define GPU_PWR_FALCON_DMATRFCMD_CTXDMA_FIELDMASK 0x00000007 +#define GPU_PWR_FALCON_DMATRFFBOFFS 0x0010a11c +#define GPU_PWR_FALCON_EXTERRADDR 0x0010a168 +#define GPU_PWR_FALCON_EXTERRSTAT 0x0010a16c +#define GPU_PWR_FALCON_EXTERRSTAT_VALID_MASK 0x80000000 +#define GPU_PWR_FALCON_EXTERRSTAT_VALID_SHIFT 0x0000001f +#define GPU_PWR_FALCON_EXTERRSTAT_VALID_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_EXTERRSTAT_VALID_TRUE_V 0x00000001 +#define GPU_PWR_PMU_FALCON_ICD_CMD 0x0010a200 +#define GPU_PWR_PMU_FALCON_ICD_CMD_OPC_SIZE 0x00000004 +#define GPU_PWR_PMU_FALCON_ICD_CMD_OPC_SHIFT 0x00000000 +#define GPU_PWR_PMU_FALCON_ICD_CMD_OPC_FIELDMASK 0x0000000f +#define GPU_PWR_PMU_FALCON_ICD_CMD_OPC_MASK 0x0000000f +#define GPU_PWR_PMU_FALCON_ICD_CMD_OPC_RREG_F 0x00000008 +#define GPU_PWR_PMU_FALCON_ICD_CMD_OPC_RSTAT_F 0x0000000e +#define GPU_PWR_PMU_FALCON_ICD_CMD_IDX_SHIFT 0x00000008 +#define GPU_PWR_PMU_FALCON_ICD_CMD_IDX_FIELDMASK 0x0000001f +#define GPU_PWR_PMU_FALCON_ICD_RDATA 0x0010a20c +#define GPU_PWR_FALCON_DMEMC__BASE 0x0010a1c0 +#define GPU_PWR_FALCON_DMEMC__STRIDE 0x00000008 +#define GPU_PWR_FALCON_DMEMC(i) (0x0010a1c0 + (i) * 0x00000008) +#define GPU_PWR_FALCON_DMEMC_OFFS_SHIFT 0x00000002 +#define GPU_PWR_FALCON_DMEMC_OFFS_FIELDMASK 0x0000003f +#define GPU_PWR_FALCON_DMEMC_OFFS_MASK 0x000000fc +#define GPU_PWR_FALCON_DMEMC_BLK_SHIFT 0x00000008 +#define GPU_PWR_FALCON_DMEMC_BLK_FIELDMASK 0x000000ff +#define GPU_PWR_FALCON_DMEMC_BLK_MASK 0x0000ff00 +#define GPU_PWR_FALCON_DMEMC_AINCW_SHIFT 0x00000018 +#define GPU_PWR_FALCON_DMEMC_AINCW_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_DMEMC_AINCR_SHIFT 0x00000019 +#define GPU_PWR_FALCON_DMEMC_AINCR_FIELDMASK 0x00000001 +#define GPU_PWR_FALCON_DMEMD__BASE 0x0010a1c4 +#define GPU_PWR_FALCON_DMEMD__STRIDE 0x00000008 +#define GPU_PWR_FALCON_DMEMD(i) (0x0010a1c4 + (i) * 0x00000008) +#define GPU_PWR_PMU_NEW_INSTBLK 0x0010a480 +#define GPU_PWR_PMU_NEW_INSTBLK_PTR_SHIFT 0x00000000 +#define GPU_PWR_PMU_NEW_INSTBLK_PTR_FIELDMASK 0x0fffffff +#define GPU_PWR_PMU_NEW_INSTBLK_TARGET_FB_F 0x00000000 +#define GPU_PWR_PMU_NEW_INSTBLK_TARGET_SYS_COH_F 0x20000000 +#define GPU_PWR_PMU_NEW_INSTBLK_TARGET_SYS_NCOH_F 0x30000000 +#define GPU_PWR_PMU_NEW_INSTBLK_VALID_SHIFT 0x0000001e +#define GPU_PWR_PMU_NEW_INSTBLK_VALID_FIELDMASK 0x00000001 +#define GPU_PWR_PMU_MUTEX_ID 0x0010a488 +#define GPU_PWR_PMU_MUTEX_ID_VALUE_SHIFT 0x00000000 +#define GPU_PWR_PMU_MUTEX_ID_VALUE_FIELDMASK 0x000000ff +#define GPU_PWR_PMU_MUTEX_ID_VALUE_INIT_V 0x00000000 +#define GPU_PWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL_V 0x000000ff +#define GPU_PWR_PMU_MUTEX_ID_RELEASE 0x0010a48c +#define GPU_PWR_PMU_MUTEX_ID_RELEASE_VALUE_SHIFT 0x00000000 +#define GPU_PWR_PMU_MUTEX_ID_RELEASE_VALUE_FIELDMASK 0x000000ff +#define GPU_PWR_PMU_MUTEX_ID_RELEASE_VALUE_MASK 0x000000ff +#define GPU_PWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT_V 0x00000000 +#define GPU_PWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT_F 0x00000000 +#define GPU_PWR_PMU_MUTEX__BASE 0x0010a580 +#define GPU_PWR_PMU_MUTEX__STRIDE 0x00000004 +#define GPU_PWR_PMU_MUTEX(i) (0x0010a580 + (i) * 0x00000004) +#define GPU_PWR_PMU_MUTEX__SIZE_1_V 0x00000010 +#define GPU_PWR_PMU_MUTEX_VALUE_SHIFT 0x00000000 +#define GPU_PWR_PMU_MUTEX_VALUE_FIELDMASK 0x000000ff +#define GPU_PWR_PMU_MUTEX_VALUE_INITIAL_LOCK_F 0x00000000 +#define GPU_PWR_PMU_QUEUE_HEAD__BASE 0x0010a4a0 +#define GPU_PWR_PMU_QUEUE_HEAD__STRIDE 0x00000004 +#define GPU_PWR_PMU_QUEUE_HEAD(i) (0x0010a4a0 + (i) * 0x00000004) +#define GPU_PWR_PMU_QUEUE_HEAD__SIZE_1_V 0x00000004 +#define GPU_PWR_PMU_QUEUE_HEAD_ADDRESS_SHIFT 0x00000000 +#define GPU_PWR_PMU_QUEUE_HEAD_ADDRESS_FIELDMASK 0xffffffff +#define GPU_PWR_PMU_QUEUE_TAIL__BASE 0x0010a4b0 +#define GPU_PWR_PMU_QUEUE_TAIL__STRIDE 0x00000004 +#define GPU_PWR_PMU_QUEUE_TAIL(i) (0x0010a4b0 + (i) * 0x00000004) +#define GPU_PWR_PMU_QUEUE_TAIL__SIZE_1_V 0x00000004 +#define GPU_PWR_PMU_QUEUE_TAIL_ADDRESS_SHIFT 0x00000000 +#define GPU_PWR_PMU_QUEUE_TAIL_ADDRESS_FIELDMASK 0xffffffff +#define GPU_PWR_PMU_MSGQ_HEAD 0x0010a4c8 +#define GPU_PWR_PMU_MSGQ_HEAD_VAL_SHIFT 0x00000000 +#define GPU_PWR_PMU_MSGQ_HEAD_VAL_FIELDMASK 0xffffffff +#define GPU_PWR_PMU_MSGQ_TAIL 0x0010a4cc +#define GPU_PWR_PMU_MSGQ_TAIL_VAL_SHIFT 0x00000000 +#define GPU_PWR_PMU_MSGQ_TAIL_VAL_FIELDMASK 0xffffffff +#define GPU_PWR_PMU_IDLE_MASK__BASE 0x0010a504 +#define GPU_PWR_PMU_IDLE_MASK__STRIDE 0x00000010 +#define GPU_PWR_PMU_IDLE_MASK(i) (0x0010a504 + (i) * 0x00000010) +#define GPU_PWR_PMU_IDLE_MASK_GR_ENABLED_F 0x00000001 +#define GPU_PWR_PMU_IDLE_MASK_CE_2_ENABLED_F 0x00200000 +#define GPU_PWR_PMU_IDLE_COUNT__BASE 0x0010a508 +#define GPU_PWR_PMU_IDLE_COUNT__STRIDE 0x00000010 +#define GPU_PWR_PMU_IDLE_COUNT(i) (0x0010a508 + (i) * 0x00000010) +#define GPU_PWR_PMU_IDLE_COUNT_VALUE_SHIFT 0x00000000 +#define GPU_PWR_PMU_IDLE_COUNT_VALUE_FIELDMASK 0x7fffffff +#define GPU_PWR_PMU_IDLE_COUNT_RESET_SHIFT 0x0000001f +#define GPU_PWR_PMU_IDLE_COUNT_RESET_FIELDMASK 0x00000001 +#define GPU_PWR_PMU_IDLE_CTRL__BASE 0x0010a50c +#define GPU_PWR_PMU_IDLE_CTRL__STRIDE 0x00000010 +#define GPU_PWR_PMU_IDLE_CTRL(i) (0x0010a50c + (i) * 0x00000010) +#define GPU_PWR_PMU_IDLE_CTRL_VALUE_MASK 0x00000003 +#define GPU_PWR_PMU_IDLE_CTRL_VALUE_SHIFT 0x00000000 +#define GPU_PWR_PMU_IDLE_CTRL_VALUE_FIELDMASK 0x00000003 +#define GPU_PWR_PMU_IDLE_CTRL_VALUE_BUSY_F 0x00000002 +#define GPU_PWR_PMU_IDLE_CTRL_VALUE_ALWAYS_F 0x00000003 +#define GPU_PWR_PMU_IDLE_CTRL_FILTER_MASK 0x00000004 +#define GPU_PWR_PMU_IDLE_CTRL_FILTER_SHIFT 0x00000002 +#define GPU_PWR_PMU_IDLE_CTRL_FILTER_FIELDMASK 0x00000001 +#define GPU_PWR_PMU_IDLE_CTRL_FILTER_DISABLED_F 0x00000000 +#define GPU_PWR_PMU_IDLE_MASK_SUPP__BASE 0x0010a9f0 +#define GPU_PWR_PMU_IDLE_MASK_SUPP__STRIDE 0x00000008 +#define GPU_PWR_PMU_IDLE_MASK_SUPP(i) (0x0010a9f0 + (i) * 0x00000008) +#define GPU_PWR_PMU_IDLE_MASK_1_SUPP__BASE 0x0010a9f4 +#define GPU_PWR_PMU_IDLE_MASK_1_SUPP__STRIDE 0x00000008 +#define GPU_PWR_PMU_IDLE_MASK_1_SUPP(i) (0x0010a9f4 + (i) * 0x00000008) +#define GPU_PWR_PMU_IDLE_CTRL_SUPP__BASE 0x0010aa30 +#define GPU_PWR_PMU_IDLE_CTRL_SUPP__STRIDE 0x00000008 +#define GPU_PWR_PMU_IDLE_CTRL_SUPP(i) (0x0010aa30 + (i) * 0x00000008) +#define GPU_PWR_PMU_DEBUG__BASE 0x0010a5c0 +#define GPU_PWR_PMU_DEBUG__STRIDE 0x00000004 +#define GPU_PWR_PMU_DEBUG(i) (0x0010a5c0 + (i) * 0x00000004) +#define GPU_PWR_PMU_DEBUG__SIZE_1_V 0x00000004 +#define GPU_PWR_PMU_MAILBOX__BASE 0x0010a450 +#define GPU_PWR_PMU_MAILBOX__STRIDE 0x00000004 +#define GPU_PWR_PMU_MAILBOX(i) (0x0010a450 + (i) * 0x00000004) +#define GPU_PWR_PMU_MAILBOX__SIZE_1_V 0x0000000c +#define GPU_PWR_PMU_BAR0_ADDR 0x0010a7a0 +#define GPU_PWR_PMU_BAR0_DATA 0x0010a7a4 +#define GPU_PWR_PMU_BAR0_CTL 0x0010a7ac +#define GPU_PWR_PMU_BAR0_TIMEOUT 0x0010a7a8 +#define GPU_PWR_PMU_BAR0_FECS_ERROR 0x0010a988 +#define GPU_PWR_PMU_BAR0_ERROR_STATUS 0x0010a7b0 +#define GPU_PWR_PMU_PG_IDLEFILTH__BASE 0x0010a6c0 +#define GPU_PWR_PMU_PG_IDLEFILTH__STRIDE 0x00000004 +#define GPU_PWR_PMU_PG_IDLEFILTH(i) (0x0010a6c0 + (i) * 0x00000004) +#define GPU_PWR_PMU_PG_PPUIDLEFILTH__BASE 0x0010a6e8 +#define GPU_PWR_PMU_PG_PPUIDLEFILTH__STRIDE 0x00000004 +#define GPU_PWR_PMU_PG_PPUIDLEFILTH(i) (0x0010a6e8 + (i) * 0x00000004) +#define GPU_PWR_PMU_PG_IDLE_CNT__BASE 0x0010a710 +#define GPU_PWR_PMU_PG_IDLE_CNT__STRIDE 0x00000004 +#define GPU_PWR_PMU_PG_IDLE_CNT(i) (0x0010a710 + (i) * 0x00000004) +#define GPU_PWR_PMU_PG_INTREN__BASE 0x0010a760 +#define GPU_PWR_PMU_PG_INTREN__STRIDE 0x00000004 +#define GPU_PWR_PMU_PG_INTREN(i) (0x0010a760 + (i) * 0x00000004) +#define GPU_PWR_FBIF_TRANSCFG__BASE 0x0010ae00 +#define GPU_PWR_FBIF_TRANSCFG__STRIDE 0x00000004 +#define GPU_PWR_FBIF_TRANSCFG(i) (0x0010ae00 + (i) * 0x00000004) +#define GPU_PWR_FBIF_TRANSCFG_TARGET_LOCAL_FB_F 0x00000000 +#define GPU_PWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM_F 0x00000001 +#define GPU_PWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM_F 0x00000002 +#define GPU_PWR_FBIF_TRANSCFG_MEM_TYPE_SIZE 0x00000001 +#define GPU_PWR_FBIF_TRANSCFG_MEM_TYPE_SHIFT 0x00000002 +#define GPU_PWR_FBIF_TRANSCFG_MEM_TYPE_FIELDMASK 0x00000001 +#define GPU_PWR_FBIF_TRANSCFG_MEM_TYPE_MASK 0x00000004 +#define GPU_PWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL_F 0x00000000 +#define GPU_PWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL_F 0x00000004 + +#define GPU_RAM_IN_RAMFC_SIZE 0x00001000 +#define GPU_RAM_IN_RAMFC_W 0x00000000 +#define GPU_RAM_IN_PAGE_DIR_BASE_TARGET_SHIFT 0x00000000 +#define GPU_RAM_IN_PAGE_DIR_BASE_TARGET_FIELDMASK 0x00000003 +#define GPU_RAM_IN_PAGE_DIR_BASE_TARGET_W 0x00000080 +#define GPU_RAM_IN_PAGE_DIR_BASE_TARGET_VID_MEM_F 0x00000000 +#define GPU_RAM_IN_PAGE_DIR_BASE_TARGET_SYS_MEM_COH_F 0x00000002 +#define GPU_RAM_IN_PAGE_DIR_BASE_TARGET_SYS_MEM_NCOH_F 0x00000003 +#define GPU_RAM_IN_PAGE_DIR_BASE_VOL_W 0x00000080 +#define GPU_RAM_IN_PAGE_DIR_BASE_VOL_TRUE_F 0x00000004 +#define GPU_RAM_IN_BIG_PAGE_SIZE_SHIFT 0x0000000b +#define GPU_RAM_IN_BIG_PAGE_SIZE_FIELDMASK 0x00000001 +#define GPU_RAM_IN_BIG_PAGE_SIZE_MASK 0x00000800 +#define GPU_RAM_IN_BIG_PAGE_SIZE_W 0x00000080 +#define GPU_RAM_IN_BIG_PAGE_SIZE_128KB_F 0x00000000 +#define GPU_RAM_IN_BIG_PAGE_SIZE_64KB_F 0x00000800 +#define GPU_RAM_IN_PAGE_DIR_BASE_LO_SHIFT 0x0000000c +#define GPU_RAM_IN_PAGE_DIR_BASE_LO_FIELDMASK 0x000fffff +#define GPU_RAM_IN_PAGE_DIR_BASE_LO_W 0x00000080 +#define GPU_RAM_IN_PAGE_DIR_BASE_HI_SHIFT 0x00000000 +#define GPU_RAM_IN_PAGE_DIR_BASE_HI_FIELDMASK 0x000000ff +#define GPU_RAM_IN_PAGE_DIR_BASE_HI_W 0x00000081 +#define GPU_RAM_IN_ADR_LIMIT_LO_SHIFT 0x0000000c +#define GPU_RAM_IN_ADR_LIMIT_LO_FIELDMASK 0x000fffff +#define GPU_RAM_IN_ADR_LIMIT_LO_W 0x00000082 +#define GPU_RAM_IN_ADR_LIMIT_HI_SHIFT 0x00000000 +#define GPU_RAM_IN_ADR_LIMIT_HI_FIELDMASK 0x000000ff +#define GPU_RAM_IN_ADR_LIMIT_HI_W 0x00000083 +#define GPU_RAM_IN_ENGINE_CS_W 0x00000084 +#define GPU_RAM_IN_ENGINE_CS_WFI_V 0x00000000 +#define GPU_RAM_IN_ENGINE_CS_WFI_F 0x00000000 +#define GPU_RAM_IN_ENGINE_CS_FG_V 0x00000001 +#define GPU_RAM_IN_ENGINE_CS_FG_F 0x00000008 +#define GPU_RAM_IN_GR_CS_W 0x00000084 +#define GPU_RAM_IN_GR_CS_WFI_F 0x00000000 +#define GPU_RAM_IN_GR_WFI_TARGET_W 0x00000084 +#define GPU_RAM_IN_GR_WFI_MODE_W 0x00000084 +#define GPU_RAM_IN_GR_WFI_MODE_PHYSICAL_V 0x00000000 +#define GPU_RAM_IN_GR_WFI_MODE_PHYSICAL_F 0x00000000 +#define GPU_RAM_IN_GR_WFI_MODE_VIRTUAL_V 0x00000001 +#define GPU_RAM_IN_GR_WFI_MODE_VIRTUAL_F 0x00000004 +#define GPU_RAM_IN_GR_WFI_PTR_LO_SHIFT 0x0000000c +#define GPU_RAM_IN_GR_WFI_PTR_LO_FIELDMASK 0x000fffff +#define GPU_RAM_IN_GR_WFI_PTR_LO_W 0x00000084 +#define GPU_RAM_IN_GR_WFI_PTR_HI_SHIFT 0x00000000 +#define GPU_RAM_IN_GR_WFI_PTR_HI_FIELDMASK 0x000000ff +#define GPU_RAM_IN_GR_WFI_PTR_HI_W 0x00000085 +#define GPU_RAM_IN_BASE_SHIFT_V 0x0000000c +#define GPU_RAM_IN_ALLOC_SIZE_V 0x00001000 +#define GPU_RAM_FC_SIZE_VAL_V 0x00000200 +#define GPU_RAM_FC_GP_PUT_W 0x00000000 +#define GPU_RAM_FC_USERD_W 0x00000002 +#define GPU_RAM_FC_USERD_HI_W 0x00000003 +#define GPU_RAM_FC_SIGNATURE_W 0x00000004 +#define GPU_RAM_FC_GP_GET_W 0x00000005 +#define GPU_RAM_FC_PB_GET_W 0x00000006 +#define GPU_RAM_FC_PB_GET_HI_W 0x00000007 +#define GPU_RAM_FC_PB_TOP_LEVEL_GET_W 0x00000008 +#define GPU_RAM_FC_PB_TOP_LEVEL_GET_HI_W 0x00000009 +#define GPU_RAM_FC_ACQUIRE_W 0x0000000c +#define GPU_RAM_FC_SEMAPHOREA_W 0x0000000e +#define GPU_RAM_FC_SEMAPHOREB_W 0x0000000f +#define GPU_RAM_FC_SEMAPHOREC_W 0x00000010 +#define GPU_RAM_FC_SEMAPHORED_W 0x00000011 +#define GPU_RAM_FC_GP_BASE_W 0x00000012 +#define GPU_RAM_FC_GP_BASE_HI_W 0x00000013 +#define GPU_RAM_FC_GP_FETCH_W 0x00000014 +#define GPU_RAM_FC_PB_FETCH_W 0x00000015 +#define GPU_RAM_FC_PB_FETCH_HI_W 0x00000016 +#define GPU_RAM_FC_PB_PUT_W 0x00000017 +#define GPU_RAM_FC_PB_PUT_HI_W 0x00000018 +#define GPU_RAM_FC_PB_HEADER_W 0x00000021 +#define GPU_RAM_FC_PB_COUNT_W 0x00000022 +#define GPU_RAM_FC_SUBDEVICE_W 0x00000025 +#define GPU_RAM_FC_FORMATS_W 0x00000027 +#define GPU_RAM_FC_SYNCPOINTA_W 0x00000029 +#define GPU_RAM_FC_SYNCPOINTB_W 0x0000002a +#define GPU_RAM_FC_TARGET_W 0x0000002b +#define GPU_RAM_FC_HCE_CTRL_W 0x00000039 +#define GPU_RAM_FC_CHID_W 0x0000003a +#define GPU_RAM_FC_CHID_ID_SHIFT 0x00000000 +#define GPU_RAM_FC_CHID_ID_FIELDMASK 0x00000fff +#define GPU_RAM_FC_CHID_ID_W 0x00000000 +#define GPU_RAM_FC_RUNLIST_TIMESLICE_W 0x0000003e +#define GPU_RAM_USERD_BASE_SHIFT_V 0x00000009 +#define GPU_RAM_USERD_CHAN_SIZE_V 0x00000200 +#define GPU_RAM_USERD_PUT_W 0x00000010 +#define GPU_RAM_USERD_GET_W 0x00000011 +#define GPU_RAM_USERD_REF_W 0x00000012 +#define GPU_RAM_USERD_PUT_HI_W 0x00000013 +#define GPU_RAM_USERD_REF_THRESHOLD_W 0x00000014 +#define GPU_RAM_USERD_TOP_LEVEL_GET_W 0x00000016 +#define GPU_RAM_USERD_TOP_LEVEL_GET_HI_W 0x00000017 +#define GPU_RAM_USERD_GET_HI_W 0x00000018 +#define GPU_RAM_USERD_GP_GET_W 0x00000022 +#define GPU_RAM_USERD_GP_PUT_W 0x00000023 +#define GPU_RAM_USERD_GP_TOP_LEVEL_GET_W 0x00000016 +#define GPU_RAM_USERD_GP_TOP_LEVEL_GET_HI_W 0x00000017 +#define GPU_RAM_RL_ENTRY_SIZE_V 0x00000008 +#define GPU_RAM_RL_ENTRY_CHID_SHIFT 0x00000000 +#define GPU_RAM_RL_ENTRY_CHID_FIELDMASK 0x00000fff +#define GPU_RAM_RL_ENTRY_ID_SHIFT 0x00000000 +#define GPU_RAM_RL_ENTRY_ID_FIELDMASK 0x00000fff +#define GPU_RAM_RL_ENTRY_TYPE_SHIFT 0x0000000d +#define GPU_RAM_RL_ENTRY_TYPE_FIELDMASK 0x00000001 +#define GPU_RAM_RL_ENTRY_TYPE_CHID_F 0x00000000 +#define GPU_RAM_RL_ENTRY_TYPE_TSG_F 0x00002000 +#define GPU_RAM_RL_ENTRY_TIMESLICE_SCALE_SHIFT 0x0000000e +#define GPU_RAM_RL_ENTRY_TIMESLICE_SCALE_FIELDMASK 0x0000000f +#define GPU_RAM_RL_ENTRY_TIMESLICE_SCALE_3_F 0x0000c000 +#define GPU_RAM_RL_ENTRY_TIMESLICE_TIMEOUT_SHIFT 0x00000012 +#define GPU_RAM_RL_ENTRY_TIMESLICE_TIMEOUT_FIELDMASK 0x000000ff +#define GPU_RAM_RL_ENTRY_TIMESLICE_TIMEOUT_128_F 0x02000000 +#define GPU_RAM_RL_ENTRY_TSG_LENGTH_SHIFT 0x0000001a +#define GPU_RAM_RL_ENTRY_TSG_LENGTH_FIELDMASK 0x0000003f + +#define GPU_THERM_USE_A 0x00020798 +#define GPU_THERM_USE_A_EXT_THERM_0_ENABLE_F 0x00000001 +#define GPU_THERM_USE_A_EXT_THERM_1_ENABLE_F 0x00000002 +#define GPU_THERM_USE_A_EXT_THERM_2_ENABLE_F 0x00000004 +#define GPU_THERM_EVT_EXT_THERM_0 0x00020700 +#define GPU_THERM_EVT_EXT_THERM_0_SLOW_FACTOR_SHIFT 0x00000008 +#define GPU_THERM_EVT_EXT_THERM_0_SLOW_FACTOR_FIELDMASK 0x0000003f +#define GPU_THERM_EVT_EXT_THERM_0_SLOW_FACTOR_INIT_V 0x00000000 +#define GPU_THERM_EVT_EXT_THERM_1 0x00020704 +#define GPU_THERM_EVT_EXT_THERM_1_SLOW_FACTOR_SHIFT 0x00000008 +#define GPU_THERM_EVT_EXT_THERM_1_SLOW_FACTOR_FIELDMASK 0x0000003f +#define GPU_THERM_EVT_EXT_THERM_1_SLOW_FACTOR_INIT_V 0x00000000 +#define GPU_THERM_EVT_EXT_THERM_2 0x00020708 +#define GPU_THERM_EVT_EXT_THERM_2_SLOW_FACTOR_SHIFT 0x00000008 +#define GPU_THERM_EVT_EXT_THERM_2_SLOW_FACTOR_FIELDMASK 0x0000003f +#define GPU_THERM_EVT_EXT_THERM_2_SLOW_FACTOR_INIT_V 0x00000000 +#define GPU_THERM_WEIGHT_1 0x00020024 +#define GPU_THERM_CONFIG1 0x00020050 +#define GPU_THERM_CONFIG2 0x00020130 +#define GPU_THERM_CONFIG2_SLOWDOWN_FACTOR_EXTENDED_SHIFT 0x00000018 +#define GPU_THERM_CONFIG2_SLOWDOWN_FACTOR_EXTENDED_FIELDMASK 0x00000001 +#define GPU_THERM_CONFIG2_GRAD_ENABLE_SHIFT 0x0000001f +#define GPU_THERM_CONFIG2_GRAD_ENABLE_FIELDMASK 0x00000001 +#define GPU_THERM_GATE_CTRL__BASE 0x00020200 +#define GPU_THERM_GATE_CTRL__STRIDE 0x00000004 +#define GPU_THERM_GATE_CTRL(i) (0x00020200 + (i) * 0x00000004) +#define GPU_THERM_GATE_CTRL_ENG_CLK_MASK 0x00000003 +#define GPU_THERM_GATE_CTRL_ENG_CLK_SHIFT 0x00000000 +#define GPU_THERM_GATE_CTRL_ENG_CLK_FIELDMASK 0x00000003 +#define GPU_THERM_GATE_CTRL_ENG_CLK_RUN_F 0x00000000 +#define GPU_THERM_GATE_CTRL_ENG_CLK_AUTO_F 0x00000001 +#define GPU_THERM_GATE_CTRL_ENG_CLK_STOP_F 0x00000002 +#define GPU_THERM_GATE_CTRL_BLK_CLK_MASK 0x0000000c +#define GPU_THERM_GATE_CTRL_BLK_CLK_SHIFT 0x00000002 +#define GPU_THERM_GATE_CTRL_BLK_CLK_FIELDMASK 0x00000003 +#define GPU_THERM_GATE_CTRL_BLK_CLK_RUN_F 0x00000000 +#define GPU_THERM_GATE_CTRL_BLK_CLK_AUTO_F 0x00000004 +#define GPU_THERM_GATE_CTRL_ENG_PWR_MASK 0x00000030 +#define GPU_THERM_GATE_CTRL_ENG_PWR_SHIFT 0x00000004 +#define GPU_THERM_GATE_CTRL_ENG_PWR_FIELDMASK 0x00000003 +#define GPU_THERM_GATE_CTRL_ENG_PWR_AUTO_F 0x00000010 +#define GPU_THERM_GATE_CTRL_ENG_PWR_OFF_V 0x00000002 +#define GPU_THERM_GATE_CTRL_ENG_PWR_OFF_F 0x00000020 +#define GPU_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP_SHIFT 0x00000008 +#define GPU_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP_FIELDMASK 0x0000001f +#define GPU_THERM_GATE_CTRL_ENG_IDLE_FILT_EXP_MASK 0x00001f00 +#define GPU_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT_SHIFT 0x0000000d +#define GPU_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT_FIELDMASK 0x00000007 +#define GPU_THERM_GATE_CTRL_ENG_IDLE_FILT_MANT_MASK 0x0000e000 +#define GPU_THERM_GATE_CTRL_ENG_DELAY_BEFORE_SHIFT 0x00000010 +#define GPU_THERM_GATE_CTRL_ENG_DELAY_BEFORE_FIELDMASK 0x0000000f +#define GPU_THERM_GATE_CTRL_ENG_DELAY_BEFORE_MASK 0x000f0000 +#define GPU_THERM_GATE_CTRL_ENG_DELAY_AFTER_SHIFT 0x00000014 +#define GPU_THERM_GATE_CTRL_ENG_DELAY_AFTER_FIELDMASK 0x0000000f +#define GPU_THERM_GATE_CTRL_ENG_DELAY_AFTER_MASK 0x00f00000 +#define GPU_THERM_FECS_IDLE_FILTER 0x00020288 +#define GPU_THERM_FECS_IDLE_FILTER_VALUE_MASK 0xffffffff +#define GPU_THERM_FECS_IDLE_FILTER_VALUE_SHIFT 0x00000000 +#define GPU_THERM_FECS_IDLE_FILTER_VALUE_FIELDMASK 0xffffffff +#define GPU_THERM_HUBMMU_IDLE_FILTER 0x0002028c +#define GPU_THERM_HUBMMU_IDLE_FILTER_VALUE_MASK 0xffffffff +#define GPU_THERM_HUBMMU_IDLE_FILTER_VALUE_SHIFT 0x00000000 +#define GPU_THERM_HUBMMU_IDLE_FILTER_VALUE_FIELDMASK 0xffffffff +#define GPU_THERM_CLK_SLOWDOWN__BASE 0x00020160 +#define GPU_THERM_CLK_SLOWDOWN__STRIDE 0x00000004 +#define GPU_THERM_CLK_SLOWDOWN(i) (0x00020160 + (i) * 0x00000004) +#define GPU_THERM_CLK_SLOWDOWN_IDLE_FACTOR_SHIFT 0x00000010 +#define GPU_THERM_CLK_SLOWDOWN_IDLE_FACTOR_FIELDMASK 0x0000003f +#define GPU_THERM_CLK_SLOWDOWN_IDLE_FACTOR_MASK 0x003f0000 +#define GPU_THERM_CLK_SLOWDOWN_IDLE_FACTOR_DISABLED_F 0x00000000 +#define GPU_THERM_GRAD_STEPPING_TABLE__BASE 0x000202c8 +#define GPU_THERM_GRAD_STEPPING_TABLE__STRIDE 0x00000004 +#define GPU_THERM_GRAD_STEPPING_TABLE(i) (0x000202c8 + (i) * 0x00000004) +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0_SHIFT 0x00000000 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0_FIELDMASK 0x0000003f +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0_MASK 0x0000003f +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0_FPDIV_BY1P5_F 0x00000001 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0_FPDIV_BY2_F 0x00000002 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0_FPDIV_BY4_F 0x00000006 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR0_FPDIV_BY8_F 0x0000000e +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR1_SHIFT 0x00000006 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR1_FIELDMASK 0x0000003f +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR1_MASK 0x00000fc0 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR2_SHIFT 0x0000000c +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR2_FIELDMASK 0x0000003f +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR2_MASK 0x0003f000 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR3_SHIFT 0x00000012 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR3_FIELDMASK 0x0000003f +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR3_MASK 0x00fc0000 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR4_SHIFT 0x00000018 +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR4_FIELDMASK 0x0000003f +#define GPU_THERM_GRAD_STEPPING_TABLE_SLOWDOWN_FACTOR4_MASK 0x3f000000 +#define GPU_THERM_GRAD_STEPPING0 0x000202c0 +#define GPU_THERM_GRAD_STEPPING0_FEATURE_SIZE 0x00000001 +#define GPU_THERM_GRAD_STEPPING0_FEATURE_SHIFT 0x00000000 +#define GPU_THERM_GRAD_STEPPING0_FEATURE_FIELDMASK 0x00000001 +#define GPU_THERM_GRAD_STEPPING0_FEATURE_MASK 0x00000001 +#define GPU_THERM_GRAD_STEPPING0_FEATURE_ENABLE_F 0x00000001 +#define GPU_THERM_GRAD_STEPPING1 0x000202c4 +#define GPU_THERM_GRAD_STEPPING1_PDIV_DURATION_SHIFT 0x00000000 +#define GPU_THERM_GRAD_STEPPING1_PDIV_DURATION_FIELDMASK 0x0001ffff +#define GPU_THERM_CLK_TIMING__BASE 0x000203c0 +#define GPU_THERM_CLK_TIMING__STRIDE 0x00000004 +#define GPU_THERM_CLK_TIMING(i) (0x000203c0 + (i) * 0x00000004) +#define GPU_THERM_CLK_TIMING_GRAD_SLOWDOWN_SHIFT 0x00000010 +#define GPU_THERM_CLK_TIMING_GRAD_SLOWDOWN_FIELDMASK 0x00000001 +#define GPU_THERM_CLK_TIMING_GRAD_SLOWDOWN_MASK 0x00010000 +#define GPU_THERM_CLK_TIMING_GRAD_SLOWDOWN_ENABLED_F 0x00010000 + +#define GPU_TIMER_PRI_TIMEOUT 0x00009080 +#define GPU_TIMER_PRI_TIMEOUT_PERIOD_SHIFT 0x00000000 +#define GPU_TIMER_PRI_TIMEOUT_PERIOD_FIELDMASK 0x00ffffff +#define GPU_TIMER_PRI_TIMEOUT_PERIOD_MASK 0x00ffffff +#define GPU_TIMER_PRI_TIMEOUT_EN_SHIFT 0x0000001f +#define GPU_TIMER_PRI_TIMEOUT_EN_FIELDMASK 0x00000001 +#define GPU_TIMER_PRI_TIMEOUT_EN_MASK 0x80000000 +#define GPU_TIMER_PRI_TIMEOUT_EN_EN_ENABLED_F 0x80000000 +#define GPU_TIMER_PRI_TIMEOUT_EN_EN_DISABLED_F 0x00000000 +#define GPU_TIMER_PRI_TIMEOUT_SAVE_0 0x00009084 +#define GPU_TIMER_PRI_TIMEOUT_SAVE_1 0x00009088 +#define GPU_TIMER_PRI_TIMEOUT_FECS_ERRCODE 0x0000908c +#define GPU_TIMER_TIME_0 0x00009400 +#define GPU_TIMER_TIME_1 0x00009410 + +#define GPU_TOP_NUM_GPCS 0x00022430 +#define GPU_TOP_NUM_GPCS_VALUE_SHIFT 0x00000000 +#define GPU_TOP_NUM_GPCS_VALUE_FIELDMASK 0x0000001f +#define GPU_TOP_TPC_PER_GPC 0x00022434 +#define GPU_TOP_TPC_PER_GPC_VALUE_SHIFT 0x00000000 +#define GPU_TOP_TPC_PER_GPC_VALUE_FIELDMASK 0x0000001f +#define GPU_TOP_NUM_FBPS 0x00022438 +#define GPU_TOP_NUM_FBPS_VALUE_SHIFT 0x00000000 +#define GPU_TOP_NUM_FBPS_VALUE_FIELDMASK 0x0000001f +#define GPU_TOP_LTC_PER_FBP 0x00022450 +#define GPU_TOP_LTC_PER_FBP_VALUE_SHIFT 0x00000000 +#define GPU_TOP_LTC_PER_FBP_VALUE_FIELDMASK 0x0000001f +#define GPU_TOP_SLICES_PER_LTC 0x0002245c +#define GPU_TOP_SLICES_PER_LTC_VALUE_SHIFT 0x00000000 +#define GPU_TOP_SLICES_PER_LTC_VALUE_FIELDMASK 0x0000001f +#define GPU_TOP_NUM_LTCS 0x00022454 +#define GPU_TOP_DEVICE_INFO__BASE 0x00022700 +#define GPU_TOP_DEVICE_INFO__STRIDE 0x00000004 +#define GPU_TOP_DEVICE_INFO(i) (0x00022700 + (i) * 0x00000004) +#define GPU_TOP_DEVICE_INFO__SIZE_1_V 0x00000040 +#define GPU_TOP_DEVICE_INFO_CHAIN_SHIFT 0x0000001f +#define GPU_TOP_DEVICE_INFO_CHAIN_FIELDMASK 0x00000001 +#define GPU_TOP_DEVICE_INFO_CHAIN_ENABLE_V 0x00000001 +#define GPU_TOP_DEVICE_INFO_ENGINE_ENUM_SHIFT 0x0000001a +#define GPU_TOP_DEVICE_INFO_ENGINE_ENUM_FIELDMASK 0x0000000f +#define GPU_TOP_DEVICE_INFO_RUNLIST_ENUM_SHIFT 0x00000015 +#define GPU_TOP_DEVICE_INFO_RUNLIST_ENUM_FIELDMASK 0x0000000f +#define GPU_TOP_DEVICE_INFO_INTR_ENUM_SHIFT 0x0000000f +#define GPU_TOP_DEVICE_INFO_INTR_ENUM_FIELDMASK 0x0000001f +#define GPU_TOP_DEVICE_INFO_RESET_ENUM_SHIFT 0x00000009 +#define GPU_TOP_DEVICE_INFO_RESET_ENUM_FIELDMASK 0x0000001f +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_SHIFT 0x00000002 +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_FIELDMASK 0x1fffffff +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS_V 0x00000000 +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_GRAPHICS_F 0x00000000 +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_COPY0_V 0x00000001 +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_COPY0_F 0x00000004 +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_COPY1_V 0x00000002 +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_COPY1_F 0x00000008 +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_COPY2_V 0x00000003 +#define GPU_TOP_DEVICE_INFO_TYPE_ENUM_COPY2_F 0x0000000c +#define GPU_TOP_DEVICE_INFO_ENGINE_SHIFT 0x00000005 +#define GPU_TOP_DEVICE_INFO_ENGINE_FIELDMASK 0x00000001 +#define GPU_TOP_DEVICE_INFO_RUNLIST_SHIFT 0x00000004 +#define GPU_TOP_DEVICE_INFO_RUNLIST_FIELDMASK 0x00000001 +#define GPU_TOP_DEVICE_INFO_INTR_SHIFT 0x00000003 +#define GPU_TOP_DEVICE_INFO_INTR_FIELDMASK 0x00000001 +#define GPU_TOP_DEVICE_INFO_RESET_SHIFT 0x00000002 +#define GPU_TOP_DEVICE_INFO_RESET_FIELDMASK 0x00000001 +#define GPU_TOP_DEVICE_INFO_ENTRY_SHIFT 0x00000000 +#define GPU_TOP_DEVICE_INFO_ENTRY_FIELDMASK 0x00000003 +#define GPU_TOP_DEVICE_INFO_ENTRY_NOT_VALID_V 0x00000000 +#define GPU_TOP_DEVICE_INFO_ENTRY_ENUM_V 0x00000002 +#define GPU_TOP_DEVICE_INFO_ENTRY_ENGINE_TYPE_V 0x00000003 +#define GPU_TOP_DEVICE_INFO_ENTRY_DATA_V 0x00000001 +#define GPU_TOP_DEVICE_INFO_DATA_TYPE_SHIFT 0x0000001e +#define GPU_TOP_DEVICE_INFO_DATA_TYPE_FIELDMASK 0x00000001 +#define GPU_TOP_DEVICE_INFO_DATA_TYPE_ENUM2_V 0x00000000 +#define GPU_TOP_DEVICE_INFO_DATA_PRI_BASE_SHIFT 0x0000000c +#define GPU_TOP_DEVICE_INFO_DATA_PRI_BASE_FIELDMASK 0x000007ff +#define GPU_TOP_DEVICE_INFO_DATA_PRI_BASE_ALIGN_V 0x0000000c +#define GPU_TOP_DEVICE_INFO_DATA_FAULT_ID_ENUM_SHIFT 0x00000003 +#define GPU_TOP_DEVICE_INFO_DATA_FAULT_ID_ENUM_FIELDMASK 0x0000001f +#define GPU_TOP_DEVICE_INFO_DATA_FAULT_ID_SHIFT 0x00000002 +#define GPU_TOP_DEVICE_INFO_DATA_FAULT_ID_FIELDMASK 0x00000001 +#define GPU_TOP_DEVICE_INFO_DATA_FAULT_ID_VALID_V 0x00000001 + +#define GPU_TRIM_SYS_GPCPLL_CFG 0x00137000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_MASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_NO_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_YES_F 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_IDDQ_MASK 0x00000002 +#define GPU_TRIM_SYS_GPCPLL_CFG_IDDQ_SHIFT 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_IDDQ_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON_V 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_MASK 0x00000004 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_SHIFT 0x00000002 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE_F 0x00000004 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_MASK 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_SHIFT 0x00000004 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF_F 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_CFG_PLL_LOCK_SHIFT 0x00000011 +#define GPU_TRIM_SYS_GPCPLL_CFG_PLL_LOCK_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_PLL_LOCK_TRUE_F 0x00020000 +#define GPU_TRIM_SYS_GPCPLL_COEFF 0x00137004 +#define GPU_TRIM_SYS_GPCPLL_COEFF_MDIV_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_COEFF_MDIV_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_COEFF_MDIV_MASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_COEFF_NDIV_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPCPLL_COEFF_NDIV_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_COEFF_NDIV_MASK 0x0000ff00 +#define GPU_TRIM_SYS_GPCPLL_COEFF_PLDIV_SHIFT 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_COEFF_PLDIV_FIELDMASK 0x0000003f +#define GPU_TRIM_SYS_GPCPLL_COEFF_PLDIV_MASK 0x003f0000 +#define GPU_TRIM_SYS_SEL_VCO 0x00137100 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_MASK 0x00000001 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_SHIFT 0x00000000 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT_V 0x00000000 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT_F 0x00000000 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS_F 0x00000000 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO_F 0x00000001 +#define GPU_TRIM_SYS_GPC2CLK_OUT 0x00137250 +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_SIZE 0x00000006 +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_FIELDMASK 0x0000003f +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_MASK 0x0000003f +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31_F 0x0000003c +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_SIZE 0x00000006 +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_FIELDMASK 0x0000003f +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_MASK 0x00003f00 +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_BY1_F 0x00000000 +#define GPU_TRIM_SYS_GPC2CLK_OUT_SDIV14_MASK 0x80000000 +#define GPU_TRIM_SYS_GPC2CLK_OUT_SDIV14_SHIFT 0x0000001f +#define GPU_TRIM_SYS_GPC2CLK_OUT_SDIV14_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE_F 0x80000000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG__BASE 0x00134124 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG__STRIDE 0x00000200 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x00134124 + (i) * 0x00000200) +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS_SHIFT 0x00000000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS_FIELDMASK 0x00003fff +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED_F 0x00010000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED_F 0x00100000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED_F 0x01000000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT__BASE 0x00134128 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT__STRIDE 0x00000200 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x00134128 + (i) * 0x00000200) +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE_SHIFT 0x00000000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE_FIELDMASK 0x000fffff +#define GPU_TRIM_SYS_GPCPLL_CFG2 0x0013700c +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_MASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x0000ff00 +#define GPU_TRIM_SYS_GPCPLL_CFG2_PLL_STEPA_SHIFT 0x00000018 +#define GPU_TRIM_SYS_GPCPLL_CFG2_PLL_STEPA_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG2_PLL_STEPA_MASK 0xff000000 +#define GPU_TRIM_SYS_GPCPLL_CFG3 0x00137018 +#define GPU_TRIM_SYS_GPCPLL_CFG3_VCO_CTRL_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG3_VCO_CTRL_FIELDMASK 0x000001ff +#define GPU_TRIM_SYS_GPCPLL_CFG3_VCO_CTRL_MASK 0x000001ff +#define GPU_TRIM_SYS_GPCPLL_CFG3_PLL_STEPB_SHIFT 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_CFG3_PLL_STEPB_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG3_PLL_STEPB_MASK 0x00ff0000 +#define GPU_TRIM_SYS_GPCPLL_CFG3_DFS_TESTOUT_SHIFT 0x00000018 +#define GPU_TRIM_SYS_GPCPLL_CFG3_DFS_TESTOUT_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS0 0x00137010 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_COEFF_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_COEFF_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_COEFF_MASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX_MASK 0x00007f00 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET_SHIFT 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET_FIELDMASK 0x0000003f +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET_MASK 0x003f0000 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_MODE_MASK 0x10000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_MODE_SHIFT 0x0000001c +#define GPU_TRIM_SYS_GPCPLL_DVFS0_MODE_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_MODE_DVFSPLL_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1 0x00137014 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_DET_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_DET_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_DET_MASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_STRB_MASK 0x00000080 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_STRB_SHIFT 0x00000007 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_STRB_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_CAL_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_CAL_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_CAL_MASK 0x00007f00 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_SEL_MASK 0x00008000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_SEL_SHIFT 0x0000000f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_SEL_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CTRL_SHIFT 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CTRL_FIELDMASK 0x00000fff +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CTRL_MASK 0x0fff0000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_SDM_MASK 0x10000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_SDM_SHIFT 0x0000001c +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_SDM_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_MASK 0x20000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_SHIFT 0x0000001d +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_CAL_MASK 0x40000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_CAL_SHIFT 0x0000001e +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_CAL_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CAL_DONE_SHIFT 0x0000001f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CAL_DONE_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS2 0x00137020 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x0013701c +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_MASK 0x00400000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 0x00000016 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_YES_F 0x00400000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_NO_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_MASK 0x80000000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 0x0000001f +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_YES_F 0x80000000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_NO_F 0x00000000 +#define GPU_TRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG 0x001328a0 +#define GPU_TRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 0x00000018 +#define GPU_TRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_FIELDMASK 0x00000001 +#define GPU_TRIM_GPC_BCAST_GPCPLL_DVFS2 0x00132820 +#define GPU_TRIM_SYS_BYPASSCTRL 0x00137340 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_MASK 0x00000001 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_SHIFT 0x00000000 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_BYPASSCLK_F 0x00000001 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_VCO_F 0x00000000 \ No newline at end of file