OmniNX/Horizon-OC
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

hocclk: major code refactor

Browse Source 
move everything into its own directory, clean codebase up a lot
This commit is contained in:
souldbminersmwc
2026-05-08 22:43:14 -04:00
parent 65dfa8f48a
commit 3ca1f17e4d
78 changed files with 138 additions and 263 deletions
Download Patch File Download Diff File Expand all files Collapse all files

314
Source/hoc-clk/sysmodule/src/soc/fuse.h Normal file
View File

@@ -0,0 +1,314 @@
/*
* Copyright (c) 2018 naehrwert
* Copyright (c) 2018 shuffle2
* Copyright (c) 2018 balika011
* Copyright (c) 2019-2025 CTCaer
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _FUSE_H_
#define _FUSE_H_
#ifndef BIT
#define BIT(n) (1U<<(n))
#endif
/*! Fuse registers. */
#define FUSE_CTRL 0x0
#define FUSE_ADDR 0x4
#define FUSE_RDATA 0x8
#define FUSE_WDATA 0xC
#define FUSE_TIME_RD1 0x10
#define FUSE_TIME_RD2 0x14
#define FUSE_TIME_PGM1 0x18
#define FUSE_TIME_PGM2 0x1C
#define FUSE_PRIV2INTFC 0x20
#define FUSE_PRIV2INTFC_START_DATA BIT(0)
#define FUSE_PRIV2INTFC_SKIP_RECORDS BIT(1)
#define FUSE_FUSEBYPASS 0x24
#define FUSE_PRIVATEKEYDISABLE 0x28
#define FUSE_PRIVKEY_DISABLE BIT(0)
#define FUSE_PRIVKEY_TZ_STICKY_BIT BIT(4)
#define FUSE_DISABLEREGPROGRAM 0x2C
#define FUSE_WRITE_ACCESS_SW 0x30
#define FUSE_PWR_GOOD_SW 0x34
#define FUSE_PRIV2RESHIFT 0x3C
#define FUSE_FUSETIME_RD0 0x40
#define FUSE_FUSETIME_RD1 0x44
#define FUSE_FUSETIME_RD2 0x48
#define FUSE_FUSETIME_RD3 0x4C
#define FUSE_PRIVATE_KEY0_NONZERO 0x80
#define FUSE_PRIVATE_KEY1_NONZERO 0x84
#define FUSE_PRIVATE_KEY2_NONZERO 0x88
#define FUSE_PRIVATE_KEY3_NONZERO 0x8C
#define FUSE_PRIVATE_KEY4_NONZERO 0x90
/*! Fuse Cached registers */
#define FUSE_RESERVED_ODM8_B01 0x98 // FUSE_READ_TZ Group 0.
#define FUSE_RESERVED_ODM9_B01 0x9C // FUSE_READ_TZ Group 0.
#define FUSE_RESERVED_ODM10_B01 0xA0 // FUSE_READ_TZ Group 0.
#define FUSE_RESERVED_ODM11_B01 0xA4 // FUSE_READ_TZ Group 0.
#define FUSE_RESERVED_ODM12_B01 0xA8 // FUSE_READ_TZ Group 1? Is value -1?
#define FUSE_RESERVED_ODM13_B01 0xAC // FUSE_READ_TZ Group 1? Is value -1?
#define FUSE_RESERVED_ODM14_B01 0xB0 // FUSE_READ_TZ Group 1? Is value -1?
#define FUSE_RESERVED_ODM15_B01 0xB4 // FUSE_READ_TZ Group 1? Is value -1?
#define FUSE_RESERVED_ODM16_B01 0xB8 // FUSE_READ_TZ Group 2? Is value -1?
#define FUSE_RESERVED_ODM17_B01 0xBC // FUSE_READ_TZ Group 2? Is value -1?
#define FUSE_RESERVED_ODM18_B01 0xC0 // FUSE_READ_TZ Group 2.
#define FUSE_RESERVED_ODM19_B01 0xC4 // FUSE_READ_TZ Group 2.
#define FUSE_RESERVED_ODM20_B01 0xC8 // FUSE_READ_TZ Group 3.
#define FUSE_RESERVED_ODM21_B01 0xCC // FUSE_READ_TZ Group 3.
#define FUSE_KEK00_B01 0xD0
#define FUSE_KEK01_B01 0xD4
#define FUSE_KEK02_B01 0xD8
#define FUSE_KEK03_B01 0xDC
#define FUSE_BEK00_B01 0xE0
#define FUSE_BEK01_B01 0xE4
#define FUSE_BEK02_B01 0xE8
#define FUSE_BEK03_B01 0xEC
#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4SVT_B01 0xF0
#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4SVT_B01 0xF4
#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4SVT_B01 0xF8
#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4SVT_B01 0xFC
#define FUSE_PRODUCTION_MODE 0x100
#define FUSE_JTAG_SECUREID_VALID 0x104
#define FUSE_ODM_LOCK 0x108
#define FUSE_OPT_OPENGL_EN 0x10C
#define FUSE_SKU_INFO 0x110
#define FUSE_CPU_SPEEDO_0_CALIB 0x114
#define FUSE_CPU_IDDQ_CALIB 0x118
#define FUSE_RESERVED_ODM22_B01 0x11C // FUSE_READ_TZ Group 3.
#define FUSE_RESERVED_ODM23_B01 0x120 // FUSE_READ_TZ Group 3.
#define FUSE_RESERVED_ODM24_B01 0x124 // FUSE_READ_TZ Group 4.
#define FUSE_OPT_FT_REV 0x128
#define FUSE_CPU_SPEEDO_1_CALIB 0x12C
#define FUSE_CPU_SPEEDO_2_CALIB 0x130
#define FUSE_SOC_SPEEDO_0_CALIB 0x134
#define FUSE_SOC_SPEEDO_1_CALIB 0x138
#define FUSE_SOC_SPEEDO_2_CALIB 0x13C
#define FUSE_SOC_IDDQ_CALIB 0x140
#define FUSE_RESERVED_ODM25_B01 0x144 // FUSE_READ_TZ Group 4.
#define FUSE_FA 0x148
#define FUSE_RESERVED_PRODUCTION 0x14C
#define FUSE_HDMI_LANE0_CALIB 0x150
#define FUSE_HDMI_LANE1_CALIB 0x154
#define FUSE_HDMI_LANE2_CALIB 0x158
#define FUSE_HDMI_LANE3_CALIB 0x15C
#define FUSE_ENCRYPTION_RATE 0x160
#define FUSE_PUBLIC_KEY0 0x164
#define FUSE_PUBLIC_KEY1 0x168
#define FUSE_PUBLIC_KEY2 0x16C
#define FUSE_PUBLIC_KEY3 0x170
#define FUSE_PUBLIC_KEY4 0x174
#define FUSE_PUBLIC_KEY5 0x178
#define FUSE_PUBLIC_KEY6 0x17C
#define FUSE_PUBLIC_KEY7 0x180
#define FUSE_TSENSOR1_CALIB 0x184 // CPU1.
#define FUSE_TSENSOR2_CALIB 0x188 // CPU2.
#define FUSE_OPT_SECURE_SCC_DIS_B01 0x18C
#define FUSE_OPT_CP_REV 0x190 // FUSE style revision - ATE. 0x101 0x100
#define FUSE_OPT_PFG 0x194
#define FUSE_TSENSOR0_CALIB 0x198 // CPU0.
#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19C
#define FUSE_SECURITY_MODE 0x1A0
#define FUSE_PRIVATE_KEY0 0x1A4
#define FUSE_PRIVATE_KEY1 0x1A8
#define FUSE_PRIVATE_KEY2 0x1AC
#define FUSE_PRIVATE_KEY3 0x1B0
#define FUSE_PRIVATE_KEY4 0x1B4
#define FUSE_ARM_JTAG_DIS 0x1B8
#define FUSE_BOOT_DEVICE_INFO 0x1BC
#define FUSE_RESERVED_SW 0x1C0
#define FUSE_OPT_VP9_DISABLE 0x1C4
#define FUSE_RESERVED_ODM0 0x1C8
#define FUSE_RESERVED_ODM1 0x1CC
#define FUSE_RESERVED_ODM2 0x1D0
#define FUSE_RESERVED_ODM3 0x1D4
#define FUSE_RESERVED_ODM4 0x1D8
#define FUSE_RESERVED_ODM5 0x1DC
#define FUSE_RESERVED_ODM6 0x1E0
#define FUSE_RESERVED_ODM7 0x1E4
#define FUSE_OBS_DIS 0x1E8
#define FUSE_OPT_NVJTAG_PROTECTION_ENABLE_B01 0x1EC
#define FUSE_USB_CALIB 0x1F0
#define FUSE_SKU_DIRECT_CONFIG 0x1F4
#define FUSE_KFUSE_PRIVKEY_CTRL 0x1F8
#define FUSE_PACKAGE_INFO 0x1FC // 1: MID, 2: DSC.
#define FUSE_OPT_VENDOR_CODE 0x200
#define FUSE_OPT_FAB_CODE 0x204
#define FUSE_OPT_LOT_CODE_0 0x208
#define FUSE_OPT_LOT_CODE_1 0x20C
#define FUSE_OPT_WAFER_ID 0x210
#define FUSE_OPT_X_COORDINATE 0x214
#define FUSE_OPT_Y_COORDINATE 0x218
#define FUSE_OPT_SEC_DEBUG_EN 0x21C
#define FUSE_OPT_OPS_RESERVED 0x220
#define FUSE_SATA_CALIB 0x224
#define FUSE_SPARE_REGISTER_ODM_B01 0x224
#define FUSE_GPU_IDDQ_CALIB 0x228
#define FUSE_TSENSOR3_CALIB 0x22C // CPU3.
#define FUSE_CLOCK_BONDOUT0 0x230
#define FUSE_CLOCK_BONDOUT1 0x234
#define FUSE_RESERVED_ODM26_B01 0x238 // FUSE_READ_TZ Group 4.
#define FUSE_RESERVED_ODM27_B01 0x23C // FUSE_READ_TZ Group 4.
#define FUSE_RESERVED_ODM28_B01 0x240 // MAX77812 phase configuration. FUSE_READ_TZ Group 5.
#define FUSE_OPT_SAMPLE_TYPE 0x244
#define FUSE_OPT_SUBREVISION 0x248 // "", "p", "q", "r". e.g: A01p.
#define FUSE_OPT_SW_RESERVED_0 0x24C
#define FUSE_OPT_SW_RESERVED_1 0x250
#define FUSE_TSENSOR4_CALIB 0x254 // GPU.
#define FUSE_TSENSOR5_CALIB 0x258 // MEM0.
#define FUSE_TSENSOR6_CALIB 0x25C // MEM1.
#define FUSE_TSENSOR7_CALIB 0x260 // PLLX.
#define FUSE_OPT_PRIV_SEC_DIS 0x264
#define FUSE_PKC_DISABLE 0x268
#define FUSE_BOOT_SECURITY_INFO_B01 0x268
#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4HVT_B01 0x26C
#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4HVT_B01 0x270
#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4HVT_B01 0x274
#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4HVT_B01 0x278
#define FUSE_FUSE2TSEC_DEBUG_DISABLE 0x27C
#define FUSE_TSENSOR_COMMON 0x280
#define FUSE_OPT_CP_BIN 0x284
#define FUSE_OPT_GPU_DISABLE 0x288
#define FUSE_OPT_FT_BIN 0x28C
#define FUSE_OPT_DONE_MAP 0x290
#define FUSE_RESERVED_ODM29_B01 0x294 // FUSE_READ_TZ Group 5? Is value -1?
#define FUSE_APB2JTAG_DISABLE 0x298
#define FUSE_ODM_INFO 0x29C // Debug features disable.
#define FUSE_ARM_CRYPT_DE_FEATURE 0x2A8
#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4SVT_B01 0x2B0
#define FUSE_OPT_RAM_RCT_TSMCDP_PO4SVT_B01 0x2B4
#define FUSE_OPT_RAM_WCT_TSMCDP_PO4SVT_B01 0x2B8
#define FUSE_OPT_RAM_KP_TSMCDP_PO4SVT_B01 0x2BC
#define FUSE_WOA_SKU_FLAG 0x2C0
#define FUSE_ECO_RESERVE_1 0x2C4
#define FUSE_GCPLEX_CONFIG_FUSE 0x2C8
#define FUSE_GPU_VPR_AUTO_FETCH_DIS BIT(0)
#define FUSE_GPU_VPR_ENABLED BIT(1)
#define FUSE_GPU_WPR_ENABLED BIT(2)
#define FUSE_PRODUCTION_MONTH 0x2CC
#define FUSE_RAM_REPAIR_INDICATOR 0x2D0
#define FUSE_TSENSOR9_CALIB 0x2D4 // AOTAG.
#define FUSE_VMIN_CALIBRATION 0x2DC
#define FUSE_AGING_SENSOR_CALIBRATION 0x2E0
#define FUSE_DEBUG_AUTHENTICATION 0x2E4
#define FUSE_SECURE_PROVISION_INDEX 0x2E8
#define FUSE_SECURE_PROVISION_INFO 0x2EC
#define FUSE_OPT_GPU_DISABLE_CP1 0x2F0
#define FUSE_SPARE_ENDIS 0x2F4
#define FUSE_ECO_RESERVE_0 0x2F8 // AID.
#define FUSE_RESERVED_CALIB0 0x304 // GPCPLL ADC Calibration.
#define FUSE_RESERVED_CALIB1 0x308
#define FUSE_OPT_GPU_TPC0_DISABLE 0x30C
#define FUSE_OPT_GPU_TPC0_DISABLE_CP1 0x310
#define FUSE_OPT_CPU_DISABLE 0x314
#define FUSE_OPT_CPU_DISABLE_CP1 0x318
#define FUSE_TSENSOR10_CALIB 0x31C
#define FUSE_TSENSOR10_CALIB_AUX 0x320
#define FUSE_OPT_RAM_SVOP_DP 0x324
#define FUSE_OPT_RAM_SVOP_PDP 0x328
#define FUSE_OPT_RAM_SVOP_REG 0x32C
#define FUSE_OPT_RAM_SVOP_SP 0x330
#define FUSE_OPT_RAM_SVOP_SMPDP 0x334
#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4HVT_B01 0x324
#define FUSE_OPT_RAM_RCT_TSMCDP_PO4HVT_B01 0x328
#define FUSE_OPT_RAM_WCT_TSMCDP_PO4HVT_B01 0x32c
#define FUSE_OPT_RAM_KP_TSMCDP_PO4HVT_B01 0x330
#define FUSE_OPT_RAM_SVOP_SP_B01 0x334
#define FUSE_OPT_GPU_TPC0_DISABLE_CP2 0x338
#define FUSE_OPT_GPU_TPC1_DISABLE 0x33C
#define FUSE_OPT_GPU_TPC1_DISABLE_CP1 0x340
#define FUSE_OPT_GPU_TPC1_DISABLE_CP2 0x344
#define FUSE_OPT_CPU_DISABLE_CP2 0x348
#define FUSE_OPT_GPU_DISABLE_CP2 0x34C
#define FUSE_USB_CALIB_EXT 0x350
#define FUSE_RESERVED_FIELD 0x354 // RMA.
#define FUSE_SPARE_REALIGNMENT_REG 0x37C
#define FUSE_SPARE_BIT_0 0x380
//...
#define FUSE_SPARE_BIT_31 0x3FC
/*! Fuse commands. */
#define FUSE_IDLE 0x0
#define FUSE_READ 0x1
#define FUSE_WRITE 0x2
#define FUSE_SENSE 0x3
#define FUSE_CMD_MASK 0x3
/*! Fuse status. */
#define FUSE_STATUS_RESET 0
#define FUSE_STATUS_POST_RESET 1
#define FUSE_STATUS_LOAD_ROW0 2
#define FUSE_STATUS_LOAD_ROW1 3
#define FUSE_STATUS_IDLE 4
#define FUSE_STATUS_READ_SETUP 5
#define FUSE_STATUS_READ_STROBE 6
#define FUSE_STATUS_SAMPLE_FUSES 7
#define FUSE_STATUS_READ_HOLD 8
#define FUSE_STATUS_FUSE_SRC_SETUP 9
#define FUSE_STATUS_WRITE_SETUP 10
#define FUSE_STATUS_WRITE_ADDR_SETUP 11
#define FUSE_STATUS_WRITE_PROGRAM 12
#define FUSE_STATUS_WRITE_ADDR_HOLD 13
#define FUSE_STATUS_FUSE_SRC_HOLD 14
#define FUSE_STATUS_LOAD_RIR 15
#define FUSE_STATUS_READ_BEFORE_WRITE_SETUP 16
#define FUSE_STATUS_READ_DEASSERT_PD 17
/*! Fuse cache registers. */
#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))
#define FUSE_ARRAY_WORDS_NUM 192
#define FUSE_ARRAY_WORDS_NUM_B01 256
enum
{
FUSE_NX_HW_TYPE_ICOSA,
FUSE_NX_HW_TYPE_IOWA,
FUSE_NX_HW_TYPE_HOAG,
FUSE_NX_HW_TYPE_AULA
};
enum
{
FUSE_NX_HW_STATE_PROD,
FUSE_NX_HW_STATE_DEV
};
#endif

116
Source/hoc-clk/sysmodule/src/soc/pllmb.cpp Normal file
View File

@@ -0,0 +1,116 @@
/*
* Copyright (c) Souldbminer
*
* Copyright (c) KazushiMe
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include "pllmb.hpp"
namespace pllmb {
#define GET_BITS(VAL, HIGH, LOW) ((VAL & ((1UL << (HIGH + 1UL)) - 1UL)) >> LOW)
#define GET_BIT(VAL, BIT) GET_BITS(VAL, BIT, BIT)
static inline volatile u32& REG(uintptr_t addr) {
return *reinterpret_cast<volatile u32*>(addr);
}
// From jetson nano kernel
typedef enum {
/* divider = 2 */
CLK_PLLX = 5,
CLK_PLLM = 2,
CLK_PLLMB = 37,
/* PLLX & PLLG are backup PLLs for CPU & GPU */
/* divider = 1 */
CLK_CCLK_G = 18, // A57 CPU cluster
CLK_EMC = 36,
} PTO_ID; // PLL Test Output Register ID
/* See if GM20B clock GPC PLL regs are accessible. */
#define PLLX_MISC0 0xE4
#define PLLM_MISC2 0x9C
double ptoGetMHz(PTO_ID pto_id, u32 divider = 1, u32 presel_reg = 0, u32 presel_mask = 0) {
u32 pre_val, val, presel_val;
if (presel_reg) {
val = REG(board::clkVirtAddr + presel_reg);
usleep(10);
presel_val = val & presel_mask;
val &= ~presel_mask;
val |= presel_mask;
REG(board::clkVirtAddr + presel_reg) = val;
usleep(10);
}
constexpr u32 cycle_count = 16;
pre_val = REG(board::clkVirtAddr + 0x60);
val = BIT(23) | BIT(13) | (cycle_count - 1);
val |= pto_id << 14;
REG(board::clkVirtAddr + 0x60) = val;
usleep(10);
REG(board::clkVirtAddr + 0x60) = val | BIT(10);
usleep(10);
REG(board::clkVirtAddr + 0x60) = val;
usleep(10);
REG(board::clkVirtAddr + 0x60) = val | BIT(9);
usleep(500);
while(REG(board::clkVirtAddr + 0x64) & BIT(31))
;
val = REG(board::clkVirtAddr + 0x64);
val &= 0xFFFFFF;
val *= divider;
double rate_hz = (u64)val * 32768. / cycle_count;
usleep(10);
REG(board::clkVirtAddr + 0x60) = pre_val;
usleep(10);
if (presel_reg) {
val = REG(board::clkVirtAddr + presel_reg);
usleep(10);
val &= ~presel_mask;
val |= presel_val;
REG(board::clkVirtAddr + presel_reg) = val;
usleep(10);
}
return rate_hz;
}
u64 getRamClockRatePLLMB() {
// printf("\n"
// "EMC: %6.1f MHz\n"
// "CCLK_G: %6.1f MHz\n"
// "PLLX: %6.1f MHz\n"
// "PLLM: %6.1f MHz\n"
// "PLLMB: %6.1f MHz\n",
// ptoGetMHz(CLK_EMC),
// ptoGetMHz(CLK_CCLK_G),
// ptoGetMHz(CLK_PLLX, 2, PLLX_MISC0, BIT(22)),
// ptoGetMHz(CLK_PLLM, 2, PLLM_MISC2, BIT(8)),
// ptoGetMHz(CLK_PLLMB, 2, PLLM_MISC2, BIT(9))
// );
u32 pllmb = ptoGetMHz(CLK_PLLMB, 2, PLLM_MISC2, BIT(9));
u32 pllm = ptoGetMHz(CLK_PLLM, 2, PLLM_MISC2, BIT(8));
return pllmb == 0 ? pllm : pllmb; // pllmb is zeroed out at times, fallback to pllm
}
}

29
Source/hoc-clk/sysmodule/src/soc/pllmb.hpp Normal file
View File

@@ -0,0 +1,29 @@
/*
* Copyright (c) Souldbminer
*
* Copyright (c) KazushiMe
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#pragma once
#include <cstdint>
#include <switch.h>
#include <hocclk.h>
#include "../board/board.hpp"
#include <registers.h>
namespace pllmb {
u64 getRamClockRatePLLMB();
}

548
Source/hoc-clk/sysmodule/src/soc/registers.h Normal file
View File

@@ -0,0 +1,548 @@
/*
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
*
* Copyright (c) Linux 4 Tegra & Linux 4 Switch contributors
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#pragma once
#define EMC_INTSTATUS_0 0x0
#define EMC_INTMASK_0 0x4
#define EMC_DBG_0 0x8
#define EMC_CFG_0 0xC
#define EMC_ADR_CFG_0 0x10
#define EMC_REFCTRL_0 0x20
#define EMC_PIN_0 0x24
#define EMC_TIMING_CONTROL_0 0x28
#define EMC_RC_0 0x2C
#define EMC_RFC_0 0x30
#define EMC_RAS_0 0x34
#define EMC_RP_0 0x38
#define EMC_R2W_0 0x3C
#define EMC_W2R_0 0x40
#define EMC_R2P_0 0x44
#define EMC_W2P_0 0x48
#define EMC_RD_RCD_0 0x4C
#define EMC_WR_RCD_0 0x50
#define EMC_RRD_0 0x54
#define EMC_REXT_0 0x58
#define EMC_WDV_0 0x5C
#define EMC_QUSE_0 0x60
#define EMC_QRST_0 0x64
#define EMC_QSAFE_0 0x68
#define EMC_RDV_0 0x6C
#define EMC_REFRESH_0 0x70
#define EMC_BURST_REFRESH_NUM_0 0x74
#define EMC_PDEX2WR_0 0x78
#define EMC_PDEX2RD_0 0x7C
#define EMC_PCHG2PDEN_0 0x80
#define EMC_ACT2PDEN_0 0x84
#define EMC_AR2PDEN_0 0x88
#define EMC_RW2PDEN_0 0x8C
#define EMC_TXSR_0 0x90
#define EMC_TCKE_0 0x94
#define EMC_TFAW_0 0x98
#define EMC_TRPAB_0 0x9C
#define EMC_TCLKSTABLE_0 0xA0
#define EMC_TCLKSTOP_0 0xA4
#define EMC_TREFBW_0 0xA8
#define EMC_TPPD_0 0xAC
#define EMC_ODT_WRITE_0 0xB0
#define EMC_PDEX2MRR_0 0xB4
#define EMC_WEXT_0 0xB8
#define EMC_RFC_SLR_0 0xC0
#define EMC_MRS_WAIT_CNT2_0 0xC4
#define EMC_MRS_WAIT_CNT_0 0xC8
#define EMC_MRS_0 0xCC
#define EMC_EMRS_0 0xD0
#define EMC_REF_0 0xD4
#define EMC_PRE_0 0xD8
#define EMC_NOP_0 0xDC
#define EMC_SELF_REF_0 0xE0
#define EMC_DPD_0 0xE4
#define EMC_MRW_0 0xE8
#define EMC_MRR_0 0xEC
#define EMC_CMDQ_0 0xF0
#define EMC_MC2EMCQ_0 0xF4
#define EMC_FBIO_SPARE_0 0x100
#define EMC_FBIO_CFG5_0 0x104
#define EMC_FBIO_CFG6_0 0x114
#define EMC_PDEX2CKE_0 0x118
#define EMC_CKE2PDEN_0 0x11C
#define EMC_CFG_RSV_0 0x120
#define EMC_ACPD_CONTROL_0 0x124
#define EMC_MPC_0 0x128
#define EMC_EMRS2_0 0x12C
#define EMC_EMRS3_0 0x130
#define EMC_MRW2_0 0x134
#define EMC_MRW3_0 0x138
#define EMC_MRW4_0 0x13C
#define EMC_CLKEN_OVERRIDE_0 0x140
#define EMC_R2R_0 0x144
#define EMC_W2W_0 0x148
#define EMC_EINPUT_0 0x14C
#define EMC_EINPUT_DURATION_0 0x150
#define EMC_PUTERM_EXTRA_0 0x154
#define EMC_TCKESR_0 0x158
#define EMC_TPD_0 0x15C
#define EMC_AUTO_CAL_CONFIG_0 0x2A4
#define EMC_AUTO_CAL_INTERVAL_0 0x2A8
#define EMC_AUTO_CAL_STATUS_0 0x2AC
#define EMC_REQ_CTRL_0 0x2B0
#define EMC_EMC_STATUS_0 0x2B4
#define EMC_CFG_2_0 0x2B8
#define EMC_CFG_DIG_DLL_0 0x2BC
#define EMC_CFG_DIG_DLL_PERIOD_0 0x2C0
#define EMC_DIG_DLL_STATUS_0 0x2C4
#define EMC_CFG_DIG_DLL_1_0 0x2C8
#define EMC_RDV_MASK_0 0x2CC
#define EMC_WDV_MASK_0 0x2D0
#define EMC_RDV_EARLY_MASK_0 0x2D4
#define EMC_RDV_EARLY_0 0x2D8
#define EMC_AUTO_CAL_CONFIG8_0 0x2DC
#define EMC_ZCAL_INTERVAL_0 0x2E0
#define EMC_ZCAL_WAIT_CNT_0 0x2E4
#define EMC_ZCAL_MRW_CMD_0 0x2E8
#define EMC_ZQ_CAL_0 0x2EC
#define EMC_XM2COMPPADCTRL3_0 0x2F4
#define EMC_AUTO_CAL_VREF_SEL_0_0 0x2F8
#define EMC_AUTO_CAL_VREF_SEL_1_0 0x300
#define EMC_XM2COMPPADCTRL_0 0x30C
#define EMC_FDPD_CTRL_DQ_0 0x310
#define EMC_FDPD_CTRL_CMD_0 0x314
#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 0x318
#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 0x31C
#define EMC_SCRATCH0_0 0x324
#define EMC_PMACRO_BRICK_CTRL_RFU1_0 0x330
#define EMC_PMACRO_BRICK_CTRL_RFU2_0 0x334
#define EMC_CMD_MAPPING_CMD0_0_0 0x380
#define EMC_CMD_MAPPING_CMD0_1_0 0x384
#define EMC_CMD_MAPPING_CMD0_2_0 0x388
#define EMC_CMD_MAPPING_CMD1_0_0 0x38C
#define EMC_CMD_MAPPING_CMD1_1_0 0x390
#define EMC_CMD_MAPPING_CMD1_2_0 0x394
#define EMC_CMD_MAPPING_CMD2_0_0 0x398
#define EMC_CMD_MAPPING_CMD2_1_0 0x39C
#define EMC_CMD_MAPPING_CMD2_2_0 0x3A0
#define EMC_CMD_MAPPING_CMD3_0_0 0x3A4
#define EMC_CMD_MAPPING_CMD3_1_0 0x3A8
#define EMC_CMD_MAPPING_CMD3_2_0 0x3AC
#define EMC_CMD_MAPPING_BYTE_0 0x3B0
#define EMC_TR_TIMING_0_0 0x3B4
#define EMC_TR_CTRL_0_0 0x3B8
#define EMC_TR_CTRL_1_0 0x3BC
#define EMC_SWITCH_BACK_CTRL_0 0x3C0
#define EMC_TR_RDV_0 0x3C4
#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 0x3C8
#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 0x3CC
#define EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 0x3D0
#define EMC_AUTO_CAL_ 0x3D4
#define EMC_SEL_DPD_CTRL_0 0x3D8
#define EMC_PRE_REFRESH_REQ_CNT_0 0x3DC
#define EMC_DYN_SELF_REF_CONTROL_0 0x3E0
#define EMC_TXSRDLL_0 0x3E4
#define EMC_CCFIFO_ADDR_0 0x3E8
#define EMC_CCFIFO_DATA_0 0x3EC
#define EMC_CCFIFO_STATUS_0 0x3F0
#define EMC_TR_QPOP_0 0x3F4
#define EMC_TR_RDV_MASK_0 0x3F8
#define EMC_TR_QSAFE_0 0x3FC
#define EMC_TR_QRST_0 0x400
#define EMC_SWIZZLE_RANK0_BYTE0_0 0x404
#define EMC_SWIZZLE_RANK0_BYTE1_0 0x408
#define EMC_SWIZZLE_RANK0_BYTE2_0 0x40C
#define EMC_SWIZZLE_RANK0_BYTE3_0 0x410
#define EMC_SWIZZLE_RANK1_BYTE0_0 0x418
#define EMC_SWIZZLE_RANK1_BYTE1_0 0x41C
#define EMC_SWIZZLE_RANK1_BYTE2_0 0x420
#define EMC_SWIZZLE_RANK1_BYTE3_0 0x424
#define EMC_ISSUE_QRST_0 0x428
#define EMC_PMC_SCRATCH1_0 0x440
#define EMC_PMC_SCRATCH2_0 0x444
#define EMC_PMC_SCRATCH3_0 0x448
#define EMC_AUTO_CAL_CONFIG2_0 0x458
#define EMC_AUTO_CAL_CONFIG3_0 0x45C
#define EMC_TR_DVFS_0 0x460
#define EMC_AUTO_CAL_CHANNEL_0 0x464
#define EMC_IBDLY_0 0x468
#define EMC_OBDLY_0 0x46C
#define EMC_TXDSRVTTGEN_0 0x480
#define EMC_WE_DURATION_0 0x48C
#define EMC_WS_DURATION_0 0x490
#define EMC_WEV_0 0x494
#define EMC_WSV_0 0x498
#define EMC_CFG_3_0 0x49C
#define EMC_MRW5_0 0x4A0
#define EMC_MRW6_0 0x4A4
#define EMC_MRW7_0 0x4A8
#define EMC_MRW8_0 0x4AC
#define EMC_MRW9_0 0x4B0
#define EMC_MRW10_0 0x4B4
#define EMC_MRW11_0 0x4B8
#define EMC_MRW12_0 0x4BC
#define EMC_MRW13_0 0x4C0
#define EMC_MRW14_0 0x4C4
#define EMC_MRW15_0 0x4D0
#define EMC_CFG_SYNC_0 0x4D4
#define EMC_FDPD_CTRL_CMD_NO_RAMP_0 0x4D8
#define EMC_WDV_CHK_0 0x4E0
#define EMC_CFG_PIPE_2_0 0x554
#define EMC_CFG_PIPE_CLK_0 0x558
#define EMC_CFG_PIPE_1_0 0x55C
#define EMC_CFG_PIPE_0 0x560
#define EMC_QPOP_0 0x564
#define EMC_QUSE_WIDTH_0 0x568
#define EMC_PUTERM_WIDTH_0 0x56C
#define EMC_BGBIAS_CTL0_0 0x570
#define EMC_AUTO_CAL_CONFIG7_0 0x574
#define EMC_XM2COMPPADCTRL2_0 0x578
#define EMC_COMP_PAD_SW_CTRL_0 0x57C
#define EMC_REFCTRL2_0 0x580
#define EMC_FBIO_CFG7_0 0x584
#define EMC_DATA_BRLSHFT_0_0 0x588
#define EMC_DATA_BRLSHFT_1_0 0x58C
#define EMC_RFCPB_0 0x590
#define EMC_DQS_BRLSHFT_0_0 0x594
#define EMC_DQS_BRLSHFT_1_0 0x598
#define EMC_CMD_BRLSHFT_0_0 0x59C
#define EMC_CMD_BRLSHFT_1_0 0x5A0
#define EMC_CMD_BRLSHFT_2_0 0x5A4
#define EMC_CMD_BRLSHFT_3_0 0x5A8
#define EMC_QUSE_BRLSHFT_0_0 0x5AC
#define EMC_AUTO_CAL_CONFIG4_0 0x5B0
#define EMC_AUTO_CAL_CONFIG5_0 0x5B4
#define EMC_QUSE_BRLSHFT_1_0 0x5B8
#define EMC_QUSE_BRLSHFT_2_0 0x5BC
#define EMC_CCDMW_0 0x5C0
#define EMC_QUSE_BRLSHFT_3_0 0x5C4
#define EMC_FBIO_CFG8_0 0x5C8
#define EMC_AUTO_CAL_CONFIG6_0 0x5CC
#define EMC_PROTOBIST_CONFIG_ADR_1_0 0x5D0
#define EMC_PROTOBIST_CONFIG_ADR_2_0 0x5D4
#define EMC_PROTOBIST_MISC_0 0x5D8
#define EMC_PROTOBIST_WDATA_LOWER_0 0x5DC
#define EMC_PROTOBIST_WDATA_UPPER_0 0x5E0
#define EMC_PROTOBIST_RDATA_0 0x5EC
#define EMC_DLL_CFG_0_0 0x5E4
#define EMC_DLL_CFG_1_0 0x5E8
#define EMC_CONFIG_SAMPLE_DELAY_0 0x5F0
#define EMC_CFG_UPDATE_0 0x5F4
#define EMC_PMACRO_QUSE_DDLL_RANK0_0_0 0x600
#define EMC_PMACRO_QUSE_DDLL_RANK0_1_0 0x604
#define EMC_PMACRO_QUSE_DDLL_RANK0_2_0 0x608
#define EMC_PMACRO_QUSE_DDLL_RANK0_3_0 0x60C
#define EMC_PMACRO_QUSE_DDLL_RANK0_4_0 0x610
#define EMC_PMACRO_QUSE_DDLL_RANK0_5_0 0x614
#define EMC_PMACRO_QUSE_DDLL_RANK1_0_0 0x620
#define EMC_PMACRO_QUSE_DDLL_RANK1_1_0 0x624
#define EMC_PMACRO_QUSE_DDLL_RANK1_2_0 0x628
#define EMC_PMACRO_QUSE_DDLL_RANK1_3_0 0x62C
#define EMC_PMACRO_QUSE_DDLL_RANK1_4_0 0x630
#define EMC_PMACRO_QUSE_DDLL_RANK1_5_0 0x634
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 0x640
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 0x644
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 0x648
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 0x64C
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 0x650
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 0x654
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 0x660
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 0x664
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 0x668
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 0x66C
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 0x670
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 0x674
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 0x680
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 0x684
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 0x688
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 0x68C
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 0x690
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 0x694
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 0x6A0
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 0x6A4
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 0x6A8
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 0x6AC
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 0x6B0
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 0x6B4
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 0x6C0
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 0x6C4
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 0x6C8
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 0x6CC
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 0x6D0
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 0x6D4
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 0x6E0
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 0x6E4
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 0x6E8
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 0x6EC
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 0x6F0
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 0x6F4
#define EMC_PMACRO_AUTOCAL_CFG_0_0 0x700
#define EMC_PMACRO_AUTOCAL_CFG_1_0 0x704
#define EMC_PMACRO_AUTOCAL_CFG_2_0 0x708
#define EMC_PMACRO_TX_PWRD_0_0 0x720
#define EMC_PMACRO_TX_PWRD_1_0 0x724
#define EMC_PMACRO_TX_PWRD_2_0 0x728
#define EMC_PMACRO_TX_PWRD_3_0 0x72C
#define EMC_PMACRO_TX_PWRD_4_0 0x730
#define EMC_PMACRO_TX_PWRD_5_0 0x734
#define EMC_PMACRO_TX_SEL_CLK_SRC_0_0 0x740
#define EMC_PMACRO_TX_SEL_CLK_SRC_1_0 0x744
#define EMC_PMACRO_TX_SEL_CLK_SRC_2_0 0x748
#define EMC_PMACRO_TX_SEL_CLK_SRC_3_0 0x74C
#define EMC_PMACRO_TX_SEL_CLK_SRC_4_0 0x750
#define EMC_PMACRO_TX_SEL_CLK_SRC_5_0 0x754
#define EMC_PMACRO_DDLL_BYPASS_0 0x760
#define EMC_PMACRO_DDLL_PWRD_0_0 0x770
#define EMC_PMACRO_DDLL_PWRD_1_0 0x774
#define EMC_PMACRO_DDLL_PWRD_2_0 0x778
#define EMC_PMACRO_CMD_CTRL_0_0 0x780
#define EMC_PMACRO_CMD_CTRL_1_0 0x784
#define EMC_PMACRO_CMD_CTRL_2_0 0x788
#define MC_REGISTER_BASE 0x70019000
#define MC_REGISTER_REGION_SIZE 0x1000
#define MC_INTSTATUS_0 0x000
#define MC_INTMASK_0 0x004
#define MC_ERR_STATUS_0 0x008
#define MC_ERR_ADR_0 0x00C
#define MC_SMMU_CONFIG_0 0x010
#define MC_SMMU_PTB_ASID_0 0x01C
#define MC_SMMU_PTB_DATA_0 0x020
#define MC_SMMU_TLB_FLUSH_0 0x030
#define MC_SMMU_PTC_FLUSH_0_0 0x034
#define MC_EMEM_CFG_0 0x050
#define MC_EMEM_ADR_CFG_0 0x054
#define MC_EMEM_ARB_CFG_0 0x090
#define MC_EMEM_ARB_OUTSTANDING_REQ_0 0x094
#define MC_EMEM_ARB_TIMING_RCD_0 0x098
#define MC_EMEM_ARB_TIMING_RP_0 0x09C
#define MC_EMEM_ARB_TIMING_RC_0 0x0A0
#define MC_EMEM_ARB_TIMING_RAS_0 0x0A4
#define MC_EMEM_ARB_TIMING_FAW_0 0x0A8
#define MC_EMEM_ARB_TIMING_RRD_0 0x0AC
#define MC_EMEM_ARB_TIMING_RAP2PRE_0 0x0B0
#define MC_EMEM_ARB_TIMING_WAP2PRE_0 0x0B4
#define MC_EMEM_ARB_TIMING_R2R_0 0x0B8
#define MC_EMEM_ARB_TIMING_W2W_0 0x0BC
#define MC_EMEM_ARB_TIMING_R2W_0 0x0C0
#define MC_EMEM_ARB_TIMING_W2R_0 0x0C4
#define MC_EMEM_ARB_MISC2_0 0x0C8
#define MC_EMEM_ARB_DA_TURNS_0 0x0D0
#define MC_EMEM_ARB_DA_COVERS_0 0x0D4
#define MC_EMEM_ARB_MISC0_0 0x0D8
#define MC_EMEM_ARB_MISC1_0 0x0DC
#define MC_TIMING_CONTROL_0 0xFC
#define MC_EMEM_ARB_RING1_THROTTLE_0 0x0E0
#define MC_CLIENT_HOTRESET_CTRL_0 0x200
#define MC_CLIENT_HOTRESET_STATUS_0 0x204
#define MC_SMMU_AFI_ASID_0 0x238
#define MC_SMMU_DC_ASID_0 0x240
#define MC_SMMU_DCB_ASID_0 0x244
#define MC_SMMU_HC_ASID_0 0x250
#define MC_SMMU_HDA_ASID_0 0x254
#define MC_SMMU_ISP2_ASID_0 0x258
#define MC_SMMU_MSENC_NVENC_ASID_0 0x264
#define MC_SMMU_NV_ASID_0 0x268
#define MC_SMMU_NV2_ASID_0 0x26C
#define MC_SMMU_PPCS_ASID_0 0x270
#define MC_SMMU_SATA_ASID_0 0x274
#define MC_SMMU_VI_ASID_0 0x280
#define MC_SMMU_VIC_ASID_0 0x284
#define MC_SMMU_XUSB_HOST_ASID_0 0x288
#define MC_SMMU_XUSB_DEV_ASID_0 0x28C
#define MC_SMMU_TSEC_ASID_0 0x294
#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2E4
#define MC_LATENCY_ALLOWANCE_DC_0 0x2E8
#define MC_LATENCY_ALLOWANCE_DC_1 0x2EC
#define MC_LATENCY_ALLOWANCE_DCB_0 0x2F4
#define MC_LATENCY_ALLOWANCE_DCB_1 0x2F8
#define MC_LATENCY_ALLOWANCE_HC_0 0x310
#define MC_LATENCY_ALLOWANCE_HC_1 0x314
#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37C
#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
#define MC_LATENCY_ALLOWANCE_GPU_0 0x3AC
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3B8
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3BC
#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3C0
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3C4
#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3D8
#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3E8
#define MC_DIS_PTSA_RATE_0 0x41C
#define MC_DIS_PTSA_MIN_0 0x420
#define MC_DIS_PTSA_MAX_0 0x424
#define MC_DISB_PTSA_RATE_0 0x428
#define MC_DISB_PTSA_MIN_0 0x42C
#define MC_DISB_PTSA_MAX_0 0x430
#define MC_VE_PTSA_RATE_0 0x434
#define MC_VE_PTSA_MIN_0 0x438
#define MC_VE_PTSA_MAX_0 0x43C
#define MC_MLL_MPCORER_PTSA_RATE_0 0x44C
#define MC_RING1_PTSA_RATE_0 0x47C
#define MC_RING1_PTSA_MIN_0 0x480
#define MC_RING1_PTSA_MAX_0 0x484
#define MC_PCX_PTSA_RATE_0 0x4AC
#define MC_PCX_PTSA_MIN_0 0x4B0
#define MC_PCX_PTSA_MAX_0 0x4B4
#define MC_MSE_PTSA_RATE_0 0x4C4
#define MC_MSE_PTSA_MIN_0 0x4C8
#define MC_MSE_PTSA_MAX_0 0x4CC
#define MC_AHB_PTSA_RATE_0 0x4DC
#define MC_AHB_PTSA_MIN_0 0x4E0
#define MC_AHB_PTSA_MAX_0 0x4E4
#define MC_APB_PTSA_RATE_0 0x4E8
#define MC_APB_PTSA_MIN_0 0x4EC
#define MC_APB_PTSA_MAX_0 0x4F0
#define MC_FTOP_PTSA_RATE_0 0x50C
#define MC_HOST_PTSA_RATE_0 0x518
#define MC_HOST_PTSA_MIN_0 0x51C
#define MC_HOST_PTSA_MAX_0 0x520
#define MC_USBX_PTSA_RATE_0 0x524
#define MC_USBX_PTSA_MIN_0 0x528
#define MC_USBX_PTSA_MAX_0 0x52C
#define MC_USBD_PTSA_RATE_0 0x530
#define MC_USBD_PTSA_MIN_0 0x534
#define MC_USBD_PTSA_MAX_0 0x538
#define MC_GK_PTSA_RATE_0 0x53C
#define MC_GK_PTSA_MIN_0 0x540
#define MC_GK_PTSA_MAX_0 0x544
#define MC_AUD_PTSA_RATE_0 0x548
#define MC_AUD_PTSA_MIN_0 0x54C
#define MC_AUD_PTSA_MAX_0 0x550
#define MC_VICPC_PTSA_RATE_0 0x554
#define MC_VICPC_PTSA_MIN_0 0x558
#define MC_VICPC_PTSA_MAX_0 0x55C
#define MC_JPG_PTSA_RATE_0 0x584
#define MC_JPG_PTSA_MIN_0 0x588
#define MC_JPG_PTSA_MAX_0 0x58C
#define MC_GK2_PTSA_RATE_0 0x610
#define MC_GK2_PTSA_MIN_0 0x614
#define MC_GK2_PTSA_MAX_0 0x618
#define MC_SDM_PTSA_RATE_0 0x61C
#define MC_SDM_PTSA_MIN_0 0x620
#define MC_SDM_PTSA_MAX_0 0x624
#define MC_HDAPC_PTSA_RATE_0 0x628
#define MC_HDAPC_PTSA_MIN_0 0x62C
#define MC_HDAPC_PTSA_MAX_0 0x630
#define MC_SEC_CARVEOUT_BOM_0 0x670
#define MC_SEC_CARVEOUT_SIZE_MB_0 0x674
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 0x690
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 0x694
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 0x698
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 0x69C
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 0x6A0
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 0x6A4
#define MC_EMEM_ARB_TIMING_RFCPB_0 0x6C0
#define MC_EMEM_ARB_TIMING_CCDMW_0 0x6C4
#define MC_EMEM_ARB_REFPB_HP_CTRL_0 0x6F0
#define MC_EMEM_ARB_REFPB_BANK_CTRL_0 0x6F4
#define MC_PTSA_GRANT_DECREMENT_0 0x960
#define MC_CLIENT_HOTRESET_CTRL_1 0x970
#define MC_CLIENT_HOTRESET_STATUS_1 0x974
#define MC_SMMU_PTC_FLUSH_1 0x9B8
#define MC_SMMU_DC1_ASID_0 0xA88
#define MC_SMMU_SDMMC1A_ASID_0 0xA94
#define MC_SMMU_SDMMC2A_ASID_0 0xA98
#define MC_SMMU_SDMMC3A_ASID_0 0xA9C
#define MC_SMMU_SDMMC4A_ASID_0 0xAA0
#define MC_SMMU_ISP2B_ASID_0 0xAA4
#define MC_SMMU_GPU_ASID_0 0xAA8
#define MC_SMMU_GPUB_ASID_0 0xAAC
#define MC_SMMU_PPCS2_ASID_0 0xAB0
#define MC_SMMU_NVDEC_ASID_0 0xAB4
#define MC_SMMU_APE_ASID_0 0xAB8
#define MC_SMMU_SE_ASID_0 0xABC
#define MC_SMMU_NVJPG_ASID_0 0xAC0
#define MC_SMMU_HC1_ASID_0 0xAC4
#define MC_SMMU_SE1_ASID_0 0xAC8
#define MC_SMMU_AXIAP_ASID_0 0xACC
#define MC_SMMU_ETR_ASID_0 0xAD0
#define MC_SMMU_TSECB_ASID_0 0xAD4
#define MC_SMMU_TSEC1_ASID_0 0xAD8
#define MC_SMMU_TSECB1_ASID_0 0xADC
#define MC_SMMU_NVDEC1_ASID_0 0xAE0
#define MC_EMEM_ARB_DHYST_CTRL_0 0xBCC
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xBD0
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xBD4
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xBD8
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xBDC
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xBE0
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xBE4
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xBE8
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xBEC
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_0 0xC00
#define MC_SECURITY_CARVEOUT2_BOM_0 0xC5C
#define MC_SECURITY_CARVEOUT3_BOM_0 0xCAC
#define CLDVFS_REGION_BASE 0x70110000
#define CLDVFS_REGION_SIZE 0x1000
#define CL_DVFS_CTRL_0 0x0
#define CL_DVFS_CONFIG_0 0x4
#define CL_DVFS_PARAMS_0 0x8
#define CL_DVFS_TUNE0_0 0xC
#define CL_DVFS_TUNE1_0 0x10
#define CL_DVFS_FREQ_REQ_0 0x14
#define CL_DVFS_SCALE_RAMP_0 0x18
#define CL_DVFS_DROOP_CTRL_0 0x1C
#define CL_DVFS_OUTPUT_CFG_0 0x20
#define CL_DVFS_OUTPUT_FORCE_0 0x24
#define CL_DVFS_MONITOR_CTRL_0 0x28
#define CL_DVFS_MONITOR_DATA_0 0x2C
#define CL_DVFS_I2C_CFG_0 0x40
#define CL_DVFS_I2C_VDD_REG_ADDR_0 0x44
#define CL_DVFS_I2C_STS_0 0x48
#define CL_DVFS_INTR_STS_0 0x5C
#define CL_DVFS_INTR_EN_0 0x60
#define DVFS_DFLL_THROTTLE_CTRL_0 0x64
#define DVFS_DFLL_THROTTLE_LIGHT_0 0x68
#define DVFS_DFLL_THROTTLE_MEDIUM_0 0x6C
#define DVFS_DFLL_THROTTLE_HEAVY_0 0x70
#define DVFS_CC4_HVC_0 0x74
#define CL_DVFS_MONITOR_DATA_0 0x2C
#define CL_DVFS_I2C_CFG_0 0x40
#define CL_DVFS_I2C_VDD_REG_ADDR_0 0x44
#define CL_DVFS_I2C_STS_0 0x48
#define CL_DVFS_INTR_STS_0 0x5C
#define CL_DVFS_I2C_CLK_DIVISOR_REGISTER_0 0x16C
#define CLK_SOURCE_EMC 0x19c
#define PLLC_BASE 0x080
#define PLLM_BASE 0x090
#define PLLP_BASE 0x0a0
#define PLLA_BASE 0x0b0
#define PLLU_BASE 0x0c0
#define _PLLD_BASE 0x0d0
#define PLLX_BASE 0x0e0
#define PLLE_BASE 0x0e8
#define PLLC2_BASE 0x4e8
#define PLLC3_BASE 0x4fc
#define PLLD2_BASE 0x4b8
#define PLLRE_BASE 0x4c4
#define PLLC4_BASE 0x5a4
#define PLLMB_BASE 0x5e8
#define PLLA1_BASE 0x6a4
#define PLLDP_BASE 0x590
#define OSC_HZ 38400000ULL

326
Source/hoc-clk/sysmodule/src/soc/t210.c Normal file
View File

@@ -0,0 +1,326 @@
/*
* Copyright (c) 2020-2023 CTCaer
* Copyright (c) 2023 p-sam
* Copyright (c) 2023 Lineon
* Copyright (c) 2026 Souldbminer
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include "t210.h"
#define WAIT_NS 1000000000UL
#define usleep(x) svcSleepThread(1000UL * x)
#define GPU_TRIM_SYS_GPCPLL_COEFF 0x4
#define GPU_TRIM_SYS_GPCPLL(x) (*(volatile u32 *)(g_gpu_base + 0x137000ul + (x)))
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL 0x60
#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS 0x64
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
#define CLK_RST_CONTROLLER_RST_DEVICES_X 0x28C
/*! PTO_CLK_CNT */
#define PTO_REF_CLK_WIN_CFG_MASK 0xF
#define PTO_REF_CLK_WIN_CFG_16P 0xF
#define PTO_CNT_EN BIT(9)
#define PTO_CNT_RST BIT(10)
#define PTO_CLK_ENABLE BIT(13)
#define PTO_SRC_SEL_SHIFT 14
#define PTO_SRC_SEL_MASK 0x1FF
#define PTO_DIV_SEL_MASK (3 << 23)
#define PTO_DIV_SEL_GATED (0 << 23)
#define PTO_DIV_SEL_DIV1 (1 << 23)
#define PTO_DIV_SEL_DIV2_RISING (2 << 23)
#define PTO_DIV_SEL_DIV2_FALLING (3 << 23)
#define PTO_DIV_SEL_CPU_EARLY (0 << 23)
#define PTO_DIV_SEL_CPU_LATE (1 << 23)
#define PTO_CLK_CNT_BUSY BIT(31)
#define PTO_CLK_CNT 0xFFFFFF
#define CLK_PTO_CCLK_G_DIV2 0x13
#define CLK_PTO_EMC 0x24
#define CLOCK(x) (*(volatile u32 *)(g_clk_base + (x)))
/* Actmon Global registers */
#define ACTMON_GLB_STATUS 0x0
#define ACTMON_MCCPU_MON_ACT BIT(8)
#define ACTMON_MCALL_MON_ACT BIT(9)
#define ACTMON_CPU_FREQ_MON_ACT BIT(10)
#define ACTMON_BPMP_MON_ACT BIT(14)
#define ACTMON_CPU_MON_ACT BIT(15)
#define ACTMON_GLB_PERIOD_CTRL 0x4
#define ACTMON_GLB_PERIOD_USEC BIT(8)
#define ACTMON_GLB_PERIOD_SAMPLE(n) (((n) - 1) & 0xFF)
/* Actmon Device Registers */
#define ACTMON_DEV_SIZE 0x40
/* Actmon CTRL */
#define ACTMON_DEV_CTRL_K_VAL(k) (((k) & 7) << 10)
#define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18)
#define ACTMON_DEV_CTRL_ENB BIT(31)
#define ACTMON_PERIOD_MS 20
#define DEV_COUNT_WEIGHT 1024
#define ACTMON_BASE (g_act_base + 0x800)
#define ACTMON_DEV_BASE (ACTMON_BASE + 0x80)
#define ACTMON(x) (*(volatile u32 *)(ACTMON_BASE + (x)))
typedef enum _actmon_dev_t
{
ACTMON_DEV_CPU,
ACTMON_DEV_BPMP,
ACTMON_DEV_AHB,
ACTMON_DEV_APB,
ACTMON_DEV_CPU_FREQ,
ACTMON_DEV_MC_ALL,
ACTMON_DEV_MC_CPU,
ACTMON_DEV_NUM,
} actmon_dev_t;
typedef struct _actmon_dev_reg_t
{
vu32 ctrl;
vu32 upper_wnark;
vu32 lower_wmark;
vu32 init_avg;
vu32 avg_upper_wmark;
vu32 avg_lower_wmark;
vu32 count_weight;
vu32 count;
vu32 avg_count;
vu32 intr_status;
vu32 ctrl2;
vu32 rsvd[5];
} actmon_dev_reg_t;
static uintptr_t g_clk_base = 0;
static uintptr_t g_gpu_base = 0;
static uintptr_t g_act_base = 0;
static u64 g_update_ticks = 0;
static u32 g_cpu_freq = 0;
static u32 g_gpu_freq = 0;
static u32 g_mem_freq = 0;
static u32 g_emc_lall = 0;
static u32 g_emc_lcpu = 0;
static u32 g_emc_bw_all = 0;
static u32 g_emc_bw_cpu = 0;
static u32 g_emc_bw_gpu = 0;
static u32 _clock_get_dev_freq(u32 id, u32 multiplier)
{
const u32 pto_win = 16;
const u32 pto_osc = 32768;
u32 val = ((id & PTO_SRC_SEL_MASK) << PTO_SRC_SEL_SHIFT) | PTO_DIV_SEL_DIV1 | PTO_CLK_ENABLE | (pto_win - 1);
CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val;
(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
usleep(2);
CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val | PTO_CNT_RST;
(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
usleep(2);
CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val;
(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
usleep(2);
CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val | PTO_CNT_EN;
(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
usleep((1000000ULL * pto_win / pto_osc) + 12 + 2); // 502 us.
while (CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS) & PTO_CLK_CNT_BUSY)
;
u32 cnt = CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS) & PTO_CLK_CNT;
CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = 0;
(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
usleep(2);
u32 freq_khz = (u64)cnt * multiplier * pto_osc / pto_win;
return freq_khz;
}
static void _actmon_dev_enable(actmon_dev_t dev, u32 freq, u32 weight)
{
actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
regs->init_avg = (u32)freq * ACTMON_PERIOD_MS / 2;
regs->count_weight = weight;
regs->ctrl = ACTMON_DEV_CTRL_ENB | ACTMON_DEV_CTRL_ENB_PERIODIC | ACTMON_DEV_CTRL_K_VAL(3); // 8 samples average.
}
static u32 _actmon_dev_get_count_avg(actmon_dev_t dev)
{
actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
return regs->avg_count;
}
static inline Result _svcQueryMemoryMappingFallback(u64* virtaddr, u64 physaddr, u64 size)
{
if(hosversionAtLeast(10,0,0))
{
u64 out_size;
return svcQueryMemoryMapping(virtaddr, &out_size, physaddr, size);
}
else
{
return svcLegacyQueryIoMapping(virtaddr, physaddr, size);
}
}
static void _clock_update_freqs(void)
{
u64 ticks = armGetSystemTick();
if(armTicksToNs(ticks - g_update_ticks) <= WAIT_NS)
{
return;
}
g_update_ticks = ticks;
if (!g_clk_base)
{
_svcQueryMemoryMappingFallback(&g_clk_base, 0x60006000ul, 0x1000);
}
if(!g_clk_base)
{
return;
}
g_mem_freq = _clock_get_dev_freq(CLK_PTO_EMC, 1);
g_cpu_freq = _clock_get_dev_freq(CLK_PTO_CCLK_G_DIV2, 2);
if (!g_gpu_base)
{
_svcQueryMemoryMappingFallback(&g_gpu_base, 0x57000000ul, 0x1000000);
}
if (!g_gpu_base)
{
return;
}
bool gpu_enabled = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) & BIT(24)) && !(CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_X) & BIT(24));
if(!gpu_enabled)
{
return;
}
if (!g_act_base)
{
_svcQueryMemoryMappingFallback(&g_act_base, 0x6000C000ul, 0x1000);
}
if(!g_act_base)
{
return;
}
const u32 osc = 38400000;
u32 coeff = GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF);
u32 divm = coeff & 0xFF;
u32 divn = (coeff >> 8) & 0xFF;
u32 divp = (coeff >> 16) & 0x3F;
g_gpu_freq = osc * divn / (divm * divp) / 2;
u32 emc_freq = g_mem_freq / 1000;
// Check if actmon is disabled
if (!(ACTMON(ACTMON_GLB_STATUS) & ACTMON_MCALL_MON_ACT))
{
ACTMON(ACTMON_GLB_PERIOD_CTRL) = ACTMON_GLB_PERIOD_SAMPLE(ACTMON_PERIOD_MS);
_actmon_dev_enable(ACTMON_DEV_MC_ALL, emc_freq, 256 * 4);
}
// Check if actmon is disabled
if (!(ACTMON(ACTMON_GLB_STATUS) & ACTMON_MCCPU_MON_ACT))
_actmon_dev_enable(ACTMON_DEV_MC_CPU, emc_freq, 256 * 4);
// Get 1000 -> 100.0.
g_emc_lall = (u64)_actmon_dev_get_count_avg(ACTMON_DEV_MC_ALL) * 10 * 100 / (emc_freq * ACTMON_PERIOD_MS);
g_emc_lcpu = (u64)_actmon_dev_get_count_avg(ACTMON_DEV_MC_CPU) * 10 * 100 / (emc_freq * ACTMON_PERIOD_MS);
// TODO: use PLL instead of actmon
// Avoid floating point arithematic
g_emc_bw_all = (u64)emc_freq * 16 * g_emc_lall / 1000000;
g_emc_bw_cpu = (u64)emc_freq * 16 * g_emc_lcpu / 1000000;
// Not 100% accurate but should be enough
g_emc_bw_gpu = g_emc_bw_all - g_emc_bw_cpu;
}
u32 t210ClkCpuFreq(void)
{
_clock_update_freqs();
return g_cpu_freq;
}
u32 t210ClkMemFreq(void)
{
_clock_update_freqs();
return g_mem_freq;
}
u32 t210ClkGpuFreq(void)
{
_clock_update_freqs();
return g_gpu_freq;
}
u32 t210EmcLoadAll()
{
_clock_update_freqs();
return g_emc_lall;
}
u32 t210EmcLoadCpu()
{
_clock_update_freqs();
return g_emc_lcpu;
}
u32 t210EmcBwAll()
{
_clock_update_freqs();
return g_emc_bw_all;
}
u32 t210EmcBwCpu()
{
_clock_update_freqs();
return g_emc_bw_cpu;
}
u32 t210EmcBwGpu()
{
_clock_update_freqs();
return g_emc_bw_gpu;
}
u32 t210EmcBwPeak()
{
_clock_update_freqs();
return ((u64)g_mem_freq * 16) / 1000000;
}

49
Source/hoc-clk/sysmodule/src/soc/t210.h Normal file
View File

@@ -0,0 +1,49 @@
/*
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
/* --------------------------------------------------------------------------
* "THE BEER-WARE LICENSE" (Revision 42):
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
* wrote this file. As long as you retain this notice you can do whatever you
* want with this stuff. If you meet any of us some day, and you think this
* stuff is worth it, you can buy us a beer in return. - The sys-clk authors
* --------------------------------------------------------------------------
*/
#pragma once
#ifdef __cplusplus
extern "C"
{
#endif
#include <switch.h>
u32 t210ClkCpuFreq(void);
u32 t210ClkMemFreq(void);
u32 t210ClkGpuFreq(void);
u32 t210EmcLoadAll(void);
u32 t210EmcLoadCpu(void);
u32 t210EmcBwAll(void);
u32 t210EmcBwCpu(void);
u32 t210EmcBwGpu(void);
u32 t210EmcBwPeak(void);
#ifdef __cplusplus
}
#endif