chore: many changes
This commit is contained in:
souldbminersmwc
@@ -29,61 +29,19 @@ namespace ams::ldr::oc {
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//volatile MarikoMtcTable MarikoMtcTablePlaceholder = { .rev = MARIKO_MTC_MAGIC, };
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volatile CustomizeTable C = {
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/* Common:
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* - Boost Clock in kHz:
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* Default: 1785000
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* Boost clock will be applied when applications request higher CPU frequency for quicker loading.
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* This will be set regardless of whether sys-clk is enabled.
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*/
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.commonCpuBoostClock = 1785000,
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/* - EMC Vddq (Erista Only) and RAM Vdd2 Voltage in uV
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* Range: 1100'000 to 1250'000 uV
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* Erista Default(HOS): 1125'000 (bootloader: 1100'000)
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* Mariko Default: 1100'000 (It will not work without sys-clk-OC.)
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* Value should be divided evenly by 12'500.
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* Not enabled by default.
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*/
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.commonEmcMemVolt = 1175000,
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.commonCpuBoostClock = 1785000, // Default boost clock
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.commonEmcMemVolt = 1175000, // LPDDR4X JEDEC Specification
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/* Erista CPU:
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* - Max Voltage in mV
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* - CpuVoltL4T: 1235
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*/
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.eristaCpuMaxVolt = 1235,
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/* Erista EMC(RAM):
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* - RAM Clock in kHz
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* [WARNING]
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* RAM overclock could be UNSTABLE if timing parameters are not suitable for your DRAM:
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* - Graphical glitches
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* - System instabilities
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* - NAND corruption
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*/
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.eristaEmcMaxClock = 1862400,
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.eristaEmcMaxClock = 1600000, // Maximum HB-MGCH ram rating
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/* Mariko CPU:
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* - Max Voltage in mV:
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* Default voltage: 1120
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*/
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.marikoCpuMaxVolt = 1120,
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/* Mariko EMC(RAM):
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* - RAM Clock in kHz:
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* Values should be ≥ 1600000, and divided evenly by 9600.
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* [WARNING]
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* RAM overclock could be UNSTABLE if timing parameters are not suitable for your DRAM:
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* - Graphical glitches
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* - System instabilities
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* - NAND corruption
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*/
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.marikoEmcMaxClock = 1996800,
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/* - EMC Vddq (Mariko Only) Voltage in uV
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* Range: 550'000 to 650'000 uV
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* Value should be divided evenly by 5'000
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* Default: 600'000
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* Not enabled by default.
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*/
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.marikoEmcMaxClock = 1862400, // Hynix NME and Samsung AM-MGCJ Rating (others are 4766MT, 2133MHz)
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.marikoEmcVddqVolt = 600000,
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.marikoCpuUV = 0,
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@@ -104,22 +62,26 @@ volatile CustomizeTable C = {
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.commonGpuVoltOffset = 0,
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.marikoEmcDvbShift = 0,
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.EmcDvbShift = 0,
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.t1_tRCD = 0,
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.t2_tRP = 0,
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.t3_tRAS = 0,
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// Defaults - (3-3-2) 0-1-4-3-6
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// Primary
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.t1_tRCD = 3,
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.t2_tRP = 3,
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.t3_tRAS = 2,
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// Secondary
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.t4_tRRD = 0,
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.t5_tRFC = 0,
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.t6_tRTW = 0,
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.t7_tWTR = 0,
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.t8_tREFI = 0,
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.t5_tRFC = 1,
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.t6_tRTW = 4,
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.t7_tWTR = 3,
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.t8_tREFI= 6,
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.mem_burst_latency = 0,
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.mem_burst_latency = 0, // 0 - 1600l, 1 = 1866bl, 2 = 2133bl
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.marikoCpuVmin = 600,
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.eristaGpuVmin = 810,
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.eristaGpuVmin = 775,
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.marikoGpuVmin = 610,
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@@ -258,44 +220,44 @@ volatile CustomizeTable C = {
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{ 691200, { }, { 1149425, 8144, -940, 808, -21583, 226 } },
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{ 768000, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
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{ 844800, { }, { 1233208, 8144, -940, 808, -21583, 226 } },
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{ 921600, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
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// { 998400, { }, { 1316991, 8144, -940, 808, -21583, 226 } },
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// { 1075200, { }, { 1358882, 8144, -940, 808, -21583, 226 } },
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// { 921600, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
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// { 998400, { }, { 1316991, 8144, -940, 808, -21583, 226 } },
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// { 1075200, { }, { 1358882, 8144, -940, 808, -21583, 226 } },
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},
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.eristaGpuDvfsTableSLT = {
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{ 76800, { }, { 772403, 8144, -940, 808, -21583, 226 } },
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{ 153600, { }, { 814294, 8144, -940, 808, -21583, 226 } },
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{ 230400, { }, { 856186, 8144, -940, 808, -21583, 226 } },
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{ 307200, { }, { 898077, 8144, -940, 808, -21583, 226 } },
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{ 384000, { }, { 939969, 8144, -940, 808, -21583, 226 } },
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{ 460800, { }, { 981860, 8144, -940, 808, -21583, 226 } },
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{ 537600, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
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{ 614400, { }, { 1065643, 8144, -940, 808, -21583, 226 } },
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{ 691200, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
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{ 768000, { }, { 1149426, 8144, -940, 808, -21583, 226 } },
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{ 844800, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
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{ 921600, { }, { 1233209, 8144, -940, 808, -21583, 226 } },
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// { 998400, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
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// { 1075200, { }, { 1316991, 8144, -940, 808, -21583, 226 } },
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{ 76800, { }, { 730512, 8144, -940, 808, -21583, 226 } },
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{ 153600, { }, { 772403, 8144, -940, 808, -21583, 226 } },
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{ 230400, { }, { 814294, 8144, -940, 808, -21583, 226 } },
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{ 307200, { }, { 856186, 8144, -940, 808, -21583, 226 } },
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{ 384000, { }, { 898077, 8144, -940, 808, -21583, 226 } },
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{ 460800, { }, { 939969, 8144, -940, 808, -21583, 226 } },
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{ 537600, { }, { 981860, 8144, -940, 808, -21583, 226 } },
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{ 614400, { }, { 1023751, 8144, -940, 808, -21583, 226 } },
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{ 691200, { }, { 1065643, 8144, -940, 808, -21583, 226 } },
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{ 768000, { }, { 1107534, 8144, -940, 808, -21583, 226 } },
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{ 844800, { }, { 1149426, 8144, -940, 808, -21583, 226 } },
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{ 921600, { }, { 1191317, 8144, -940, 808, -21583, 226 } },
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// { 998400, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
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// { 1075200, { }, { 1316991, 8144, -940, 808, -21583, 226 } },
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},
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.eristaGpuDvfsTableHigh = {
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{ 76800, { }, { 730512, 8144, -940, 808, -21583, 226 } },
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{ 153600, { }, { 772403, 8144, -940, 808, -21583, 226 } },
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{ 230400, { }, { 814295, 8144, -940, 808, -21583, 226 } },
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{ 307200, { }, { 856186, 8144, -940, 808, -21583, 226 } },
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{ 384000, { }, { 898078, 8144, -940, 808, -21583, 226 } },
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{ 460800, { }, { 939969, 8144, -940, 808, -21583, 226 } },
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{ 537600, { }, { 981860, 8144, -940, 808, -21583, 226 } },
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{ 614400, { }, { 1023752, 8144, -940, 808, -21583, 226 } },
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{ 691200, { }, { 1065643, 8144, -940, 808, -21583, 226 } },
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{ 768000, { }, { 1107535, 8144, -940, 808, -21583, 226 } },
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{ 844800, { }, { 1149426, 8144, -940, 808, -21583, 226 } },
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{ 921600, { }, { 1191318, 8144, -940, 808, -21583, 226 } },
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// { 998400, { }, { 1233209, 8144, -940, 808, -21583, 226 } },
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// { 1075200, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
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{ 76800, { }, { 646730, 8144, -940, 808, -21583, 226 } },
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{ 153600, { }, { 688621, 8144, -940, 808, -21583, 226 } },
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{ 230400, { }, { 730512, 8144, -940, 808, -21583, 226 } },
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{ 307200, { }, { 772403, 8144, -940, 808, -21583, 226 } },
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{ 384000, { }, { 814295, 8144, -940, 808, -21583, 226 } },
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{ 460800, { }, { 856186, 8144, -940, 808, -21583, 226 } },
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{ 537600, { }, { 898078, 8144, -940, 808, -21583, 226 } },
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{ 614400, { }, { 939969, 8144, -940, 808, -21583, 226 } },
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{ 691200, { }, { 981860, 8144, -940, 808, -21583, 226 } },
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{ 768000, { }, { 1023752, 8144, -940, 808, -21583, 226 } },
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{ 844800, { }, { 1065643, 8144, -940, 808, -21583, 226 } },
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{ 921600, { }, { 1107535, 8144, -940, 808, -21583, 226 } },
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{ 998400, { }, { 1149426, 8144, -940, 808, -21583, 226 } },
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// { 1075200, { }, { 1275100, 8144, -940, 808, -21583, 226 } },
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},
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/* - Mariko GPU DVFS Table:
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@@ -66,7 +66,7 @@
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u32 commonGpuVoltOffset;
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u32 marikoEmcDvbShift;
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u32 EmcDvbShift;
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// advanced config
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u32 t1_tRCD;
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@@ -12,171 +12,140 @@
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* from GCC preprocessor output
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*/
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#pragma once
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#include "oc_common.hpp"
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#pragma once
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namespace ams::ldr::oc {
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#define MAX(A, B) std::max(A, B)
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#define MIN(A, B) std::min(A, B)
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#define CEIL(A) std::ceil(A)
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#define FLOOR(A) std::floor(A)
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#include "oc_common.hpp"
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/* Primary timings. */
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const std::array<double, 8> tRCD_values = {18, 17, 16, 15, 14, 13, 12, 11};
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const std::array<double, 8> tRP_values = {18, 17, 16, 15, 14, 13, 12, 11};
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const std::array<double, 10> tRAS_values = {42, 36, 34, 32, 30, 28, 26, 24, 22, 20};
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namespace ams::ldr::oc {
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#define MAX(A, B) std::max(A, B)
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#define MIN(A, B) std::min(A, B)
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#define CEIL(A) std::ceil(A)
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#define FLOOR(A) std::floor(A)
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/* Secondary timings. */
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const std::array<double, 8> tRRD_values = {10.0, 7.5, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0};
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const std::array<double, 6> tRFC_values = {140, 120, 100, 80, 60, 40};
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const std::array<u32, 10> tRTW_values = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; /* Is this even correct? */
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const std::array<double, 10> tWTR_values = {10, 9, 8, 7, 6, 5, 4, 3, 2, 1};
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const std::array<u32, 7> tREFpb_values = {488, 732, 488 * 2, 488 * 3, 488 * 4, 488 * 6, 488 * 8}; /* TODO: Figure out if it's actually 8 and if this is even right. */
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//Preset One
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const std::array<u32, 8> tRCD_values = {18, 17, 16, 15, 14, 13, 12, 11};
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const std::array<u32, 8> tRP_values = {18, 17, 16, 15, 14, 13, 12, 11};
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const std::array<u32, 10> tRAS_values = {42, 36, 34, 32, 30, 28, 26, 24, 22, 20};
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// Preset Two
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const std::array<double, 8> tRRD_values = {10, 7.5, 6, 5, 4, 3, 2, 1};
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const std::array<double, 5> tFAW_values = {40, 30, 24, 16, 12};
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// Preset Three
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const std::array<u32, 6> tWR_values = {18, 15, 15, 12, 12, 8}; // TODO: identify what exactly eos tRTW even is (is it even real?)
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const std::array<double, 6> tRTP_values = {7.5, 7.5, 6, 6, 4, 4};
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// Preset Four
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const std::array<u32, 6> tRFC_values = {140, 120, 100, 80, 70, 60};
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// Preset Five
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const std::array<u32, 10> tWTR_values = {10, 9, 8, 7, 6, 5, 4, 3, 2, 1};
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// Preset Six
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const std::array<u32, 6> tREFpb_values = {488, 976, 1952, 3256, 6512, 9999};
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// const u32 TIMING_PRESET_ONE = C.ramTimingPresetOne;
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// const u32 TIMING_PRESET_TWO = C.ramTimingPresetTwo;
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const u32 TIMING_PRESET_THREE = 0;
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// const u32 TIMING_PRESET_FOUR = C.ramTimingPresetFour;
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// const u32 TIMING_PRESET_FIVE = C.ramTimingPresetFive;
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// const u32 TIMING_PRESET_SIX = C.ramTimingPresetSix;
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// const u32 TIMING_PRESET_SEVEN = C.ramTimingPresetSeven;
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// Burst Length
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const u32 BL = 16;
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// Write Latency
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const u32 BL = 16;
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const u32 RL = 28 + C.mem_burst_latency;
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const u32 WL = 14 + C.mem_burst_latency;
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// Read Latency
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const u32 RL = 32 + C.mem_burst_latency;
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// tRFCpb (refresh cycle time per bank) in ns for 8Gb density
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const u32 tRFCpb = !C.t5_tRFC ? 140 : tRFC_values[C.t5_tRFC-1];
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// tRFCab (refresh cycle time all banks) in ns for 8Gb density
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const u32 tRFCab = !C.t5_tRFC ? 280 : 2*tRFCpb;
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// tRAS (row active time) in ns
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const u32 tRAS = !C.t3_tRAS ? 42 : tRAS_values[C.t3_tRAS-1];
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// tRPpb (row precharge time per bank) in ns
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const u32 tRPpb = !C.t2_tRP ? 18 : tRP_values[C.t2_tRP-1];
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// tRPab (row precharge time all banks) in ns
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const u32 tRPab = !C.t2_tRP ? 21 : tRPpb + 3;
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// tRC (ACTIVATE-ACTIVATE command period same bank) in ns
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const u32 tRC = tRPab + tRAS;
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/* Refresh Cycle time. (All Banks) */
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const u32 tRFCab = (u32)(tRFC_values[C.t5_tRFC] * 1.5);
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/* Precharge to Precharge Delay. (Cycles) */
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/* Don't touch! */
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const u32 tPPD = 4;
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const u32 tRTW = !C.t6_tRTW ? 10 : tWTR_values[C.t6_tRTW-1];
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/* Four-bank ACTIVATE Window */
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const u32 tFAW = 30;
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// Write-to-Read delay
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const u32 tWTR = !C.t7_tWTR ? 10 : tWTR_values[C.t7_tWTR-1];
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// Internal READ-to-PRE-CHARGE command delay in ns
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const double tRTP = !TIMING_PRESET_THREE ? 7.5 : tRTP_values[TIMING_PRESET_THREE-1];
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// write recovery time
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const u32 tWR = !TIMING_PRESET_THREE ? 18 : tWR_values[TIMING_PRESET_THREE-1];
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// tRCD (RAS-CAS delay) in ns
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const u32 tRCD = !C.t1_tRCD ? 18 : tRCD_values[C.t1_tRCD-1];
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// tRRD (Active bank-A to Active bank-B) in ns
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const double tRRD = !C.t4_tRRD ? 10. : tRRD_values[C.t4_tRRD-1];
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// tREFpb (average refresh interval per bank) in ns for 8Gb density
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const u32 tREFpb = !C.t8_tREFI ? 488 : tREFpb_values[C.t8_tREFI-1];
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// Exit power-down to next valid command delay
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const double tXP = 7.5;
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// tXSR (SELF REFRESH exit to next valid command delay) in ns
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const double tXSR = tRFCab + 7.5;
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// Minimum self refresh time (entry to exit)
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const u32 tSR = 15;
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// tFAW (Four-bank Activate Window) in ns
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const u32 tFAW = 40;// !TIMING_PRESET_TWO ? 40 : tFAW_values[TIMING_PRESET_TWO-1]; TOGO
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// #_of_rows per die for 8Gb density
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const u32 numOfRows = 131072;
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// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
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// emc_clk_period = dram_clk / 2;
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// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
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const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.marikoEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
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const u32 REFBW = MIN((u32)65536, REFRESH+64);
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// DQS output access time from CK_t/CK_c
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const double tDQSCK_min = 1.5;
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/* DQS output access time from CK_t/CK_c. */
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const double tDQSCK_max = 3.5;
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// Write preamble (tCK)
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const double tWPRE = 1.8;
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// Read postamble (tCK)
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const double tRPST = 0.4;
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const double tWPRE = 2.0;
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/* tCK Read postamble. */
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const double tRPST = 0.5;
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namespace pcv::erista {
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// tCK_avg (average clock period) in ns
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const double tCK_avg = 1000'000. / C.eristaEmcMaxClock;
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/* tCK_avg may have to be improved... */
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||||
const double tCK_avg = 1000'000.0 / C.eristaEmcMaxClock;
|
||||
|
||||
// minimum number of cycles from any read command to any write command, irrespective of bank
|
||||
const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6;
|
||||
/* Primary timings. */
|
||||
const double tRCD = MAX(tRCD_values[C.t1_tRCD], 4.0 * tCK_avg);
|
||||
const double tRPpb = MAX(tRP_values[C.t2_tRP], 4.0 * tCK_avg);
|
||||
const double tRAS = MAX(tRAS_values[C.t3_tRAS], 3.0 * tCK_avg);
|
||||
|
||||
// Delay Time From WRITE-to-READ
|
||||
const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg) - 6;
|
||||
/* Secondary timings. */
|
||||
const double tRRD = MAX(tRRD_values[C.t4_tRRD], 4.0 * tCK_avg);
|
||||
const double tRFCpb = tRFC_values[C.t5_tRFC];
|
||||
const u32 tRTW = tRTW_values[C.t6_tRTW];
|
||||
const double tWTR = MAX(tWTR_values[C.t7_tWTR], 8.0 * tCK_avg);
|
||||
const u32 tREFpb = tREFpb_values[C.t8_tREFI];
|
||||
|
||||
// write-to-precharge time for commands to the same bank in cycles
|
||||
const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
|
||||
/* Latency stuff. */
|
||||
const u32 R2W = CEIL(RL + CEIL(tDQSCK_max/tCK_avg) + (BL/2) - WL + tWPRE + FLOOR(tRPST)) + 6;
|
||||
const u32 W2R = WL + (BL/2) + 1 + tWTR - 4;
|
||||
const u32 WTP = WL + (BL/2) + 1 + tWTR - 6;
|
||||
|
||||
/* Refresh stuff. */
|
||||
const u32 numOfRows = 65536;
|
||||
|
||||
// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
|
||||
// emc_clk_period = dram_clk / 2;
|
||||
// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
|
||||
const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.eristaEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
|
||||
const u32 REFBW = MIN((u32)65536, REFRESH+64);
|
||||
|
||||
|
||||
/* Do not touch stuff. */
|
||||
/* ACTIVATE-to-ACTIVATE command period. (same bank) */
|
||||
const double tRC = tRAS + tRPpb;
|
||||
|
||||
/* Minimum Self-Refresh Time. (Entry to Exit) */
|
||||
const double tSR = MAX(15.0, 3.0 * tCK_avg);
|
||||
/* SELF REFRESH exit to next valid command delay. */
|
||||
const double tXSR = MAX(tRFCab + 7.5, 2.0 * tCK_avg);
|
||||
|
||||
/* Exit power down to next valid command delay. */
|
||||
const double tXP = MAX(7.5, 5.0 * tCK_avg);
|
||||
|
||||
/* Internal READ to PRECHARGE command delay. */
|
||||
const double tRTP = MAX(7.5, 8.0 * tCK_avg);
|
||||
|
||||
/* Row Precharge Time. (all banks) */
|
||||
const double tRPab = MAX(21.0, 4.0 * tCK_avg);
|
||||
}
|
||||
|
||||
namespace pcv::mariko {
|
||||
// tCK_avg (average clock period) in ns
|
||||
const double tCK_avg = 1000'000. / C.marikoEmcMaxClock;
|
||||
/* tCK_avg may have to be improved... */
|
||||
const double tCK_avg = 1000'000.0 / C.marikoEmcMaxClock;
|
||||
|
||||
const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6;
|
||||
/* Primary timings. */
|
||||
const double tRCD = MAX(tRCD_values[C.t1_tRCD], 4.0 * tCK_avg);
|
||||
const double tRPpb = MAX(tRP_values[C.t2_tRP], 4.0 * tCK_avg);
|
||||
const double tRAS = MAX(tRAS_values[C.t3_tRAS], 3.0 * tCK_avg);
|
||||
|
||||
// Delay Time From WRITE-to-READ
|
||||
const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg) - 6;
|
||||
/* Secondary timings. */
|
||||
const double tRRD = MAX(tRRD_values[C.t4_tRRD], 4.0 * tCK_avg);
|
||||
const double tRFCpb = tRFC_values[C.t5_tRFC];
|
||||
const u32 tRTW = tRTW_values[C.t6_tRTW];
|
||||
const double tWTR = MAX(tWTR_values[C.t7_tWTR], 8.0 * tCK_avg);
|
||||
const u32 tREFpb = tREFpb_values[C.t8_tREFI];
|
||||
|
||||
// write-to-precharge time for commands to the same bank in cycles
|
||||
const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
|
||||
/* Latency stuff. */
|
||||
const u32 R2W = CEIL(RL + CEIL(tDQSCK_max/tCK_avg) + (BL/2) - WL + tWPRE + FLOOR(tRPST)) + 6;
|
||||
const u32 W2R = WL + (BL/2) + 1 + tWTR - 6;
|
||||
const u32 WTP = WL + (BL/2) + 1 + tWTR - 8;
|
||||
|
||||
const u32 numOfRows = 131072;
|
||||
/* Refresh stuff. */
|
||||
const u32 numOfRows = 65536;
|
||||
const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.eristaEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
|
||||
const u32 REFBW = MIN((u32)65536, REFRESH+64);
|
||||
|
||||
/* Do not touch stuff. */
|
||||
/* ACTIVATE-to-ACTIVATE command period. (same bank) */
|
||||
const double tRC = tRAS + tRPpb;
|
||||
|
||||
/* Minimum Self-Refresh Time. (Entry to Exit) */
|
||||
const double tSR = MAX(15.0, 3.0 * tCK_avg);
|
||||
/* SELF REFRESH exit to next valid command delay. */
|
||||
const double tXSR = MAX(tRFCab + 7.5, 2.0 * tCK_avg);
|
||||
|
||||
/* Exit power down to next valid command delay. */
|
||||
const double tXP = MAX(7.5, 5.0 * tCK_avg);
|
||||
|
||||
/* Internal READ to PRECHARGE command delay. */
|
||||
const double tRTP = MAX(7.5, 8.0 * tCK_avg);
|
||||
|
||||
/* Row Precharge Time. (all banks) */
|
||||
const double tRPab = MAX(21.0, 4.0 * tCK_avg);
|
||||
|
||||
// {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
|
||||
// emc_clk_period = dram_clk / 2;
|
||||
// 1600 MHz: 5894, but N' set to 6176 (~4.8% margin)
|
||||
const u32 REFRESH = MIN((u32)65472, u32(std::ceil((double(tREFpb) * C.marikoEmcMaxClock / numOfRows * 1.048 / 2 - 64))) / 4 * 4);
|
||||
const u32 REFBW = MIN((u32)130944, REFRESH+64);
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
@@ -65,10 +65,10 @@ Result GpuVmin(u32 *ptr) {
|
||||
Result CpuVoltDfll(u32* ptr) {
|
||||
cvb_cpu_dfll_data *entry = reinterpret_cast<cvb_cpu_dfll_data *>(ptr);
|
||||
|
||||
// R_UNLESS(entry->tune0_low == 0x0000FFCF, ldr::ResultInvalidCpuVoltDfllEntry());
|
||||
// R_UNLESS(entry->tune0_high == 0x00000000, ldr::ResultInvalidCpuVoltDfllEntry());
|
||||
// R_UNLESS(entry->tune1_low == 0x012207FF, ldr::ResultInvalidCpuVoltDfllEntry());
|
||||
// R_UNLESS(entry->tune1_high == 0x03FFF7FF, ldr::ResultInvalidCpuVoltDfllEntry());
|
||||
R_UNLESS(entry->tune0_low == 0x152f01, ldr::ResultInvalidCpuVoltDfllEntry());
|
||||
R_UNLESS(entry->tune0_high == 0x00000000, ldr::ResultInvalidCpuVoltDfllEntry());
|
||||
R_UNLESS(entry->tune1_low == 0x00000000, ldr::ResultInvalidCpuVoltDfllEntry());
|
||||
R_UNLESS(entry->tune1_high == 0x00000000, ldr::ResultInvalidCpuVoltDfllEntry());
|
||||
if(!C.eristaCpuUV) {
|
||||
R_SKIP();
|
||||
}
|
||||
@@ -78,24 +78,24 @@ Result GpuVmin(u32 *ptr) {
|
||||
|
||||
switch(C.eristaCpuUV) {
|
||||
case 1:
|
||||
PATCH_OFFSET(&(entry->tune0_low), 0x0000FFFF); //process_id 0 // EOS UV1
|
||||
PATCH_OFFSET(&(entry->tune1_low), 0x027007FF);
|
||||
PATCH_OFFSET(&(entry->tune0_high), 0xFFFF); //process_id 0 // EOS UV1
|
||||
PATCH_OFFSET(&(entry->tune1_high), 0x027007FF);
|
||||
break;
|
||||
case 2:
|
||||
PATCH_OFFSET(&(entry->tune0_low), 0x0000EFFF); //process_id 1 // EOS Uv2
|
||||
PATCH_OFFSET(&(entry->tune1_low), 0x027407FF);
|
||||
PATCH_OFFSET(&(entry->tune0_high), 0x0000EFFF); //process_id 1 // EOS Uv2
|
||||
PATCH_OFFSET(&(entry->tune1_high), 0x027407FF);
|
||||
break;
|
||||
case 3:
|
||||
PATCH_OFFSET(&(entry->tune0_low), 0x0000DFFF); //process_id 0 // EOS UV3
|
||||
PATCH_OFFSET(&(entry->tune1_low), 0x027807FF);
|
||||
PATCH_OFFSET(&(entry->tune0_high), 0x0000DFFF); //process_id 0 // EOS UV3
|
||||
PATCH_OFFSET(&(entry->tune1_high), 0x027807FF);
|
||||
break;
|
||||
case 4:
|
||||
PATCH_OFFSET(&(entry->tune0_low), 0x0000DFDF); //process_id 1 // EOS Uv4
|
||||
PATCH_OFFSET(&(entry->tune1_low), 0x027A07FF);
|
||||
PATCH_OFFSET(&(entry->tune0_high), 0x0000DFDF); //process_id 1 // EOS Uv4
|
||||
PATCH_OFFSET(&(entry->tune1_high), 0x027A07FF);
|
||||
break;
|
||||
case 5:
|
||||
PATCH_OFFSET(&(entry->tune0_low), 0x0000CFDF); // EOS UV5
|
||||
PATCH_OFFSET(&(entry->tune1_low), 0x037007FF);
|
||||
PATCH_OFFSET(&(entry->tune0_high), 0x0000CFDF); // EOS UV5
|
||||
PATCH_OFFSET(&(entry->tune1_high), 0x037007FF);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
@@ -159,91 +159,97 @@ Result GpuVmin(u32 *ptr) {
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
void MemMtcTableAutoAdjust(EristaMtcTable *table) {
|
||||
if (C.mtcConf != AUTO_ADJ)
|
||||
return;
|
||||
void MemMtcTableAutoAdjust(EristaMtcTable *table) {
|
||||
if (C.mtcConf != AUTO_ADJ)
|
||||
return;
|
||||
|
||||
#define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \
|
||||
TABLE->burst_regs.PARAM = VALUE; \
|
||||
TABLE->shadow_regs_ca_train.PARAM = VALUE; \
|
||||
TABLE->shadow_regs_quse_train.PARAM = VALUE; \
|
||||
TABLE->shadow_regs_rdwr_train.PARAM = VALUE;
|
||||
using namespace pcv::erista;
|
||||
|
||||
#define GET_CYCLE_CEIL(PARAM) u32(CEIL(double(PARAM) / tCK_avg))
|
||||
#define WRITE_PARAM_ALL_REG(TABLE, PARAM, VALUE) \
|
||||
TABLE->burst_regs.PARAM = VALUE; \
|
||||
TABLE->shadow_regs_ca_train.PARAM = VALUE; \
|
||||
TABLE->shadow_regs_quse_train.PARAM = VALUE; \
|
||||
TABLE->shadow_regs_rdwr_train.PARAM = VALUE;
|
||||
|
||||
WRITE_PARAM_ALL_REG(table, emc_rc, GET_CYCLE_CEIL(tRC));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rfc, GET_CYCLE_CEIL(tRFCab));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb));
|
||||
WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb));
|
||||
WRITE_PARAM_ALL_REG(table, emc_r2p, GET_CYCLE_CEIL(tRTP));
|
||||
WRITE_PARAM_ALL_REG(table, emc_r2w, R2W);
|
||||
WRITE_PARAM_ALL_REG(table, emc_w2r, W2R);
|
||||
WRITE_PARAM_ALL_REG(table, emc_w2p, WTP);
|
||||
WRITE_PARAM_ALL_REG(table, emc_rd_rcd, GET_CYCLE_CEIL(tRCD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_wr_rcd, GET_CYCLE_CEIL(tRCD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rrd, GET_CYCLE_CEIL(tRRD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_refresh, REFRESH);
|
||||
WRITE_PARAM_ALL_REG(table, emc_pre_refresh_req_cnt, REFRESH / 4);
|
||||
WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tXP));
|
||||
WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tXP));
|
||||
WRITE_PARAM_ALL_REG(table, emc_txsr, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
|
||||
WRITE_PARAM_ALL_REG(table, emc_txsrdll, MIN(GET_CYCLE_CEIL(tXSR), (u32)0x3fe));
|
||||
WRITE_PARAM_ALL_REG(table, emc_tckesr, GET_CYCLE_CEIL(tSR));
|
||||
WRITE_PARAM_ALL_REG(table, emc_tfaw, GET_CYCLE_CEIL(tFAW));
|
||||
WRITE_PARAM_ALL_REG(table, emc_trpab, GET_CYCLE_CEIL(tRPab));
|
||||
WRITE_PARAM_ALL_REG(table, emc_trefbw, REFBW);
|
||||
#define GET_CYCLE_CEIL(PARAM) u32(CEIL(double(PARAM) / tCK_avg))
|
||||
|
||||
#define WRITE_PARAM_BURST_MC_REG(TABLE, PARAM, VALUE) TABLE->burst_mc_regs.PARAM = VALUE;
|
||||
/* Primary timings. */
|
||||
// WRITE_PARAM_ALL_REG(table, emc_tckesr, GET_CYCLE_CEIL(tCK_avg));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rd_rcd, GET_CYCLE_CEIL(tRCD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_wr_rcd, GET_CYCLE_CEIL(tRCD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_ras, GET_CYCLE_CEIL(tRAS));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rp, GET_CYCLE_CEIL(tRPpb));
|
||||
|
||||
constexpr u32 MC_ARB_DIV = 4;
|
||||
constexpr u32 MC_ARB_SFA = 2;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rcd = CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV) - 2;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rp = CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV) - 1 + MC_ARB_SFA;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rc = CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV) - 1;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_ras = CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_faw = CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rrd = CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rap2pre = CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_wap2pre = CEIL(WTP / MC_ARB_DIV);
|
||||
table->burst_mc_regs.mc_emem_arb_timing_r2r = CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_w2w = CEIL(table->burst_regs.emc_wext / MC_ARB_DIV) - 1 + MC_ARB_SFA;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_r2w = CEIL(R2W / MC_ARB_DIV) - 1 + MC_ARB_SFA;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_w2r = CEIL(W2R / MC_ARB_DIV) - 1 + MC_ARB_SFA;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rfcpb = CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV);
|
||||
// table->burst_mc_regs.mc_emem_arb_timing_ccdmw = CEIL(tCCDMW / MC_ARB_DIV) -1 + MC_ARB_SFA;
|
||||
}
|
||||
/* Secondary timings. */
|
||||
WRITE_PARAM_ALL_REG(table, emc_rrd, GET_CYCLE_CEIL(tRRD));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rfcpb, GET_CYCLE_CEIL(tRFCpb));
|
||||
WRITE_PARAM_ALL_REG(table, emc_r2w, R2W);
|
||||
WRITE_PARAM_ALL_REG(table, emc_w2r, W2R);
|
||||
WRITE_PARAM_ALL_REG(table, emc_trefbw, REFBW);
|
||||
|
||||
WRITE_PARAM_ALL_REG(table, emc_rfc, GET_CYCLE_CEIL(tRFCab));
|
||||
WRITE_PARAM_ALL_REG(table, emc_tppd, tPPD);
|
||||
WRITE_PARAM_ALL_REG(table, emc_tfaw, GET_CYCLE_CEIL(tFAW));
|
||||
WRITE_PARAM_ALL_REG(table, emc_rc, GET_CYCLE_CEIL(tRC));
|
||||
WRITE_PARAM_ALL_REG(table, emc_tckesr, GET_CYCLE_CEIL(tSR));
|
||||
|
||||
WRITE_PARAM_ALL_REG(table, emc_tcke, MAX(4u, GET_CYCLE_CEIL(7.5)));
|
||||
WRITE_PARAM_ALL_REG(table, emc_txsr, GET_CYCLE_CEIL(tXSR));
|
||||
WRITE_PARAM_ALL_REG(table, emc_r2p, GET_CYCLE_CEIL(tRTP));
|
||||
WRITE_PARAM_ALL_REG(table, emc_w2p, WTP);
|
||||
WRITE_PARAM_ALL_REG(table, emc_pdex2wr, GET_CYCLE_CEIL(tXP));
|
||||
WRITE_PARAM_ALL_REG(table, emc_pdex2rd, GET_CYCLE_CEIL(tXP));
|
||||
|
||||
constexpr u32 MC_ARB_DIV = 4;
|
||||
constexpr u32 MC_ARB_SFA = 2;
|
||||
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rcd = u32(CEIL(GET_CYCLE_CEIL(tRCD) / double(MC_ARB_DIV))) - 2;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rp = u32(CEIL(GET_CYCLE_CEIL(tRPpb) / double(MC_ARB_DIV))) - 1 + MC_ARB_SFA;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rc = u32(CEIL(GET_CYCLE_CEIL(tRC) / double(MC_ARB_DIV))) - 1;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_ras = u32(CEIL(GET_CYCLE_CEIL(tRAS) / double(MC_ARB_DIV))) - 2;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_faw = u32(CEIL(GET_CYCLE_CEIL(tFAW) / double(MC_ARB_DIV))) - 1;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rrd = u32(CEIL(GET_CYCLE_CEIL(tRRD) / double(MC_ARB_DIV))) - 1;
|
||||
table->burst_mc_regs.mc_emem_arb_timing_rap2pre = u32(CEIL(GET_CYCLE_CEIL(tRTP) / double(MC_ARB_DIV)));
|
||||
table->burst_mc_regs.mc_emem_arb_timing_r2w = u32(CEIL(R2W / double(MC_ARB_DIV)));
|
||||
table->burst_mc_regs.mc_emem_arb_timing_w2r = u32(CEIL(W2R / double(MC_ARB_DIV)));
|
||||
#undef GET_CYCLE_CEIL
|
||||
}
|
||||
|
||||
Result MemFreqMtcTable(u32 *ptr) {
|
||||
u32 khz_list[] = {1600000, 1331200, 1065600, 800000, 665600, 408000, 204000, 102000, 68000, 40800};
|
||||
u32 khz_list_size = sizeof(khz_list) / sizeof(u32);
|
||||
if(C.eristaEmcMaxClock != EmcClkOSLimit) {
|
||||
u32 khz_list[] = {1600000, 1331200, 1065600, 800000, 665600, 408000, 204000, 102000, 68000, 40800};
|
||||
u32 khz_list_size = sizeof(khz_list) / sizeof(u32);
|
||||
|
||||
// Generate list for mtc table pointers
|
||||
EristaMtcTable *table_list[khz_list_size];
|
||||
for (u32 i = 0; i < khz_list_size; i++) {
|
||||
u8 *table = reinterpret_cast<u8 *>(ptr) - offsetof(EristaMtcTable, rate_khz) - i * sizeof(EristaMtcTable);
|
||||
table_list[i] = reinterpret_cast<EristaMtcTable *>(table);
|
||||
R_UNLESS(table_list[i]->rate_khz == khz_list[i], ldr::ResultInvalidMtcTable());
|
||||
R_UNLESS(table_list[i]->rev == MTC_TABLE_REV, ldr::ResultInvalidMtcTable());
|
||||
// Generate list for mtc table pointers
|
||||
EristaMtcTable *table_list[khz_list_size];
|
||||
for (u32 i = 0; i < khz_list_size; i++) {
|
||||
u8 *table = reinterpret_cast<u8 *>(ptr) - offsetof(EristaMtcTable, rate_khz) - i * sizeof(EristaMtcTable);
|
||||
table_list[i] = reinterpret_cast<EristaMtcTable *>(table);
|
||||
R_UNLESS(table_list[i]->rate_khz == khz_list[i], ldr::ResultInvalidMtcTable());
|
||||
R_UNLESS(table_list[i]->rev == MTC_TABLE_REV, ldr::ResultInvalidMtcTable());
|
||||
|
||||
}
|
||||
|
||||
if (C.eristaEmcMaxClock <= EmcClkOSLimit)
|
||||
R_SKIP();
|
||||
|
||||
// Make room for new mtc table, discarding useless 40.8 MHz table
|
||||
// 40800 overwritten by 68000, ..., 1331200 overwritten by 1600000, leaving table_list[0] not overwritten
|
||||
for (u32 i = khz_list_size - 1; i > 0; i--)
|
||||
std::memcpy(static_cast<void *>(table_list[i]), static_cast<void *>(table_list[i - 1]), sizeof(EristaMtcTable));
|
||||
|
||||
MemMtcTableAutoAdjust(table_list[0]);
|
||||
PATCH_OFFSET(ptr, C.eristaEmcMaxClock);
|
||||
|
||||
// Handle customize table replacement
|
||||
// if (C.mtcConf == CUSTOMIZED_ALL) {
|
||||
// MemMtcCustomizeTable(table_list[0], const_cast<EristaMtcTable *>(C.eristaMtcTable));
|
||||
//}
|
||||
|
||||
R_SUCCEED();
|
||||
} else {
|
||||
R_SUCCEED(); // Skip changing table on default freq
|
||||
}
|
||||
|
||||
if (C.eristaEmcMaxClock <= EmcClkOSLimit)
|
||||
R_SKIP();
|
||||
|
||||
// Make room for new mtc table, discarding useless 40.8 MHz table
|
||||
// 40800 overwritten by 68000, ..., 1331200 overwritten by 1600000, leaving table_list[0] not overwritten
|
||||
for (u32 i = khz_list_size - 1; i > 0; i--)
|
||||
std::memcpy(static_cast<void *>(table_list[i]), static_cast<void *>(table_list[i - 1]), sizeof(EristaMtcTable));
|
||||
|
||||
MemMtcTableAutoAdjust(table_list[0]);
|
||||
PATCH_OFFSET(ptr, C.eristaEmcMaxClock);
|
||||
|
||||
// Handle customize table replacement
|
||||
// if (C.mtcConf == CUSTOMIZED_ALL) {
|
||||
// MemMtcCustomizeTable(table_list[0], const_cast<EristaMtcTable *>(C.eristaMtcTable));
|
||||
//}
|
||||
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
Result MemFreqMax(u32 *ptr) {
|
||||
@@ -255,6 +261,42 @@ Result GpuVmin(u32 *ptr) {
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
// Result MemFreqDvbTable(u32* ptr) {
|
||||
// emc_dvb_dvfs_table_t* default_end = reinterpret_cast<emc_dvb_dvfs_table_t *>(ptr);
|
||||
// emc_dvb_dvfs_table_t* new_start = default_end + 1;
|
||||
|
||||
// // Validate existing table
|
||||
// void* mem_dvb_table_head = reinterpret_cast<u8 *>(new_start) - sizeof(EmcDvbTableDefault);
|
||||
// bool validated = std::memcmp(mem_dvb_table_head, EmcDvbTableDefault, sizeof(EmcDvbTableDefault)) == 0;
|
||||
// R_UNLESS(validated, ldr::ResultInvalidDvbTable());
|
||||
|
||||
// if (C.eristaEmcMaxClock <= EmcClkOSLimit)
|
||||
// R_SKIP();
|
||||
|
||||
// int32_t voltAdd = 25*C.EmcDvbShift;
|
||||
|
||||
// #define DVB_VOLT(zero, one, two) std::min(zero+voltAdd, 1050), std::min(one+voltAdd, 1025), std::min(two+voltAdd, 1000),
|
||||
|
||||
// if (C.marikoEmcMaxClock < 1862400) {
|
||||
// std::memcpy(new_start, default_end, sizeof(emc_dvb_dvfs_table_t));
|
||||
// } else if (C.marikoEmcMaxClock < 2131200){
|
||||
// emc_dvb_dvfs_table_t oc_table = { 1862400, { 950, 925, 900, } };
|
||||
// std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
// } else if (C.marikoEmcMaxClock < 2227000){
|
||||
// emc_dvb_dvfs_table_t oc_table = { 2131200, { 975, 950, 925, } };
|
||||
// std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
// } else {
|
||||
// emc_dvb_dvfs_table_t oc_table = { 2227000, { DVB_VOLT(1000, 975, 950) } };
|
||||
// std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
// }
|
||||
// new_start->freq = C.eristaEmcMaxClock;
|
||||
// /* Max dvfs entry is 32, but HOS doesn't seem to boot if exact freq doesn't exist in dvb table,
|
||||
// reason why it's like this
|
||||
// */
|
||||
|
||||
// R_SUCCEED();
|
||||
// }
|
||||
|
||||
void Patch(uintptr_t mapped_nso, size_t nso_size) {
|
||||
u32 CpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(CpuCvbTableDefault)->freq);
|
||||
u32 GpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(GpuCvbTableDefault)->freq);
|
||||
@@ -270,6 +312,7 @@ Result GpuVmin(u32 *ptr) {
|
||||
{"MEM Freq Mtc", &MemFreqMtcTable, 0, nullptr, EmcClkOSLimit},
|
||||
{"MEM Freq Max", &MemFreqMax, 0, nullptr, EmcClkOSLimit},
|
||||
{"MEM Freq PLLM", &MemFreqPllmLimit, 2, nullptr, EmcClkPllmLimit},
|
||||
// {"MEM Freq Dvb", &MemFreqDvbTable, 1, nullptr, EmcClkOSLimit},
|
||||
{"MEM Volt", &MemVoltHandler, 2, nullptr, MemVoltHOS},
|
||||
{"GPU Vmin", &GpuVmin, 0, nullptr, gpuVmin},
|
||||
};
|
||||
|
||||
@@ -324,7 +324,7 @@ namespace ams::ldr::oc::pcv::mariko
|
||||
constexpr u32 MC_ARB_DIV = 4;
|
||||
constexpr u32 MC_ARB_SFA = 2;
|
||||
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_cfg, C.marikoEmcMaxClock / (33.3 * 1000) / MC_ARB_DIV); //CYCLES_PER_UPDATE: The number of mcclk cycles per deadline timer update
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_cfg, C.marikoEmcMaxClock / (33.3 * 1000) / MC_ARB_DIV); // CYCLES_PER_UPDATE: The number of mcclk cycles per deadline timer update
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rcd, CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV) - 2)
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rp, CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rc, CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV) - 1)
|
||||
@@ -333,9 +333,9 @@ namespace ams::ldr::oc::pcv::mariko
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rrd, CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1)
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rap2pre, CEIL(GET_CYCLE_CEIL(tRTP) / MC_ARB_DIV))
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_wap2pre, CEIL((WTP) / MC_ARB_DIV))
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2r, CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA)
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2w, CEIL((R2W) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_w2r, CEIL((W2R) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2r, CEIL(table->burst_regs.emc_rext / MC_ARB_DIV) - 1 + MC_ARB_SFA)
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_r2w, CEIL((R2W) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_w2r, CEIL((W2R) / MC_ARB_DIV) - 1 + MC_ARB_SFA)
|
||||
WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_timing_rfcpb, CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV))
|
||||
}
|
||||
|
||||
@@ -412,48 +412,70 @@ namespace ams::ldr::oc::pcv::mariko
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
Result MemFreqDvbTable(u32* ptr) {
|
||||
emc_dvb_dvfs_table_t* default_end = reinterpret_cast<emc_dvb_dvfs_table_t *>(ptr);
|
||||
emc_dvb_dvfs_table_t* new_start = default_end + 1;
|
||||
|
||||
Result MemFreqDvbTable(u32 *ptr)
|
||||
{
|
||||
emc_dvb_dvfs_table_t *default_end = reinterpret_cast<emc_dvb_dvfs_table_t *>(ptr);
|
||||
emc_dvb_dvfs_table_t *new_start = default_end + 1;
|
||||
|
||||
// Validate existing table
|
||||
void* mem_dvb_table_head = reinterpret_cast<u8 *>(new_start) - sizeof(EmcDvbTableDefault);
|
||||
void *mem_dvb_table_head = reinterpret_cast<u8 *>(new_start) - sizeof(EmcDvbTableDefault);
|
||||
bool validated = std::memcmp(mem_dvb_table_head, EmcDvbTableDefault, sizeof(EmcDvbTableDefault)) == 0;
|
||||
R_UNLESS(validated, ldr::ResultInvalidDvbTable());
|
||||
|
||||
|
||||
if (C.marikoEmcMaxClock <= EmcClkOSLimit)
|
||||
R_SKIP();
|
||||
|
||||
int32_t voltAdd = 25*C.marikoEmcDvbShift;
|
||||
|
||||
#define DVB_VOLT(zero, one, two) std::min(zero+voltAdd, 1050), std::min(one+voltAdd, 1025), std::min(two+voltAdd, 1000),
|
||||
|
||||
if (C.marikoEmcMaxClock < 1862400) {
|
||||
|
||||
int32_t voltAdd = 25 * C.EmcDvbShift;
|
||||
|
||||
#define DVB_VOLT(zero, one, two) std::min(zero + voltAdd, 1050), std::min(one + voltAdd, 1025), std::min(two + voltAdd, 1000),
|
||||
|
||||
if (C.marikoEmcMaxClock < 1862400)
|
||||
{
|
||||
std::memcpy(new_start, default_end, sizeof(emc_dvb_dvfs_table_t));
|
||||
} else if (C.marikoEmcMaxClock < 2131200){
|
||||
emc_dvb_dvfs_table_t oc_table = { 1862400, { 700, 675, 650, } };
|
||||
}
|
||||
else if (C.marikoEmcMaxClock < 2131200)
|
||||
{
|
||||
emc_dvb_dvfs_table_t oc_table = {1862400, {
|
||||
700,
|
||||
675,
|
||||
650,
|
||||
}};
|
||||
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
} else if (C.marikoEmcMaxClock < 2400000){
|
||||
emc_dvb_dvfs_table_t oc_table = { 2131200, { 725, 700, 675, } };
|
||||
}
|
||||
else if (C.marikoEmcMaxClock < 2400000)
|
||||
{
|
||||
emc_dvb_dvfs_table_t oc_table = {2131200, {
|
||||
725,
|
||||
700,
|
||||
675,
|
||||
}};
|
||||
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
} else if (C.marikoEmcMaxClock < 2665600){
|
||||
emc_dvb_dvfs_table_t oc_table = { 2400000, { DVB_VOLT(750, 725, 700) } };
|
||||
}
|
||||
else if (C.marikoEmcMaxClock < 2665600)
|
||||
{
|
||||
emc_dvb_dvfs_table_t oc_table = {2400000, {DVB_VOLT(750, 725, 700)}};
|
||||
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
} else if (C.marikoEmcMaxClock < 2931200){
|
||||
emc_dvb_dvfs_table_t oc_table = { 2665600, { DVB_VOLT(775, 750, 725) } };
|
||||
}
|
||||
else if (C.marikoEmcMaxClock < 2931200)
|
||||
{
|
||||
emc_dvb_dvfs_table_t oc_table = {2665600, {DVB_VOLT(775, 750, 725)}};
|
||||
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
} else if (C.marikoEmcMaxClock < 3200000){
|
||||
emc_dvb_dvfs_table_t oc_table = { 2931200, { DVB_VOLT(800, 775, 750) } };
|
||||
}
|
||||
else if (C.marikoEmcMaxClock < 3200000)
|
||||
{
|
||||
emc_dvb_dvfs_table_t oc_table = {2931200, {DVB_VOLT(800, 775, 750)}};
|
||||
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
} else {
|
||||
emc_dvb_dvfs_table_t oc_table = { 3200000, { DVB_VOLT(800, 800, 775) } };
|
||||
}
|
||||
else
|
||||
{
|
||||
emc_dvb_dvfs_table_t oc_table = {3200000, {DVB_VOLT(800, 800, 775)}};
|
||||
std::memcpy(new_start, &oc_table, sizeof(emc_dvb_dvfs_table_t));
|
||||
}
|
||||
new_start->freq = C.marikoEmcMaxClock;
|
||||
/* Max dvfs entry is 32, but HOS doesn't seem to boot if exact freq doesn't exist in dvb table,
|
||||
reason why it's like this
|
||||
*/
|
||||
|
||||
reason why it's like this
|
||||
*/
|
||||
|
||||
R_SUCCEED();
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user