Revert "revert"

This reverts commit 35fa56d3f7.

Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv.cpp

@@ -1,8 +1,6 @@
 /*
  * Copyright (C) Switch-OC-Suite
  *
- * Copyright (c) 2023 hanai3Bi
- * 
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
  * version 2, as published by the Free Software Foundation.
@@ -16,11 +14,11 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include "pcv.hpp"
+ #include "pcv.hpp"
 
-namespace ams::ldr::oc::pcv {
+ namespace ams::ldr::oc::pcv {
  
-Result MemFreqPllmLimit(u32* ptr) {
+ Result MemFreqPllmLimit(u32* ptr) {
      clk_pll_param* entry = reinterpret_cast<clk_pll_param *>(ptr);
      R_UNLESS(entry->freq == entry->vco_max, ldr::ResultInvalidMemPllmEntry());
  
@@ -29,9 +27,9 @@ Result MemFreqPllmLimit(u32* ptr) {
      entry->freq = max_clk;
      entry->vco_max = max_clk;
      R_SUCCEED();
-}
+ }
  
-Result MemVoltHandler(u32* ptr) {
+ Result MemVoltHandler(u32* ptr) {
      // ptr value might be default_uv or max_uv
      regulator* entries[2] = {
          reinterpret_cast<regulator *>(reinterpret_cast<u8 *>(ptr) - offsetof(regulator, type_1.default_uv)),
@@ -68,9 +66,9 @@ Result MemVoltHandler(u32* ptr) {
      PATCH_OFFSET(ptr, emc_uv);
  
      R_SUCCEED();
-}
+ }
  
-void SafetyCheck() {
+ void SafetyCheck() {
      if (C.custRev != CUST_REV)
          CRASH("Triggered");
  
@@ -114,11 +112,11 @@ void SafetyCheck() {
      
      sValidator validators[] = {
          { C.commonCpuBoostClock, 1020'000, 3000'000, true },
-        { C.commonEmcMemVolt,    1100'000, 1250'000 },
+         { C.commonEmcMemVolt,    1000'000, 1350'000 },
          { C.eristaCpuMaxVolt,        1100,     1300 },
          { C.eristaEmcMaxClock,   1600'000, 2131'200 },
-        { C.marikoCpuMaxVolt,        1100,     1300 },
+         { C.marikoCpuMaxVolt,         800,     1160 },
-        { C.marikoEmcMaxClock,   1600'000, 2800'000 },
+         { C.marikoEmcMaxClock,   1600'000, 3600'000 },
          { C.marikoEmcVddqVolt,    550'000,  650'000 },
          { eristaCpuDvfsMaxFreq,  1785'000, 3000'000 },
          { marikoCpuDvfsMaxFreq,  1785'000, 3000'000 },
@@ -130,9 +128,9 @@ void SafetyCheck() {
          if (R_FAILED(i.check()))
              CRASH("Triggered");
      }
-}
+ }
  
-void Patch(uintptr_t mapped_nso, size_t nso_size) {
+ void Patch(uintptr_t mapped_nso, size_t nso_size) {
      #ifdef ATMOSPHERE_IS_STRATOSPHERE
      SafetyCheck();
      bool isMariko = (spl::GetSocType() == spl::SocType_Mariko);
@@ -141,6 +139,6 @@ void Patch(uintptr_t mapped_nso, size_t nso_size) {
      else
          erista::Patch(mapped_nso, nso_size);
      #endif
-}
+ }
  
-}
+ }

Source/Atmosphere/stratosphere/loader/source/oc/pcv/pcv_mariko.cpp

@@ -1,8 +1,6 @@
 /*
  * Copyright (C) Switch-OC-Suite
  *
- * Copyright (c) 2023 hanai3Bi
- * 
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
  * version 2, as published by the Free Software Foundation.
@@ -16,13 +14,12 @@
  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
-#include "pcv.hpp"
+ #include "pcv.hpp"
-#include "../mtc_timing_value.hpp"
+ #include "../mtc_timing_value.hpp"
-#include "../customize.hpp"
  
-namespace ams::ldr::oc::pcv::mariko {
+ namespace ams::ldr::oc::pcv::mariko {
  
-Result CpuFreqVdd(u32* ptr) {
+ Result CpuFreqVdd(u32* ptr) {
      dvfs_rail* entry = reinterpret_cast<dvfs_rail *>(reinterpret_cast<u8 *>(ptr) - offsetof(dvfs_rail, freq));
  
      R_UNLESS(entry->id == 1,            ldr::ResultInvalidCpuFreqVddEntry());
@@ -37,9 +34,9 @@ Result CpuFreqVdd(u32* ptr) {
      }
      
      R_SUCCEED();
-}
+ }
  
-Result CpuVoltRange(u32* ptr) {
+ Result CpuVoltRange(u32* ptr) {
      u32 min_volt_got = *(ptr - 1);
      for (const auto& mv : CpuMinVolts) {
          if (min_volt_got != mv)
@@ -62,9 +59,9 @@ Result CpuVoltRange(u32* ptr) {
          R_SUCCEED();
      }
      R_THROW(ldr::ResultInvalidCpuMinVolt());
-}
+ }
  
-Result CpuVoltDfll(u32* ptr) {
+ Result CpuVoltDfll(u32* ptr) {
      cvb_cpu_dfll_data *entry = reinterpret_cast<cvb_cpu_dfll_data *>(ptr);
  
      R_UNLESS(entry->tune0_low == 0x0000FFCF,   ldr::ResultInvalidCpuVoltDfllEntry());
@@ -75,18 +72,22 @@ Result CpuVoltDfll(u32* ptr) {
      if (C.marikoCpuUV) {
          if (C.marikoCpuUV == 1) {
              PATCH_OFFSET(&(entry->tune0_low), 0x0000FF90); //process_id 0
-        } else if (C.marikoCpuUV == 2) {
-            PATCH_OFFSET(&(entry->tune0_low), 0x0000FFA0); //process_id 1
-        }
              PATCH_OFFSET(&(entry->tune0_high), 0x0000FFFF);
              PATCH_OFFSET(&(entry->tune1_low), 0x021107FF);
              PATCH_OFFSET(&(entry->tune1_high), 0x00000000);
          } 
+         else if (C.marikoCpuUV == 2) {
+             PATCH_OFFSET(&(entry->tune0_low), 0x0000FFA0); //process_id 1
+             PATCH_OFFSET(&(entry->tune0_high), 0x0000FFFF);
+             PATCH_OFFSET(&(entry->tune1_low), 0x021107FF);
+             PATCH_OFFSET(&(entry->tune1_high), 0x00000000);
+         }
+     }
  
      R_SUCCEED();
-}
+ }
  
-Result GpuFreqMaxAsm(u32* ptr32) {
+ Result GpuFreqMaxAsm(u32* ptr32) {
      // Check if both two instructions match the pattern
      u32 ins1 = *ptr32, ins2 = *(ptr32 + 1);
      if (!(asm_compare_no_rd(ins1, asm_pattern[0]) && asm_compare_no_rd(ins2, asm_pattern[1])))
@@ -120,9 +121,9 @@ Result GpuFreqMaxAsm(u32* ptr32) {
      PATCH_OFFSET(ptr32 + 1, asm_patch[1]);
  
      R_SUCCEED();
-}
+ }
  
-Result GpuFreqPllLimit(u32* ptr) {
+ Result GpuFreqPllLimit(u32* ptr) {
      clk_pll_param* entry = reinterpret_cast<clk_pll_param *>(ptr);
  
      // All zero except for freq
@@ -134,9 +135,9 @@ Result GpuFreqPllLimit(u32* ptr) {
      u32 max_clk = entry->freq * 2;
      entry->freq = max_clk;
      R_SUCCEED();
-}
+ }
  
-void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
+ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
      /* Official Tegra X1 TRM, sign up for nvidia developer program (free) to download:
       *     https://developer.nvidia.com/embedded/dlc/tegra-x1-technical-reference-manual
       *     Section 18.11: MC Registers
@@ -196,7 +197,7 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
      WRITE_PARAM_ALL_REG(table, emc_twtm,                WTM);
      WRITE_PARAM_ALL_REG(table, emc_tratm,               RATM);
      WRITE_PARAM_ALL_REG(table, emc_twatm,               WATM);
-    //WRITE_PARAM_ALL_REG(table, emc_tr2ref,              GET_CYCLE_CEIL(C.tR2REF));
+     //WRITE_PARAM_ALL_REG(table, emc_tr2ref,              GET_CYCLE_CEIL(tR2REF));
      WRITE_PARAM_ALL_REG(table, emc_rd_rcd,              GET_CYCLE_CEIL(C.tRCD));
      WRITE_PARAM_ALL_REG(table, emc_wr_rcd,              GET_CYCLE_CEIL(C.tRCD));
      WRITE_PARAM_ALL_REG(table, emc_rrd,                 GET_CYCLE_CEIL(C.tRRD));
@@ -210,7 +211,7 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
      WRITE_PARAM_ALL_REG(table, emc_ar2pden,             GET_CYCLE_CEIL(C.tCMDCKE));
      WRITE_PARAM_ALL_REG(table, emc_rw2pden,             WTPDEN);
      WRITE_PARAM_ALL_REG(table, emc_cke2pden,            GET_CYCLE_CEIL(C.tCKELCS));
-    //WRITE_PARAM_ALL_REG(table, emc_pdex2cke,            GET_CYCLE_CEIL(C.tCSCKEH));
+     //WRITE_PARAM_ALL_REG(table, emc_pdex2cke,            GET_CYCLE_CEIL(tCSCKEH));
      WRITE_PARAM_ALL_REG(table, emc_pdex2mrr,            GET_CYCLE_CEIL(tPDEX2MRR));
      WRITE_PARAM_ALL_REG(table, emc_txsr,                MIN(GET_CYCLE_CEIL(C.tXSR), (u32)0x3fe));
      WRITE_PARAM_ALL_REG(table, emc_txsrdll,             MIN(GET_CYCLE_CEIL(C.tXSR), (u32)0x3fe));
@@ -219,7 +220,7 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
      WRITE_PARAM_ALL_REG(table, emc_tpd,                 GET_CYCLE_CEIL(C.tCKE));
      WRITE_PARAM_ALL_REG(table, emc_tfaw,                GET_CYCLE_CEIL(C.tFAW));
      WRITE_PARAM_ALL_REG(table, emc_trpab,               GET_CYCLE_CEIL(C.tRPab));
-    //WRITE_PARAM_ALL_REG(table, emc_tclkstable,          GET_CYCLE_CEIL(C.tCKCKEH));
+     //WRITE_PARAM_ALL_REG(table, emc_tclkstable,          GET_CYCLE_CEIL(tCKCKEH));
      WRITE_PARAM_ALL_REG(table, emc_tclkstop,            GET_CYCLE_CEIL(C.tCKE) + 8);
      WRITE_PARAM_ALL_REG(table, emc_trefbw,              REFBW);
  
@@ -324,9 +325,9 @@ void MemMtcTableAutoAdjust(MarikoMtcTable* table, const MarikoMtcTable* ref) {
      //table->dram_timings.rl = 32;
  
      table->emc_cfg_2 = 0x0011083d;
-}
+ }
  
-void MemMtcTableCustomAdjust(MarikoMtcTable* table) {
+ void MemMtcTableCustomAdjust(MarikoMtcTable* table) {
      if (C.mtcConf != CUSTOM_ADJ_ALL)
          return;
         
@@ -357,9 +358,9 @@ void MemMtcTableCustomAdjust(MarikoMtcTable* table) {
      DA_COVERS |= (R_COVER << 8); //RCD_R COVER
      DA_COVERS |= (W_COVER << 16); //RCD_W COVER
      WRITE_PARAM_BURST_MC_REG(table, mc_emem_arb_da_covers,       DA_COVERS);
-}
+ }
  
-void MemMtcPllmbDivisor(MarikoMtcTable* table) {
+ void MemMtcPllmbDivisor(MarikoMtcTable* table) {
      // Calculate DIVM and DIVN (clock divisors)
      // Common PLL oscillator is 38.4 MHz
      // PLLMB_OUT = 38.4 MHz / PLLLMB_DIVM * PLLMB_DIVN
@@ -386,9 +387,9 @@ void MemMtcPllmbDivisor(MarikoMtcTable* table) {
  
      table->pllmb_divm = divm;
      table->pllmb_divn = divn;
-}
+ }
  
-Result MemFreqMtcTable(u32* ptr) {
+ Result MemFreqMtcTable(u32* ptr) {
      u32 khz_list[] = { 1600000, 1331200, 204000 };
      u32 khz_list_size = sizeof(khz_list) / sizeof(u32);
  
@@ -426,9 +427,9 @@ Result MemFreqMtcTable(u32* ptr) {
      // }
  
      R_SUCCEED();
-}
+ }
  
-Result MemFreqDvbTable(u32* ptr) {
+ Result MemFreqDvbTable(u32* ptr) {
      emc_dvb_dvfs_table_t* default_end  = reinterpret_cast<emc_dvb_dvfs_table_t *>(ptr);
      emc_dvb_dvfs_table_t* new_start = default_end + 1;
  
@@ -471,17 +472,17 @@ Result MemFreqDvbTable(u32* ptr) {
      */ 
  
      R_SUCCEED();
-}
+ }
  
-Result MemFreqMax(u32* ptr) {
+ Result MemFreqMax(u32* ptr) {
      if (C.marikoEmcMaxClock <= EmcClkOSLimit)
          R_SKIP();
  
      PATCH_OFFSET(ptr, C.marikoEmcMaxClock);
      R_SUCCEED();
-}
+ }
  
-Result I2cSet_U8(I2cDevice dev, u8 reg, u8 val) {
+ Result I2cSet_U8(I2cDevice dev, u8 reg, u8 val) {
      struct {
          u8 reg;
          u8 val;
@@ -497,9 +498,9 @@ Result I2cSet_U8(I2cDevice dev, u8 reg, u8 val) {
      res = i2csessionSendAuto(&_session, &cmd, sizeof(cmd), I2cTransactionOption_All);
      i2csessionClose(&_session);
      return res;
-}
+ }
  
-Result EmcVddqVolt(u32* ptr) {
+ Result EmcVddqVolt(u32* ptr) {
      regulator* entry = reinterpret_cast<regulator *>(reinterpret_cast<u8 *>(ptr) - offsetof(regulator, type_2_3.default_uv));
  
      constexpr u32 uv_step = 5'000;
@@ -529,9 +530,9 @@ Result EmcVddqVolt(u32* ptr) {
      i2cExit();
  
      R_SUCCEED();
-}
+ }
  
-void Patch(uintptr_t mapped_nso, size_t nso_size) {
+ void Patch(uintptr_t mapped_nso, size_t nso_size) {
      u32 CpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(CpuCvbTableDefault)->freq);
      u32 GpuCvbDefaultMaxFreq = static_cast<u32>(GetDvfsTableLastEntry(GpuCvbTableDefault)->freq);
  
@@ -567,6 +568,6 @@ void Patch(uintptr_t mapped_nso, size_t nso_size) {
          if (R_FAILED(entry.CheckResult()))
              CRASH(entry.description);
      }
-}
+ }
  
-}
+ }