Clean up, replaced 2600Mhz 2133bl with correct file, added scripts.
This commit is contained in:
Lightos1
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timings.zip
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timings.zip
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528
timings/Mariko/AA/1600/emc/1600_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/1600_emc.txt
Normal file
@@ -0,0 +1,528 @@
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Dumping EMC registers from BASE=0x7001B000
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-----------------------------------
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EMC_INTSTATUS_0 = 0x00000030
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EMC_INTMASK_0 = 0x00000000
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EMC_DBG_0 = 0x01000C00
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EMC_CFG_0 = 0xF3200000
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EMC_ADR_CFG_0 = 0x00000000
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EMC_REFCTRL_0 = 0x80000002
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EMC_PIN_0 = 0x00003101
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EMC_TIMING_CONTROL_0 = 0x00000001
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EMC_RC_0 = 0x00000060
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EMC_RFC_0 = 0x000001C0
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EMC_RAS_0 = 0x00000044
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EMC_RP_0 = 0x0000001D
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EMC_R2W_0 = 0x00000029
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EMC_W2R_0 = 0x00000021
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EMC_R2P_0 = 0x0000000C
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EMC_W2P_0 = 0x0000002D
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EMC_RD_RCD_0 = 0x0000001D
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EMC_WR_RCD_0 = 0x0000001D
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EMC_RRD_0 = 0x00000010
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EMC_REXT_0 = 0x00000017
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EMC_WDV_0 = 0x0000000E
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EMC_QUSE_0 = 0x00000024
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EMC_QRST_0 = 0x0006000C
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EMC_QSAFE_0 = 0x00000033
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EMC_RDV_0 = 0x00000039
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EMC_REFRESH_0 = 0x00001820
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EMC_BURST_REFRESH_NUM_0 = 0x00000000
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EMC_PDEX2WR_0 = 0x00000010
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EMC_PDEX2RD_0 = 0x00000010
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EMC_PCHG2PDEN_0 = 0x00000003
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EMC_ACT2PDEN_0 = 0x00000017
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EMC_AR2PDEN_0 = 0x00000003
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EMC_RW2PDEN_0 = 0x00000038
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EMC_TXSR_0 = 0x000001CC
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EMC_TCKE_0 = 0x0000000D
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EMC_TFAW_0 = 0x00000040
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EMC_TRPAB_0 = 0x00000022
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EMC_TCLKSTABLE_0 = 0x00000004
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EMC_TCLKSTOP_0 = 0x00000014
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EMC_TREFBW_0 = 0x00001860
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EMC_TPPD_0 = 0x00000004
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EMC_ODT_WRITE_0 = 0x00000000
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EMC_PDEX2MRR_0 = 0x0000002E
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EMC_WEXT_0 = 0x00000016
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EMC_RFC_SLR_0 = 0x00000000
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EMC_MRS_WAIT_CNT2_0 = 0x01900017
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EMC_MRS_WAIT_CNT_0 = 0x0640002F
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EMC_MRS_0 = 0x00000000
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EMC_EMRS_0 = 0x00000000
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EMC_REF_0 = 0x80000000
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EMC_PRE_0 = 0x00000000
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EMC_NOP_0 = 0x00000000
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EMC_SELF_REF_0 = 0x00000000
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EMC_DPD_0 = 0x00000000
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EMC_MRW_0 = 0x00170040
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EMC_MRR_0 = 0x8012C0DC
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EMC_CMDQ_0 = 0x10004408
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EMC_MC2EMCQ_0 = 0x06000404
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EMC_FBIO_SPARE_0 = 0x00000012
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EMC_FBIO_CFG5_0 = 0x9160A00D
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EMC_FBIO_CFG6_0 = 0x00001010
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EMC_PDEX2CKE_0 = 0x00000002
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EMC_CKE2PDEN_0 = 0x0000000E
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EMC_CFG_RSV_0 = 0xFF00FF00
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EMC_ACPD_CONTROL_0 = 0x00000000
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EMC_MPC_0 = 0x0000004B
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EMC_EMRS2_0 = 0x00000000
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EMC_EMRS3_0 = 0x00000000
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EMC_MRW2_0 = 0x8802002D
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EMC_MRW3_0 = 0x8C0D0000
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EMC_MRW4_0 = 0xC0000000
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EMC_CLKEN_OVERRIDE_0 = 0x00000000
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EMC_R2R_0 = 0x00000000
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EMC_W2W_0 = 0x00000000
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EMC_EINPUT_0 = 0x00000014
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EMC_EINPUT_DURATION_0 = 0x0000001C
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EMC_PUTERM_EXTRA_0 = 0x00000001
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EMC_TCKESR_0 = 0x00000018
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EMC_TPD_0 = 0x0000000C
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EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
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EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
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EMC_AUTO_CAL_STATUS_0 = 0x1D190000
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EMC_REQ_CTRL_0 = 0x00000000
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EMC_EMC_STATUS_0 = 0x0B430035
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EMC_CFG_2_0 = 0x00110835
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EMC_CFG_DIG_DLL_0 = 0x002C03A9
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EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
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EMC_DIG_DLL_STATUS_0 = 0x00000004
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EMC_CFG_DIG_DLL_1_0 = 0x000F3701
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EMC_RDV_MASK_0 = 0x0000003B
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EMC_WDV_MASK_0 = 0x0000000E
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EMC_RDV_EARLY_MASK_0 = 0x00000039
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EMC_RDV_EARLY_0 = 0x00000037
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EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
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EMC_ZCAL_INTERVAL_0 = 0x00064000
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EMC_ZCAL_WAIT_CNT_0 = 0x00310640
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EMC_ZCAL_MRW_CMD_0 = 0x8051004F
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EMC_ZQ_CAL_0 = 0x80000002
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EMC_XM2COMPPADCTRL3_0 = 0x00901000
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EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
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EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
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EMC_XM2COMPPADCTRL_0 = 0x00000030
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EMC_FDPD_CTRL_DQ_0 = 0x8020221F
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EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
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EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
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EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
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EMC_SCRATCH0_0 = 0x00000000
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EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
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EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
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EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
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EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
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EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
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EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
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EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
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EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
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EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
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EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
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EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
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EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
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EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
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EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
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EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
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EMC_TR_TIMING_0_0 = 0x01186190
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EMC_TR_CTRL_0_0 = 0x00000020
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EMC_TR_CTRL_1_0 = 0x00000000
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EMC_SWITCH_BACK_CTRL_0 = 0x00000001
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EMC_TR_RDV_0 = 0x00000039
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EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
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EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
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EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
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EMC_AUTO_CAL_ = 0x3F1F070A
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EMC_SEL_DPD_CTRL_0 = 0x0004000C
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EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000608
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EMC_DYN_SELF_REF_CONTROL_0 = 0x8000308C
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EMC_TXSRDLL_0 = 0x000001CC
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EMC_CCFIFO_ADDR_0 = 0x80000000
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EMC_CCFIFO_DATA_0 = 0x00000000
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EMC_CCFIFO_STATUS_0 = 0x00000000
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EMC_TR_QPOP_0 = 0x0000002B
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EMC_TR_RDV_MASK_0 = 0x0000003B
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EMC_TR_QSAFE_0 = 0x00000033
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EMC_TR_QRST_0 = 0x0006000C
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EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
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EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
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EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
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EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
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EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
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EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
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EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
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EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
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EMC_ISSUE_QRST_0 = 0x00000000
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EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
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EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
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EMC_PMC_SCRATCH3_0 = 0x4036D71F
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EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
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EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
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EMC_TR_DVFS_0 = 0x00000000
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EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00309
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EMC_IBDLY_0 = 0x1000001C
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EMC_OBDLY_0 = 0x10000002
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EMC_TXDSRVTTGEN_0 = 0x00000000
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EMC_WE_DURATION_0 = 0x0000000E
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EMC_WS_DURATION_0 = 0x00000008
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EMC_WEV_0 = 0x0000000A
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EMC_WSV_0 = 0x0000000C
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EMC_CFG_3_0 = 0x00000040
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EMC_MRW5_0 = 0x00000000
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EMC_MRW6_0 = 0x8803F1F1
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EMC_MRW7_0 = 0xC803F1F1
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EMC_MRW8_0 = 0x880B0606
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EMC_MRW9_0 = 0x8C0E5D5D
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EMC_MRW10_0 = 0x880C5D5D
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EMC_MRW11_0 = 0xC80C5D5D
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EMC_MRW12_0 = 0x880E0B09
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EMC_MRW13_0 = 0xC80E0000
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EMC_MRW14_0 = 0x88161414
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EMC_MRW15_0 = 0xC8161414
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EMC_CFG_SYNC_0 = 0x00000001
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EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
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EMC_WDV_CHK_0 = 0x00000006
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EMC_CFG_PIPE_2_0 = 0x00000000
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EMC_CFG_PIPE_CLK_0 = 0x00000000
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EMC_CFG_PIPE_1_0 = 0x0FFF0000
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EMC_CFG_PIPE_0 = 0x0FFF0000
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EMC_QPOP_0 = 0x0000002B
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EMC_QUSE_WIDTH_0 = 0x00000008
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EMC_PUTERM_WIDTH_0 = 0x80000000
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EMC_BGBIAS_CTL0_0 = 0x00000000
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EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
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EMC_XM2COMPPADCTRL2_0 = 0x16001000
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EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
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EMC_REFCTRL2_0 = 0x00000000
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EMC_FBIO_CFG7_0 = 0x00003BFF
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EMC_DATA_BRLSHFT_0_0 = 0x00000249
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EMC_DATA_BRLSHFT_1_0 = 0x00000000
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EMC_RFCPB_0 = 0x000000E0
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EMC_DQS_BRLSHFT_0_0 = 0x00000000
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EMC_DQS_BRLSHFT_1_0 = 0x00000000
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EMC_CMD_BRLSHFT_0_0 = 0x00000000
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EMC_CMD_BRLSHFT_1_0 = 0x00000000
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EMC_CMD_BRLSHFT_2_0 = 0x00000012
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EMC_CMD_BRLSHFT_3_0 = 0x00000012
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EMC_QUSE_BRLSHFT_0_0 = 0x00000000
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EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
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EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
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EMC_QUSE_BRLSHFT_1_0 = 0x00000000
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EMC_QUSE_BRLSHFT_2_0 = 0x00000000
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EMC_CCDMW_0 = 0x00000020
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EMC_QUSE_BRLSHFT_3_0 = 0x00000000
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EMC_FBIO_CFG8_0 = 0x0CF30000
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EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
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EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
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EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
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EMC_PROTOBIST_MISC_0 = 0x00000000
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EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
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EMC_PROTOBIST_WDATA_UPPER_0 = 0xC4204002
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EMC_PROTOBIST_RDATA_0 = 0x00000000
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EMC_DLL_CFG_0_0 = 0x1F136120
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EMC_DLL_CFG_1_0 = 0x00012014
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EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
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EMC_CFG_UPDATE_0 = 0x70000301
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EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x000E0006
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210027
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200027
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002A
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000B
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020007
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00080000
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000005
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220023
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0022
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||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x001F0022
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x2E2F2F2F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2D2B292D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2B2E2C2C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x32323333
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x2F313228
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x252C2D2B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2A292623
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x2C2F2D2E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353134
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2F2E2A2B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2C2B2D29
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03050505
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050205
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040306
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050504
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232527
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27272325
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x070A070A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/1866_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/1866_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000070
|
||||||
|
EMC_RFC_0 = 0x0000020B
|
||||||
|
EMC_RAS_0 = 0x0000004F
|
||||||
|
EMC_RP_0 = 0x00000022
|
||||||
|
EMC_R2W_0 = 0x0000002A
|
||||||
|
EMC_W2R_0 = 0x00000022
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x00000022
|
||||||
|
EMC_WR_RCD_0 = 0x00000022
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001A
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000024
|
||||||
|
EMC_QRST_0 = 0x00070008
|
||||||
|
EMC_QSAFE_0 = 0x00000034
|
||||||
|
EMC_RDV_0 = 0x0000003A
|
||||||
|
EMC_REFRESH_0 = 0x00001C2D
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000013
|
||||||
|
EMC_PDEX2RD_0 = 0x00000013
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000001B
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x00000039
|
||||||
|
EMC_TXSR_0 = 0x00000219
|
||||||
|
EMC_TCKE_0 = 0x00000010
|
||||||
|
EMC_TFAW_0 = 0x0000004B
|
||||||
|
EMC_TRPAB_0 = 0x00000028
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x00000017
|
||||||
|
EMC_TREFBW_0 = 0x00001C6D
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000037
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x01D3001B
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x074A0030
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80122A40
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000010
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000011
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000020
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000001C
|
||||||
|
EMC_TPD_0 = 0x0000000E
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003C
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003A
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000038
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x0039074A
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011861D3
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003A
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000070B
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80003873
|
||||||
|
EMC_TXSRDLL_0 = 0x00000219
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002C
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003C
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000034
|
||||||
|
EMC_TR_QRST_0 = 0x00070008
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030A
|
||||||
|
EMC_IBDLY_0 = 0x1000001B
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0B
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002C
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x00000009
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000106
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0009000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00100007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230027
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0009000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00100007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00090000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00090000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001F0022
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00200023
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x393A3A3A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x39353337
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000038
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x37393737
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x35393235
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000034
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x3E3C3E3E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x3A3C3F32
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x30363736
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x35342F2D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000032
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x373B393B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x383B3838
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x37353737
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000036
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x42424341
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x3F413D3F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000003E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3A393436
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x37353833
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000035
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04060506
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05070307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060809
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06060800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050706
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040105
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02020303
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020101
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040203
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03030200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242526
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x2B262822
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000F000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00100010
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080F
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000403A5
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2133_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2133_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000080
|
||||||
|
EMC_RFC_0 = 0x00000256
|
||||||
|
EMC_RAS_0 = 0x0000005A
|
||||||
|
EMC_RP_0 = 0x00000027
|
||||||
|
EMC_R2W_0 = 0x0000002B
|
||||||
|
EMC_W2R_0 = 0x00000025
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x00000027
|
||||||
|
EMC_WR_RCD_0 = 0x00000027
|
||||||
|
EMC_RRD_0 = 0x00000010
|
||||||
|
EMC_REXT_0 = 0x0000001A
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000024
|
||||||
|
EMC_QRST_0 = 0x00070005
|
||||||
|
EMC_QSAFE_0 = 0x00000035
|
||||||
|
EMC_RDV_0 = 0x0000003B
|
||||||
|
EMC_REFRESH_0 = 0x0000203F
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000016
|
||||||
|
EMC_PDEX2RD_0 = 0x00000016
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000001E
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x00000039
|
||||||
|
EMC_TXSR_0 = 0x00000266
|
||||||
|
EMC_TCKE_0 = 0x00000012
|
||||||
|
EMC_TFAW_0 = 0x00000040
|
||||||
|
EMC_TRPAB_0 = 0x0000002D
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001A
|
||||||
|
EMC_TREFBW_0 = 0x0000207F
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000003F
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x0216001E
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80040101
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000013
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000E
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000020
|
||||||
|
EMC_TPD_0 = 0x00000010
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003D
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003B
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000039
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186216
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003B
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000080F
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004062
|
||||||
|
EMC_TXSRDLL_0 = 0x00000266
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002D
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003D
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000035
|
||||||
|
EMC_TR_QRST_0 = 0x00070005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||||
|
EMC_IBDLY_0 = 0x1000001B
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0E0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002D
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000012B
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000A0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000A0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00250025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x45454546
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x43403E43
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000043
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x42444241
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3F443C3F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x49474A49
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x4548493C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000047
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x38404140
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3E3D3934
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050304
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x00060102
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x413F4041
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4141413E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0E0E0F0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0B0D080B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x44433E40
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x413E433D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03070706
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x060A0409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0708090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080406
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050507
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050205
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06020401
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27262629
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27292629
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004042B
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2166_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2166_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000082
|
||||||
|
EMC_RFC_0 = 0x0000025F
|
||||||
|
EMC_RAS_0 = 0x0000005B
|
||||||
|
EMC_RP_0 = 0x00000027
|
||||||
|
EMC_R2W_0 = 0x0000002B
|
||||||
|
EMC_W2R_0 = 0x00000025
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x00000027
|
||||||
|
EMC_WR_RCD_0 = 0x00000027
|
||||||
|
EMC_RRD_0 = 0x00000011
|
||||||
|
EMC_REXT_0 = 0x00000019
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000025
|
||||||
|
EMC_QRST_0 = 0x00070006
|
||||||
|
EMC_QSAFE_0 = 0x00000036
|
||||||
|
EMC_RDV_0 = 0x0000003C
|
||||||
|
EMC_REFRESH_0 = 0x000020BF
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000017
|
||||||
|
EMC_PDEX2RD_0 = 0x00000017
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000001F
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x00000039
|
||||||
|
EMC_TXSR_0 = 0x0000026F
|
||||||
|
EMC_TCKE_0 = 0x00000013
|
||||||
|
EMC_TFAW_0 = 0x00000041
|
||||||
|
EMC_TRPAB_0 = 0x0000002E
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001A
|
||||||
|
EMC_TREFBW_0 = 0x000020FF
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000040
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x021E001F
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012AFC4
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000013
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000F
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000021
|
||||||
|
EMC_TPD_0 = 0x00000011
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003A
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118621E
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003C
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000082F
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000415D
|
||||||
|
EMC_TXSRDLL_0 = 0x0000026F
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002E
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000036
|
||||||
|
EMC_TR_QRST_0 = 0x00070006
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||||
|
EMC_IBDLY_0 = 0x1000001C
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002E
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000130
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x8C200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200023
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x47474747
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x45413F45
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000045
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x44464342
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x41463E40
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x49484A4A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x46484A3C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000047
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x39414242
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x403E3A36
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x01060306
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060202
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x42414142
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4241423F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000041
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0E0F100E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0C0E090C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x46443F41
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4340443D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04070707
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090309
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0807090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070908
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050101
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01030002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06040302
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x04020100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25232828
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29282623
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004043B
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2200_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2200_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000084
|
||||||
|
EMC_RFC_0 = 0x00000268
|
||||||
|
EMC_RAS_0 = 0x0000005D
|
||||||
|
EMC_RP_0 = 0x00000028
|
||||||
|
EMC_R2W_0 = 0x0000002B
|
||||||
|
EMC_W2R_0 = 0x00000025
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x00000028
|
||||||
|
EMC_WR_RCD_0 = 0x00000028
|
||||||
|
EMC_RRD_0 = 0x00000011
|
||||||
|
EMC_REXT_0 = 0x00000019
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000025
|
||||||
|
EMC_QRST_0 = 0x00070006
|
||||||
|
EMC_QSAFE_0 = 0x00000036
|
||||||
|
EMC_RDV_0 = 0x0000003C
|
||||||
|
EMC_REFRESH_0 = 0x00002144
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000017
|
||||||
|
EMC_PDEX2RD_0 = 0x00000017
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000001F
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x00000039
|
||||||
|
EMC_TXSR_0 = 0x00000279
|
||||||
|
EMC_TCKE_0 = 0x00000013
|
||||||
|
EMC_TFAW_0 = 0x00000042
|
||||||
|
EMC_TRPAB_0 = 0x0000002F
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001A
|
||||||
|
EMC_TREFBW_0 = 0x00002184
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000041
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x0226001F
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80129FB3
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000013
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000F
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000021
|
||||||
|
EMC_TPD_0 = 0x00000011
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003A
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186226
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003C
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000851
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000425F
|
||||||
|
EMC_TXSRDLL_0 = 0x00000279
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002E
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000036
|
||||||
|
EMC_TR_QRST_0 = 0x00070006
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x1000001C
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D0B
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002E
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x0000024A
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000134
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x8C200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0021002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200023
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x07080707
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06020005
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x46474543
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x42473F41
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4B494C4C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x474A4B3D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3B434443
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x41403B37
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x03080507
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x04090405
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020300
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1111120F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0E0F0B0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x47454042
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4441453F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000041
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04070807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0807090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060908
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020201
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252729
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27272624
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004044C
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0B
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2233_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2233_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000086
|
||||||
|
EMC_RFC_0 = 0x00000272
|
||||||
|
EMC_RAS_0 = 0x0000005E
|
||||||
|
EMC_RP_0 = 0x00000029
|
||||||
|
EMC_R2W_0 = 0x0000002B
|
||||||
|
EMC_W2R_0 = 0x00000026
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x00000029
|
||||||
|
EMC_WR_RCD_0 = 0x00000029
|
||||||
|
EMC_RRD_0 = 0x00000011
|
||||||
|
EMC_REXT_0 = 0x00000019
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000025
|
||||||
|
EMC_QRST_0 = 0x00070005
|
||||||
|
EMC_QSAFE_0 = 0x00000036
|
||||||
|
EMC_RDV_0 = 0x0000003C
|
||||||
|
EMC_REFRESH_0 = 0x000021C5
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000017
|
||||||
|
EMC_PDEX2RD_0 = 0x00000017
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000020
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x00000282
|
||||||
|
EMC_TCKE_0 = 0x00000013
|
||||||
|
EMC_TFAW_0 = 0x00000043
|
||||||
|
EMC_TRPAB_0 = 0x0000002F
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001A
|
||||||
|
EMC_TREFBW_0 = 0x00002205
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000042
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x022F0020
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80040101
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000013
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000E
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000022
|
||||||
|
EMC_TPD_0 = 0x00000011
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003A
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118622F
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003C
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000871
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000435A
|
||||||
|
EMC_TXSRDLL_0 = 0x00000282
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002E
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000036
|
||||||
|
EMC_TR_QRST_0 = 0x00070005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x1000001C
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002E
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000252
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000139
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210023
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x08090809
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06030106
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06080605
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04080103
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4D4B4E4E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x494D4E3F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000004A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3B444544
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x42413C38
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x05090608
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x05090505
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000022
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05030405
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x11131310
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0F110C0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08080104
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020601
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080806
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050908
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050206
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020300
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2725272A
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282625
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004045D
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2266_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2266_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000088
|
||||||
|
EMC_RFC_0 = 0x0000027B
|
||||||
|
EMC_RAS_0 = 0x00000060
|
||||||
|
EMC_RP_0 = 0x00000029
|
||||||
|
EMC_R2W_0 = 0x0000002B
|
||||||
|
EMC_W2R_0 = 0x00000026
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x00000029
|
||||||
|
EMC_WR_RCD_0 = 0x00000029
|
||||||
|
EMC_RRD_0 = 0x00000011
|
||||||
|
EMC_REXT_0 = 0x0000001A
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000025
|
||||||
|
EMC_QRST_0 = 0x00070005
|
||||||
|
EMC_QSAFE_0 = 0x00000036
|
||||||
|
EMC_RDV_0 = 0x0000003C
|
||||||
|
EMC_REFRESH_0 = 0x00002245
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000017
|
||||||
|
EMC_PDEX2RD_0 = 0x00000017
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000020
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x0000028C
|
||||||
|
EMC_TCKE_0 = 0x00000013
|
||||||
|
EMC_TFAW_0 = 0x00000044
|
||||||
|
EMC_TRPAB_0 = 0x00000030
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001B
|
||||||
|
EMC_TREFBW_0 = 0x00002285
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000042
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02370020
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0031
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x88010054
|
||||||
|
EMC_MRR_0 = 0x8012768A
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000014
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00C0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000E
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000022
|
||||||
|
EMC_TPD_0 = 0x00000011
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003A
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186237
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003C
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000891
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004455
|
||||||
|
EMC_TXSRDLL_0 = 0x0000028C
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002E
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000036
|
||||||
|
EMC_TR_QRST_0 = 0x00070005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x1000001C
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0F0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002E
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000013E
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210023
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0A0B0A0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x08040207
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x07090806
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x040A0203
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0E0C0F0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0E0F00
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3C454745
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2B2A2723
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x050A0709
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x060B0607
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040506
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06050502
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x13141512
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x11120E0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09080305
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040702
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050306
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050504
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x03020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252729
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28282525
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004046D
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0B
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2300_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2300_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000008A
|
||||||
|
EMC_RFC_0 = 0x00000284
|
||||||
|
EMC_RAS_0 = 0x00000061
|
||||||
|
EMC_RP_0 = 0x0000002A
|
||||||
|
EMC_R2W_0 = 0x0000002C
|
||||||
|
EMC_W2R_0 = 0x00000026
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002A
|
||||||
|
EMC_WR_RCD_0 = 0x0000002A
|
||||||
|
EMC_RRD_0 = 0x00000012
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000024
|
||||||
|
EMC_QRST_0 = 0x00070004
|
||||||
|
EMC_QSAFE_0 = 0x00000037
|
||||||
|
EMC_RDV_0 = 0x0000003C
|
||||||
|
EMC_REFRESH_0 = 0x000022CA
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000019
|
||||||
|
EMC_PDEX2RD_0 = 0x00000019
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000021
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x00000296
|
||||||
|
EMC_TCKE_0 = 0x00000014
|
||||||
|
EMC_TFAW_0 = 0x00000045
|
||||||
|
EMC_TRPAB_0 = 0x00000031
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001B
|
||||||
|
EMC_TREFBW_0 = 0x0000230A
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000045
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x023F0021
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80125E72
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000014
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000D
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000023
|
||||||
|
EMC_TPD_0 = 0x00000012
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003A
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118623F
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003C
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008B2
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004558
|
||||||
|
EMC_TXSRDLL_0 = 0x00000296
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002E
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000037
|
||||||
|
EMC_TR_QRST_0 = 0x00070004
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x1000001B
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002E
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000142
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x22004120
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0A0B0C0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0A050309
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090A0807
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060B0305
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0F0E1011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0C0F1002
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3D464746
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x44433E3A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000041
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x070C090B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x070C0708
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x07060704
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x14151613
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x11130F10
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0B0A0406
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08060903
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A0409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060206
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010304
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040504
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252828
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29272726
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2333_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2333_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000008C
|
||||||
|
EMC_RFC_0 = 0x0000028E
|
||||||
|
EMC_RAS_0 = 0x00000062
|
||||||
|
EMC_RP_0 = 0x0000002A
|
||||||
|
EMC_R2W_0 = 0x0000002C
|
||||||
|
EMC_W2R_0 = 0x00000027
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002A
|
||||||
|
EMC_WR_RCD_0 = 0x0000002A
|
||||||
|
EMC_RRD_0 = 0x00000012
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000024
|
||||||
|
EMC_QRST_0 = 0x00070003
|
||||||
|
EMC_QSAFE_0 = 0x00000038
|
||||||
|
EMC_RDV_0 = 0x0000003C
|
||||||
|
EMC_REFRESH_0 = 0x0000234B
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000019
|
||||||
|
EMC_PDEX2RD_0 = 0x00000019
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000021
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x0000029F
|
||||||
|
EMC_TCKE_0 = 0x00000014
|
||||||
|
EMC_TFAW_0 = 0x00000046
|
||||||
|
EMC_TRPAB_0 = 0x00000031
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001B
|
||||||
|
EMC_TREFBW_0 = 0x0000238B
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000045
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02480021
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80124B5F
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000014
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000C
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000023
|
||||||
|
EMC_TPD_0 = 0x00000012
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003C
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003A
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186248
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003C
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008D2
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004653
|
||||||
|
EMC_TXSRDLL_0 = 0x0000029F
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002E
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003E
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000038
|
||||||
|
EMC_TR_QRST_0 = 0x00070003
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x1000001B
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0E09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002E
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000147
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0C0B0C0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x09060509
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0B0A09
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x080C0506
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x100F1212
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0D101102
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3F484948
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4544403B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000043
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x080E0A0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x090E0909
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x08070808
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x09080805
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x16161815
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x13151012
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0C0B0507
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08060A04
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03040506
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x040B030B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03090005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06060700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060808
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050205
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040306
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020406
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03030003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624292A
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29262529
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004048F
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2366_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2366_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000008E
|
||||||
|
EMC_RFC_0 = 0x00000297
|
||||||
|
EMC_RAS_0 = 0x00000064
|
||||||
|
EMC_RP_0 = 0x0000002B
|
||||||
|
EMC_R2W_0 = 0x0000002C
|
||||||
|
EMC_W2R_0 = 0x00000027
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002B
|
||||||
|
EMC_WR_RCD_0 = 0x0000002B
|
||||||
|
EMC_RRD_0 = 0x00000012
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000026
|
||||||
|
EMC_QRST_0 = 0x0006000C
|
||||||
|
EMC_QSAFE_0 = 0x00000037
|
||||||
|
EMC_RDV_0 = 0x0000003D
|
||||||
|
EMC_REFRESH_0 = 0x000023CB
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000019
|
||||||
|
EMC_PDEX2RD_0 = 0x00000019
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000022
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002A9
|
||||||
|
EMC_TCKE_0 = 0x00000014
|
||||||
|
EMC_TFAW_0 = 0x00000047
|
||||||
|
EMC_TRPAB_0 = 0x00000032
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001C
|
||||||
|
EMC_TREFBW_0 = 0x0000240B
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000046
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02500022
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80122A41
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000015
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000E
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000024
|
||||||
|
EMC_TPD_0 = 0x00000012
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430021
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003B
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186250
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003D
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008F2
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000474E
|
||||||
|
EMC_TXSRDLL_0 = 0x000002A9
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002F
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000037
|
||||||
|
EMC_TR_QRST_0 = 0x00070005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x1000001D
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0E0B
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002F
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000014C
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A00A010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00150009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00150009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0D0D0D0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0B07050B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0C0D0B0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x090E0608
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x11111413
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0F121304
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x404A4A49
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4746413C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000044
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0A0E0C0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0A0F0A0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0A080A0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0A090A06
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x17181916
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x14161213
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F0C0708
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0B070C05
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070306
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010405
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05030104
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020303
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26242429
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262325
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004049F
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0B
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2400_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2400_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000090
|
||||||
|
EMC_RFC_0 = 0x000002A0
|
||||||
|
EMC_RAS_0 = 0x00000065
|
||||||
|
EMC_RP_0 = 0x0000002C
|
||||||
|
EMC_R2W_0 = 0x0000002C
|
||||||
|
EMC_W2R_0 = 0x00000027
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002C
|
||||||
|
EMC_WR_RCD_0 = 0x0000002C
|
||||||
|
EMC_RRD_0 = 0x00000012
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000026
|
||||||
|
EMC_QRST_0 = 0x00070005
|
||||||
|
EMC_QSAFE_0 = 0x00000037
|
||||||
|
EMC_RDV_0 = 0x0000003D
|
||||||
|
EMC_REFRESH_0 = 0x00002450
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000019
|
||||||
|
EMC_PDEX2RD_0 = 0x00000019
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000022
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002B2
|
||||||
|
EMC_TCKE_0 = 0x00000014
|
||||||
|
EMC_TFAW_0 = 0x00000048
|
||||||
|
EMC_TRPAB_0 = 0x00000033
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001C
|
||||||
|
EMC_TREFBW_0 = 0x00002490
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000047
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02580022
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80122D40
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000015
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000E
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000024
|
||||||
|
EMC_TPD_0 = 0x00000012
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003B
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186258
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003D
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000914
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004850
|
||||||
|
EMC_TXSRDLL_0 = 0x000002B2
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002F
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000037
|
||||||
|
EMC_TR_QRST_0 = 0x00070005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x1000001D
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0E0C
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002F
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000150
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0E100F0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0E0A080D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0D0F0C0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x12121514
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x10131405
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2D2C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4747423D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000045
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0A100C0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0A090B0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0B0A0A08
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x18191A17
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x16171315
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F0D080A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0B090C07
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090907
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B030B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060907
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010405
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030302
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050206
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624292A
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26292628
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000404B0
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0C
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2433_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2433_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000092
|
||||||
|
EMC_RFC_0 = 0x000002AA
|
||||||
|
EMC_RAS_0 = 0x00000067
|
||||||
|
EMC_RP_0 = 0x0000002C
|
||||||
|
EMC_R2W_0 = 0x0000002C
|
||||||
|
EMC_W2R_0 = 0x00000028
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002C
|
||||||
|
EMC_WR_RCD_0 = 0x0000002C
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000026
|
||||||
|
EMC_QRST_0 = 0x00070004
|
||||||
|
EMC_QSAFE_0 = 0x00000038
|
||||||
|
EMC_RDV_0 = 0x0000003D
|
||||||
|
EMC_REFRESH_0 = 0x000024D1
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001A
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001A
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000023
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002BC
|
||||||
|
EMC_TCKE_0 = 0x00000015
|
||||||
|
EMC_TFAW_0 = 0x00000049
|
||||||
|
EMC_TRPAB_0 = 0x00000034
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001C
|
||||||
|
EMC_TREFBW_0 = 0x00002511
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000048
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02610023
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012283F
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000015
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000D
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000025
|
||||||
|
EMC_TPD_0 = 0x00000013
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003B
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186261
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000000
|
||||||
|
EMC_TR_RDV_0 = 0x0000003D
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F070A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000934
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000494B
|
||||||
|
EMC_TXSRDLL_0 = 0x000002BC
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002F
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000038
|
||||||
|
EMC_TR_QRST_0 = 0x00070004
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x1000001D
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D0B
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002F
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000155
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x10111010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0E0A080E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0E100E0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0B10080A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x14131516
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x10131505
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x414B4D4B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4848433E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000046
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0B100D0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0B100B0B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0C0A0C0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1A1A1C18
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x16181416
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x110E090A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0D0A0E08
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05080807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x040B040B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02080006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080406
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020504
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030504
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27242927
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282729
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x00000000
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2466_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2466_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000094
|
||||||
|
EMC_RFC_0 = 0x000002B3
|
||||||
|
EMC_RAS_0 = 0x00000068
|
||||||
|
EMC_RP_0 = 0x0000002D
|
||||||
|
EMC_R2W_0 = 0x0000002C
|
||||||
|
EMC_W2R_0 = 0x00000028
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002D
|
||||||
|
EMC_WR_RCD_0 = 0x0000002D
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000026
|
||||||
|
EMC_QRST_0 = 0x00070004
|
||||||
|
EMC_QSAFE_0 = 0x00000038
|
||||||
|
EMC_RDV_0 = 0x0000003D
|
||||||
|
EMC_REFRESH_0 = 0x00002551
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001A
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001A
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000023
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002C5
|
||||||
|
EMC_TCKE_0 = 0x00000015
|
||||||
|
EMC_TFAW_0 = 0x0000004A
|
||||||
|
EMC_TRPAB_0 = 0x00000034
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001C
|
||||||
|
EMC_TREFBW_0 = 0x00002591
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000049
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02690023
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80120215
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000015
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000D
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000001C
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000025
|
||||||
|
EMC_TPD_0 = 0x00000013
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430021
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003B
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186190
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003D
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000954
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004A46
|
||||||
|
EMC_TXSRDLL_0 = 0x000002C5
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002F
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000038
|
||||||
|
EMC_TR_QRST_0 = 0x00070004
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x1000001D
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D0C
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002B
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000015A
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xCC200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x11131011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2E2B292D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x10120F0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x20221E20
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x15141616
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x11151607
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x434C4D4C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4A49443F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000047
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0C110E10
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0C110C0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0E0C0E0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0D0D0E0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1A1A1C19
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x171A1517
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x12100A0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0E0C0F08
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080906
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B040B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03090006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A08
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020404
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07030403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030300
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232628
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28292726
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000404D1
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0C
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2500_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2500_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000096
|
||||||
|
EMC_RFC_0 = 0x000002BC
|
||||||
|
EMC_RAS_0 = 0x00000069
|
||||||
|
EMC_RP_0 = 0x0000002D
|
||||||
|
EMC_R2W_0 = 0x0000002D
|
||||||
|
EMC_W2R_0 = 0x00000028
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002D
|
||||||
|
EMC_WR_RCD_0 = 0x0000002D
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001A
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000025
|
||||||
|
EMC_QRST_0 = 0x00070003
|
||||||
|
EMC_QSAFE_0 = 0x00000039
|
||||||
|
EMC_RDV_0 = 0x0000003D
|
||||||
|
EMC_REFRESH_0 = 0x000025D6
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001A
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001A
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000023
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002CF
|
||||||
|
EMC_TCKE_0 = 0x00000015
|
||||||
|
EMC_TFAW_0 = 0x0000004B
|
||||||
|
EMC_TRPAB_0 = 0x00000035
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001D
|
||||||
|
EMC_TREFBW_0 = 0x00002616
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000049
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02710023
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012F002
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000016
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000C
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000028
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000026
|
||||||
|
EMC_TPD_0 = 0x00000013
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003B
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186271
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003D
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000975
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004B49
|
||||||
|
EMC_TXSRDLL_0 = 0x000002CF
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002F
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000039
|
||||||
|
EMC_TR_QRST_0 = 0x00070003
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x1000001C
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0B
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002F
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000015E
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x13141313
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x110C0A10
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x11130F10
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0E130B0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x16151718
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x30323328
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2D2C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0B0A0500
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0E121012
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0E130E0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0F0D0E0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0F0E0E0B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1B1C1E1A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x191A1617
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000016
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x14110B0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0F0C100A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0806090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060A09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040208
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07030403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04030003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07040403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624232A
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26292626
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000404E2
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2533_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2533_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000098
|
||||||
|
EMC_RFC_0 = 0x000002C6
|
||||||
|
EMC_RAS_0 = 0x0000006B
|
||||||
|
EMC_RP_0 = 0x0000002E
|
||||||
|
EMC_R2W_0 = 0x0000002D
|
||||||
|
EMC_W2R_0 = 0x00000029
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002E
|
||||||
|
EMC_WR_RCD_0 = 0x0000002E
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001C
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000025
|
||||||
|
EMC_QRST_0 = 0x00080001
|
||||||
|
EMC_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_RDV_0 = 0x0000003D
|
||||||
|
EMC_REFRESH_0 = 0x00002657
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001A
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001A
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000024
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002D9
|
||||||
|
EMC_TCKE_0 = 0x00000015
|
||||||
|
EMC_TFAW_0 = 0x0000004C
|
||||||
|
EMC_TRPAB_0 = 0x00000036
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001D
|
||||||
|
EMC_TREFBW_0 = 0x00002697
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004A
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x027A0024
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80040101
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000016
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000B
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000026
|
||||||
|
EMC_TPD_0 = 0x00000013
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1E180000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003D
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003B
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118627A
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003D
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000995
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004C44
|
||||||
|
EMC_TXSRDLL_0 = 0x000002D9
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x0000002F
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x0000003F
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_TR_QRST_0 = 0x00080001
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x1000001B
|
||||||
|
EMC_OBDLY_0 = 0x10000000
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002F
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000163
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A00A010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00210029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00060000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0021
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x14151414
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x120E0B11
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x12141111
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0F140C0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1817191A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x15181909
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000016
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x040F100E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2B2A2723
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0F141113
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0F150F11
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x100F1010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x100F100C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1E1E1F1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1A1D181A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000018
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x14120D0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x100E120B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090908
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00040505
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07040000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040706
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040404
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07060207
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08030503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242428
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25292825
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000404F3
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2566_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2566_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000009A
|
||||||
|
EMC_RFC_0 = 0x000002CF
|
||||||
|
EMC_RAS_0 = 0x0000006C
|
||||||
|
EMC_RP_0 = 0x0000002F
|
||||||
|
EMC_R2W_0 = 0x0000002D
|
||||||
|
EMC_W2R_0 = 0x00000029
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002F
|
||||||
|
EMC_WR_RCD_0 = 0x0000002F
|
||||||
|
EMC_RRD_0 = 0x00000014
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000026
|
||||||
|
EMC_QRST_0 = 0x00080002
|
||||||
|
EMC_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_RDV_0 = 0x0000003E
|
||||||
|
EMC_REFRESH_0 = 0x000026D7
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001B
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001B
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000024
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002E2
|
||||||
|
EMC_TCKE_0 = 0x00000016
|
||||||
|
EMC_TFAW_0 = 0x0000004D
|
||||||
|
EMC_TRPAB_0 = 0x00000036
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001D
|
||||||
|
EMC_TREFBW_0 = 0x00002717
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004C
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02820024
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0032
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012D4E6
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000016
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000C
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000027
|
||||||
|
EMC_TPD_0 = 0x00000014
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003C
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186282
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003E
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009B5
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004D3F
|
||||||
|
EMC_TXSRDLL_0 = 0x000002E2
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000030
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_TR_QRST_0 = 0x00080002
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x1000001C
|
||||||
|
EMC_OBDLY_0 = 0x10000000
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000030
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000168
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x15151416
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x130F0C13
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x13161312
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x10160D0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x19191B1B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x16191A0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000017
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0610110F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0D0C0702
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x10151214
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x10161011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x110F1113
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1110110E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1D1F211C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1B1D181A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000018
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x15140E0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x110F120B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A050A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080900
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08060307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27232629
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28262425
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2600_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2600_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000009C
|
||||||
|
EMC_RFC_0 = 0x000002D8
|
||||||
|
EMC_RAS_0 = 0x0000006E
|
||||||
|
EMC_RP_0 = 0x0000002F
|
||||||
|
EMC_R2W_0 = 0x0000002D
|
||||||
|
EMC_W2R_0 = 0x00000029
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x0000002F
|
||||||
|
EMC_WR_RCD_0 = 0x0000002F
|
||||||
|
EMC_RRD_0 = 0x00000014
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000026
|
||||||
|
EMC_QRST_0 = 0x00080002
|
||||||
|
EMC_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_RDV_0 = 0x0000003E
|
||||||
|
EMC_REFRESH_0 = 0x0000275C
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001B
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001B
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000025
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002EC
|
||||||
|
EMC_TCKE_0 = 0x00000016
|
||||||
|
EMC_TFAW_0 = 0x0000004E
|
||||||
|
EMC_TRPAB_0 = 0x00000037
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001E
|
||||||
|
EMC_TREFBW_0 = 0x0000279C
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004C
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x028A0025
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0033
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80040101
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000017
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000C
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000027
|
||||||
|
EMC_TPD_0 = 0x00000014
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003C
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118628A
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003E
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009D7
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004E41
|
||||||
|
EMC_TXSRDLL_0 = 0x000002EC
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000030
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_TR_QRST_0 = 0x00080002
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||||
|
EMC_IBDLY_0 = 0x1000001C
|
||||||
|
EMC_OBDLY_0 = 0x10000000
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0B
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000030
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000016C
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x16161515
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x140F0E14
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x15161414
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x11170E11
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1B1A1C1C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x171A1C0B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000018
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x07111311
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0F0E0903
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x12181416
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x12181213
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000016
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x12111213
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353234
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x17160F11
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02060004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020506
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020203
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020302
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050205
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26232528
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28282627
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040514
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2633_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2633_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000009E
|
||||||
|
EMC_RFC_0 = 0x000002E2
|
||||||
|
EMC_RAS_0 = 0x0000006F
|
||||||
|
EMC_RP_0 = 0x00000030
|
||||||
|
EMC_R2W_0 = 0x0000002D
|
||||||
|
EMC_W2R_0 = 0x0000002A
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x00000030
|
||||||
|
EMC_WR_RCD_0 = 0x00000030
|
||||||
|
EMC_RRD_0 = 0x00000014
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000026
|
||||||
|
EMC_QRST_0 = 0x00080001
|
||||||
|
EMC_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_RDV_0 = 0x0000003E
|
||||||
|
EMC_REFRESH_0 = 0x000027DD
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001B
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001B
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000025
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002F5
|
||||||
|
EMC_TCKE_0 = 0x00000016
|
||||||
|
EMC_TFAW_0 = 0x0000004F
|
||||||
|
EMC_TRPAB_0 = 0x00000038
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001E
|
||||||
|
EMC_TREFBW_0 = 0x0000281D
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004D
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02930025
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0033
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012B1C2
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000017
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000B
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000028
|
||||||
|
EMC_TPD_0 = 0x00000014
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003C
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186293
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003E
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009F7
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004F3C
|
||||||
|
EMC_TXSRDLL_0 = 0x000002F5
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000030
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_TR_QRST_0 = 0x00080001
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||||
|
EMC_IBDLY_0 = 0x1000001C
|
||||||
|
EMC_OBDLY_0 = 0x10000000
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000030
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000171
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00240026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00240027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x18181818
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x16120F15
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000017
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x16181615
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x12180F12
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1C1C1D1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x191C1D0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x08121311
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0F0E0A04
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x12171417
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x13181314
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000022
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x13121315
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1312130F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2021231F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1E201A1C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x17161011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1411150E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x040A0A09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070E0A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x090A0300
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060309
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040404
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08070408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03010101
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2A222428
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x23272726
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040525
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1600/emc/2666_emc.txt
Normal file
528
timings/Mariko/AA/1600/emc/2666_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000A0
|
||||||
|
EMC_RFC_0 = 0x000002EB
|
||||||
|
EMC_RAS_0 = 0x00000070
|
||||||
|
EMC_RP_0 = 0x00000030
|
||||||
|
EMC_R2W_0 = 0x0000002D
|
||||||
|
EMC_W2R_0 = 0x0000002A
|
||||||
|
EMC_R2P_0 = 0x0000000C
|
||||||
|
EMC_W2P_0 = 0x0000002D
|
||||||
|
EMC_RD_RCD_0 = 0x00000030
|
||||||
|
EMC_WR_RCD_0 = 0x00000030
|
||||||
|
EMC_RRD_0 = 0x00000014
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x0000000E
|
||||||
|
EMC_QUSE_0 = 0x00000026
|
||||||
|
EMC_QRST_0 = 0x00080001
|
||||||
|
EMC_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_RDV_0 = 0x0000003E
|
||||||
|
EMC_REFRESH_0 = 0x0000285D
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001B
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001B
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000026
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003A
|
||||||
|
EMC_TXSR_0 = 0x000002FF
|
||||||
|
EMC_TCKE_0 = 0x00000016
|
||||||
|
EMC_TFAW_0 = 0x00000050
|
||||||
|
EMC_TRPAB_0 = 0x00000038
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001E
|
||||||
|
EMC_TREFBW_0 = 0x0000289D
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004D
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x029B0026
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0033
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012A5B6
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000017
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802002D
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000B
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000028
|
||||||
|
EMC_TPD_0 = 0x00000014
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003C
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118629B
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003E
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A17
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005037
|
||||||
|
EMC_TXSRDLL_0 = 0x000002FF
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000030
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_TR_QRST_0 = 0x00080001
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||||
|
EMC_IBDLY_0 = 0x1000001C
|
||||||
|
EMC_OBDLY_0 = 0x10000000
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000C
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000030
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000176
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00240027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x19191818
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x17121016
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000017
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x18191616
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x33323433
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x191D1F0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x09141513
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x11100B05
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x131A1618
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x14191516
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000019
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x15141516
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x14141511
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x20221C1E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x19171113
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1412160F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090909
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05000007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B050B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04080005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080A0E
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01090B09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090508
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0306050A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05050807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06050504
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08030403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04010001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050105
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05040301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24242628
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262827
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040535
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
288
timings/Mariko/AA/1600/mc/1600_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/1600_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77DEB251
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000006
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x00000007
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000018
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x000D080C
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x726C2419
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C511020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80100080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A930850
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000037
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000228
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00800038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00800005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00800095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00800041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0080003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00800090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000080
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080016
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00800019
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00800005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00800018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/1866_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/1866_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x4A005160
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x75C5BF41
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000007
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000001C
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x000E090E
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x726E2A1D
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x00000041
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C111020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02013000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000041
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x000000F2
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000335
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001B
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x00001501
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x006D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x006D0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x006D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x006D0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x006D006D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x006D0019
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x006D0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x006D0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x006D0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x006D003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x006D0016
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000006D
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x006D0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x006D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000006D
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080013
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x006D0016
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x006D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x006D0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2133_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2133_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD0B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E72431
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80050080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x000F0A10
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72703021
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004A
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00600004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00600038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00600005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00600014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00600060
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00600016
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00600095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00600041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00600080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0060003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00600013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000060
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00600090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00600004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000060
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080011
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00600013
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00600005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00600018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2166_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2166_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD8B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E3E631
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000010
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x000F0A10
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72713121
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004B
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005E0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005E0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005E0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005E0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005E005E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005E0015
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005E0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005E0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005E0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005E003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005E0013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005E
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005E0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005E0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005E0013
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005E0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005E0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2200_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2200_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77D49341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000010
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B10
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72713222
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02910800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004C
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005D0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005D0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005D005D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005D0015
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005D0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005D0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005D0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005D003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005D0012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005D
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005D0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005D
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005D0012
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005D0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2233_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2233_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01011200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E3F551
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000010
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80040080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B10
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72713322
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02132800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004E
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005B0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005B0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005B0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005B0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005B005B
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005B0015
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005B0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005B0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005B0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005B003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005B0012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005B
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005B0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005B0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005B
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005B0012
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005B0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005B0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2266_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2266_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFDBB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E6F6D1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72713323
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004F
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005A0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005A0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005A0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005A0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005A005A
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005A0014
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005A0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005A0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005A0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005A003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005A0012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005A
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005A0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005A0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005A
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005A0012
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005A0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005A0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2300_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2300_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01211200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFDDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E4C761
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000011
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72723423
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C111020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02132800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000050
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00590004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00590038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00590005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00590014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00590059
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00590014
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00590095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00590041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00590080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0059003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00590012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000059
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00590090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00590004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000059
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00590012
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00590005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00590018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2333_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2333_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x00000000
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFC1B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E44061
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000011
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72723523
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02000000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000051
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00570004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00570038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00570005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00570014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00570057
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00570014
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00570095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00570041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00570080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0057003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000057
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00570090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00570004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000057
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00570011
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00570005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00570018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2366_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2366_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01211200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCEB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E38391
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000011
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000023
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B11
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72723624
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C151000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000052
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00560004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00560038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00560005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00560014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00560056
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00560013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00560095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00560041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00560080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0056003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00560011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000056
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00560090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00560004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000056
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00560011
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00560005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00560018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2400_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2400_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD4B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77CDF531
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72723625
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A110000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000053
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00550004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00550038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00550005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00550014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00550055
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00550013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00550095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00550041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00550080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0055003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00550011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000055
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00550090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00550004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000055
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00550011
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00550005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00550018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2433_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2433_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01010200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000007F
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0x00000000
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFDFB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x7A41F7E1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000012
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72733725
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000C0800
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8800
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1910A0
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000055
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000120
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000120
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x00000000
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000E
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00540004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00540038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00540005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00540014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00540054
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00540013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00540095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00540041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00540080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0054003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00540011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000054
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00540090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00540004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000054
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00540011
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00540005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00540018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2466_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2466_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCFB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E273C1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000012
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80040080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72733826
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000056
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00530004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00530038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00530005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00530014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00530053
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00530013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00530095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00530041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00530080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0053003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00530010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000053
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00530090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00530004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000053
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00530010
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00530005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00530018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2500_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2500_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFC6B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77D351A1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000012
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x800C0080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C12
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72733926
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02910800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000057
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00510004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00510038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00510005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00510014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00510051
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00510012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00510095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00510041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00510080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0051003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00510010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000051
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00510090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00510004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000051
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00510010
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00510005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00510018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2533_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2533_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77DCA341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000013
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C13
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72733927
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x00023070
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000058
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00500004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00500038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00500005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00500014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00500050
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00500012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00500095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00500041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00500080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0050003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00500010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000050
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00500090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00500004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000050
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00500010
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00500005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00500018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2566_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2566_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E72341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000013
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C13
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72743A27
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C111000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02110000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000059
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004F0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004F0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004F0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004F0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004F004F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004F0012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004F0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004F0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004F0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004F003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004F0010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004F
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004F0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004F0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004F
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004F0010
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004F0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004F0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2600_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2600_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E74541
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000013
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C13
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72743B28
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005A
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004E0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004E0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004E0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004E0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004E004E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004E0012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004E0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004E0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004E0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004E003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004E0010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004E
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004E0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004E0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004E0010
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004E0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004E0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1600/mc/2633_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2633_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0xF4028180
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD3B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E8C4C1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000013
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00120D13
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x00000040
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80070080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A930850
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005C
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004D0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004D0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004D004D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004D0011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004D0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004D0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004D0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004D003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004D000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004D
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004D0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004D
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004D000F
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004D0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1600/mc/2666_mc.txt
Normal file
288
timings/Mariko/AA/1600/mc/2666_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x4225CF41
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000014
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00120D13
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005D
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004C0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004C0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004C0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004C0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004C004C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004C0011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004C0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004C0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004C0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004C003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004C000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004C
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004C0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004C0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004C
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004C000F
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004C0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004C0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
528
timings/Mariko/AA/1866/emc/1866_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/1866_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000070
|
||||||
|
EMC_RFC_0 = 0x0000020B
|
||||||
|
EMC_RAS_0 = 0x0000004F
|
||||||
|
EMC_RP_0 = 0x00000022
|
||||||
|
EMC_R2W_0 = 0x0000002E
|
||||||
|
EMC_W2R_0 = 0x00000025
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000022
|
||||||
|
EMC_WR_RCD_0 = 0x00000022
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001A
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000028
|
||||||
|
EMC_QRST_0 = 0x0007000C
|
||||||
|
EMC_QSAFE_0 = 0x00000038
|
||||||
|
EMC_RDV_0 = 0x0000003E
|
||||||
|
EMC_REFRESH_0 = 0x00001C2D
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000013
|
||||||
|
EMC_PDEX2RD_0 = 0x00000013
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000001B
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003F
|
||||||
|
EMC_TXSR_0 = 0x00000219
|
||||||
|
EMC_TCKE_0 = 0x00000010
|
||||||
|
EMC_TFAW_0 = 0x0000004B
|
||||||
|
EMC_TRPAB_0 = 0x00000028
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x00000017
|
||||||
|
EMC_TREFBW_0 = 0x00001C6D
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000037
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x01D3001B
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x074A0034
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80040101
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000010
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000015
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000020
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000001C
|
||||||
|
EMC_TPD_0 = 0x0000000E
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003E
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003C
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x0039074A
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011861D3
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003E
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000070B
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80003873
|
||||||
|
EMC_TXSRDLL_0 = 0x00000219
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000030
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000040
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000038
|
||||||
|
EMC_TR_QRST_0 = 0x0007000C
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030A
|
||||||
|
EMC_IBDLY_0 = 0x1000001F
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000030
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x00000009
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000106
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0009000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00100007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230027
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0009000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00100007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00090000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00090000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001F0023
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00200023
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x31323332
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x312E2C30
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000030
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2F302E2E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2D312A2C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000002B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x37363837
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x3436372B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000035
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x282F302F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2D2D2925
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000002A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x20242123
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2F333030
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2F2E2E2F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2E2E2E2C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x3A3A3B39
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x38393638
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000035
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x31312D2E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x302E312C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04060506
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05070307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050706
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05040100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00030205
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040106
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000203
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00030002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04030103
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x04030201
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25202726
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29272322
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000F000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00070007
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00100010
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080F
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000403A5
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2133_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2133_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000080
|
||||||
|
EMC_RFC_0 = 0x00000256
|
||||||
|
EMC_RAS_0 = 0x0000005A
|
||||||
|
EMC_RP_0 = 0x00000027
|
||||||
|
EMC_R2W_0 = 0x0000002F
|
||||||
|
EMC_W2R_0 = 0x00000027
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000027
|
||||||
|
EMC_WR_RCD_0 = 0x00000027
|
||||||
|
EMC_RRD_0 = 0x00000010
|
||||||
|
EMC_REXT_0 = 0x0000001A
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000028
|
||||||
|
EMC_QRST_0 = 0x00070009
|
||||||
|
EMC_QSAFE_0 = 0x00000039
|
||||||
|
EMC_RDV_0 = 0x0000003F
|
||||||
|
EMC_REFRESH_0 = 0x0000203F
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000016
|
||||||
|
EMC_PDEX2RD_0 = 0x00000016
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000001E
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003F
|
||||||
|
EMC_TXSR_0 = 0x00000266
|
||||||
|
EMC_TCKE_0 = 0x00000012
|
||||||
|
EMC_TFAW_0 = 0x00000040
|
||||||
|
EMC_TRPAB_0 = 0x0000002D
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001A
|
||||||
|
EMC_TREFBW_0 = 0x0000207F
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000003F
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x0216001E
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012273E
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000013
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000012
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000020
|
||||||
|
EMC_TPD_0 = 0x00000010
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000041
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x0000003F
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003D
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186216
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x0000003F
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000080F
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004062
|
||||||
|
EMC_TXSRDLL_0 = 0x00000266
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000031
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000041
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000039
|
||||||
|
EMC_TR_QRST_0 = 0x00070009
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||||
|
EMC_IBDLY_0 = 0x1000001F
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000031
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000012B
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A002018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x80200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000A0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000A0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00250025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210023
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x3E3F3F40
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x3D39383D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000003D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3A3D3A39
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x393D3538
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000036
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x43424443
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x3F424336
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x323A3B3A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3937332F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000036
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x393D3B3E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3A3E3A3B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3A39393A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3A393936
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000039
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08080907
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05070205
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3D3D3839
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x3B3A3C37
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000039
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03070706
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03060003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080900
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070306
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03030505
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04030302
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26262629
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29292A27
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004042B
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2166_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2166_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000082
|
||||||
|
EMC_RFC_0 = 0x0000025F
|
||||||
|
EMC_RAS_0 = 0x0000005B
|
||||||
|
EMC_RP_0 = 0x00000027
|
||||||
|
EMC_R2W_0 = 0x0000002F
|
||||||
|
EMC_W2R_0 = 0x00000027
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000027
|
||||||
|
EMC_WR_RCD_0 = 0x00000027
|
||||||
|
EMC_RRD_0 = 0x00000011
|
||||||
|
EMC_REXT_0 = 0x00000019
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000029
|
||||||
|
EMC_QRST_0 = 0x0007000A
|
||||||
|
EMC_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_RDV_0 = 0x00000040
|
||||||
|
EMC_REFRESH_0 = 0x000020BF
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000017
|
||||||
|
EMC_PDEX2RD_0 = 0x00000017
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000001F
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003F
|
||||||
|
EMC_TXSR_0 = 0x0000026F
|
||||||
|
EMC_TCKE_0 = 0x00000013
|
||||||
|
EMC_TFAW_0 = 0x00000041
|
||||||
|
EMC_TRPAB_0 = 0x0000002E
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001A
|
||||||
|
EMC_TREFBW_0 = 0x000020FF
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000040
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x021E001F
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012AFCD
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000013
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000013
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000021
|
||||||
|
EMC_TPD_0 = 0x00000011
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003E
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118621E
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000040
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000082F
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000415D
|
||||||
|
EMC_TXSRDLL_0 = 0x0000026F
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000032
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_TR_QRST_0 = 0x0007000A
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||||
|
EMC_IBDLY_0 = 0x10000020
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000032
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000130
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A002010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00250025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x40414141
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x3F3B393E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000003F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3C3E3C3B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3B3F373A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000038
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x44434444
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x41434437
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000042
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x333B3C3B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3A393431
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000037
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3A3F3D3E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3C3F3C3C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3B3A3B3C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3B3B3B39
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x090A0B08
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x07080406
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3E3F393C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x3D3B3E38
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03060706
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x02000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02060004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07080A0B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060508
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040502
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040105
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2823282A
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29292628
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004043B
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2200_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2200_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000084
|
||||||
|
EMC_RFC_0 = 0x00000268
|
||||||
|
EMC_RAS_0 = 0x0000005D
|
||||||
|
EMC_RP_0 = 0x00000028
|
||||||
|
EMC_R2W_0 = 0x0000002F
|
||||||
|
EMC_W2R_0 = 0x00000027
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000028
|
||||||
|
EMC_WR_RCD_0 = 0x00000028
|
||||||
|
EMC_RRD_0 = 0x00000011
|
||||||
|
EMC_REXT_0 = 0x00000019
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000029
|
||||||
|
EMC_QRST_0 = 0x0007000A
|
||||||
|
EMC_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_RDV_0 = 0x00000040
|
||||||
|
EMC_REFRESH_0 = 0x00002144
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000017
|
||||||
|
EMC_PDEX2RD_0 = 0x00000017
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000001F
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x0000003F
|
||||||
|
EMC_TXSR_0 = 0x00000279
|
||||||
|
EMC_TCKE_0 = 0x00000013
|
||||||
|
EMC_TFAW_0 = 0x00000042
|
||||||
|
EMC_TRPAB_0 = 0x0000002F
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001A
|
||||||
|
EMC_TREFBW_0 = 0x00002184
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000041
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x0226001F
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012293F
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000013
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000013
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000021
|
||||||
|
EMC_TPD_0 = 0x00000011
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003E
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186226
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000040
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000851
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000425F
|
||||||
|
EMC_TXSRDLL_0 = 0x00000279
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000032
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_TR_QRST_0 = 0x0007000A
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x10000020
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002B
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000134
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00010014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210027
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0022
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x41414242
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x403C3A3F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3E403D3D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3D42393B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x46444747
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x42454638
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000043
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x353D3E3D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3B3A3532
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000038
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3C413F41
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3E423E3E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3C3B3C3D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3C3C3C39
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0B0C0D0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x080A0608
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x40413B3D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04070707
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03010005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060908
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02030102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040502
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252729
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29272827
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004044C
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2233_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2233_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000086
|
||||||
|
EMC_RFC_0 = 0x00000272
|
||||||
|
EMC_RAS_0 = 0x0000005E
|
||||||
|
EMC_RP_0 = 0x00000029
|
||||||
|
EMC_R2W_0 = 0x0000002F
|
||||||
|
EMC_W2R_0 = 0x00000028
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000029
|
||||||
|
EMC_WR_RCD_0 = 0x00000029
|
||||||
|
EMC_RRD_0 = 0x00000011
|
||||||
|
EMC_REXT_0 = 0x00000019
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000029
|
||||||
|
EMC_QRST_0 = 0x00070009
|
||||||
|
EMC_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_RDV_0 = 0x00000040
|
||||||
|
EMC_REFRESH_0 = 0x000021C5
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000017
|
||||||
|
EMC_PDEX2RD_0 = 0x00000017
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000020
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x00000282
|
||||||
|
EMC_TCKE_0 = 0x00000013
|
||||||
|
EMC_TFAW_0 = 0x00000043
|
||||||
|
EMC_TRPAB_0 = 0x0000002F
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001A
|
||||||
|
EMC_TREFBW_0 = 0x00002205
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000042
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x022F0020
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012839F
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000013
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000012
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000022
|
||||||
|
EMC_TPD_0 = 0x00000011
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003E
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118622F
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000040
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000871
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000435A
|
||||||
|
EMC_TXSRDLL_0 = 0x00000282
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000032
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_TR_QRST_0 = 0x00070009
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x10000020
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000032
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000139
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200023
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x42424344
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x413D3B40
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000041
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3F423F3E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3E433A3D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x48474949
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x4547483B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000046
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x353E403E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3D3B3633
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000039
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3E424042
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3F433F3F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000041
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3E3C3D3F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3E3E3E3B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0D0E0E0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0A0B0809
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x42433D3E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2C2B2E29
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080806
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01060004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050908
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07040100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060206
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000204
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2825262A
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29272627
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004045D
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2266_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2266_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000088
|
||||||
|
EMC_RFC_0 = 0x0000027B
|
||||||
|
EMC_RAS_0 = 0x00000060
|
||||||
|
EMC_RP_0 = 0x00000029
|
||||||
|
EMC_R2W_0 = 0x0000002F
|
||||||
|
EMC_W2R_0 = 0x00000028
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000029
|
||||||
|
EMC_WR_RCD_0 = 0x00000029
|
||||||
|
EMC_RRD_0 = 0x00000011
|
||||||
|
EMC_REXT_0 = 0x0000001A
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000029
|
||||||
|
EMC_QRST_0 = 0x00070009
|
||||||
|
EMC_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_RDV_0 = 0x00000040
|
||||||
|
EMC_REFRESH_0 = 0x00002245
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000017
|
||||||
|
EMC_PDEX2RD_0 = 0x00000017
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000020
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x0000028C
|
||||||
|
EMC_TCKE_0 = 0x00000013
|
||||||
|
EMC_TFAW_0 = 0x00000044
|
||||||
|
EMC_TRPAB_0 = 0x00000030
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001B
|
||||||
|
EMC_TREFBW_0 = 0x00002285
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000042
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02370020
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0035
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012283F
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000014
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000012
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000022
|
||||||
|
EMC_TPD_0 = 0x00000011
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430021
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003E
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186237
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000040
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000891
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004455
|
||||||
|
EMC_TXSRDLL_0 = 0x0000028C
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000032
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_TR_QRST_0 = 0x00070009
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x10000020
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0E0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000032
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000013E
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x44444545
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x433F3D42
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000043
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x4143403F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3F443B3F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x49484B4A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x474A4A3C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000048
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3741413F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3E3D3934
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3F444143
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x40444040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000042
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3F3E3F3F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x403F3F3C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0F0F100D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0B0E090B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x43433E40
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4140433D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04050606
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06060700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02030604
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04020302
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050206
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07040402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26252629
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28282B29
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004046D
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2300_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2300_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000008A
|
||||||
|
EMC_RFC_0 = 0x00000284
|
||||||
|
EMC_RAS_0 = 0x00000061
|
||||||
|
EMC_RP_0 = 0x0000002A
|
||||||
|
EMC_R2W_0 = 0x00000030
|
||||||
|
EMC_W2R_0 = 0x00000028
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x0000002A
|
||||||
|
EMC_WR_RCD_0 = 0x0000002A
|
||||||
|
EMC_RRD_0 = 0x00000012
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000028
|
||||||
|
EMC_QRST_0 = 0x00070008
|
||||||
|
EMC_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_RDV_0 = 0x00000040
|
||||||
|
EMC_REFRESH_0 = 0x000022CA
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000019
|
||||||
|
EMC_PDEX2RD_0 = 0x00000019
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000021
|
||||||
|
EMC_AR2PDEN_0 = 0x00000003
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x00000296
|
||||||
|
EMC_TCKE_0 = 0x00000014
|
||||||
|
EMC_TFAW_0 = 0x00000040
|
||||||
|
EMC_TRPAB_0 = 0x00000031
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001B
|
||||||
|
EMC_TREFBW_0 = 0x0000230A
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000045
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x023F0021
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80125975
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000014
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000011
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000023
|
||||||
|
EMC_TPD_0 = 0x00000012
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003E
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118623F
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000040
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008B2
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004558
|
||||||
|
EMC_TXSRDLL_0 = 0x00000296
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000032
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_TR_QRST_0 = 0x00070008
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x1000001F
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0B09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000032
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000142
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x45464747
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x45403F43
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000044
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x42444141
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x40443D40
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4B4A4B4C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x484A4B3D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000048
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x38424341
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x403E3936
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060305
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x01050102
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x41404141
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4240413D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0F10110F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0C0F0A0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x45453F42
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4341443F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03010004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090309
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060306
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050106
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252828
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27272628
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004047E
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2333_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2333_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000008C
|
||||||
|
EMC_RFC_0 = 0x0000028E
|
||||||
|
EMC_RAS_0 = 0x00000062
|
||||||
|
EMC_RP_0 = 0x0000002A
|
||||||
|
EMC_R2W_0 = 0x00000030
|
||||||
|
EMC_W2R_0 = 0x00000029
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x0000002A
|
||||||
|
EMC_WR_RCD_0 = 0x0000002A
|
||||||
|
EMC_RRD_0 = 0x00000012
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000028
|
||||||
|
EMC_QRST_0 = 0x00070007
|
||||||
|
EMC_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_RDV_0 = 0x00000040
|
||||||
|
EMC_REFRESH_0 = 0x0000234B
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000019
|
||||||
|
EMC_PDEX2RD_0 = 0x00000019
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000021
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x0000029F
|
||||||
|
EMC_TCKE_0 = 0x00000014
|
||||||
|
EMC_TFAW_0 = 0x00000046
|
||||||
|
EMC_TRPAB_0 = 0x00000031
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001B
|
||||||
|
EMC_TREFBW_0 = 0x0000238B
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000045
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02480021
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80124762
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000014
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000010
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000023
|
||||||
|
EMC_TPD_0 = 0x00000012
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000040
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003E
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186248
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000040
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008D2
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004653
|
||||||
|
EMC_TXSRDLL_0 = 0x0000029F
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000032
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000042
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003A
|
||||||
|
EMC_TR_QRST_0 = 0x00070007
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x1000001F
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0B0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000032
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x0000024A
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000147
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x06070707
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06010004
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x45464443
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x42473F41
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4C4C4D4D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x494B4D3E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000004A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3A434442
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x41403B37
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x02070507
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03080304
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x43414243
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4342423F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000041
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x11121311
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0F110C0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06060102
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x04020600
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x040A040A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02080005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08070800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010304
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050105
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26262929
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x29282627
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2366_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2366_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000008E
|
||||||
|
EMC_RFC_0 = 0x00000297
|
||||||
|
EMC_RAS_0 = 0x00000064
|
||||||
|
EMC_RP_0 = 0x0000002B
|
||||||
|
EMC_R2W_0 = 0x00000030
|
||||||
|
EMC_W2R_0 = 0x00000029
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x0000002B
|
||||||
|
EMC_WR_RCD_0 = 0x0000002B
|
||||||
|
EMC_RRD_0 = 0x00000012
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002A
|
||||||
|
EMC_QRST_0 = 0x00070009
|
||||||
|
EMC_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_RDV_0 = 0x00000041
|
||||||
|
EMC_REFRESH_0 = 0x000023CB
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000019
|
||||||
|
EMC_PDEX2RD_0 = 0x00000019
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000022
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x000002A9
|
||||||
|
EMC_TCKE_0 = 0x00000014
|
||||||
|
EMC_TFAW_0 = 0x00000047
|
||||||
|
EMC_TRPAB_0 = 0x00000032
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001C
|
||||||
|
EMC_TREFBW_0 = 0x0000240B
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000002E
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02500022
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012304B
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000015
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000012
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000024
|
||||||
|
EMC_TPD_0 = 0x00000012
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003F
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186250
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000041
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008F2
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000474E
|
||||||
|
EMC_TXSRDLL_0 = 0x000002A9
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000033
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_TR_QRST_0 = 0x00070009
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000033
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000014C
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xCC200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00150009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00150009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x07080909
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x07030005
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06080504
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04090003
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0E0D0F0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0D0E00
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3B454543
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x42413C38
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x04090608
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x05090506
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020404
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040502
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x12131511
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x10110D0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08090204
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040801
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04050506
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03010005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070306
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02030102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06040402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040104
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252529
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28292629
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2400_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2400_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000090
|
||||||
|
EMC_RFC_0 = 0x000002A0
|
||||||
|
EMC_RAS_0 = 0x00000065
|
||||||
|
EMC_RP_0 = 0x0000002C
|
||||||
|
EMC_R2W_0 = 0x00000030
|
||||||
|
EMC_W2R_0 = 0x00000029
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x0000002C
|
||||||
|
EMC_WR_RCD_0 = 0x0000002C
|
||||||
|
EMC_RRD_0 = 0x00000012
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002A
|
||||||
|
EMC_QRST_0 = 0x00070009
|
||||||
|
EMC_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_RDV_0 = 0x00000041
|
||||||
|
EMC_REFRESH_0 = 0x00002450
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000019
|
||||||
|
EMC_PDEX2RD_0 = 0x00000019
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000022
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x000002B2
|
||||||
|
EMC_TCKE_0 = 0x00000014
|
||||||
|
EMC_TFAW_0 = 0x00000048
|
||||||
|
EMC_TRPAB_0 = 0x00000033
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001C
|
||||||
|
EMC_TREFBW_0 = 0x00002490
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000047
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02580022
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80121F39
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000015
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000012
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000024
|
||||||
|
EMC_TPD_0 = 0x00000012
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003F
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186258
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000041
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000914
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004850
|
||||||
|
EMC_TXSRDLL_0 = 0x000002B2
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000033
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_TR_QRST_0 = 0x00070009
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000033
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000150
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0A0A0B0B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x09050307
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06090606
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x050A0104
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0F0E1011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0C0F0F01
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3C464745
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x44433D39
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000041
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x040A070A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x060A0607
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05040506
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06050503
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x14151713
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x12130F11
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09090305
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050902
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A040A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02080005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06050000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000304
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040301
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2724282A
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x2A27262B
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000404B0
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2433_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2433_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000092
|
||||||
|
EMC_RFC_0 = 0x000002AA
|
||||||
|
EMC_RAS_0 = 0x00000067
|
||||||
|
EMC_RP_0 = 0x0000002C
|
||||||
|
EMC_R2W_0 = 0x00000030
|
||||||
|
EMC_W2R_0 = 0x0000002A
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x0000002C
|
||||||
|
EMC_WR_RCD_0 = 0x0000002C
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002A
|
||||||
|
EMC_QRST_0 = 0x00070008
|
||||||
|
EMC_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_RDV_0 = 0x00000041
|
||||||
|
EMC_REFRESH_0 = 0x000024D1
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001A
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001A
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000023
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x000002BC
|
||||||
|
EMC_TCKE_0 = 0x00000015
|
||||||
|
EMC_TFAW_0 = 0x00000049
|
||||||
|
EMC_TRPAB_0 = 0x00000034
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001C
|
||||||
|
EMC_TREFBW_0 = 0x00002511
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000048
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02610023
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80122A41
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000015
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000011
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000025
|
||||||
|
EMC_TPD_0 = 0x00000013
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003F
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186261
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000041
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000934
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000494B
|
||||||
|
EMC_TXSRDLL_0 = 0x000002BC
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000033
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_TR_QRST_0 = 0x00070008
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0B
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000033
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000155
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0B0C0C0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0B060409
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x080B0807
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x070C0306
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x10101112
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0D101102
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3D474846
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x45443F3A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000041
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x050A080A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x060A0707
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x07060607
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x07070703
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x13151012
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0B0B0506
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09070A03
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080806
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020405
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05020302
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040105
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030401
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2723242A
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262426
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00050005
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000404C1
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2466_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2466_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000094
|
||||||
|
EMC_RFC_0 = 0x000002B3
|
||||||
|
EMC_RAS_0 = 0x00000068
|
||||||
|
EMC_RP_0 = 0x0000002D
|
||||||
|
EMC_R2W_0 = 0x00000030
|
||||||
|
EMC_W2R_0 = 0x0000002A
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x0000002D
|
||||||
|
EMC_WR_RCD_0 = 0x0000002D
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002A
|
||||||
|
EMC_QRST_0 = 0x00070008
|
||||||
|
EMC_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_RDV_0 = 0x00000041
|
||||||
|
EMC_REFRESH_0 = 0x00002551
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000010
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001A
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000023
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x000002C5
|
||||||
|
EMC_TCKE_0 = 0x00000015
|
||||||
|
EMC_TFAW_0 = 0x0000004A
|
||||||
|
EMC_TRPAB_0 = 0x00000034
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001C
|
||||||
|
EMC_TREFBW_0 = 0x00002591
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000049
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02690023
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012001A
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000015
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000011
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000025
|
||||||
|
EMC_TPD_0 = 0x00000013
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003F
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186269
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000041
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000954
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004A46
|
||||||
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EMC_TXSRDLL_0 = 0x000002C5
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000033
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_TR_QRST_0 = 0x00070008
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
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EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
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EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
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EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000033
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000015A
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x20000100
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x00082000
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0C0D0E0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0B07050A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0C0909
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x080D0407
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x11111313
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0E111303
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3F494A48
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4746413C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000043
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x070C090B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x080C0808
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x09070909
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x09090905
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x18181A16
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x14161214
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0D0D0708
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00040505
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010404
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050504
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030302
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2724232A
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28292628
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E181E18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1E181E18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000404D1
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2500_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2500_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000096
|
||||||
|
EMC_RFC_0 = 0x000002BC
|
||||||
|
EMC_RAS_0 = 0x00000069
|
||||||
|
EMC_RP_0 = 0x0000002D
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002A
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x0000002D
|
||||||
|
EMC_WR_RCD_0 = 0x0000002D
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001A
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000029
|
||||||
|
EMC_QRST_0 = 0x00070007
|
||||||
|
EMC_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_RDV_0 = 0x00000041
|
||||||
|
EMC_REFRESH_0 = 0x000025D6
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001A
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001A
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000023
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x000002CF
|
||||||
|
EMC_TCKE_0 = 0x00000015
|
||||||
|
EMC_TFAW_0 = 0x0000004B
|
||||||
|
EMC_TRPAB_0 = 0x00000035
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001D
|
||||||
|
EMC_TREFBW_0 = 0x00002616
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000049
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02710023
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012ED06
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000016
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000010
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000028
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000026
|
||||||
|
EMC_TPD_0 = 0x00000013
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003F
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118614D
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000041
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000975
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004B49
|
||||||
|
EMC_TXSRDLL_0 = 0x000002CF
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000033
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003B
|
||||||
|
EMC_TR_QRST_0 = 0x00070007
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x10000020
|
||||||
|
EMC_OBDLY_0 = 0x10000004
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000033
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000015E
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00060000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0F0F1010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0D09070C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0B0D0A0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x090E0508
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x12121414
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0F121404
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x252C2D2C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4847423D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000045
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x090D0B0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0A0E0A0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0B090A0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0A0A0A07
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1A1A1B19
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x16181415
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F0E070A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0C090D07
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080407
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07060A0C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060806
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040208
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02040704
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04020403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06040403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24232627
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27292B27
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000404E2
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2533_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2533_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000098
|
||||||
|
EMC_RFC_0 = 0x000002C6
|
||||||
|
EMC_RAS_0 = 0x0000006B
|
||||||
|
EMC_RP_0 = 0x0000002E
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002B
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x0000001D
|
||||||
|
EMC_WR_RCD_0 = 0x0000002E
|
||||||
|
EMC_RRD_0 = 0x00000013
|
||||||
|
EMC_REXT_0 = 0x0000001C
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000029
|
||||||
|
EMC_QRST_0 = 0x00080005
|
||||||
|
EMC_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_RDV_0 = 0x00000041
|
||||||
|
EMC_REFRESH_0 = 0x00002657
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001A
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001A
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000024
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x000002D9
|
||||||
|
EMC_TCKE_0 = 0x00000015
|
||||||
|
EMC_TFAW_0 = 0x0000004C
|
||||||
|
EMC_TRPAB_0 = 0x00000036
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001D
|
||||||
|
EMC_TREFBW_0 = 0x00002697
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004A
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x027A0024
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012D7F0
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000016
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000F
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000026
|
||||||
|
EMC_TPD_0 = 0x00000013
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000041
|
||||||
|
EMC_RDV_EARLY_0 = 0x0000003F
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118627A
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000041
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000995
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004C44
|
||||||
|
EMC_TXSRDLL_0 = 0x000002D9
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000033
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000043
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_TR_QRST_0 = 0x00080005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x1000001F
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0B
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000033
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000163
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x10111111
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0F0A080D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0E0F0D0B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0C10070A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x14141616
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x12141606
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x414C4D4B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4948433E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000046
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0A0F0C0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0A0F0B0B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2C2D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0C0B0C08
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1B1C1D1B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x181A1517
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000016
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F10090B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0E0B0E08
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080808
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03010006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050908
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05040000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000304
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07040106
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07040402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242428
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282627
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000404F3
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2566_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2566_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000009A
|
||||||
|
EMC_RFC_0 = 0x000002CF
|
||||||
|
EMC_RAS_0 = 0x0000006C
|
||||||
|
EMC_RP_0 = 0x0000002F
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002B
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x0000002F
|
||||||
|
EMC_WR_RCD_0 = 0x0000002F
|
||||||
|
EMC_RRD_0 = 0x00000014
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002A
|
||||||
|
EMC_QRST_0 = 0x00080006
|
||||||
|
EMC_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_RDV_0 = 0x00000042
|
||||||
|
EMC_REFRESH_0 = 0x000026D7
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001B
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001B
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000024
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x000002E2
|
||||||
|
EMC_TCKE_0 = 0x00000016
|
||||||
|
EMC_TFAW_0 = 0x0000004D
|
||||||
|
EMC_TRPAB_0 = 0x00000036
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001D
|
||||||
|
EMC_TREFBW_0 = 0x00002717
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004C
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02820024
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0036
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012CAE3
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000016
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000010
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000027
|
||||||
|
EMC_TPD_0 = 0x00000014
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000044
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000040
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186282
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000042
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009B5
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004D3F
|
||||||
|
EMC_TXSRDLL_0 = 0x000002E2
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000034
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003C
|
||||||
|
EMC_TR_QRST_0 = 0x00080006
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||||
|
EMC_IBDLY_0 = 0x10000020
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000034
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000168
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x11111313
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x100C0A0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x10110E0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0D12090C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x17161818
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x13171808
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x020D0E0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A090500
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0C110E11
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0D110D0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0D0C0C0D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0D0D0D0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1C1C1E1B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x191B1618
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000017
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x11120B0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0F0C1009
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0706090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000304
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050106
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050402
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2724252B
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x272A2627
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040503
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
87
timings/Mariko/AA/1866/emc/2600_emc.txt
Normal file
87
timings/Mariko/AA/1866/emc/2600_emc.txt
Normal file
@@ -0,0 +1,87 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
emc_cfg = 0xF3200000
|
||||||
|
emc_rc = 0x0000009C
|
||||||
|
emc_rfc = 0x000002D8
|
||||||
|
emc_ras = 0x0000006E
|
||||||
|
emc_rp = 0x0000002F
|
||||||
|
emc_r2w = 0x00000031
|
||||||
|
emc_w2r = 0x0000002B
|
||||||
|
emc_r2p = 0x0000000E
|
||||||
|
emc_w2p = 0x00000033
|
||||||
|
emc_rd_rcd = 0x0000002F
|
||||||
|
emc_wr_rcd = 0x0000002F
|
||||||
|
emc_rrd = 0x00000014
|
||||||
|
emc_rext = 0x0000001B
|
||||||
|
emc_qsafe = 0x0000003C
|
||||||
|
emc_refresh = 0x0000275C
|
||||||
|
emc_burst_refresh_num = 0x00000000
|
||||||
|
emc_pdex2wr = 0x0000001B
|
||||||
|
emc_pdex2rd = 0x0000001B
|
||||||
|
emc_pchg2pden = 0x00000005
|
||||||
|
emc_act2pden = 0x00000025
|
||||||
|
emc_ar2pden = 0x00000005
|
||||||
|
emc_rw2pden = 0x00000040
|
||||||
|
emc_txsr = 0x000002EC
|
||||||
|
emc_tcke = 0x00000016
|
||||||
|
emc_tfaw = 0x0000004E
|
||||||
|
emc_trpab = 0x00000037
|
||||||
|
emc_tclkstable = 0x00000004
|
||||||
|
emc_tclkstop = 0x0000001E
|
||||||
|
emc_trefbw = 0x0000279C
|
||||||
|
emc_tppd = 0x00000004
|
||||||
|
emc_odt_write = 0x00000000
|
||||||
|
emc_pdex2mrr = 0x0000004C
|
||||||
|
emc_wext = 0x00000019
|
||||||
|
emc_rfc_slr = 0x00000000
|
||||||
|
emc_mrs_wait_cnt2 = 0x028A0025
|
||||||
|
emc_mrs_wait_cnt = 0x07FF0037
|
||||||
|
emc_mrs = 0x00000000
|
||||||
|
emc_emrs = 0x00000000
|
||||||
|
emc_mrw = 0x00170040
|
||||||
|
emc_fbio_spare = 0x00000012
|
||||||
|
emc_fbio_cfg5 = 0x9160A00D
|
||||||
|
emc_pdex2cke = 0x00000003
|
||||||
|
emc_cke2pden = 0x00000017
|
||||||
|
emc_r2r = 0x00000000
|
||||||
|
emc_einput = 0x00000010
|
||||||
|
emc_einput_duration = 0x00000029
|
||||||
|
emc_puterm_extra = 0x00000001
|
||||||
|
emc_tckesr = 0x00000027
|
||||||
|
emc_tpd = 0x00000014
|
||||||
|
emc_cfg_2 = 0x0011083D
|
||||||
|
emc_cfg_dig_dll = 0x002C03A9
|
||||||
|
emc_cfg_dig_dll_period = 0x00008000
|
||||||
|
emc_rdv_mask = 0x00000044
|
||||||
|
emc_wdv_mask = 0x00000010
|
||||||
|
emc_rdv_early_mask = 0x00000042
|
||||||
|
emc_rdv_early = 0x00000040
|
||||||
|
emc_fdpd_ctrl_dq = 0x8020221F
|
||||||
|
emc_fdpd_ctrl_cmd = 0x0220F40F
|
||||||
|
emc_sel_dpd_ctrl = 0x0004000C
|
||||||
|
emc_pre_refresh_req_cnt = 0x000009D7
|
||||||
|
emc_dyn_self_ref_control = 0x80004E41
|
||||||
|
emc_txsrdll = 0x000002EC
|
||||||
|
emc_ibdly = 0x10000020
|
||||||
|
emc_obdly = 0x10000002
|
||||||
|
emc_txdsrvttgen = 0x00000000
|
||||||
|
emc_we_duration = 0x0000000E
|
||||||
|
emc_ws_duration = 0x00000008
|
||||||
|
emc_wev = 0x0000000C
|
||||||
|
emc_cfg_3 = 0x00000040
|
||||||
|
emc_wdv_chk = 0x00000006
|
||||||
|
emc_cfg_pipe_2 = 0x00000000
|
||||||
|
emc_cfg_pipe_1 = 0x0FFF0000
|
||||||
|
emc_cfg_pipe = 0x0FFF0000
|
||||||
|
emc_quse_width = 0x0000000B
|
||||||
|
emc_puterm_width = 0x80000000
|
||||||
|
emc_fbio_cfg7 = 0x00003BFF
|
||||||
|
emc_rfcpb = 0x0000016C
|
||||||
|
emc_ccdmw = 0x00000020
|
||||||
|
emc_config_sample_delay = 0x00000020
|
||||||
|
emc_wdv = 0x00000010
|
||||||
|
emc_quse = 0x0000002A
|
||||||
|
emc_qrst = 0x00080006
|
||||||
|
emc_rdv = 0x00000042
|
||||||
|
emc_wsv = 0x0000000E
|
||||||
|
emc_qpop = 0x00000034
|
||||||
528
timings/Mariko/AA/1866/emc/2633_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2633_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x0000009E
|
||||||
|
EMC_RFC_0 = 0x000002E2
|
||||||
|
EMC_RAS_0 = 0x0000006F
|
||||||
|
EMC_RP_0 = 0x00000030
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002C
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000030
|
||||||
|
EMC_WR_RCD_0 = 0x00000030
|
||||||
|
EMC_RRD_0 = 0x00000014
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002A
|
||||||
|
EMC_QRST_0 = 0x00080005
|
||||||
|
EMC_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_RDV_0 = 0x00000042
|
||||||
|
EMC_REFRESH_0 = 0x000027DD
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001B
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001B
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000025
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x000002F5
|
||||||
|
EMC_TCKE_0 = 0x00000016
|
||||||
|
EMC_TFAW_0 = 0x0000004F
|
||||||
|
EMC_TRPAB_0 = 0x00000038
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001E
|
||||||
|
EMC_TREFBW_0 = 0x0000281D
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004D
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02930025
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80040101
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000017
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000F
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000028
|
||||||
|
EMC_TPD_0 = 0x00000014
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000044
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000040
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186293
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000042
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009F7
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004F3C
|
||||||
|
EMC_TXSRDLL_0 = 0x000002F5
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000034
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_TR_QRST_0 = 0x00080005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||||
|
EMC_IBDLY_0 = 0x10000020
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D08
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000034
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000171
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200027
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270029
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x15151516
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x130F0D12
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x10141010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0F150B0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1A1A1C1B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x171B1B0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000019
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x050F110E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0D0C0701
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0E131114
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x10151011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x100E0F10
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x100F100C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x201F211F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1C1E191C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x14150E0F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1110130B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05080909
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090508
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02060004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07080A0F
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0900
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070B09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07070200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04030606
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04040304
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07040106
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08040502
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27262428
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26262627
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040525
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D08
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2666_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2666_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000A0
|
||||||
|
EMC_RFC_0 = 0x000002EB
|
||||||
|
EMC_RAS_0 = 0x00000070
|
||||||
|
EMC_RP_0 = 0x00000030
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002C
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000030
|
||||||
|
EMC_WR_RCD_0 = 0x00000030
|
||||||
|
EMC_RRD_0 = 0x00000014
|
||||||
|
EMC_REXT_0 = 0x0000001B
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002A
|
||||||
|
EMC_QRST_0 = 0x00080005
|
||||||
|
EMC_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_RDV_0 = 0x00000042
|
||||||
|
EMC_REFRESH_0 = 0x0000285D
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001B
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001B
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000026
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x000002FF
|
||||||
|
EMC_TCKE_0 = 0x00000016
|
||||||
|
EMC_TFAW_0 = 0x00000050
|
||||||
|
EMC_TRPAB_0 = 0x00000038
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001E
|
||||||
|
EMC_TREFBW_0 = 0x0000289D
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004D
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x029B0026
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80129EB6
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000017
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000F
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000028
|
||||||
|
EMC_TPD_0 = 0x00000014
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000035
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000040
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x0118629B
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000042
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A17
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005037
|
||||||
|
EMC_TXSRDLL_0 = 0x000002FF
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000034
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_TR_QRST_0 = 0x00080005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||||
|
EMC_IBDLY_0 = 0x10000020
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000034
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000176
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270029
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x16171717
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x15100D14
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x12151211
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x11160C10
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x33323333
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x181B1C0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000019
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2D2C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2A2A2624
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x10161315
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x11161212
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x11101112
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1211110E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x21222320
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1E201C1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x16160F11
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1410140D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B050B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03080005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080B08
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07040100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090508
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03080509
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020506
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03030202
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05020403
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08050208
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09050604
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25252729
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25262628
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040535
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2700_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2700_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000A2
|
||||||
|
EMC_RFC_0 = 0x000002F4
|
||||||
|
EMC_RAS_0 = 0x00000072
|
||||||
|
EMC_RP_0 = 0x00000031
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002C
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000031
|
||||||
|
EMC_WR_RCD_0 = 0x00000031
|
||||||
|
EMC_RRD_0 = 0x00000015
|
||||||
|
EMC_REXT_0 = 0x0000001C
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000029
|
||||||
|
EMC_QRST_0 = 0x00080004
|
||||||
|
EMC_QSAFE_0 = 0x0000003E
|
||||||
|
EMC_RDV_0 = 0x00000042
|
||||||
|
EMC_REFRESH_0 = 0x000028E2
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001C
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001C
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000026
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x00000309
|
||||||
|
EMC_TCKE_0 = 0x00000017
|
||||||
|
EMC_TFAW_0 = 0x00000051
|
||||||
|
EMC_TRPAB_0 = 0x00000039
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001E
|
||||||
|
EMC_TREFBW_0 = 0x00002922
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000004F
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02A30026
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80128FA7
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000017
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000E
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002B
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000029
|
||||||
|
EMC_TPD_0 = 0x00000015
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000044
|
||||||
|
EMC_WDV_MASK_0 = 0x0000000E
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000040
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x00310640
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862A3
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000042
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A38
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000513A
|
||||||
|
EMC_TXSRDLL_0 = 0x00000309
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000034
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003E
|
||||||
|
EMC_TR_QRST_0 = 0x00080004
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||||
|
EMC_IBDLY_0 = 0x1000001F
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000034
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000017A
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0018000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0016
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0018000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270029
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x17171818
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x16110F15
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000016
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x14171313
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E282B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1C1B1E1E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x191C1D0C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x08131412
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x100F0A04
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x11171517
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x12171313
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000017
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x13121213
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1312130F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x23232422
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1F221C1F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x18181112
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1512160E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000011
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0509090A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A050A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04080005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070A08
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09060000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02020203
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03030202
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x03020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24252628
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22272725
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00180018
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040546
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2733_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2733_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000A4
|
||||||
|
EMC_RFC_0 = 0x000002FE
|
||||||
|
EMC_RAS_0 = 0x00000073
|
||||||
|
EMC_RP_0 = 0x00000032
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002D
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000032
|
||||||
|
EMC_WR_RCD_0 = 0x00000032
|
||||||
|
EMC_RRD_0 = 0x00000015
|
||||||
|
EMC_REXT_0 = 0x0000001C
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x00000029
|
||||||
|
EMC_QRST_0 = 0x00080003
|
||||||
|
EMC_QSAFE_0 = 0x0000003F
|
||||||
|
EMC_RDV_0 = 0x00000042
|
||||||
|
EMC_REFRESH_0 = 0x00002963
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001C
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001C
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000027
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x00000312
|
||||||
|
EMC_TCKE_0 = 0x00000017
|
||||||
|
EMC_TFAW_0 = 0x00000052
|
||||||
|
EMC_TRPAB_0 = 0x0000003A
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x000029A3
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000050
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02AC0027
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80128198
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000018
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000D
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000029
|
||||||
|
EMC_TPD_0 = 0x00000015
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000044
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000042
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000040
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862AC
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000042
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A58
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005235
|
||||||
|
EMC_TXSRDLL_0 = 0x00000312
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000034
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000044
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003F
|
||||||
|
EMC_TR_QRST_0 = 0x00080003
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||||
|
EMC_IBDLY_0 = 0x1000001F
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C0A
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000034
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000017F
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x000B0005
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0017
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0018000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x191A1A1A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x18131016
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000018
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x16181515
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x14190F13
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1D1E1F1E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1A1D1E0E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000031
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x09141513
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x12100B05
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x13191619
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x141A1515
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000018
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x14131414
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x14141410
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000012
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x25252623
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x20231E20
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1A191114
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x16131811
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090509
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080A0F
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070C09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09080200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050208
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05030103
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030401
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24232426
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x24262824
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000E000E
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00180018
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040557
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2766_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2766_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000A6
|
||||||
|
EMC_RFC_0 = 0x00000307
|
||||||
|
EMC_RAS_0 = 0x00000075
|
||||||
|
EMC_RP_0 = 0x00000032
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x00000021
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000032
|
||||||
|
EMC_WR_RCD_0 = 0x00000032
|
||||||
|
EMC_RRD_0 = 0x00000015
|
||||||
|
EMC_REXT_0 = 0x0000001D
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002B
|
||||||
|
EMC_QRST_0 = 0x00080005
|
||||||
|
EMC_QSAFE_0 = 0x00000033
|
||||||
|
EMC_RDV_0 = 0x00000043
|
||||||
|
EMC_REFRESH_0 = 0x000029E3
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001C
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001C
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000027
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000040
|
||||||
|
EMC_TXSR_0 = 0x0000031C
|
||||||
|
EMC_TCKE_0 = 0x00000017
|
||||||
|
EMC_TFAW_0 = 0x00000053
|
||||||
|
EMC_TRPAB_0 = 0x0000003B
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002A23
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000050
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02B40027
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012738A
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000018
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000F
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002B
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000002A
|
||||||
|
EMC_TPD_0 = 0x00000015
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000041
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862B4
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000043
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A78
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005330
|
||||||
|
EMC_TXSRDLL_0 = 0x0000031C
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000035
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003E
|
||||||
|
EMC_TR_QRST_0 = 0x00080005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000035
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000184
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0018000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0017
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0018000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1A1A1B1C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x18141218
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000019
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x171B1717
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x161B1115
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1F1E2121
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1B1F200F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0B161715
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x13110D07
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x151B181B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x161B1717
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000019
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x16141617
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x15151611
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x27262725
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x22251F22
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000020
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1B1A1314
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x17141811
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0509090A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05000007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x070A060A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04070005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08090B0F
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0B0A0A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01080C0A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03020405
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020202
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08030404
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05030103
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07060105
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040401
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25242528
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25252423
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00180018
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040567
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2800_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2800_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000A8
|
||||||
|
EMC_RFC_0 = 0x00000310
|
||||||
|
EMC_RAS_0 = 0x00000076
|
||||||
|
EMC_RP_0 = 0x00000033
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002D
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000033
|
||||||
|
EMC_WR_RCD_0 = 0x00000033
|
||||||
|
EMC_RRD_0 = 0x00000015
|
||||||
|
EMC_REXT_0 = 0x0000001D
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002B
|
||||||
|
EMC_QRST_0 = 0x00080005
|
||||||
|
EMC_QSAFE_0 = 0x0000003E
|
||||||
|
EMC_RDV_0 = 0x00000043
|
||||||
|
EMC_REFRESH_0 = 0x00002A68
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001C
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001C
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000028
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000041
|
||||||
|
EMC_TXSR_0 = 0x00000325
|
||||||
|
EMC_TCKE_0 = 0x00000017
|
||||||
|
EMC_TFAW_0 = 0x00000054
|
||||||
|
EMC_TRPAB_0 = 0x0000003B
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002AA8
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000051
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02BC0028
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012667C
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000018
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000F
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002B
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000002A
|
||||||
|
EMC_TPD_0 = 0x00000015
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000041
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862BC
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000043
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F070B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A9A
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005432
|
||||||
|
EMC_TXSRDLL_0 = 0x00000325
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000035
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003E
|
||||||
|
EMC_TR_QRST_0 = 0x00080005
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||||
|
EMC_IBDLY_0 = 0x10000016
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0B09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000035
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000188
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x80204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200026
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1C1B1C1C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1A151319
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x171B1717
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x161B1115
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x21202222
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1D202211
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x1B212120
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x15130D08
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000010
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x161B191C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x171B1818
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x17161617
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x17161713
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x27282926
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x24262024
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000021
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1B1C1416
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x18161A13
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0409090A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090C060C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060A0007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x09090C10
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0B0A0B00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080C0A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09060100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x04070308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000205
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01010002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x09030405
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x06030104
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050106
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030401
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232527
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25272222
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00190019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x070B070B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040578
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2833_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2833_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000AA
|
||||||
|
EMC_RFC_0 = 0x0000031A
|
||||||
|
EMC_RAS_0 = 0x00000077
|
||||||
|
EMC_RP_0 = 0x00000033
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002E
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000033
|
||||||
|
EMC_WR_RCD_0 = 0x00000033
|
||||||
|
EMC_RRD_0 = 0x00000016
|
||||||
|
EMC_REXT_0 = 0x0000001D
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002B
|
||||||
|
EMC_QRST_0 = 0x00080004
|
||||||
|
EMC_QSAFE_0 = 0x0000003F
|
||||||
|
EMC_RDV_0 = 0x00000043
|
||||||
|
EMC_REFRESH_0 = 0x00002AE9
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001D
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001D
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000005
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000028
|
||||||
|
EMC_AR2PDEN_0 = 0x00000005
|
||||||
|
EMC_RW2PDEN_0 = 0x00000041
|
||||||
|
EMC_TXSR_0 = 0x0000032F
|
||||||
|
EMC_TCKE_0 = 0x00000018
|
||||||
|
EMC_TFAW_0 = 0x00000055
|
||||||
|
EMC_TRPAB_0 = 0x0000003C
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002B29
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000052
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02C50028
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0037
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80125A71
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000003
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000019
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000E
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000002B
|
||||||
|
EMC_TPD_0 = 0x00000016
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000041
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862C5
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000043
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000ABA
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000552D
|
||||||
|
EMC_TXSRDLL_0 = 0x0000032F
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000035
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003F
|
||||||
|
EMC_TR_QRST_0 = 0x00080004
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D08
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000035
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000018D
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0017
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1C1C1C1E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2D2A292D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x191C1A19
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x22232524
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x2F313328
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0D181917
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x15150F0A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000013
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x171D1B1E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x21232121
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1918181A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x19171915
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000017
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2A2B2C28
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x26272225
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000023
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1D1D1617
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1A171B15
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000017
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x050A0A0A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x080B060B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080C09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x01020304
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x09040504
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05030104
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x03020003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020302
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232427
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x24262325
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040589
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D08
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2866_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2866_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000AC
|
||||||
|
EMC_RFC_0 = 0x00000323
|
||||||
|
EMC_RAS_0 = 0x00000079
|
||||||
|
EMC_RP_0 = 0x00000034
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002E
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000034
|
||||||
|
EMC_WR_RCD_0 = 0x00000034
|
||||||
|
EMC_RRD_0 = 0x00000016
|
||||||
|
EMC_REXT_0 = 0x0000001D
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002B
|
||||||
|
EMC_QRST_0 = 0x00080004
|
||||||
|
EMC_QSAFE_0 = 0x0000003F
|
||||||
|
EMC_RDV_0 = 0x00000043
|
||||||
|
EMC_REFRESH_0 = 0x00002B69
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001E
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001E
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000006
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000029
|
||||||
|
EMC_AR2PDEN_0 = 0x00000006
|
||||||
|
EMC_RW2PDEN_0 = 0x00000041
|
||||||
|
EMC_TXSR_0 = 0x00000338
|
||||||
|
EMC_TCKE_0 = 0x00000018
|
||||||
|
EMC_TFAW_0 = 0x00000056
|
||||||
|
EMC_TRPAB_0 = 0x0000003D
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002BA9
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000054
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02CD0029
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012475D
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000004
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000019
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0000
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000014
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000001C
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000002B
|
||||||
|
EMC_TPD_0 = 0x00000016
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430020
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000041
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862CD
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000043
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000ADA
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005628
|
||||||
|
EMC_TXSRDLL_0 = 0x00000338
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000035
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003F
|
||||||
|
EMC_TR_QRST_0 = 0x00080004
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0F09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000035
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000192
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xCC200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0018
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1F1F1F20
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1D19161D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1B1D1B1B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x191D1518
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000016
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x25242625
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x21242513
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000022
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0E191A19
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1816100B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x181F1C1F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x191E1A1A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1B191A1B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1A191B16
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000019
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2B2B2D2A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x27282326
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000024
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1E1F171A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E2A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000018
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03050606
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0C050C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060A0007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x09090B0F
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080C09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0407040A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02030001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0A040505
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x06030104
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09060109
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0A040805
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24242327
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25252225
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00180018
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000018
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040599
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C08
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2900_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2900_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000AE
|
||||||
|
EMC_RFC_0 = 0x0000032C
|
||||||
|
EMC_RAS_0 = 0x0000007A
|
||||||
|
EMC_RP_0 = 0x00000035
|
||||||
|
EMC_R2W_0 = 0x00000032
|
||||||
|
EMC_W2R_0 = 0x0000002E
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000035
|
||||||
|
EMC_WR_RCD_0 = 0x00000035
|
||||||
|
EMC_RRD_0 = 0x00000016
|
||||||
|
EMC_REXT_0 = 0x0000001D
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002B
|
||||||
|
EMC_QRST_0 = 0x00080004
|
||||||
|
EMC_QSAFE_0 = 0x0000003F
|
||||||
|
EMC_RDV_0 = 0x00000043
|
||||||
|
EMC_REFRESH_0 = 0x00002BEE
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001E
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001E
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000006
|
||||||
|
EMC_ACT2PDEN_0 = 0x00000029
|
||||||
|
EMC_AR2PDEN_0 = 0x00000006
|
||||||
|
EMC_RW2PDEN_0 = 0x00000041
|
||||||
|
EMC_TXSR_0 = 0x00000342
|
||||||
|
EMC_TCKE_0 = 0x00000018
|
||||||
|
EMC_TFAW_0 = 0x00000057
|
||||||
|
EMC_TRPAB_0 = 0x0000003D
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002C2E
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000055
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02D50029
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80124258
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000004
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000019
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000E
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000002C
|
||||||
|
EMC_TPD_0 = 0x00000016
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000041
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862D5
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000043
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F070B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000AFB
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000572B
|
||||||
|
EMC_TXSRDLL_0 = 0x00000342
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000035
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003F
|
||||||
|
EMC_TR_QRST_0 = 0x00080004
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0D09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000035
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x00000196
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x80204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0018
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0018
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00010006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00060000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x20202021
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1E19171E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1B1E1B1C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1A1E1519
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000016
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x26262827
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x22252616
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0F1A1B1A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1717110B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000014
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x181F1C1F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1A1E1B1A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1B1A1B1B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1A1A1B16
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000019
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2C2D2E2B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x292B2428
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000025
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1F20171A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1C191E16
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000017
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x050A0A0B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x02000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x080C050C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A090300
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0308040A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000206
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08040504
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04030004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09060108
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09040704
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25212426
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22252123
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00180018
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00190019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000018
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000405AA
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2933_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2933_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000B0
|
||||||
|
EMC_RFC_0 = 0x00000336
|
||||||
|
EMC_RAS_0 = 0x0000007C
|
||||||
|
EMC_RP_0 = 0x00000035
|
||||||
|
EMC_R2W_0 = 0x00000032
|
||||||
|
EMC_W2R_0 = 0x0000002F
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000035
|
||||||
|
EMC_WR_RCD_0 = 0x00000035
|
||||||
|
EMC_RRD_0 = 0x00000016
|
||||||
|
EMC_REXT_0 = 0x0000001C
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002A
|
||||||
|
EMC_QRST_0 = 0x00080002
|
||||||
|
EMC_QSAFE_0 = 0x00000041
|
||||||
|
EMC_RDV_0 = 0x00000043
|
||||||
|
EMC_REFRESH_0 = 0x00002C6F
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001E
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001E
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000006
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000002A
|
||||||
|
EMC_AR2PDEN_0 = 0x00000006
|
||||||
|
EMC_RW2PDEN_0 = 0x00000041
|
||||||
|
EMC_TXSR_0 = 0x0000034C
|
||||||
|
EMC_TCKE_0 = 0x00000018
|
||||||
|
EMC_TFAW_0 = 0x00000058
|
||||||
|
EMC_TRPAB_0 = 0x0000003E
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002CAF
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000055
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02DE002A
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80123147
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000004
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000019
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000C
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002E
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000002C
|
||||||
|
EMC_TPD_0 = 0x00000016
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000041
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862DE
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000043
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B1B
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005826
|
||||||
|
EMC_TXSRDLL_0 = 0x0000034C
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000035
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000041
|
||||||
|
EMC_TR_QRST_0 = 0x00080002
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||||
|
EMC_IBDLY_0 = 0x10000020
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000035
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000019B
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0018
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001A000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0018
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001A000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00260028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x21222122
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1F1B181F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1C201C1C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1C20181B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000018
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x28272A29
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x23262817
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000025
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x101B1E1A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1818120C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1B201D21
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1B201C1C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1D1C1C1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1C1B1C1A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2F2F302E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2A2C272A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000027
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2121191C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1E1B1F17
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x040A090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090D070D
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x070B0008
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x090A0C10
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A090A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080D0A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09080200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0307040A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x06000408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01040004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07040604
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04040005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09060108
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09040603
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25222426
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22232023
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00180018
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001A001A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000018
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000818
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000405BB
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/2966_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/2966_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000B2
|
||||||
|
EMC_RFC_0 = 0x0000033F
|
||||||
|
EMC_RAS_0 = 0x0000007D
|
||||||
|
EMC_RP_0 = 0x00000036
|
||||||
|
EMC_R2W_0 = 0x00000032
|
||||||
|
EMC_W2R_0 = 0x0000002F
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000036
|
||||||
|
EMC_WR_RCD_0 = 0x00000036
|
||||||
|
EMC_RRD_0 = 0x00000017
|
||||||
|
EMC_REXT_0 = 0x0000001D
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002B
|
||||||
|
EMC_QRST_0 = 0x00080003
|
||||||
|
EMC_QSAFE_0 = 0x00000041
|
||||||
|
EMC_RDV_0 = 0x00000044
|
||||||
|
EMC_REFRESH_0 = 0x00002CEF
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x0000001F
|
||||||
|
EMC_PDEX2RD_0 = 0x0000001F
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000006
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000002A
|
||||||
|
EMC_AR2PDEN_0 = 0x00000006
|
||||||
|
EMC_RW2PDEN_0 = 0x00000041
|
||||||
|
EMC_TXSR_0 = 0x00000355
|
||||||
|
EMC_TCKE_0 = 0x00000019
|
||||||
|
EMC_TFAW_0 = 0x00000059
|
||||||
|
EMC_TRPAB_0 = 0x0000003F
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002D2F
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000057
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02E6002A
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012273D
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000004
|
||||||
|
EMC_CKE2PDEN_0 = 0x0000001A
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000D
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002E
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000002D
|
||||||
|
EMC_TPD_0 = 0x00000017
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03E9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000046
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000042
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862E6
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000044
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B3B
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005921
|
||||||
|
EMC_TXSRDLL_0 = 0x00000355
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000036
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000041
|
||||||
|
EMC_TR_QRST_0 = 0x00080003
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00309
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0F09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x0000002B
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x000001A0
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0019
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001A000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230034
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0019
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001A000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00260028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00250027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x23232324
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x201C1A20
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000021
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1E211E1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1C22191C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x2A292A2B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x24282A17
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000025
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x121D1F1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1B1A140E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000017
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1B211E22
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1C211D1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000020
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1E1C1D1E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1D1C1D1B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x3030322E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2B2D272B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000029
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x23221B1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1F1C211A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x040A0A0A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090E070E
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x070B0008
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x090A0C10
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A090B00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000008
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00090D0A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A080200
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090509
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03070609
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03080B07
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x08030802
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x09040604
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x06040105
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08050107
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08030503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24222327
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22262925
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00190019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001A001A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000818
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000405CB
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/3000_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/3000_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000B4
|
||||||
|
EMC_RFC_0 = 0x00000348
|
||||||
|
EMC_RAS_0 = 0x0000007E
|
||||||
|
EMC_RP_0 = 0x00000036
|
||||||
|
EMC_R2W_0 = 0x00000032
|
||||||
|
EMC_W2R_0 = 0x0000002F
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000036
|
||||||
|
EMC_WR_RCD_0 = 0x00000036
|
||||||
|
EMC_RRD_0 = 0x00000017
|
||||||
|
EMC_REXT_0 = 0x0000001D
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002B
|
||||||
|
EMC_QRST_0 = 0x00080003
|
||||||
|
EMC_QSAFE_0 = 0x00000041
|
||||||
|
EMC_RDV_0 = 0x00000044
|
||||||
|
EMC_REFRESH_0 = 0x00002D74
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000020
|
||||||
|
EMC_PDEX2RD_0 = 0x00000020
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000006
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000002A
|
||||||
|
EMC_AR2PDEN_0 = 0x00000006
|
||||||
|
EMC_RW2PDEN_0 = 0x00000041
|
||||||
|
EMC_TXSR_0 = 0x0000035F
|
||||||
|
EMC_TCKE_0 = 0x00000019
|
||||||
|
EMC_TFAW_0 = 0x0000005A
|
||||||
|
EMC_TRPAB_0 = 0x0000003F
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002DB4
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000058
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02EE002A
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80121A30
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000004
|
||||||
|
EMC_CKE2PDEN_0 = 0x0000001A
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000D
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002E
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000002D
|
||||||
|
EMC_TPD_0 = 0x00000017
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000046
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000042
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862EE
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000044
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B5D
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005A23
|
||||||
|
EMC_TXSRDLL_0 = 0x0000035F
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000036
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000041
|
||||||
|
EMC_TR_QRST_0 = 0x00080003
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00310
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0C08
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000036
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x000001A4
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0019
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001A000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230034
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0019
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001A000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250029
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x24252525
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x221C1A22
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000021
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1F221F1F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1D231A1C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x2A2A2C2B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x25282B19
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000026
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x131F211E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1B1B160F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000018
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1C231F23
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1E221E1E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1F1D1D1F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1E1D1F1B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x3232332F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2D2F2A2C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000002A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x24241C1E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x060A0A0B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06010007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090D070C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060A0007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0A0A0D10
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09080A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00090E0A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A080201
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060409
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x06000308
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01040104
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0A050605
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x07040105
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04030103
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08040503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23202225
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x23272023
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00190019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001A001A
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000818
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000405DC
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C08
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/3033_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/3033_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000B6
|
||||||
|
EMC_RFC_0 = 0x00000352
|
||||||
|
EMC_RAS_0 = 0x0000007F
|
||||||
|
EMC_RP_0 = 0x00000037
|
||||||
|
EMC_R2W_0 = 0x00000032
|
||||||
|
EMC_W2R_0 = 0x00000030
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000037
|
||||||
|
EMC_WR_RCD_0 = 0x00000037
|
||||||
|
EMC_RRD_0 = 0x00000017
|
||||||
|
EMC_REXT_0 = 0x0000001D
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002B
|
||||||
|
EMC_QRST_0 = 0x00080002
|
||||||
|
EMC_QSAFE_0 = 0x00000042
|
||||||
|
EMC_RDV_0 = 0x00000044
|
||||||
|
EMC_REFRESH_0 = 0x00002DF5
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000020
|
||||||
|
EMC_PDEX2RD_0 = 0x00000020
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000006
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000002B
|
||||||
|
EMC_AR2PDEN_0 = 0x00000006
|
||||||
|
EMC_RW2PDEN_0 = 0x00000041
|
||||||
|
EMC_TXSR_0 = 0x00000368
|
||||||
|
EMC_TCKE_0 = 0x00000019
|
||||||
|
EMC_TFAW_0 = 0x0000005B
|
||||||
|
EMC_TRPAB_0 = 0x0000003F
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002E35
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x00000059
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02F7002B
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80120D22
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000004
|
||||||
|
EMC_CKE2PDEN_0 = 0x0000001A
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000C
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002F
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000018
|
||||||
|
EMC_TPD_0 = 0x00000017
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000046
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000042
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862F7
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000044
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B7D
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005B1E
|
||||||
|
EMC_TXSRDLL_0 = 0x00000368
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000036
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000042
|
||||||
|
EMC_TR_QRST_0 = 0x00080002
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00310
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000C
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0B08
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000036
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x000001A9
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0019
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001B000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230034
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0019
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001B000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x25262627
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x231E1B23
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000022
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x20232020
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1F241B1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000001B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x2C2B2C2C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x27292C1A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000026
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x1B212120
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1E1C1611
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000001B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1E262125
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x20252020
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000024
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x211E1F21
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x201E201C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x33343531
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2E302B2E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000002C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x25251D1F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x211E231B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0409090A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05000006
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090D070C
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060A0007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x090A0D10
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x04040400
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000008
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00090C09
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09060100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0008040A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0307040A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05000408
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08040603
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04030005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09070209
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0A040705
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x22212226
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x21232023
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00190019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001B001B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B08
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
528
timings/Mariko/AA/1866/emc/3066_emc.txt
Normal file
528
timings/Mariko/AA/1866/emc/3066_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x000000B7
|
||||||
|
EMC_RFC_0 = 0x0000035B
|
||||||
|
EMC_RAS_0 = 0x0000007F
|
||||||
|
EMC_RP_0 = 0x00000038
|
||||||
|
EMC_R2W_0 = 0x00000032
|
||||||
|
EMC_W2R_0 = 0x00000030
|
||||||
|
EMC_R2P_0 = 0x0000000E
|
||||||
|
EMC_W2P_0 = 0x00000033
|
||||||
|
EMC_RD_RCD_0 = 0x00000038
|
||||||
|
EMC_WR_RCD_0 = 0x00000038
|
||||||
|
EMC_RRD_0 = 0x00000017
|
||||||
|
EMC_REXT_0 = 0x0000001D
|
||||||
|
EMC_WDV_0 = 0x00000010
|
||||||
|
EMC_QUSE_0 = 0x0000002B
|
||||||
|
EMC_QRST_0 = 0x00080002
|
||||||
|
EMC_QSAFE_0 = 0x00000042
|
||||||
|
EMC_RDV_0 = 0x00000044
|
||||||
|
EMC_REFRESH_0 = 0x00002E75
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000020
|
||||||
|
EMC_PDEX2RD_0 = 0x00000020
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000006
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000002B
|
||||||
|
EMC_AR2PDEN_0 = 0x00000006
|
||||||
|
EMC_RW2PDEN_0 = 0x00000041
|
||||||
|
EMC_TXSR_0 = 0x00000372
|
||||||
|
EMC_TCKE_0 = 0x00000019
|
||||||
|
EMC_TFAW_0 = 0x0000005C
|
||||||
|
EMC_TRPAB_0 = 0x0000003F
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001F
|
||||||
|
EMC_TREFBW_0 = 0x00002EB5
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000005A
|
||||||
|
EMC_WEXT_0 = 0x00000019
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x02FF002B
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0038
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x80120C21
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000004
|
||||||
|
EMC_CKE2PDEN_0 = 0x0000001B
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x88020036
|
||||||
|
EMC_MRW3_0 = 0x8C0D0010
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x0000000C
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x0000002F
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x0000002E
|
||||||
|
EMC_TPD_0 = 0x00000017
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000046
|
||||||
|
EMC_WDV_MASK_0 = 0x00000010
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000042
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x011862FF
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000044
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B9D
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005C19
|
||||||
|
EMC_TXSRDLL_0 = 0x00000372
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000036
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||||
|
EMC_TR_QSAFE_0 = 0x00000042
|
||||||
|
EMC_TR_QRST_0 = 0x00080002
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00309
|
||||||
|
EMC_IBDLY_0 = 0x10000021
|
||||||
|
EMC_OBDLY_0 = 0x10000002
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000A
|
||||||
|
EMC_WSV_0 = 0x0000000E
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0A09
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000036
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x000001AE
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x00100019
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001B000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230034
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x00100019
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001B000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200027
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x24242424
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x231D1B23
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1F211F1F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1F24191D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000001A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x27272C2A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x25262A19
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000025
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x131E1F1E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1D1B150F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000019
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x20252224
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x20242022
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1D1D1F1C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x3031322E
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2B2D2A2B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000027
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x25251C1D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x221D2419
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x060B0B0B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x07000008
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090D060D
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060B0008
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0B0A0C10
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0B0A0A00
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000009
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080D0A
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A080300
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0008050B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0306040B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05000307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00010001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08070307
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050604
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25232526
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22241F24
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00190019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001B001B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000019
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000819
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x000405FD
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000A09
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
288
timings/Mariko/AA/1866/mc/1866_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/1866_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD3B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77D584D1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000007
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000001C
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x000F0A0E
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x726E2A1D
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000041
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x000000F2
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000335
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001B
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x00001501
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x006D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x006D0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x006D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x006D0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x006D006D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x006D0019
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x006D0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x006D0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x006D0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x006D003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000006D
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x006D0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x006D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000006D
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080013
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x006D0016
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x006D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x006D0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2133_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2133_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E6E341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B10
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72703021
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004A
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00600004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00600038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00600005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00600014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00600060
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00600016
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00600095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00600041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00600080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0060003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00600013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000060
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00600090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00600004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000060
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080011
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00600013
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00600005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00600018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2166_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2166_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD3B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E7F4D1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000010
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00100B10
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72713121
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x08130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004B
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005E0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005E0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005E0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005E0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005E005E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005E0015
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005E0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005E0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005E0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005E003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005E0013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005E
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005E0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005E0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005E0013
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005E0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005E0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2200_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2200_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E63341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000010
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80030080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110B10
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72713222
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004C
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005D0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005D0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005D005D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005D0015
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005D0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005D0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005D0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005D003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005D0012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005D
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005D0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005D
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005D0012
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005D0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2233_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2233_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01010200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E85341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000010
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110B10
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72713322
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004E
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005B0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005B0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005B0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005B0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005B005B
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005B0015
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005B0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005B0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005B0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005B003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005B0012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005B
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005B0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005B0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005B
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005B0012
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005B0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005B0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2266_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2266_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x79FBF7A0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E77541
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110B11
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72713323
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80050080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x00001060
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02002000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000037
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005A0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005A0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005A0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005A0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005A005A
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005A0014
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005A0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005A0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005A0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005A003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005A0012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005A
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005A0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005A0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005A
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005A0012
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005A0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00800018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2300_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2300_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x68372880
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x456B4F41
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000011
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C11
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72723423
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000050
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00590004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00590038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00590005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00590014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00590059
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00590014
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00590095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00590041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00590080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0059003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00590012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000059
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00590090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00590004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000059
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00590012
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00590005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00590018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2333_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2333_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD4B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x7ABA9521
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000011
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C11
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72723523
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000051
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00570004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00570038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00570005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00570014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00570057
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00570014
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00570095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00570041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00570080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0057003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00570011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000057
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00570090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00570004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000057
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00570011
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00570005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00570018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2366_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2366_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFC5B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E06141
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000011
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000023
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00110C11
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72723624
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02121000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000052
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00560004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00560038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00560005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00560014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00560056
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00560013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00560095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00560041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00560080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0056003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00560011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000056
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00560090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00560004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000056
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00560011
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00560005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00560018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2400_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2400_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01211200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E3D341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C12
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72723625
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000400C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000053
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00550004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00550038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00550005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00550014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00550055
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00550013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00550095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00550041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00550080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0055003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00550011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000055
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00550090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00550004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000055
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00550011
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00550005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00550018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2433_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2433_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01211200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77CE0341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000012
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C12
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72733725
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000055
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00540004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00540038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00540005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00540014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00540054
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00540013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00540095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00540041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00540080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0054003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00540011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000054
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00540090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00540004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000054
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00540011
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00540005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00540018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2466_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2466_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E38341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000012
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80030080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06060000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C12
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72733826
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000400C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000056
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00530004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00530038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00530005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00530014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00530053
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00530013
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00800095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00530041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00530080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0053003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00530010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000053
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00530090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00530004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000053
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00530010
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00530005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00530018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2500_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2500_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E3A341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000012
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80100080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C12
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72733926
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80030080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02930800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000057
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00510004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00510038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00510005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00510014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00510051
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00510012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00510095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00510041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00510080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0051003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00510010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000051
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00510090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00510004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000051
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00510010
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00510005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00510018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2533_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2533_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01211200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x7878C351
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000013
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00120D13
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72733927
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000020C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000058
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00500004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00500038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00500005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00500014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00500050
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00500012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00500095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00500041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00500080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0050003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00500010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000050
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00500090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00500004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000050
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00500010
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00500005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00500018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
288
timings/Mariko/AA/1866/mc/2566_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2566_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000F839B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x3596FE41
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000013
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80090080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00120D13
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72743A27
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x00000040
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000059
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004F0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004F0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004F0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004F0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004F004F
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004F0012
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004F0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004F0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004F0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004F003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004F0010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004F
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004F0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004F0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004F
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004F0010
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004F0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004F0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||||
56
timings/Mariko/AA/1866/mc/2600_mc.txt
Normal file
56
timings/Mariko/AA/1866/mc/2600_mc.txt
Normal file
@@ -0,0 +1,56 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
mc_emem_arb_cfg = 0x08000013
|
||||||
|
mc_emem_arb_outstanding_req = 0x80040080
|
||||||
|
mc_emem_arb_timing_rcd = 0x0000000A
|
||||||
|
mc_emem_arb_timing_rp = 0x0000000B
|
||||||
|
mc_emem_arb_timing_rc = 0x00000027
|
||||||
|
mc_emem_arb_timing_ras = 0x0000001A
|
||||||
|
mc_emem_arb_timing_faw = 0x00000013
|
||||||
|
mc_emem_arb_timing_rrd = 0x00000004
|
||||||
|
mc_emem_arb_timing_rap2pre = 0x00000004
|
||||||
|
mc_emem_arb_timing_wap2pre = 0x0000000F
|
||||||
|
mc_emem_arb_timing_r2r = 0x00000001
|
||||||
|
mc_emem_arb_timing_w2w = 0x00000001
|
||||||
|
mc_emem_arb_timing_r2w = 0x0000000E
|
||||||
|
mc_emem_arb_timing_w2r = 0x0000000C
|
||||||
|
mc_emem_arb_da_turns = 0x06070000
|
||||||
|
mc_emem_arb_da_covers = 0x00120D13
|
||||||
|
mc_emem_arb_misc0 = 0x72743B28
|
||||||
|
mc_emem_arb_misc1 = 0x70000F0F
|
||||||
|
mc_emem_arb_misc2 = 0x00000000
|
||||||
|
mc_emem_arb_ring1_throttle = 0x001F0000
|
||||||
|
mc_emem_arb_timing_rfcpb = 0x0000005A
|
||||||
|
mc_emem_arb_timing_ccdmw = 0x00000008
|
||||||
|
mc_emem_arb_dhyst_ctrl = 0x000A1020
|
||||||
|
mc_emem_arb_dhyst_timeout_util_0 = 0x0000001A
|
||||||
|
mc_emem_arb_dhyst_timeout_util_1 = 0x0000001A
|
||||||
|
mc_emem_arb_dhyst_timeout_util_2 = 0x0000001A
|
||||||
|
mc_emem_arb_dhyst_timeout_util_3 = 0x0000001A
|
||||||
|
mc_emem_arb_dhyst_timeout_util_4 = 0x0000001A
|
||||||
|
mc_emem_arb_dhyst_timeout_util_5 = 0x0000001A
|
||||||
|
mc_emem_arb_dhyst_timeout_util_6 = 0x0000001A
|
||||||
|
mc_emem_arb_dhyst_timeout_util_7 = 0x0000001A
|
||||||
|
mc_mll_mpcorer_ptsa_rate = 0x00000115
|
||||||
|
mc_ftop_ptsa_rate = 0x00000000
|
||||||
|
mc_ptsa_grant_decrement = 0x000017FF
|
||||||
|
mc_latency_allowance_avpc_0 = 0x004E0004
|
||||||
|
mc_latency_allowance_sdmmcaa_0 = 0x004E0005
|
||||||
|
mc_latency_allowance_sdmmca_0 = 0x004E0014
|
||||||
|
mc_latency_allowance_isp2_0 = 0x0000002C
|
||||||
|
mc_latency_allowance_isp2_1 = 0x004E004E
|
||||||
|
mc_latency_allowance_vic_0 = 0x004E0012
|
||||||
|
mc_latency_allowance_nvdec_0 = 0x004E0095
|
||||||
|
mc_latency_allowance_tsec_0 = 0x004E0041
|
||||||
|
mc_latency_allowance_ppcs_1 = 0x004E0080
|
||||||
|
mc_latency_allowance_xusb_0 = 0x004E003D
|
||||||
|
mc_latency_allowance_ppcs_0 = 0x00340049
|
||||||
|
mc_latency_allowance_gpu2_0 = 0x004E0010
|
||||||
|
mc_latency_allowance_hc_1 = 0x0000004E
|
||||||
|
mc_latency_allowance_sdmmc_0 = 0x004E0090
|
||||||
|
mc_latency_allowance_mpcore_0 = 0x004E0004
|
||||||
|
mc_latency_allowance_vi2_0 = 0x0000004E
|
||||||
|
mc_latency_allowance_hc_0 = 0x0008000E
|
||||||
|
mc_latency_allowance_gpu_0 = 0x004E0010
|
||||||
|
mc_latency_allowance_sdmmcab_0 = 0x004E0005
|
||||||
|
mc_latency_allowance_nvenc_0 = 0x004E0018
|
||||||
288
timings/Mariko/AA/1866/mc/2633_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2633_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01211200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E3F341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000013
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00130D13
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005C
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004D0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004D0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004D004D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004D0011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004D0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004D0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004D0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004D003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004D000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004D
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004D0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004D0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004D
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004D000F
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004D0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004D0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2666_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2666_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCBB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E372C1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000014
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00130D13
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x00001060
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02022000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005D
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004C0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004C0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004C0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004C0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004C004C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004C0011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004C0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004C0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004C0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004C003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004C000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004C
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004C0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004C0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004C
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004C000F
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004C0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004C0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2700_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2700_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x01010200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFB9B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x104AEE61
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000014
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000028
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001B
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00130D14
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72753D29
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000020C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x00063090
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005E
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004B0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00800038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004B0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004B004B
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004B0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004B0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004B0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004B003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004B000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004B0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004B0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004B
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004B000F
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004B0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004B0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2733_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2733_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77C89261
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000014
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000029
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001B
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00130E14
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72753E2A
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005F
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004A0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004A0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004A0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004A0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004A004A
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004A0011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004A0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004A0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004A0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004A003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004A000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004A
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004A0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004A0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004A
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004A000F
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004A0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004A0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2766_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2766_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD8B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E71611
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000014
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x00000029
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001C
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00130E14
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72753F2A
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x001E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x003E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80090080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000060
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004A0004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004A0038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004A0005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004A0014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004A004A
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004A0011
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004A0095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004A0041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004A0080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004A003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004A000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004A
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004A0090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004A0004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004A
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004A000F
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004A0005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004A0018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2800_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2800_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x11010200
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCAB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E8C291
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000015
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80080080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002A
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001C
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x000D080C
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x72753F2B
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000020C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80050080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000230B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x08130850
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000061
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x00000DB7
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00490038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00490005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00490014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00490049
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00490010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00490095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00490041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00490080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0049003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0049000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000049
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00490090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00490004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000049
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0049000E
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00490005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00490018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2833_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2833_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFC8B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E64231
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000015
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002A
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001C
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00130E15
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x7276402B
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x001E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x003E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000400C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A110800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000063
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00480004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00480038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00480005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00480014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00480048
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00480010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00480095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00480041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00480080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0048003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0048000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000048
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00480090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00480004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000048
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0048000E
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00480005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00480018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2866_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2866_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCBB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x787982C1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000015
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002B
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001D
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E15
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x7276412C
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000620F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000064
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00470004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00470038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00470005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00470014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00470047
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00470010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00470095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00470041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00470080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0047003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0047000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000047
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00470090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00470004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000047
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0047000E
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00470005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00470018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2900_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2900_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E64541
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000015
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002B
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001D
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E15
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x7276422C
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A930850
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000065
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00460004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00460038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00460005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00460014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00460046
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00460010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00460095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00460041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00460080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0046003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0046000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000046
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00460090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00460004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000046
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0046000E
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00460005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00460018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2933_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2933_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0xF3010780
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFC1B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E6EAE1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002C
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001D
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E16
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x7276422D
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C111020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000066
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00450004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00450038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00450005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00450014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00450045
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00450010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00450095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00450041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00450080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0045003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0045000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000045
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00450090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00450004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000045
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0045000E
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00450005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00450018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/2966_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/2966_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0xF300A680
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCFB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E623F1
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x04000016
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80030080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002C
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00140F16
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x7257432D
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130800
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000067
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x00000011
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00450004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00450038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00450005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00450014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00450045
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00450010
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00450095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00450041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00450080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0045003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0045000E
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000045
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00450090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00450004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000045
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0045000E
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00800005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00450018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/3000_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/3000_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E7C341
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x08000016
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002C
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00140F16
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x7277442D
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x00001060
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A511000
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000068
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00440004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00440038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00440005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00440014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00440044
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0044000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00990095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00440041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00440080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0044003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0044000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000044
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00440090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00440004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000044
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0044000D
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00440005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00440018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/3033_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/3033_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFD1B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77DC7451
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x0C000016
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00140F16
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x7277452E
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C1914A0
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x801C0080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000410A0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006A
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00430004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00430038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00430005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00430014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00430043
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0043000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00430095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00430041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00430080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0043003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0043000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00430090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00430004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000043
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0043000D
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00430005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00430018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
288
timings/Mariko/AA/1866/mc/3066_mc.txt
Normal file
288
timings/Mariko/AA/1866/mc/3066_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
|||||||
|
Dumping MC registers from BASE=0x70019000
|
||||||
|
-----------------------------------
|
||||||
|
MC_ERR_ADR_0 = 0x4AC01800
|
||||||
|
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||||
|
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||||
|
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||||
|
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||||
|
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||||
|
MC_SMMU_TLB_FLUSH_0 = 0x000FFC5B
|
||||||
|
MC_SMMU_PTC_FLUSH_0 = 0x77E3D141
|
||||||
|
MC_EMEM_CFG_0 = 0x00001000
|
||||||
|
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||||
|
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||||
|
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||||
|
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||||
|
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||||
|
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_ARB_CFG_0 = 0x00000017
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80090080
|
||||||
|
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||||
|
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||||
|
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||||
|
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||||
|
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||||
|
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||||
|
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000F
|
||||||
|
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||||
|
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||||
|
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||||
|
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||||
|
MC_EMEM_ARB_DA_COVERS_0 = 0x00150F16
|
||||||
|
MC_EMEM_ARB_MISC0_0 = 0x7277452E
|
||||||
|
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||||
|
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||||
|
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||||
|
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||||
|
MC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
MC_STAT_CONTROL_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||||
|
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||||
|
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||||
|
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||||
|
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||||
|
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||||
|
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||||
|
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||||
|
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||||
|
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||||
|
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||||
|
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||||
|
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||||
|
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_ERR_SEC_STATUS_0 = 0x000230B0
|
||||||
|
MC_ERR_SEC_ADR_0 = 0x08130810
|
||||||
|
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||||
|
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||||
|
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006B
|
||||||
|
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||||
|
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||||
|
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||||
|
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||||
|
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||||
|
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||||
|
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||||
|
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||||
|
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||||
|
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||||
|
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||||
|
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||||
|
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||||
|
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||||
|
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||||
|
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||||
|
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||||
|
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||||
|
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||||
|
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||||
|
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||||
|
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||||
|
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||||
|
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||||
|
MC_DA_CONFIG0_0 = 0x00000001
|
||||||
|
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||||
|
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||||
|
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||||
|
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||||
|
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||||
|
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||||
|
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||||
|
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||||
|
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||||
|
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||||
|
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||||
|
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||||
|
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||||
|
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||||
|
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||||
|
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||||
|
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||||
|
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||||
|
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||||
|
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00420004
|
||||||
|
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00420038
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00420005
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00420014
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||||
|
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00420042
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0042000F
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00420095
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00420041
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00420080
|
||||||
|
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0042003D
|
||||||
|
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||||
|
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||||
|
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0042000D
|
||||||
|
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000042
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00420090
|
||||||
|
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||||
|
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||||
|
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||||
|
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00420004
|
||||||
|
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000042
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||||
|
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||||
|
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||||
|
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||||
|
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0042000D
|
||||||
|
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00990005
|
||||||
|
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||||
|
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00420018
|
||||||
|
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||||
528
timings/Mariko/AA/2133/emc/2133_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2133_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
|||||||
|
Dumping EMC registers from BASE=0x7001B000
|
||||||
|
-----------------------------------
|
||||||
|
EMC_INTSTATUS_0 = 0x00000030
|
||||||
|
EMC_INTMASK_0 = 0x00000000
|
||||||
|
EMC_DBG_0 = 0x01000C00
|
||||||
|
EMC_CFG_0 = 0xF3200000
|
||||||
|
EMC_ADR_CFG_0 = 0x00000000
|
||||||
|
EMC_REFCTRL_0 = 0x80000002
|
||||||
|
EMC_PIN_0 = 0x00003101
|
||||||
|
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||||
|
EMC_RC_0 = 0x00000080
|
||||||
|
EMC_RFC_0 = 0x00000256
|
||||||
|
EMC_RAS_0 = 0x0000005A
|
||||||
|
EMC_RP_0 = 0x00000027
|
||||||
|
EMC_R2W_0 = 0x00000031
|
||||||
|
EMC_W2R_0 = 0x0000002B
|
||||||
|
EMC_R2P_0 = 0x00000010
|
||||||
|
EMC_W2P_0 = 0x0000003B
|
||||||
|
EMC_RD_RCD_0 = 0x00000027
|
||||||
|
EMC_WR_RCD_0 = 0x00000027
|
||||||
|
EMC_RRD_0 = 0x00000010
|
||||||
|
EMC_REXT_0 = 0x0000001A
|
||||||
|
EMC_WDV_0 = 0x00000012
|
||||||
|
EMC_QUSE_0 = 0x0000002C
|
||||||
|
EMC_QRST_0 = 0x0007000D
|
||||||
|
EMC_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_RDV_0 = 0x00000043
|
||||||
|
EMC_REFRESH_0 = 0x0000203F
|
||||||
|
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||||
|
EMC_PDEX2WR_0 = 0x00000016
|
||||||
|
EMC_PDEX2RD_0 = 0x00000016
|
||||||
|
EMC_PCHG2PDEN_0 = 0x00000004
|
||||||
|
EMC_ACT2PDEN_0 = 0x0000001E
|
||||||
|
EMC_AR2PDEN_0 = 0x00000004
|
||||||
|
EMC_RW2PDEN_0 = 0x00000047
|
||||||
|
EMC_TXSR_0 = 0x00000266
|
||||||
|
EMC_TCKE_0 = 0x00000012
|
||||||
|
EMC_TFAW_0 = 0x00000040
|
||||||
|
EMC_TRPAB_0 = 0x0000002D
|
||||||
|
EMC_TCLKSTABLE_0 = 0x00000004
|
||||||
|
EMC_TCLKSTOP_0 = 0x0000001A
|
||||||
|
EMC_TREFBW_0 = 0x0000207F
|
||||||
|
EMC_TPPD_0 = 0x00000004
|
||||||
|
EMC_ODT_WRITE_0 = 0x00000000
|
||||||
|
EMC_PDEX2MRR_0 = 0x0000003F
|
||||||
|
EMC_WEXT_0 = 0x00000016
|
||||||
|
EMC_RFC_SLR_0 = 0x00000000
|
||||||
|
EMC_MRS_WAIT_CNT2_0 = 0x0216001E
|
||||||
|
EMC_MRS_WAIT_CNT_0 = 0x07FF0039
|
||||||
|
EMC_MRS_0 = 0x00000000
|
||||||
|
EMC_EMRS_0 = 0x00000000
|
||||||
|
EMC_REF_0 = 0x80000000
|
||||||
|
EMC_PRE_0 = 0x00000000
|
||||||
|
EMC_NOP_0 = 0x00000000
|
||||||
|
EMC_SELF_REF_0 = 0x00000000
|
||||||
|
EMC_DPD_0 = 0x00000000
|
||||||
|
EMC_MRW_0 = 0x00170040
|
||||||
|
EMC_MRR_0 = 0x8012CBE9
|
||||||
|
EMC_CMDQ_0 = 0x10004408
|
||||||
|
EMC_MC2EMCQ_0 = 0x06000404
|
||||||
|
EMC_FBIO_SPARE_0 = 0x00000012
|
||||||
|
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||||
|
EMC_FBIO_CFG6_0 = 0x00001010
|
||||||
|
EMC_PDEX2CKE_0 = 0x00000002
|
||||||
|
EMC_CKE2PDEN_0 = 0x00000013
|
||||||
|
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||||
|
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||||
|
EMC_MPC_0 = 0x0000004B
|
||||||
|
EMC_EMRS2_0 = 0x00000000
|
||||||
|
EMC_EMRS3_0 = 0x00000000
|
||||||
|
EMC_MRW2_0 = 0x8802003F
|
||||||
|
EMC_MRW3_0 = 0x8C0D00D0
|
||||||
|
EMC_MRW4_0 = 0xC0000000
|
||||||
|
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||||
|
EMC_R2R_0 = 0x00000000
|
||||||
|
EMC_W2W_0 = 0x00000000
|
||||||
|
EMC_EINPUT_0 = 0x00000016
|
||||||
|
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||||
|
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||||
|
EMC_TCKESR_0 = 0x00000020
|
||||||
|
EMC_TPD_0 = 0x00000010
|
||||||
|
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||||
|
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||||
|
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||||
|
EMC_REQ_CTRL_0 = 0x00000000
|
||||||
|
EMC_EMC_STATUS_0 = 0x0B430035
|
||||||
|
EMC_CFG_2_0 = 0x0011083D
|
||||||
|
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||||
|
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||||
|
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||||
|
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||||
|
EMC_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_WDV_MASK_0 = 0x00000012
|
||||||
|
EMC_RDV_EARLY_MASK_0 = 0x00000043
|
||||||
|
EMC_RDV_EARLY_0 = 0x00000041
|
||||||
|
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||||
|
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||||
|
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||||
|
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||||
|
EMC_ZQ_CAL_0 = 0x80000002
|
||||||
|
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||||
|
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||||
|
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||||
|
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||||
|
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||||
|
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||||
|
EMC_SCRATCH0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||||
|
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||||
|
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||||
|
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||||
|
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||||
|
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||||
|
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||||
|
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||||
|
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||||
|
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||||
|
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||||
|
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||||
|
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||||
|
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||||
|
EMC_TR_TIMING_0_0 = 0x01186216
|
||||||
|
EMC_TR_CTRL_0_0 = 0x00000020
|
||||||
|
EMC_TR_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||||
|
EMC_TR_RDV_0 = 0x00000043
|
||||||
|
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_ = 0x3F1F070A
|
||||||
|
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||||
|
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000080F
|
||||||
|
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004062
|
||||||
|
EMC_TXSRDLL_0 = 0x00000266
|
||||||
|
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||||
|
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||||
|
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||||
|
EMC_TR_QPOP_0 = 0x00000035
|
||||||
|
EMC_TR_RDV_MASK_0 = 0x00000045
|
||||||
|
EMC_TR_QSAFE_0 = 0x0000003D
|
||||||
|
EMC_TR_QRST_0 = 0x0007000D
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||||
|
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||||
|
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||||
|
EMC_ISSUE_QRST_0 = 0x00000000
|
||||||
|
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||||
|
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||||
|
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||||
|
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||||
|
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||||
|
EMC_TR_DVFS_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||||
|
EMC_IBDLY_0 = 0x10000023
|
||||||
|
EMC_OBDLY_0 = 0x10000006
|
||||||
|
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||||
|
EMC_WE_DURATION_0 = 0x0000000E
|
||||||
|
EMC_WS_DURATION_0 = 0x00000008
|
||||||
|
EMC_WEV_0 = 0x0000000E
|
||||||
|
EMC_WSV_0 = 0x00000010
|
||||||
|
EMC_CFG_3_0 = 0x00000040
|
||||||
|
EMC_MRW5_0 = 0x00000000
|
||||||
|
EMC_MRW6_0 = 0x8803F1F1
|
||||||
|
EMC_MRW7_0 = 0xC803F1F1
|
||||||
|
EMC_MRW8_0 = 0x880B0606
|
||||||
|
EMC_MRW9_0 = 0x8C0E5D5D
|
||||||
|
EMC_MRW10_0 = 0x880C5D5D
|
||||||
|
EMC_MRW11_0 = 0xC80C5D5D
|
||||||
|
EMC_MRW12_0 = 0x880E0A0B
|
||||||
|
EMC_MRW13_0 = 0xC80E0000
|
||||||
|
EMC_MRW14_0 = 0x88161414
|
||||||
|
EMC_MRW15_0 = 0xC8161414
|
||||||
|
EMC_CFG_SYNC_0 = 0x00000001
|
||||||
|
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||||
|
EMC_WDV_CHK_0 = 0x00000006
|
||||||
|
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||||
|
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||||
|
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||||
|
EMC_QPOP_0 = 0x00000035
|
||||||
|
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||||
|
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||||
|
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||||
|
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||||
|
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||||
|
EMC_REFCTRL2_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||||
|
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||||
|
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_RFCPB_0 = 0x0000012B
|
||||||
|
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||||
|
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||||
|
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||||
|
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||||
|
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||||
|
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||||
|
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||||
|
EMC_CCDMW_0 = 0x00000020
|
||||||
|
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||||
|
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||||
|
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||||
|
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||||
|
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||||
|
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||||
|
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||||
|
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||||
|
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||||
|
EMC_DLL_CFG_1_0 = 0x00012014
|
||||||
|
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||||
|
EMC_CFG_UPDATE_0 = 0x70000301
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000A0000
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||||
|
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000A0000
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240026
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210024
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||||
|
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||||
|
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||||
|
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||||
|
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||||
|
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||||
|
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x3E3F3F40
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x3D39383C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000003C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3A3C3938
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x383C3438
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000035
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x43424343
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x3F414236
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000040
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x323A3B39
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3837332F
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000035
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x393D3B3D
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3A3D393B
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003C
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3A39393A
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3A393A37
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000039
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08080907
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04070204
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3D3D3839
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x3B393C36
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000038
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080707
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010005
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06090309
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0708090B
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060907
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070406
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050507
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010304
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020001
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040503
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040004
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03010100
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x28262627
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28252729
|
||||||
|
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||||
|
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000B
|
||||||
|
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||||
|
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||||
|
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||||
|
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||||
|
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||||
|
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||||
|
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||||
|
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||||
|
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||||
|
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||||
|
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||||
|
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||||
|
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||||
|
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||||
|
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||||
|
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||||
|
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||||
|
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||||
|
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||||
|
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||||
|
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||||
|
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||||
|
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||||
|
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||||
|
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||||
|
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||||
|
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||||
|
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||||
|
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||||
|
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||||
|
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||||
|
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||||
|
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||||
|
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||||
|
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||||
|
EMC_TRAINING_MPC_0 = 0x00000000
|
||||||
|
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||||
|
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||||
|
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||||
|
EMC_TRAINING_VREF_SETTLE_0 = 0x0004042B
|
||||||
|
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||||
|
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||||
|
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user