Clean up, replaced 2600Mhz 2133bl with correct file, added scripts.
This commit is contained in:
Lightos1
288
timings/Mariko/AA/2133/mc/2133_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2133_mc.txt
Normal file
@@ -0,0 +1,288 @@
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Dumping MC registers from BASE=0x70019000
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-----------------------------------
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MC_ERR_ADR_0 = 0x7FFFFFE0
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MC_SMMU_CONFIG_0 = 0xFFFFFFFF
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MC_SMMU_TLB_CONFIG_0 = 0x30000030
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MC_SMMU_PTC_CONFIG_0 = 0x2800003F
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MC_SMMU_PTB_ASID_0 = 0x0000000C
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MC_SMMU_PTB_DATA_0 = 0xE00FF80C
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MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
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MC_SMMU_PTC_FLUSH_0 = 0x77E6A271
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MC_EMEM_CFG_0 = 0x00001000
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MC_EMEM_ROW_WIDTH = 0x00000000
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MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
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MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
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MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
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MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
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MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
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MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
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MC_SECURITY_CFG0_0 = 0xFFFFFFFF
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MC_SECURITY_CFG1_0 = 0xFFFFFFFF
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MC_EMEM_ARB_CFG_0 = 0x00000010
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MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
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MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
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MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
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MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
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MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
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MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
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MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
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MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
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MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
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MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
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MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
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MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
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MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
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MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
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MC_EMEM_ARB_DA_COVERS_0 = 0x00110B10
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MC_EMEM_ARB_MISC0_0 = 0x72703021
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C_EMEM_ARB_MISC1_0 = 0x70000F0F
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MC_EMEM_ARB_MISC2_0 = 0x00000000
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MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
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MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
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MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
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MC_EMEM_ARB_RSV_0 = 0xFF00FF00
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MC_CLKEN_OVERRIDE_0 = 0x00008000
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MC_TIMING_CONTROL_0 = 0x00000001
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MC_STAT_CONTROL_0 = 0x00000000
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MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
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MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
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MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
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MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
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MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
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MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
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MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
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MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
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MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
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MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
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MC_SMMU_AFI_ASID_0 = 0x8000000B
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MC_SMMU_AVPC_ASID_0 = 0x80000002
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MC_SMMU_DC_ASID_0 = 0x80000005
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MC_SMMU_DCB_ASID_0 = 0x80000006
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MC_SMMU_HC_ASID_0 = 0x80000000
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MC_SMMU_HDA_ASID_0 = 0x00000000
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MC_SMMU_ISP2_ASID_0 = 0x00000000
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MC_SMMU_NVENC_ASID_0 = 0x80000000
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MC_SMMU_NV_ASID_0 = 0x00000000
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MC_SMMU_NV2_ASID_0 = 0x00000000
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MC_SMMU_PPCS_ASID_0 = 0x80000003
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MC_SMMU_SATA_ASID_0 = 0x00000000
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MC_SMMU_VI_ASID_0 = 0x00000000
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MC_SMMU_VIC_ASID_0 = 0x80000000
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MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
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MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
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MC_SMMU_TSEC_ASID_0 = 0x80000000
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MC_SMMU_PPCS1_ASID_0 = 0x80000003
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MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
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MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
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MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
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MC_DISPLAY_SNAP_RING_0 = 0x00000000
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MC_ERR_VPR_STATUS_0 = 0x000000C0
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MC_ERR_VPR_ADR_0 = 0x0C191000
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MC_IRAM_REG_CTRL_0 = 0x00000001
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MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
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MC_TZ_SECURITY_CTRL_0 = 0x00000000
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MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
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MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
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MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
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MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
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MC_ERR_SEC_STATUS_0 = 0x000630B0
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MC_ERR_SEC_ADR_0 = 0x02930810
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MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
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MC_STUTTER_CONTROL_0 = 0x00000000
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MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
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MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
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MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
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MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004A
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MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
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MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
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MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
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MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
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MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
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MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
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MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
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MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
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MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
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MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
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MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
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MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
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MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
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MC_SECURITY_CFG3_0 = 0xFFFFFFFF
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MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
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MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
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MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
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MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
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MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
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MC_SMMU_DC1_ASID_0 = 0x80000005
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MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
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MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
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MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
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MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
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MC_SMMU_ISP2B_ASID_0 = 0x80000003
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MC_SMMU_GPU_ASID_0 = 0x00000000
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MC_SMMU_GPUB_ASID_0 = 0x8A090807
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MC_SMMU_PPCS2_ASID_0 = 0x80000003
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MC_SMMU_NVDEC_ASID_0 = 0x80000000
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MC_SMMU_APE_ASID_0 = 0x80000004
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MC_SMMU_SE_ASID_0 = 0x80000003
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MC_SMMU_NVJPG_ASID_0 = 0x80000000
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MC_SMMU_HC1_ASID_0 = 0x00000000
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MC_SMMU_SE1_ASID_0 = 0x80000003
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MC_SMMU_AXIAP_ASID_0 = 0x00000000
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MC_SMMU_ETR_ASID_0 = 0x00000000
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MC_SMMU_TSECB_ASID_0 = 0x80000000
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MC_SMMU_TSEC1_ASID_0 = 0x00000000
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MC_SMMU_TSECB1_ASID_0 = 0x00000000
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MC_SMMU_NVDEC1_ASID_0 = 0x00000000
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MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
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MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
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MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
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MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
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MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
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MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
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MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
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MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
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MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
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MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
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MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
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MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
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MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
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MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
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MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
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MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
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MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
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MC_DA_CONFIG0_0 = 0x00000001
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MC_AHB_PTSA_MIN_0 = 0x0000003F
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MC_AUD_PTSA_MIN_0 = 0x0000003F
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MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
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MC_RING2_PTSA_RATE_0 = 0x00000000
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MC_USBD_PTSA_RATE_0 = 0x00000000
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MC_USBX_PTSA_MIN_0 = 0x0000003F
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MC_USBD_PTSA_MIN_0 = 0x0000003F
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MC_APB_PTSA_MAX_0 = 0x0000003F
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MC_JPG_PTSA_RATE_0 = 0x00000000
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MC_DIS_PTSA_MIN_0 = 0x0000003B
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MC_AVP_PTSA_MAX_0 = 0x0000003F
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MC_AVP_PTSA_RATE_0 = 0x00000000
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MC_RING1_PTSA_MIN_0 = 0x0000003B
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MC_DIS_PTSA_MAX_0 = 0x0000001F
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MC_SD_PTSA_MAX_0 = 0x0000003F
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MC_MSE_PTSA_RATE_0 = 0x00000000
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MC_VICPC_PTSA_MIN_0 = 0x0000003F
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MC_PCX_PTSA_MAX_0 = 0x0000003F
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MC_ISP_PTSA_RATE_0 = 0x00000000
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MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
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MC_RING2_PTSA_MAX_0 = 0x0000003F
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MC_AUD_PTSA_RATE_0 = 0x00000000
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MC_HOST_PTSA_MIN_0 = 0x0000003F
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MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
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MC_SD_PTSA_MIN_0 = 0x0000003F
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MC_RING1_PTSA_RATE_0 = 0x0000035C
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MC_JPG_PTSA_MIN_0 = 0x0000003F
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MC_HDAPC_PTSA_MIN_0 = 0x0000003F
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MC_AVP_PTSA_MIN_0 = 0x0000003F
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MC_JPG_PTSA_MAX_0 = 0x0000003F
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MC_VE_PTSA_MAX_0 = 0x0000003F
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MC_DFD_PTSA_MAX_0 = 0x0000003F
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MC_VICPC_PTSA_RATE_0 = 0x00000000
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MC_GK_PTSA_MAX_0 = 0x0000003F
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MC_VICPC_PTSA_MAX_0 = 0x0000003F
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MC_SDM_PTSA_MAX_0 = 0x0000003F
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MC_SAX_PTSA_RATE_0 = 0x00000000
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MC_PCX_PTSA_MIN_0 = 0x0000003F
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MC_APB_PTSA_MIN_0 = 0x0000003F
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MC_GK2_PTSA_MIN_0 = 0x0000003F
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MC_PCX_PTSA_RATE_0 = 0x00000000
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MC_RING1_PTSA_MAX_0 = 0x0000001F
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MC_HDAPC_PTSA_RATE_0 = 0x00000000
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MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
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MC_GK2_PTSA_MAX_0 = 0x0000003F
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MC_AUD_PTSA_MAX_0 = 0x0000003F
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MC_GK2_PTSA_RATE_0 = 0x00000000
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MC_ISP_PTSA_MAX_0 = 0x0000003F
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MC_DISB_PTSA_RATE_0 = 0x00000445
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MC_VE2_PTSA_MAX_0 = 0x0000003F
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MC_DFD_PTSA_MIN_0 = 0x0000003F
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MC_FTOP_PTSA_RATE_0 = 0x0000001F
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MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
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MC_VE2_PTSA_MIN_0 = 0x0000003F
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MC_USBX_PTSA_MAX_0 = 0x0000003F
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MC_DIS_PTSA_RATE_0 = 0x00000000
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MC_USBD_PTSA_MAX_0 = 0x0000003F
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MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
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MC_USBX_PTSA_RATE_0 = 0x00000000
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MC_FTOP_PTSA_MAX_0 = 0x0000003F
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MC_HDAPC_PTSA_MAX_0 = 0x0000003F
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MC_SD_PTSA_RATE_0 = 0x00000000
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MC_DFD_PTSA_RATE_0 = 0x00000000
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MC_FTOP_PTSA_MIN_0 = 0x0000003F
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MC_SDM_PTSA_RATE_0 = 0x00000000
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MC_AHB_PTSA_RATE_0 = 0x00000000
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MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
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MC_RING2_PTSA_MIN_0 = 0x0000003F
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MC_SDM_PTSA_MIN_0 = 0x0000003F
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MC_APB_PTSA_RATE_0 = 0x00000000
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MC_MSE_PTSA_MIN_0 = 0x0000003F
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MC_HOST_PTSA_RATE_0 = 0x00000000
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MC_VE_PTSA_RATE_0 = 0x00000000
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MC_AHB_PTSA_MAX_0 = 0x0000003F
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MC_SAX_PTSA_MIN_0 = 0x0000003F
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MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
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MC_ISP_PTSA_MIN_0 = 0x0000003F
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MC_HOST_PTSA_MAX_0 = 0x0000003F
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MC_SAX_PTSA_MAX_0 = 0x0000003F
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MC_VE_PTSA_MIN_0 = 0x0000003F
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MC_GK_PTSA_MIN_0 = 0x0000003F
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MC_MSE_PTSA_MAX_0 = 0x0000003F
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MC_DISB_PTSA_MAX_0 = 0x0000001F
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MC_DISB_PTSA_MIN_0 = 0x0000003B
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MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
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MC_VE2_PTSA_RATE_0 = 0x00000000
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MC_GK_PTSA_RATE_0 = 0x00000000
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MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
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MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00600004
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MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
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MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00600038
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MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
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MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00600005
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MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00600014
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MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
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MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
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MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00600060
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MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
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MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00600016
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MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
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MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00600095
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MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
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MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00600041
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MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
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MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
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MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00600080
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MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0060003D
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MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
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MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
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MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
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MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
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MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
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MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
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MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
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MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
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MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00600013
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MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
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MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000060
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MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00600090
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MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
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MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
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MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
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MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00600004
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MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000060
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MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
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MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
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MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
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MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
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MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080011
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MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
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MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00600013
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MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00600005
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MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
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MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00600018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2166_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2166_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000F7B9B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x58681E41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80030080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713121
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00001020
|
||||
MC_ERR_SEC_ADR_0 = 0x02000000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004B
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005E0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005E0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005E0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005E0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005E005E
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005E0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005E0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005E0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005E0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005E003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005E0013
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005E
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005E0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005E0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005E0013
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005E0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005E0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2200_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2200_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD4B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77D4C531
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713222
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00040041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02110000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005D005D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005D0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005D0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005D0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2233_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2233_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01211200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7981FF41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713322
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x001E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x003E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02123000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004E
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005B0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005B0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005B0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005B0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005B005B
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005B0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005B0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005B0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005B0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005B003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005B0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005B
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005B0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005B0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005B
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005B0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005B0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005B0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2266_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2266_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01011200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FF37F
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x4AF0EDF1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713323
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00040041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02013000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004F
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005A0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005A0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005A0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005A0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005A005A
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005A0014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005A0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005A0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005A0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005A003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005A0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005A
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005A0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005A0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005A
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005A0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005A0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005A0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2300_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2300_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCFB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7ABA83D1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723423
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02022000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000050
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00590004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00590038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00590005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00590014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00590059
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00590014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00590095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00590041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00590080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0059003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00590012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000059
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00590090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00590004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000059
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00590012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00590005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00590018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2333_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2333_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD4B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7ABA6511
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723523
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80030080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02132810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000051
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00570004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00570038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00570005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00570014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00570057
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00570014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00570095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00570041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00570080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0057003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00570011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000057
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00570090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00570004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000057
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00570011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00570005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00570018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2366_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2366_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x78694471
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000023
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723624
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80080080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000052
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00560004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00560038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00560005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00560014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00560056
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00560013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00560095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00560041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00560080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0056003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00560011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000056
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00560090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00560004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000056
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00560011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00560005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00560018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2400_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2400_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD7B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77CE85E1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80060080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723625
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000040
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130010
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000053
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00550004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00550038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00550005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00550014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00550055
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00550013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00550095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00550041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00550080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0055003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00550011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000055
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00550090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00550004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000055
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00550011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00550005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00550018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2433_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2433_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E80541
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733725
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000610F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02132000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000055
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00540004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00540038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00540005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00540014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00540054
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00540013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00540095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00540041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00540080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0054003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00540011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000054
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00540090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00540004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000054
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00540011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00540005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00540018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2466_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2466_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD1B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E49471
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733826
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x001E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x003E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000056
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00530004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00530038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00530005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00530014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00530053
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00530013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00530095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00530041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00530080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0053003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00530010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00530090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00530004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000053
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00530010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00530005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00530018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2500_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2500_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E6B271
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80030080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733926
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02932800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000057
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00510004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00510038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00510005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00510014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00510051
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00510012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00510095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00510041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00510080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0051003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00510010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000051
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00510090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00510004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000051
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00510010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00510005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00510018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2533_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2533_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFDAB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E826A1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733927
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00023070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000058
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00500004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00500038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00500005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00500014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00500050
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00500012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00500095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00500041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00500080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0050003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00500010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000050
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00500090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00500004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000050
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00500010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00500005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00500018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2566_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2566_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DD7551
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743A27
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02930000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000059
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004F0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004F0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004F0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004F0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004F004F
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004F0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004F0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004F0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004F0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004F003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004F0010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004F
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004F0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004F0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004F
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004F0010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004F0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004F0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2600_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2600_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD1B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7B210471
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0000000C
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000006
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000007
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000D080C
|
||||
MC_EMEM_ARB_MISC0_0 = 0x726C2419
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C181000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063090
|
||||
MC_ERR_SEC_ADR_0 = 0x08130850
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000037
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000230
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000010
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00800038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00800095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00800041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0080003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00800090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000080
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080016
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00800018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2633_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2633_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x68372880
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD8B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x784C7621
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02030000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004D004D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004D0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004D000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004D000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2666_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2666_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E5A541
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000014
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x800D0080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80030080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005D
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004C0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004C0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004C0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004C0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004C004C
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004C0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004C0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004C0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004C0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004C003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004C000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004C
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004C0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004C0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004C
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004C000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004C0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004C0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2700_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2700_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FF9DB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x0B948741
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000014
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000028
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001B
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140D14
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72753D29
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005E
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004B0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004B0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004B0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004B0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004B004B
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004B0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004B0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00990041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004B0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004B003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004B000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004B
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00800090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004B0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004B
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0099001E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004B0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004B0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2733_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2733_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DEB341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000014
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000029
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001B
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E14
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72753E2A
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C111000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000230B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005F
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004A0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004A0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004A0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004A0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004A004A
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004A0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004A0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004A0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004A0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004A003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004A000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004A
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004A0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004A0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004A
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004A000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004A0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004A0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2766_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2766_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x11210200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E71141
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000014
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000029
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001C
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E14
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72753F2A
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000060
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004A0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004A0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004A0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004A0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004A004A
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004A0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004A0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004A0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004A0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004A003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004A000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004A
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004A0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004A0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004A
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004A000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004A0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004A0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2800_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2800_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E18341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000015
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002A
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001C
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E15
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72753F2B
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02112810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000061
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00490004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00490038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00490005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00490014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00490049
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00490010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00490095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00490041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00490080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0049003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0049000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000049
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00490090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00490004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000049
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0049000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00490005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00490018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2833_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2833_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E5D341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000015
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002A
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001C
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E15
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7276402B
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x800E0080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A003000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000063
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00480004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00480038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00480005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00480014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00480048
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00480010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00480095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00480041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00480080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0048003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0048000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000048
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00480090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00480004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000048
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0048000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00480005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00480018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2866_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2866_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD0B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E42421
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000015
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002B
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001D
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150E15
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7276412C
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000400C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000064
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00470004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00470038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00470005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00470014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00470047
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00470010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00470095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00470041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00470080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0047003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0047000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000047
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00470090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00470004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000047
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0047000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00470005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00470018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2900_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2900_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD0B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E8E401
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000015
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002B
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001D
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150E15
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7276422C
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80030080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00001060
|
||||
MC_ERR_SEC_ADR_0 = 0x02023000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000065
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00460004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00460038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00460005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00460014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00460046
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00460010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00460095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00460041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00460080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0046003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0046000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000046
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00460090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00460004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000046
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0046000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00460005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00460018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2933_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2933_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x31050F41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000016
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002C
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001D
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150E16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7276422D
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x42130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000066
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00450004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00450038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00450005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00450014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00450045
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00450010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00990095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00450041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00450080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0045003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0045000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000045
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00450090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00450004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000045
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0045000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00450005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00450018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2966_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2966_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77EA0261
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000016
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002C
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7257432D
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000067
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00450004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00450038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00450005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00450014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00450045
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00450010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00450095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00450041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00450080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0045003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0045000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000045
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00450090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00450004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000045
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0045000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00450005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00450018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3000_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3000_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x19211200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFE4B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7A43E911
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000016
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002C
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7277442D
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000400C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02910810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000068
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00440004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00440038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00440005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00440014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00440044
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0044000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00440095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00440041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00440080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0044003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0044000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000044
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00440090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00440004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000044
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0044000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00440005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00440018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3033_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3033_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC8B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77D7A221
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000016
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7277452E
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02003000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006A
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00430004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00430038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00430005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00430014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00430043
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0043000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00430095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00430041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00430080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0043003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0043000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000043
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00430090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00430004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000043
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0043000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00430005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00430018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3066_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3066_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCEB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E1F3B1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000017
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00160F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7277452E
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006B
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00420004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00420038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00420005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00420014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00420042
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0042000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00420095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00420041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00420080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0042003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0042000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000042
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00420090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00420004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000042
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0042000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00420005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00420018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3100_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3100_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFB5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7A3C0D41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000017
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00160F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7258462E
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130100
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00000C63
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00420038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00420095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00800041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00420080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0080003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0042000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000042
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00420090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00420004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000042
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000B
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0042000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00420005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00420018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3133_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3133_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01011200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCCB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DD8331
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000017
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00160F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7258472E
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000040
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006D
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00410004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00410038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00410005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00410014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00410041
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0041000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00410095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00410041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00410080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0041003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0041000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00410090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00410004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000041
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000B
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0041000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00410005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00410018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
Reference in New Issue
Block a user