Clean up, replaced 2600Mhz 2133bl with correct file, added scripts.
This commit is contained in:
Lightos1
528
timings/Mariko/AA/2133/emc/2133_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2133_emc.txt
Normal file
@@ -0,0 +1,528 @@
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Dumping EMC registers from BASE=0x7001B000
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-----------------------------------
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EMC_INTSTATUS_0 = 0x00000030
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EMC_INTMASK_0 = 0x00000000
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EMC_DBG_0 = 0x01000C00
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EMC_CFG_0 = 0xF3200000
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EMC_ADR_CFG_0 = 0x00000000
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EMC_REFCTRL_0 = 0x80000002
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EMC_PIN_0 = 0x00003101
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EMC_TIMING_CONTROL_0 = 0x00000001
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EMC_RC_0 = 0x00000080
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EMC_RFC_0 = 0x00000256
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EMC_RAS_0 = 0x0000005A
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EMC_RP_0 = 0x00000027
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EMC_R2W_0 = 0x00000031
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EMC_W2R_0 = 0x0000002B
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EMC_R2P_0 = 0x00000010
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EMC_W2P_0 = 0x0000003B
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EMC_RD_RCD_0 = 0x00000027
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EMC_WR_RCD_0 = 0x00000027
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EMC_RRD_0 = 0x00000010
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EMC_REXT_0 = 0x0000001A
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EMC_WDV_0 = 0x00000012
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EMC_QUSE_0 = 0x0000002C
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EMC_QRST_0 = 0x0007000D
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EMC_QSAFE_0 = 0x0000003D
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EMC_RDV_0 = 0x00000043
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EMC_REFRESH_0 = 0x0000203F
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EMC_BURST_REFRESH_NUM_0 = 0x00000000
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EMC_PDEX2WR_0 = 0x00000016
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EMC_PDEX2RD_0 = 0x00000016
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EMC_PCHG2PDEN_0 = 0x00000004
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EMC_ACT2PDEN_0 = 0x0000001E
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EMC_AR2PDEN_0 = 0x00000004
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EMC_RW2PDEN_0 = 0x00000047
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EMC_TXSR_0 = 0x00000266
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EMC_TCKE_0 = 0x00000012
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EMC_TFAW_0 = 0x00000040
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EMC_TRPAB_0 = 0x0000002D
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EMC_TCLKSTABLE_0 = 0x00000004
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EMC_TCLKSTOP_0 = 0x0000001A
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EMC_TREFBW_0 = 0x0000207F
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EMC_TPPD_0 = 0x00000004
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EMC_ODT_WRITE_0 = 0x00000000
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EMC_PDEX2MRR_0 = 0x0000003F
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EMC_WEXT_0 = 0x00000016
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EMC_RFC_SLR_0 = 0x00000000
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EMC_MRS_WAIT_CNT2_0 = 0x0216001E
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EMC_MRS_WAIT_CNT_0 = 0x07FF0039
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EMC_MRS_0 = 0x00000000
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EMC_EMRS_0 = 0x00000000
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EMC_REF_0 = 0x80000000
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EMC_PRE_0 = 0x00000000
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EMC_NOP_0 = 0x00000000
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EMC_SELF_REF_0 = 0x00000000
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EMC_DPD_0 = 0x00000000
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EMC_MRW_0 = 0x00170040
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EMC_MRR_0 = 0x8012CBE9
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EMC_CMDQ_0 = 0x10004408
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EMC_MC2EMCQ_0 = 0x06000404
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EMC_FBIO_SPARE_0 = 0x00000012
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EMC_FBIO_CFG5_0 = 0x9160A00D
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EMC_FBIO_CFG6_0 = 0x00001010
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EMC_PDEX2CKE_0 = 0x00000002
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EMC_CKE2PDEN_0 = 0x00000013
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EMC_CFG_RSV_0 = 0xFF00FF00
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EMC_ACPD_CONTROL_0 = 0x00000000
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EMC_MPC_0 = 0x0000004B
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EMC_EMRS2_0 = 0x00000000
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EMC_EMRS3_0 = 0x00000000
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EMC_MRW2_0 = 0x8802003F
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EMC_MRW3_0 = 0x8C0D00D0
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EMC_MRW4_0 = 0xC0000000
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EMC_CLKEN_OVERRIDE_0 = 0x00000000
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EMC_R2R_0 = 0x00000000
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EMC_W2W_0 = 0x00000000
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EMC_EINPUT_0 = 0x00000016
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EMC_EINPUT_DURATION_0 = 0x00000024
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EMC_PUTERM_EXTRA_0 = 0x00000001
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EMC_TCKESR_0 = 0x00000020
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EMC_TPD_0 = 0x00000010
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EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
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EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
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EMC_AUTO_CAL_STATUS_0 = 0x1D180000
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EMC_REQ_CTRL_0 = 0x00000000
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EMC_EMC_STATUS_0 = 0x0B430035
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EMC_CFG_2_0 = 0x0011083D
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EMC_CFG_DIG_DLL_0 = 0x002C03A9
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EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
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EMC_DIG_DLL_STATUS_0 = 0x00000004
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EMC_CFG_DIG_DLL_1_0 = 0x000F3701
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EMC_RDV_MASK_0 = 0x00000045
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EMC_WDV_MASK_0 = 0x00000012
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EMC_RDV_EARLY_MASK_0 = 0x00000043
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EMC_RDV_EARLY_0 = 0x00000041
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EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
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EMC_ZCAL_INTERVAL_0 = 0x00064000
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EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
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EMC_ZCAL_MRW_CMD_0 = 0x8051004F
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EMC_ZQ_CAL_0 = 0x80000002
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EMC_XM2COMPPADCTRL3_0 = 0x00901000
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EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
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EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
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EMC_XM2COMPPADCTRL_0 = 0x00000030
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EMC_FDPD_CTRL_DQ_0 = 0x8020221F
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EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
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EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
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EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
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EMC_SCRATCH0_0 = 0x00000000
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EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
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EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
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EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
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EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
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EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
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EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
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EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
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EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
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EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
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EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
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EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
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EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
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EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
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EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
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EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
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EMC_TR_TIMING_0_0 = 0x01186216
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EMC_TR_CTRL_0_0 = 0x00000020
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EMC_TR_CTRL_1_0 = 0x00000000
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EMC_SWITCH_BACK_CTRL_0 = 0x00000001
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EMC_TR_RDV_0 = 0x00000043
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EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
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EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
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EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
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EMC_AUTO_CAL_ = 0x3F1F070A
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EMC_SEL_DPD_CTRL_0 = 0x0004000C
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EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000080F
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EMC_DYN_SELF_REF_CONTROL_0 = 0x80004062
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EMC_TXSRDLL_0 = 0x00000266
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EMC_CCFIFO_ADDR_0 = 0x80000000
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EMC_CCFIFO_DATA_0 = 0x00000000
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EMC_CCFIFO_STATUS_0 = 0x00000000
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EMC_TR_QPOP_0 = 0x00000035
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EMC_TR_RDV_MASK_0 = 0x00000045
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EMC_TR_QSAFE_0 = 0x0000003D
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EMC_TR_QRST_0 = 0x0007000D
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EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
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EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
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EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
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EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
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EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
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EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
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EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
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EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
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EMC_ISSUE_QRST_0 = 0x00000000
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EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
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EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
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EMC_PMC_SCRATCH3_0 = 0x4036D71F
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EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
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EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
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EMC_TR_DVFS_0 = 0x00000000
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EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
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EMC_IBDLY_0 = 0x10000023
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EMC_OBDLY_0 = 0x10000006
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EMC_TXDSRVTTGEN_0 = 0x00000000
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EMC_WE_DURATION_0 = 0x0000000E
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EMC_WS_DURATION_0 = 0x00000008
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EMC_WEV_0 = 0x0000000E
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EMC_WSV_0 = 0x00000010
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EMC_CFG_3_0 = 0x00000040
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EMC_MRW5_0 = 0x00000000
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EMC_MRW6_0 = 0x8803F1F1
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EMC_MRW7_0 = 0xC803F1F1
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EMC_MRW8_0 = 0x880B0606
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EMC_MRW9_0 = 0x8C0E5D5D
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EMC_MRW10_0 = 0x880C5D5D
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EMC_MRW11_0 = 0xC80C5D5D
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EMC_MRW12_0 = 0x880E0A0B
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EMC_MRW13_0 = 0xC80E0000
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EMC_MRW14_0 = 0x88161414
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EMC_MRW15_0 = 0xC8161414
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EMC_CFG_SYNC_0 = 0x00000001
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EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
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EMC_WDV_CHK_0 = 0x00000006
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EMC_CFG_PIPE_2_0 = 0x00000000
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EMC_CFG_PIPE_CLK_0 = 0x00000000
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EMC_CFG_PIPE_1_0 = 0x0FFF0000
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EMC_CFG_PIPE_0 = 0x0FFF0000
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EMC_QPOP_0 = 0x00000035
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EMC_QUSE_WIDTH_0 = 0x0000000A
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EMC_PUTERM_WIDTH_0 = 0x80000000
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EMC_BGBIAS_CTL0_0 = 0x00000000
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EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
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EMC_XM2COMPPADCTRL2_0 = 0x16001000
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EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
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EMC_REFCTRL2_0 = 0x00000000
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EMC_FBIO_CFG7_0 = 0x00003BFF
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EMC_DATA_BRLSHFT_0_0 = 0x00000249
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EMC_DATA_BRLSHFT_1_0 = 0x00000000
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EMC_RFCPB_0 = 0x0000012B
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EMC_DQS_BRLSHFT_0_0 = 0x00000000
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EMC_DQS_BRLSHFT_1_0 = 0x00000000
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EMC_CMD_BRLSHFT_0_0 = 0x00000000
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EMC_CMD_BRLSHFT_1_0 = 0x00000000
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EMC_CMD_BRLSHFT_2_0 = 0x00000024
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EMC_CMD_BRLSHFT_3_0 = 0x00000024
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EMC_QUSE_BRLSHFT_0_0 = 0x00000000
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EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
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EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
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EMC_QUSE_BRLSHFT_1_0 = 0x00000000
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EMC_QUSE_BRLSHFT_2_0 = 0x00000000
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EMC_CCDMW_0 = 0x00000020
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EMC_QUSE_BRLSHFT_3_0 = 0x00000000
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EMC_FBIO_CFG8_0 = 0x0CF30000
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EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
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EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
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EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
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EMC_PROTOBIST_MISC_0 = 0x00000000
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EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
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EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
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EMC_PROTOBIST_RDATA_0 = 0x00000000
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EMC_DLL_CFG_0_0 = 0x1F136120
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EMC_DLL_CFG_1_0 = 0x00012014
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EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
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EMC_CFG_UPDATE_0 = 0x70000301
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EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
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EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
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EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000A0000
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
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EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000A0000
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240026
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200024
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210024
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
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EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
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EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
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EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
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EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
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EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
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EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
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EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
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EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
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EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
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EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
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EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
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EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
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EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
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EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
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EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
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EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
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EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
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EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
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EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
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EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x3E3F3F40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x3D39383C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000003C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3A3C3938
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x383C3438
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000035
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x43424343
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x3F414236
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x323A3B39
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3837332F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000035
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x393D3B3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3A3D393B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3A39393A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3A393A37
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000039
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08080907
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04070204
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3D3D3839
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x3B393C36
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000038
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06090309
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0708090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060907
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050507
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03010100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x28262627
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28252729
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004042B
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2166_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2166_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000082
|
||||
EMC_RFC_0 = 0x0000025F
|
||||
EMC_RAS_0 = 0x0000005B
|
||||
EMC_RP_0 = 0x00000027
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000027
|
||||
EMC_WR_RCD_0 = 0x00000027
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002D
|
||||
EMC_QRST_0 = 0x0007000E
|
||||
EMC_QSAFE_0 = 0x0000003E
|
||||
EMC_RDV_0 = 0x00000044
|
||||
EMC_REFRESH_0 = 0x000020BF
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001F
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000047
|
||||
EMC_TXSR_0 = 0x0000026F
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000041
|
||||
EMC_TRPAB_0 = 0x0000002E
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x000020FF
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000040
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x021E001F
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0039
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000017
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000021
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x00110835
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000046
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||
EMC_RDV_EARLY_0 = 0x00000042
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118621E
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000044
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x0000082F
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000415D
|
||||
EMC_TXSRDLL_0 = 0x0000026F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000036
|
||||
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||
EMC_TR_QSAFE_0 = 0x0000003E
|
||||
EMC_TR_QRST_0 = 0x0007000E
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030B
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000036
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000130
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00060000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00200024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x3F404141
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x3F3B393D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3B3E3B3A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3A3E3639
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000037
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x44434444
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x41434437
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x333B3C3B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3A393430
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000037
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3A3F3D3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3B3F3B3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3B3A3A3B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3B3A3B38
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x090A0B08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x06080406
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x3F3F393C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x3D3B3E38
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03070707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03010005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04080308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07080A0B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010204
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05050104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x28242628
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28262628
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004043B
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2200_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2200_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000084
|
||||
EMC_RFC_0 = 0x00000268
|
||||
EMC_RAS_0 = 0x0000005D
|
||||
EMC_RP_0 = 0x00000028
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000028
|
||||
EMC_WR_RCD_0 = 0x0000001D
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002D
|
||||
EMC_QRST_0 = 0x0007000E
|
||||
EMC_QSAFE_0 = 0x0000003E
|
||||
EMC_RDV_0 = 0x00000044
|
||||
EMC_REFRESH_0 = 0x00002144
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x0000001F
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000047
|
||||
EMC_TXSR_0 = 0x00000279
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000042
|
||||
EMC_TRPAB_0 = 0x0000002F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x00002184
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000041
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x0226001F
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0039
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80129CB9
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000017
|
||||
EMC_EINPUT_DURATION_0 = 0x00000024
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000021
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000046
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||
EMC_RDV_EARLY_0 = 0x00000042
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186226
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000044
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000851
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000425F
|
||||
EMC_TXSRDLL_0 = 0x00000279
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000036
|
||||
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||
EMC_TR_QSAFE_0 = 0x0000003E
|
||||
EMC_TR_QRST_0 = 0x0007000E
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000036
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000134
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0021002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00130009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x40414242
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x403C3A3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3D3F3D3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3C41373B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000039
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x46444747
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x42454638
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000044
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x343D3E3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3B3A3532
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000038
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3C413E40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3E413D3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3C3B3C3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3D3C3C39
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0B0B0C09
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x08090508
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x40403B3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x3E3D3F39
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04070707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03090309
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050101
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03030505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04030303
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26252929
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27272826
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x070A070A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004044C
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2233_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2233_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000086
|
||||
EMC_RFC_0 = 0x00000272
|
||||
EMC_RAS_0 = 0x0000005E
|
||||
EMC_RP_0 = 0x00000029
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000029
|
||||
EMC_WR_RCD_0 = 0x00000029
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x00000019
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002D
|
||||
EMC_QRST_0 = 0x0007000D
|
||||
EMC_QSAFE_0 = 0x0000003E
|
||||
EMC_RDV_0 = 0x00000044
|
||||
EMC_REFRESH_0 = 0x000021C5
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x00000020
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x00000282
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000043
|
||||
EMC_TRPAB_0 = 0x0000002F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001A
|
||||
EMC_TREFBW_0 = 0x00002205
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000042
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x022F0020
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0039
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012809D
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000013
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000016
|
||||
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000022
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000046
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||
EMC_RDV_EARLY_0 = 0x00000042
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118622F
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000044
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000871
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000435A
|
||||
EMC_TXSRDLL_0 = 0x00000282
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000036
|
||||
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||
EMC_TR_QSAFE_0 = 0x0000003E
|
||||
EMC_TR_QRST_0 = 0x0007000D
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000036
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000139
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xCC200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x42424444
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x413D3B40
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x3F413E3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3D423A3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x48474949
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x4548483A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000046
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x363F3F3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3C3B3733
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000039
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3E424042
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x3E433F3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3E3C3D3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x3E3E3E3B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0D0E0F0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0A0C0809
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x41423C3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x403E413B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04040105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2726252A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282625
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00120012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000012
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000812
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004045D
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2266_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2266_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000088
|
||||
EMC_RFC_0 = 0x0000027B
|
||||
EMC_RAS_0 = 0x00000060
|
||||
EMC_RP_0 = 0x00000029
|
||||
EMC_R2W_0 = 0x00000031
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000029
|
||||
EMC_WR_RCD_0 = 0x00000029
|
||||
EMC_RRD_0 = 0x00000011
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002D
|
||||
EMC_QRST_0 = 0x0007000D
|
||||
EMC_QSAFE_0 = 0x0000003E
|
||||
EMC_RDV_0 = 0x00000044
|
||||
EMC_REFRESH_0 = 0x00002245
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000017
|
||||
EMC_PDEX2RD_0 = 0x00000017
|
||||
EMC_PCHG2PDEN_0 = 0x00000004
|
||||
EMC_ACT2PDEN_0 = 0x00000020
|
||||
EMC_AR2PDEN_0 = 0x00000004
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x0000028C
|
||||
EMC_TCKE_0 = 0x00000013
|
||||
EMC_TFAW_0 = 0x00000044
|
||||
EMC_TRPAB_0 = 0x00000030
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x00002285
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000042
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02370020
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF0039
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80126E8A
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000016
|
||||
EMC_EINPUT_DURATION_0 = 0x00000025
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000022
|
||||
EMC_TPD_0 = 0x00000011
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000046
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||
EMC_RDV_EARLY_0 = 0x00000042
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186237
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000044
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000891
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004455
|
||||
EMC_TXSRDLL_0 = 0x0000028C
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000036
|
||||
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||
EMC_TR_QSAFE_0 = 0x0000003E
|
||||
EMC_TR_QRST_0 = 0x0007000D
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000036
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000013E
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000B0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000B0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00060000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x43444545
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x433F3D42
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000042
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x40423F3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x3F433B3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x49494A4A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x46494A3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000047
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3740413F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3E3C3834
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x3F444144
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x41444040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000042
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x3F3E3F3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x403F3F3C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0E0E100D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0B0D090B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x43433E3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4140433C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x040A0309
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x02020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05050104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27242828
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28282628
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004046D
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2300_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2300_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008A
|
||||
EMC_RFC_0 = 0x00000284
|
||||
EMC_RAS_0 = 0x00000061
|
||||
EMC_RP_0 = 0x0000002A
|
||||
EMC_R2W_0 = 0x00000032
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002A
|
||||
EMC_WR_RCD_0 = 0x0000002A
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002C
|
||||
EMC_QRST_0 = 0x0007000C
|
||||
EMC_QSAFE_0 = 0x0000003E
|
||||
EMC_RDV_0 = 0x00000044
|
||||
EMC_REFRESH_0 = 0x000022CA
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000021
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x00000296
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000045
|
||||
EMC_TRPAB_0 = 0x00000031
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x0000230A
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000045
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x023F0021
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003A
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80125975
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000015
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000023
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000046
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||
EMC_RDV_EARLY_0 = 0x00000042
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118623F
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000044
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008B2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004558
|
||||
EMC_TXSRDLL_0 = 0x00000296
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000036
|
||||
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||
EMC_TR_QSAFE_0 = 0x0000003E
|
||||
EMC_TR_QRST_0 = 0x0007000C
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000023
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0B0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000036
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000142
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x45454647
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x44403E43
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000044
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x42444140
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x40453C3F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4B4A4B4C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x48494B3D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000047
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x38414241
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x3F3E3935
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00050305
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050102
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x41404041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4140413E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0F10110E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0C0E0A0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x45453F41
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4341443F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01020001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06040403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x28252629
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27282727
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004047E
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000B0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2333_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2333_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0x03200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008C
|
||||
EMC_RFC_0 = 0x0000028E
|
||||
EMC_RAS_0 = 0x00000062
|
||||
EMC_RP_0 = 0x0000002A
|
||||
EMC_R2W_0 = 0x00000032
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002A
|
||||
EMC_WR_RCD_0 = 0x0000002A
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002C
|
||||
EMC_QRST_0 = 0x0007000B
|
||||
EMC_QSAFE_0 = 0x0000003E
|
||||
EMC_RDV_0 = 0x00000044
|
||||
EMC_REFRESH_0 = 0x0000234B
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000021
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x0000029F
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000046
|
||||
EMC_TRPAB_0 = 0x00000031
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001B
|
||||
EMC_TREFBW_0 = 0x0000238B
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000045
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02480021
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003A
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000014
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000014
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000023
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000046
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000044
|
||||
EMC_RDV_EARLY_0 = 0x00000042
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186248
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000044
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008D2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004653
|
||||
EMC_TXSRDLL_0 = 0x000001CC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000036
|
||||
EMC_TR_RDV_MASK_0 = 0x00000046
|
||||
EMC_TR_QSAFE_0 = 0x0000003E
|
||||
EMC_TR_QRST_0 = 0x0007000B
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000023
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000036
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000147
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A032010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240028
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002F
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00140009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000B0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000B0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x46474747
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x45403F43
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000045
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x44464342
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x42473E41
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000003F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x4C4B4E4E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x494C4C3E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000004A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3A434342
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x403F3B37
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000003E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x02070407
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03070304
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x42404143
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x4341423F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x11111311
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0F100C0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x46464142
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x4442453F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03090408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02060003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07080800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01070909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02030504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03030302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06020301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x26242629
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28262927
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2366_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2366_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000008E
|
||||
EMC_RFC_0 = 0x00000297
|
||||
EMC_RAS_0 = 0x00000064
|
||||
EMC_RP_0 = 0x0000001D
|
||||
EMC_R2W_0 = 0x00000032
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002B
|
||||
EMC_WR_RCD_0 = 0x0000002B
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002E
|
||||
EMC_QRST_0 = 0x0007000D
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000045
|
||||
EMC_REFRESH_0 = 0x000023CB
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000022
|
||||
EMC_AR2PDEN_0 = 0x00000003
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000001CC
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000047
|
||||
EMC_TRPAB_0 = 0x00000032
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x0000240B
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000046
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02500022
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003A
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122C43
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000016
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000024
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000047
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000045
|
||||
EMC_RDV_EARLY_0 = 0x00000037
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186250
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000039
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000008F2
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000474E
|
||||
EMC_TXSRDLL_0 = 0x000002A9
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000037
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003B
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x0007000D
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030C
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000037
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000014C
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A00A018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x00150009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x00150009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x07070909
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06020004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x06070504
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0E0D0F0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0D0E00
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3B454544
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x42413C38
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x04090608
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x05080505
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04020404
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x12131412
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x0F110D10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07080204
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040701
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A0409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05020300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27242629
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28262629
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00130013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00090009
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000013
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000813
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x0004049F
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2400_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2400_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000090
|
||||
EMC_RFC_0 = 0x000002A0
|
||||
EMC_RAS_0 = 0x00000065
|
||||
EMC_RP_0 = 0x0000002C
|
||||
EMC_R2W_0 = 0x00000032
|
||||
EMC_W2R_0 = 0x0000002B
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002C
|
||||
EMC_WR_RCD_0 = 0x0000002C
|
||||
EMC_RRD_0 = 0x00000012
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002E
|
||||
EMC_QRST_0 = 0x0007000D
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000045
|
||||
EMC_REFRESH_0 = 0x00002450
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000019
|
||||
EMC_PDEX2RD_0 = 0x00000019
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000022
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000002B2
|
||||
EMC_TCKE_0 = 0x00000014
|
||||
EMC_TFAW_0 = 0x00000048
|
||||
EMC_TRPAB_0 = 0x00000033
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002490
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000047
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02580022
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003A
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122641
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000016
|
||||
EMC_EINPUT_DURATION_0 = 0x00000026
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000024
|
||||
EMC_TPD_0 = 0x00000012
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000047
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000045
|
||||
EMC_RDV_EARLY_0 = 0x00000043
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186258
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000045
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000914
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004850
|
||||
EMC_TXSRDLL_0 = 0x000002B2
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000037
|
||||
EMC_TR_RDV_MASK_0 = 0x00000047
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x0007000D
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000037
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000150
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0A0B0B0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0A050308
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x07080605
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E282A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0F0E1010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0B0E0F00
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3D464745
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x43433D39
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000040
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x050A070A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x060A0607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x06040506
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06050503
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x14151613
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x12130F11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09090305
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050802
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090907
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08080900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050807
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2525242A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27262425
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404B0
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2433_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2433_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000092
|
||||
EMC_RFC_0 = 0x000002AA
|
||||
EMC_RAS_0 = 0x00000067
|
||||
EMC_RP_0 = 0x0000002C
|
||||
EMC_R2W_0 = 0x00000032
|
||||
EMC_W2R_0 = 0x0000002C
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002C
|
||||
EMC_WR_RCD_0 = 0x0000002C
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002E
|
||||
EMC_QRST_0 = 0x0007000C
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000045
|
||||
EMC_REFRESH_0 = 0x000024D1
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000002BC
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x00000049
|
||||
EMC_TRPAB_0 = 0x00000034
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002511
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000048
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02610023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003A
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122B41
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000015
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000025
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430020
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000047
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000045
|
||||
EMC_RDV_EARLY_0 = 0x00000043
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186261
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000045
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080A
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000934
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000494B
|
||||
EMC_TXSRDLL_0 = 0x000002BC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000037
|
||||
EMC_TR_RDV_MASK_0 = 0x00000047
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x0007000C
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000037
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000155
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0015000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0B0C0C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0B060409
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x080A0807
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060C0205
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x100F1111
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0C101102
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3D474846
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x45443F3A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000041
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x050A080A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x060B0607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x07060603
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x16171815
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x13151012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0B0B0506
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09070A03
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090907
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04090408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x02060005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00050808
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03010404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030301
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232327
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28252727
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404C1
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2466_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2466_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000094
|
||||
EMC_RFC_0 = 0x000002B3
|
||||
EMC_RAS_0 = 0x00000068
|
||||
EMC_RP_0 = 0x0000002D
|
||||
EMC_R2W_0 = 0x00000032
|
||||
EMC_W2R_0 = 0x0000002C
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002D
|
||||
EMC_WR_RCD_0 = 0x0000002D
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002E
|
||||
EMC_QRST_0 = 0x0007000C
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000045
|
||||
EMC_REFRESH_0 = 0x00002551
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000002C5
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004A
|
||||
EMC_TRPAB_0 = 0x00000034
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001C
|
||||
EMC_TREFBW_0 = 0x00002591
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000049
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02690023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003A
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012041E
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000015
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000015
|
||||
EMC_EINPUT_DURATION_0 = 0x00000027
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000025
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000047
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000045
|
||||
EMC_RDV_EARLY_0 = 0x00000043
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186269
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000045
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000954
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004A46
|
||||
EMC_TXSRDLL_0 = 0x000002C5
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000037
|
||||
EMC_TR_RDV_MASK_0 = 0x00000047
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x0007000C
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000037
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000A
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000015A
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x80204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000C0014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0C0D0E0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0C07060A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090B0807
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x070D0306
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x11101313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0E111202
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x3F494A48
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4645413B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000043
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x070B080B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x080C0808
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x08070708
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x09070804
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x17181916
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x14151114
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0C0C0607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0A070B04
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03080806
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A0409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0707090C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07060207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2622272B
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26282626
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00140014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000014
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D181D18
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404D1
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2500_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2500_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000096
|
||||
EMC_RFC_0 = 0x000002BC
|
||||
EMC_RAS_0 = 0x00000069
|
||||
EMC_RP_0 = 0x0000002D
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002C
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002D
|
||||
EMC_WR_RCD_0 = 0x0000002D
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001A
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002D
|
||||
EMC_QRST_0 = 0x0007000B
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000045
|
||||
EMC_REFRESH_0 = 0x000025D6
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000023
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000002CF
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004B
|
||||
EMC_TRPAB_0 = 0x00000035
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002616
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000049
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02710023
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003A
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000014
|
||||
EMC_EINPUT_DURATION_0 = 0x00000028
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000026
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D180000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000047
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000045
|
||||
EMC_RDV_EARLY_0 = 0x00000043
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186271
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000045
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000975
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004B49
|
||||
EMC_TXSRDLL_0 = 0x000002CF
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000037
|
||||
EMC_TR_RDV_MASK_0 = 0x00000047
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x0007000B
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000006
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000037
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000015E
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230030
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220025
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00240026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0E0E1010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0D09070C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0B0D0A09
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x090E0508
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x12121414
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0F121404
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x404B4B4A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4847413D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000044
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x080D0B0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x090E090A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0A080A0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0B090A07
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x191A1A18
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x16171315
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0E0E080A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0C0A0D06
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03070706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x03080407
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x01050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070800
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060A08
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x07050100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00060207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040207
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010405
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04030103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08040504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x2624232A
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26292626
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080A080A
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000814
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000404E2
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2533_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2533_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000098
|
||||
EMC_RFC_0 = 0x000002C6
|
||||
EMC_RAS_0 = 0x0000006B
|
||||
EMC_RP_0 = 0x0000002E
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002D
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002E
|
||||
EMC_WR_RCD_0 = 0x0000002E
|
||||
EMC_RRD_0 = 0x00000013
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002D
|
||||
EMC_QRST_0 = 0x00080009
|
||||
EMC_QSAFE_0 = 0x0000003F
|
||||
EMC_RDV_0 = 0x00000045
|
||||
EMC_REFRESH_0 = 0x00002657
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001A
|
||||
EMC_PDEX2RD_0 = 0x0000001A
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000024
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000002D9
|
||||
EMC_TCKE_0 = 0x00000015
|
||||
EMC_TFAW_0 = 0x0000004C
|
||||
EMC_TRPAB_0 = 0x00000036
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002697
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004A
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x027A0024
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003A
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000013
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000026
|
||||
EMC_TPD_0 = 0x00000013
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430031
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000047
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000045
|
||||
EMC_RDV_EARLY_0 = 0x00000043
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118627A
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000045
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000995
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004C44
|
||||
EMC_TXSRDLL_0 = 0x000002D9
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000037
|
||||
EMC_TR_RDV_MASK_0 = 0x00000047
|
||||
EMC_TR_QSAFE_0 = 0x0000003F
|
||||
EMC_TR_QRST_0 = 0x00080009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000023
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000037
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000292
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000163
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000C0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000C0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00260028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x10101111
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x0F0B090E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0E0F0D0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0B10070A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000008
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x15151717
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x11151607
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x424C4D4B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x4A49433E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000046
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0A0F0C0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0B0F0B0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0C0B0B0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0C0B0C08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1B1B1D1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x181A1517
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0F10090B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0E0B0E08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04080908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04010007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05090608
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x07070A0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060908
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x05030000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25222228
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26292526
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040299
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2566_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2566_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009A
|
||||
EMC_RFC_0 = 0x000002CF
|
||||
EMC_RAS_0 = 0x0000006C
|
||||
EMC_RP_0 = 0x0000002F
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002D
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x0000002F
|
||||
EMC_WR_RCD_0 = 0x0000002F
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002E
|
||||
EMC_QRST_0 = 0x0008000A
|
||||
EMC_QSAFE_0 = 0x00000040
|
||||
EMC_RDV_0 = 0x00000046
|
||||
EMC_REFRESH_0 = 0x000026D7
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000024
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000002E2
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004D
|
||||
EMC_TRPAB_0 = 0x00000036
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001D
|
||||
EMC_TREFBW_0 = 0x00002717
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004C
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02820024
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003A
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012CDE6
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000016
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000014
|
||||
EMC_EINPUT_DURATION_0 = 0x00000029
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000027
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000048
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000046
|
||||
EMC_RDV_EARLY_0 = 0x00000044
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186282
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000046
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009B5
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004D3F
|
||||
EMC_TXSRDLL_0 = 0x000002E2
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000038
|
||||
EMC_TR_RDV_MASK_0 = 0x00000048
|
||||
EMC_TR_QSAFE_0 = 0x00000040
|
||||
EMC_TR_QRST_0 = 0x0008000A
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030D
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000038
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000168
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00240029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0016000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x11111213
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x100C090F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0F110E0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0D11090C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x17171919
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x13171808
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x030D0E0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0B090400
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0C110E11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0D120D0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0D0C0C0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x0D0C0D0A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x1D1D1E1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1A1C1719
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x11120B0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0F0C1009
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090907
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A050A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03070004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0606090B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x07070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00060A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03050308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04010505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x03020102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020402
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08060307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232729
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26282626
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00150015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000A000A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000015
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000815
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040503
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2600_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2600_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x00000060
|
||||
EMC_RFC_0 = 0x000001C0
|
||||
EMC_RAS_0 = 0x00000044
|
||||
EMC_RP_0 = 0x0000001D
|
||||
EMC_R2W_0 = 0x00000029
|
||||
EMC_W2R_0 = 0x00000021
|
||||
EMC_R2P_0 = 0x0000000C
|
||||
EMC_W2P_0 = 0x0000002D
|
||||
EMC_RD_RCD_0 = 0x0000001D
|
||||
EMC_WR_RCD_0 = 0x0000001D
|
||||
EMC_RRD_0 = 0x00000010
|
||||
EMC_REXT_0 = 0x00000017
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x00000024
|
||||
EMC_QRST_0 = 0x0006000C
|
||||
EMC_QSAFE_0 = 0x00000033
|
||||
EMC_RDV_0 = 0x00000039
|
||||
EMC_REFRESH_0 = 0x00001820
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000010
|
||||
EMC_PDEX2RD_0 = 0x00000010
|
||||
EMC_PCHG2PDEN_0 = 0x00000003
|
||||
EMC_ACT2PDEN_0 = 0x00000017
|
||||
EMC_AR2PDEN_0 = 0x00000003
|
||||
EMC_RW2PDEN_0 = 0x00000038
|
||||
EMC_TXSR_0 = 0x000001CC
|
||||
EMC_TCKE_0 = 0x0000000D
|
||||
EMC_TFAW_0 = 0x00000040
|
||||
EMC_TRPAB_0 = 0x00000022
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x00000014
|
||||
EMC_TREFBW_0 = 0x00001860
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000002E
|
||||
EMC_WEXT_0 = 0x00000016
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x01900017
|
||||
EMC_MRS_WAIT_CNT_0 = 0x0640002F
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012C6E3
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000002
|
||||
EMC_CKE2PDEN_0 = 0x0000000E
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802002D
|
||||
EMC_MRW3_0 = 0x8C0D00C0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000014
|
||||
EMC_EINPUT_DURATION_0 = 0x0000001C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000018
|
||||
EMC_TPD_0 = 0x0000000C
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x00110835
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003B
|
||||
EMC_WDV_MASK_0 = 0x0000000E
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000039
|
||||
EMC_RDV_EARLY_0 = 0x00000037
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x00310640
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186190
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000039
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F070B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000608
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000308C
|
||||
EMC_TXSRDLL_0 = 0x000001CC
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002B
|
||||
EMC_TR_RDV_MASK_0 = 0x0000003B
|
||||
EMC_TR_QSAFE_0 = 0x00000033
|
||||
EMC_TR_QRST_0 = 0x0006000C
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00309
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002B
|
||||
EMC_QUSE_WIDTH_0 = 0x00000008
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000000E0
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A002018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x80200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x00210027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00080000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00080000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00240024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x001E0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x001F0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x2E2F2F2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2D2A292D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2C2E2C2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x33323333
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x30323328
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x262C2C2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2A2A2623
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x2C2F2D2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2C2B2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2C2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x36363635
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353233
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2F2E2A2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2C2B2D29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03040506
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x06040100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02040206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x05050503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23242425
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26252324
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2633_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2633_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x0000009E
|
||||
EMC_RFC_0 = 0x000002E2
|
||||
EMC_RAS_0 = 0x0000006F
|
||||
EMC_RP_0 = 0x00000030
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002E
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000030
|
||||
EMC_WR_RCD_0 = 0x00000030
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002E
|
||||
EMC_QRST_0 = 0x00080009
|
||||
EMC_QSAFE_0 = 0x00000040
|
||||
EMC_RDV_0 = 0x00000046
|
||||
EMC_REFRESH_0 = 0x000027DD
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000025
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000002F5
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x0000004F
|
||||
EMC_TRPAB_0 = 0x00000038
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000281D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004D
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02930025
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003B
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012ACC4
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000013
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000028
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000048
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000046
|
||||
EMC_RDV_EARLY_0 = 0x00000044
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186293
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000046
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x000009F7
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80004F3C
|
||||
EMC_TXSRDLL_0 = 0x000002F5
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000038
|
||||
EMC_TR_RDV_MASK_0 = 0x00000048
|
||||
EMC_TR_QSAFE_0 = 0x00000040
|
||||
EMC_TR_QRST_0 = 0x00080009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000038
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000171
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0x88200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230031
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x15151616
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x130F0D13
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x12141110
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x0F150C0F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1A1A1B1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x171A1B0B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x050F110F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0C0C0702
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0F141214
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x10141011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x100F0F10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x100F100C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2020211F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x1C1E191C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x14150E10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1210130C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x04090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A050A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03080005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080C09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09080300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04040606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04040303
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x05040104
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05040200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x27252628
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28272726
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040525
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2666_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2666_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A0
|
||||
EMC_RFC_0 = 0x000002EB
|
||||
EMC_RAS_0 = 0x00000070
|
||||
EMC_RP_0 = 0x00000030
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002E
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000030
|
||||
EMC_WR_RCD_0 = 0x00000030
|
||||
EMC_RRD_0 = 0x00000014
|
||||
EMC_REXT_0 = 0x0000001B
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002E
|
||||
EMC_QRST_0 = 0x00080009
|
||||
EMC_QSAFE_0 = 0x00000040
|
||||
EMC_RDV_0 = 0x00000046
|
||||
EMC_REFRESH_0 = 0x0000285D
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001B
|
||||
EMC_PDEX2RD_0 = 0x0000001B
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000026
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x000002FF
|
||||
EMC_TCKE_0 = 0x00000016
|
||||
EMC_TFAW_0 = 0x00000050
|
||||
EMC_TRPAB_0 = 0x00000038
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x0000289D
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004D
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x029B0026
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003B
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012BAD6
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000013
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002A
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000028
|
||||
EMC_TPD_0 = 0x00000014
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000048
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000046
|
||||
EMC_RDV_EARLY_0 = 0x00000044
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x0118629B
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000046
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A17
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005037
|
||||
EMC_TXSRDLL_0 = 0x000002FF
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000038
|
||||
EMC_TR_RDV_MASK_0 = 0x00000048
|
||||
EMC_TR_QSAFE_0 = 0x00000040
|
||||
EMC_TR_QRST_0 = 0x00080009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000038
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000176
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000D0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0017000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x16171717
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x15100E14
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x12151212
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x11160D10
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1B1B1D1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x181B1C0C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x07111311
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0F0D0903
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x10161216
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x11161112
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x11101012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1111110D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x22222320
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353233
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x16160F11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05080909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B050B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03090005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x0A0A0A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080B09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09080200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05030607
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04040304
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x06020303
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050206
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07050401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25252727
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27252627
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040535
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2700_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2700_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A2
|
||||
EMC_RFC_0 = 0x000002F4
|
||||
EMC_RAS_0 = 0x00000072
|
||||
EMC_RP_0 = 0x00000031
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002E
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000031
|
||||
EMC_WR_RCD_0 = 0x00000031
|
||||
EMC_RRD_0 = 0x00000015
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002D
|
||||
EMC_QRST_0 = 0x00080008
|
||||
EMC_QSAFE_0 = 0x00000040
|
||||
EMC_RDV_0 = 0x00000046
|
||||
EMC_REFRESH_0 = 0x000028E2
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001C
|
||||
EMC_PDEX2RD_0 = 0x0000001C
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000026
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x00000309
|
||||
EMC_TCKE_0 = 0x00000017
|
||||
EMC_TFAW_0 = 0x00000051
|
||||
EMC_TRPAB_0 = 0x00000039
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001E
|
||||
EMC_TREFBW_0 = 0x00002922
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000004F
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02A30026
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003B
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x801291A9
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000017
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000012
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002B
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000029
|
||||
EMC_TPD_0 = 0x00000015
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000048
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000046
|
||||
EMC_RDV_EARLY_0 = 0x00000044
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862A3
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000046
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A38
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000513A
|
||||
EMC_TXSRDLL_0 = 0x00000309
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000038
|
||||
EMC_TR_RDV_MASK_0 = 0x00000048
|
||||
EMC_TR_QSAFE_0 = 0x00000040
|
||||
EMC_TR_QRST_0 = 0x00080008
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000023
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000038
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000017A
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x17181818
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x16110F15
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x14171313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x12180E11
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000000F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1C1C1E1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1A1C1E0D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x08121512
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x100E0A04
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x11171417
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x12171313
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x13121213
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2C2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x23232422
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x34353234
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000001D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x18181112
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1512160F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000012
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03050606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050B050B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03090005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08070A0E
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090900
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01080B09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00040205
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08020303
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x03010002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04030103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x05040201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24242627
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x26262825
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00160016
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00050005
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000816
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2733_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2733_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A4
|
||||
EMC_RFC_0 = 0x000002FE
|
||||
EMC_RAS_0 = 0x00000073
|
||||
EMC_RP_0 = 0x00000032
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002F
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000032
|
||||
EMC_WR_RCD_0 = 0x00000032
|
||||
EMC_RRD_0 = 0x00000015
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002D
|
||||
EMC_QRST_0 = 0x00080007
|
||||
EMC_QSAFE_0 = 0x00000040
|
||||
EMC_RDV_0 = 0x00000046
|
||||
EMC_REFRESH_0 = 0x00002963
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001C
|
||||
EMC_PDEX2RD_0 = 0x0000001C
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000027
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x00000312
|
||||
EMC_TCKE_0 = 0x00000017
|
||||
EMC_TFAW_0 = 0x00000052
|
||||
EMC_TRPAB_0 = 0x0000003A
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x000029A3
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000050
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02AC0027
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003B
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122B41
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000018
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000011
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x00000029
|
||||
EMC_TPD_0 = 0x00000015
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000048
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000046
|
||||
EMC_RDV_EARLY_0 = 0x00000044
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862AC
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000039
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A58
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000308C
|
||||
EMC_TXSRDLL_0 = 0x00000312
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000038
|
||||
EMC_TR_RDV_MASK_0 = 0x00000048
|
||||
EMC_TR_QSAFE_0 = 0x00000040
|
||||
EMC_TR_QRST_0 = 0x00080007
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000023
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C0A
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000038
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000000E0
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A002010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000D0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000D0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00270029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x19191A1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x18131117
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2C2E2C2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1D1D1F1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1A1E1E0E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x09141514
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x12100B06
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000000E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x13191619
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2D2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x15141411
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x25252623
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x20231E20
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1A191114
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x05090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x060A060A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03080006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070A08
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08050000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060309
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04000306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01030003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08030404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05020103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06030401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232628
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x24262223
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040557
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C0A
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2766_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2766_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A6
|
||||
EMC_RFC_0 = 0x00000307
|
||||
EMC_RAS_0 = 0x00000075
|
||||
EMC_RP_0 = 0x00000032
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002F
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000032
|
||||
EMC_WR_RCD_0 = 0x00000032
|
||||
EMC_RRD_0 = 0x00000015
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080009
|
||||
EMC_QSAFE_0 = 0x00000041
|
||||
EMC_RDV_0 = 0x00000047
|
||||
EMC_REFRESH_0 = 0x000029E3
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001C
|
||||
EMC_PDEX2RD_0 = 0x0000001C
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000027
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000048
|
||||
EMC_TXSR_0 = 0x0000031C
|
||||
EMC_TCKE_0 = 0x00000017
|
||||
EMC_TFAW_0 = 0x00000053
|
||||
EMC_TRPAB_0 = 0x0000003B
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002A23
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000050
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02B40027
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003B
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80127289
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000018
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000013
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002B
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002A
|
||||
EMC_TPD_0 = 0x00000015
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000049
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000047
|
||||
EMC_RDV_EARLY_0 = 0x00000045
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862B4
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000047
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A78
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005330
|
||||
EMC_TXSRDLL_0 = 0x0000031C
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000039
|
||||
EMC_TR_RDV_MASK_0 = 0x00000049
|
||||
EMC_TR_QSAFE_0 = 0x00000041
|
||||
EMC_TR_QRST_0 = 0x00080009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030E
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000039
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000184
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0018000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00080000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000009
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x001F0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1A1A1B1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x19141218
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x171B1717
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x1F1E2120
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1B1E200F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000031
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0B161615
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x13110D07
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000010
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x151B181B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x151B1716
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x16141616
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x15151612
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x27272725
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x27282527
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000020
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1B1A1314
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2C2B2E29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0509090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x04000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x050A050A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03080005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070C09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04040607
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04030003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x06050105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x06040401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25232628
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25252523
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040567
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2800_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2800_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000A8
|
||||
EMC_RFC_0 = 0x00000310
|
||||
EMC_RAS_0 = 0x00000076
|
||||
EMC_RP_0 = 0x00000033
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x0000002F
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000033
|
||||
EMC_WR_RCD_0 = 0x00000033
|
||||
EMC_RRD_0 = 0x00000015
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x0006000C
|
||||
EMC_QSAFE_0 = 0x00000041
|
||||
EMC_RDV_0 = 0x00000047
|
||||
EMC_REFRESH_0 = 0x00002A68
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001C
|
||||
EMC_PDEX2RD_0 = 0x0000001C
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000028
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x00000325
|
||||
EMC_TCKE_0 = 0x00000017
|
||||
EMC_TFAW_0 = 0x00000054
|
||||
EMC_TRPAB_0 = 0x0000003B
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002AA8
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000051
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02BC0028
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003B
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122B42
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000018
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000013
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002B
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002A
|
||||
EMC_TPD_0 = 0x00000015
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000049
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000047
|
||||
EMC_RDV_EARLY_0 = 0x00000045
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862BC
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000047
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000A9A
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005432
|
||||
EMC_TXSRDLL_0 = 0x00000325
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000039
|
||||
EMC_TR_RDV_MASK_0 = 0x00000049
|
||||
EMC_TR_QSAFE_0 = 0x00000041
|
||||
EMC_TR_QRST_0 = 0x00080009
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000039
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000188
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A002010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230032
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00240027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1C1B1C1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1A151319
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x181C1818
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x161B1215
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000013
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x21212323
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1D212211
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x0000001F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0C161816
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x14120E08
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000011
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x151B191B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x17161717
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x17171613
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x28282A27
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x25272123
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000021
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1B1C1416
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x18161A13
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03040606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05010006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090C050C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060A0007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080A0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08070100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03070509
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04040706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x06040403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x09030404
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05030103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x08050107
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08040603
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25222326
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x23262523
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00190019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040578
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2833_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2833_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000AA
|
||||
EMC_RFC_0 = 0x0000031A
|
||||
EMC_RAS_0 = 0x00000077
|
||||
EMC_RP_0 = 0x00000033
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x00000030
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000033
|
||||
EMC_WR_RCD_0 = 0x00000033
|
||||
EMC_RRD_0 = 0x00000016
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x0000000E
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080008
|
||||
EMC_QSAFE_0 = 0x00000041
|
||||
EMC_RDV_0 = 0x00000033
|
||||
EMC_REFRESH_0 = 0x00002AE9
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001D
|
||||
EMC_PDEX2RD_0 = 0x0000001D
|
||||
EMC_PCHG2PDEN_0 = 0x00000005
|
||||
EMC_ACT2PDEN_0 = 0x00000028
|
||||
EMC_AR2PDEN_0 = 0x00000005
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x0000032F
|
||||
EMC_TCKE_0 = 0x00000018
|
||||
EMC_TFAW_0 = 0x00000055
|
||||
EMC_TRPAB_0 = 0x0000003C
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002B29
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000052
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02C50028
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003B
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80040101
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000003
|
||||
EMC_CKE2PDEN_0 = 0x00000019
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000012
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002B
|
||||
EMC_TPD_0 = 0x00000016
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000049
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000047
|
||||
EMC_RDV_EARLY_0 = 0x00000045
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862C5
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000033
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F070B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000ABA
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000552D
|
||||
EMC_TXSRDLL_0 = 0x0000032F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000039
|
||||
EMC_TR_RDV_MASK_0 = 0x00000049
|
||||
EMC_TR_QSAFE_0 = 0x00000041
|
||||
EMC_TR_QRST_0 = 0x00080008
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x0000000C
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0D09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000039
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000000E0
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A082010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8280002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000E0017
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0003000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00240028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x1C1C1C1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1B17131A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1A1C1A1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x181C1416
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x22222524
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x1E232412
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000030
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0D181A17
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2A2A2624
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x2C2F2D2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x181C181A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x19171914
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000002C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x36363736
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x25282225
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000023
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1D1D1618
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1A171B14
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x050A0A09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x080B050B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x05090006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080A0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00070C09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08070100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03070509
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x03000305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00020002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05020103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09060107
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x08040603
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25232227
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x23252124
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00170017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000B000B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00190019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000017
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000817
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040589
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000D09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2866_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2866_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000AC
|
||||
EMC_RFC_0 = 0x00000323
|
||||
EMC_RAS_0 = 0x00000079
|
||||
EMC_RP_0 = 0x00000034
|
||||
EMC_R2W_0 = 0x00000033
|
||||
EMC_W2R_0 = 0x00000030
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000034
|
||||
EMC_WR_RCD_0 = 0x00000034
|
||||
EMC_RRD_0 = 0x00000016
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080008
|
||||
EMC_QSAFE_0 = 0x00000041
|
||||
EMC_RDV_0 = 0x00000047
|
||||
EMC_REFRESH_0 = 0x00002B69
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001E
|
||||
EMC_PDEX2RD_0 = 0x0000001E
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x00000029
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x00000338
|
||||
EMC_TCKE_0 = 0x00000018
|
||||
EMC_TFAW_0 = 0x00000056
|
||||
EMC_TRPAB_0 = 0x0000003D
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002BA9
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000054
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02CD0029
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003C
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012485F
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x00000019
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000012
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002B
|
||||
EMC_TPD_0 = 0x00000016
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000049
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000047
|
||||
EMC_RDV_EARLY_0 = 0x00000045
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862CD
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000047
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000608
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005628
|
||||
EMC_TXSRDLL_0 = 0x00000338
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000039
|
||||
EMC_TR_RDV_MASK_0 = 0x00000049
|
||||
EMC_TR_QSAFE_0 = 0x00000041
|
||||
EMC_TR_QRST_0 = 0x00080008
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C08
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000039
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x00000192
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC0200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x00280029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x001F0022
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x201F1F20
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1D19171D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1B1D1B1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x191D1518
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x24242625
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x20242513
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0E191A19
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1816100B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x181F1C1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x191E1B1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1B191A1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1A1A1A16
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2B2B2D29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x27282426
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x1F1F171A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1B191D16
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x040A0B0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0C060C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060A0007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080B0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080C09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08060100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090509
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0308060A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04040606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05040302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0A060109
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0A040705
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232227
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x21252524
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00190019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040599
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C08
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2900_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2900_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000AE
|
||||
EMC_RFC_0 = 0x0000032C
|
||||
EMC_RAS_0 = 0x0000007A
|
||||
EMC_RP_0 = 0x00000035
|
||||
EMC_R2W_0 = 0x00000034
|
||||
EMC_W2R_0 = 0x00000030
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000035
|
||||
EMC_WR_RCD_0 = 0x00000035
|
||||
EMC_RRD_0 = 0x00000016
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080008
|
||||
EMC_QSAFE_0 = 0x00000041
|
||||
EMC_RDV_0 = 0x00000047
|
||||
EMC_REFRESH_0 = 0x00002BEE
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001E
|
||||
EMC_PDEX2RD_0 = 0x0000001E
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x00000029
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x00000342
|
||||
EMC_TCKE_0 = 0x00000018
|
||||
EMC_TFAW_0 = 0x00000057
|
||||
EMC_TRPAB_0 = 0x0000003D
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002C2E
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000055
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02D50029
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003C
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80123C53
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x00000019
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000012
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002C
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002C
|
||||
EMC_TPD_0 = 0x00000016
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0F430025
|
||||
EMC_CFG_2_0 = 0x00110835
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000003B
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000039
|
||||
EMC_RDV_EARLY_0 = 0x00000045
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862D5
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000047
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000AFB
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x8000572B
|
||||
EMC_TXSRDLL_0 = 0x00000342
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000039
|
||||
EMC_TR_RDV_MASK_0 = 0x00000049
|
||||
EMC_TR_QSAFE_0 = 0x00000041
|
||||
EMC_TR_QRST_0 = 0x00080008
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000039
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000B
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000000E0
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x0019000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x0019000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000E0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000E0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x20202021
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1E19171E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1C1E1B1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1B1E1619
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000017
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x26262827
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x22252716
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x0F1A1B19
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1817110B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000014
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x191E1C1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1A1E1B1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1B1A1A1B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1A1A1B17
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2D2D2E2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x282A2527
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000025
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x211F181B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1C1A1E16
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x050B0B0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090B050C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x060A0007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08090C10
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080C0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09070100
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090509
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x01040105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04040606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x05030403
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08050504
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05040005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x07030401
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x22232327
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x25252023
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x00190019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x070B070B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000818
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2933_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2933_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000B0
|
||||
EMC_RFC_0 = 0x00000336
|
||||
EMC_RAS_0 = 0x0000007C
|
||||
EMC_RP_0 = 0x00000035
|
||||
EMC_R2W_0 = 0x00000034
|
||||
EMC_W2R_0 = 0x00000031
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000035
|
||||
EMC_WR_RCD_0 = 0x00000035
|
||||
EMC_RRD_0 = 0x00000016
|
||||
EMC_REXT_0 = 0x0000001C
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002E
|
||||
EMC_QRST_0 = 0x00080006
|
||||
EMC_QSAFE_0 = 0x00000041
|
||||
EMC_RDV_0 = 0x00000047
|
||||
EMC_REFRESH_0 = 0x00002C6F
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001E
|
||||
EMC_PDEX2RD_0 = 0x0000001E
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x0000002A
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x0000034C
|
||||
EMC_TCKE_0 = 0x00000018
|
||||
EMC_TFAW_0 = 0x00000058
|
||||
EMC_TRPAB_0 = 0x0000003E
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002CAF
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000055
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02DE002A
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003C
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80123147
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x00000019
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000010
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002E
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002C
|
||||
EMC_TPD_0 = 0x00000016
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1E190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x00000049
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000047
|
||||
EMC_RDV_EARLY_0 = 0x00000045
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862DE
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000047
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B1B
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005826
|
||||
EMC_TXSRDLL_0 = 0x0000034C
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x00000039
|
||||
EMC_TR_RDV_MASK_0 = 0x00000049
|
||||
EMC_TR_QSAFE_0 = 0x00000041
|
||||
EMC_TR_QRST_0 = 0x00080006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000024
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C07
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x00000039
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x0000019B
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001A000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230033
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0018
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001A000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x21212022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x1F1A181F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000001E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1D201C1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1B1F181A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x28282A29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x24262817
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000025
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x101B1E1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1918120D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1B211E21
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1B201C1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000001F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1D1B1C1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1B1C1C19
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x2F2F302D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2A2C2729
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000027
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2222191C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x1E1C1F18
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03050606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06010007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080E0B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A090300
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00080409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0307040A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x04030607
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x04040303
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07050603
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05040005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09050107
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09030603
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x25212224
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22232422
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00180018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001A001A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000018
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000818
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000405BB
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C07
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/2966_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/2966_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000B2
|
||||
EMC_RFC_0 = 0x0000033F
|
||||
EMC_RAS_0 = 0x0000007D
|
||||
EMC_RP_0 = 0x00000036
|
||||
EMC_R2W_0 = 0x00000034
|
||||
EMC_W2R_0 = 0x00000031
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000036
|
||||
EMC_WR_RCD_0 = 0x00000036
|
||||
EMC_RRD_0 = 0x00000017
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080007
|
||||
EMC_QSAFE_0 = 0x00000042
|
||||
EMC_RDV_0 = 0x00000048
|
||||
EMC_REFRESH_0 = 0x00002CEF
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x0000001F
|
||||
EMC_PDEX2RD_0 = 0x0000001F
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x0000002A
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x00000355
|
||||
EMC_TCKE_0 = 0x00000019
|
||||
EMC_TFAW_0 = 0x00000059
|
||||
EMC_TRPAB_0 = 0x0000003F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002D2F
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000057
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02E6002A
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003C
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012263C
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x0000001A
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000011
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002E
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002D
|
||||
EMC_TPD_0 = 0x00000017
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000004A
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000048
|
||||
EMC_RDV_EARLY_0 = 0x00000046
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x00290534
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862E6
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000048
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B3B
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005921
|
||||
EMC_TXSRDLL_0 = 0x00000355
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000002B
|
||||
EMC_TR_RDV_MASK_0 = 0x0000004A
|
||||
EMC_TR_QSAFE_0 = 0x00000033
|
||||
EMC_TR_QRST_0 = 0x0006000C
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E0030F
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000003A
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000001A0
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0019
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001A000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00210029
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0008000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x000E0006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x00000005
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000003
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00220023
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x23232324
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x2D2B292D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000020
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1E221E1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1C22191C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x33323333
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x24282A17
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000025
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x1B212120
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1B19140E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1B211D22
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1C211D1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1E1C1D1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1D1C1D1A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x3030322E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2B2D272B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2F2E2B2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x2D2B2E29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x03050606
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x04050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06060709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090B00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080D0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x09080200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x000B0608
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03090909
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02010102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x02040103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x09040603
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x05030005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04030103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020201
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232427
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x28272523
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001A001A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000818
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/3000_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/3000_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000B4
|
||||
EMC_RFC_0 = 0x00000348
|
||||
EMC_RAS_0 = 0x0000007E
|
||||
EMC_RP_0 = 0x00000036
|
||||
EMC_R2W_0 = 0x00000034
|
||||
EMC_W2R_0 = 0x00000031
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000036
|
||||
EMC_WR_RCD_0 = 0x00000036
|
||||
EMC_RRD_0 = 0x00000017
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080007
|
||||
EMC_QSAFE_0 = 0x00000042
|
||||
EMC_RDV_0 = 0x00000048
|
||||
EMC_REFRESH_0 = 0x00002D74
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000020
|
||||
EMC_PDEX2RD_0 = 0x00000020
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x0000002A
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x0000035F
|
||||
EMC_TCKE_0 = 0x00000019
|
||||
EMC_TFAW_0 = 0x0000005A
|
||||
EMC_TRPAB_0 = 0x0000003F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002DB4
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000058
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02EE002A
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003C
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80121B31
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x0000001A
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000011
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002E
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002D
|
||||
EMC_TPD_0 = 0x00000017
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430021
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000004A
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000048
|
||||
EMC_RDV_EARLY_0 = 0x00000046
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862EE
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000048
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B5D
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005A23
|
||||
EMC_TXSRDLL_0 = 0x0000035F
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000003A
|
||||
EMC_TR_RDV_MASK_0 = 0x0000004A
|
||||
EMC_TR_QSAFE_0 = 0x00000042
|
||||
EMC_TR_QRST_0 = 0x00080007
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00310
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C08
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000003A
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000001A4
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8204002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0019
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001A000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230034
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0019
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001A000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00260028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x24252525
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x221C1A22
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000021
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x1F231F1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1D23191C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x2B2A2C2B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x25282B18
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000026
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x141F211F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1B1B150F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1C241F23
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1D231E1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1F1C1D1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1F1D1E1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x32323330
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2C2F292C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000002A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x24231B1E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x211D221A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x040A0A0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x06000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090E070E
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x070C0008
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0A0A0D10
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x08090A00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01090D0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A070200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05000408
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x00040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x0A050505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x06030105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x09060107
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x22202526
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x22271F22
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00190019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001A001A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000818
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000405DC
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C08
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/3033_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/3033_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000B6
|
||||
EMC_RFC_0 = 0x00000352
|
||||
EMC_RAS_0 = 0x0000007F
|
||||
EMC_RP_0 = 0x00000037
|
||||
EMC_R2W_0 = 0x00000034
|
||||
EMC_W2R_0 = 0x00000032
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000037
|
||||
EMC_WR_RCD_0 = 0x00000037
|
||||
EMC_RRD_0 = 0x00000017
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080006
|
||||
EMC_QSAFE_0 = 0x00000042
|
||||
EMC_RDV_0 = 0x00000048
|
||||
EMC_REFRESH_0 = 0x00002DF5
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000020
|
||||
EMC_PDEX2RD_0 = 0x00000020
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x0000002B
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x00000368
|
||||
EMC_TCKE_0 = 0x00000019
|
||||
EMC_TFAW_0 = 0x0000005B
|
||||
EMC_TRPAB_0 = 0x0000003F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002E35
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x00000059
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02F7002B
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003C
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80120C22
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x0000001A
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000010
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002F
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002E
|
||||
EMC_TPD_0 = 0x00000017
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000004A
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000048
|
||||
EMC_RDV_EARLY_0 = 0x00000046
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862F7
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000048
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B7D
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005B1E
|
||||
EMC_TXSRDLL_0 = 0x00000368
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000003A
|
||||
EMC_TR_RDV_MASK_0 = 0x0000004A
|
||||
EMC_TR_QSAFE_0 = 0x00000042
|
||||
EMC_TR_QRST_0 = 0x00080006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00310
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000A
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C08
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000003A
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000001A9
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x000F0019
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001B000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x00200027
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x00230026
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230034
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x000F0019
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001B000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00080000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00260028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00210027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x25262627
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x231D1B23
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x20232020
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1F241B1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x2C2B2D2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x272A2C19
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000027
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x15202220
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1D1C1611
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1E252225
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2C2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000024
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x201E1F21
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x37373735
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2E302B2E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000002C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x25251D1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x221E231B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x0409090A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x05000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x090E060E
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x070C0008
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x0A0A0D0F
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090B00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000007
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00090D09
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A070200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0008050A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x0407040A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x05000307
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01040103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08040603
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04040005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0A050109
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x09040704
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x22202526
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x20232122
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x00190019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x000F000F
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x00000019
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000080D
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000405ED
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C08
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/3066_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/3066_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000B7
|
||||
EMC_RFC_0 = 0x0000035B
|
||||
EMC_RAS_0 = 0x0000007F
|
||||
EMC_RP_0 = 0x00000038
|
||||
EMC_R2W_0 = 0x00000034
|
||||
EMC_W2R_0 = 0x00000032
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000038
|
||||
EMC_WR_RCD_0 = 0x00000038
|
||||
EMC_RRD_0 = 0x00000017
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080006
|
||||
EMC_QSAFE_0 = 0x00000042
|
||||
EMC_RDV_0 = 0x00000048
|
||||
EMC_REFRESH_0 = 0x00002E75
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000020
|
||||
EMC_PDEX2RD_0 = 0x00000020
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x0000002B
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x00000372
|
||||
EMC_TCKE_0 = 0x00000019
|
||||
EMC_TFAW_0 = 0x0000005C
|
||||
EMC_TRPAB_0 = 0x0000003F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002EB5
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000005A
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x02FF002B
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003C
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012162B
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x0000001B
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000010
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002F
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002E
|
||||
EMC_TPD_0 = 0x00000017
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000004A
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000048
|
||||
EMC_RDV_EARLY_0 = 0x00000046
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x011862FF
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000039
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000B9D
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005C19
|
||||
EMC_TXSRDLL_0 = 0x00000372
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000003A
|
||||
EMC_TR_RDV_MASK_0 = 0x0000004A
|
||||
EMC_TR_QSAFE_0 = 0x00000042
|
||||
EMC_TR_QRST_0 = 0x00080006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00310
|
||||
EMC_IBDLY_0 = 0x10000025
|
||||
EMC_OBDLY_0 = 0x10000004
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000003A
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000000E0
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000012
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x00100019
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001B000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x0022002A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x00100019
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001B000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x00000006
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000015
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x00020007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0029002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220024
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00230027
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x26262626
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x221A1922
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000023
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x21242121
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x1D24191B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x29292929
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x27282919
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000027
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x121E211F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1C1C1410
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000019
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1F252325
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1F272021
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000023
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x211F1F21
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1F1E211D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x34353530
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2B30282B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000032
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x2526191C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x211D2219
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x080B0B0C
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0E060E
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x070D0009
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x090A0C12
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x09090B00
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000008
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x01060707
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x0A090200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x0004020A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02060406
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01010001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x08040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04030004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x0A060208
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x0A050706
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x23232427
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x20252121
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000C000C
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001B001B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000819
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x000405FD
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/3100_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/3100_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000B7
|
||||
EMC_RFC_0 = 0x00000364
|
||||
EMC_RAS_0 = 0x0000007F
|
||||
EMC_RP_0 = 0x00000038
|
||||
EMC_R2W_0 = 0x00000035
|
||||
EMC_W2R_0 = 0x00000032
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000038
|
||||
EMC_WR_RCD_0 = 0x00000038
|
||||
EMC_RRD_0 = 0x00000018
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080006
|
||||
EMC_QSAFE_0 = 0x00000042
|
||||
EMC_RDV_0 = 0x00000048
|
||||
EMC_REFRESH_0 = 0x00002EFA
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000021
|
||||
EMC_PDEX2RD_0 = 0x00000021
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x0000002C
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x0000037C
|
||||
EMC_TCKE_0 = 0x0000001A
|
||||
EMC_TFAW_0 = 0x0000005D
|
||||
EMC_TRPAB_0 = 0x0000003F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002F3A
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000005B
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x0307002C
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003C
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x80122F44
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x0000001B
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D00D0
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x00000010
|
||||
EMC_EINPUT_DURATION_0 = 0x0000002F
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002F
|
||||
EMC_TPD_0 = 0x00000018
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x0011083D
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000004A
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000048
|
||||
EMC_RDV_EARLY_0 = 0x00000046
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186307
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000048
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000BBE
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005D1C
|
||||
EMC_TXSRDLL_0 = 0x0000037C
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000003A
|
||||
EMC_TR_RDV_MASK_0 = 0x0000004A
|
||||
EMC_TR_QSAFE_0 = 0x00000042
|
||||
EMC_TR_QRST_0 = 0x00080006
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00310
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0C09
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000002B
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000C
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000249
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000001B2
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000012
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A012018
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0010001A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001B000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0025002B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00230035
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0010001A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001B000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x000F0000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x000F0000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00250028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00210028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x25262526
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x251F1A25
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x0000002D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x2C2E2D2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x2B2E292A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000029
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x2E2B2E2E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x30323329
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000026
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x252C2D2C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x2B2A2623
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x2C2F2E2F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x2D2F2C2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x0000002E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x2D2C2D2D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x2C2C2D2A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001A
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x32353531
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x2F32292E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x26251B1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x211E2418
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x040B0B0B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x03000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x0A0E060E
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x04050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x06050709
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06060700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00040505
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08070000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00090509
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x02050306
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000005
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x02000102
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x07040503
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04040004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x07050105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x03020200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x22222426
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27252325
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00100010
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x00060006
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x001B001B
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1E191E19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x00000819
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000C09
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
528
timings/Mariko/AA/2133/emc/3133_emc.txt
Normal file
528
timings/Mariko/AA/2133/emc/3133_emc.txt
Normal file
@@ -0,0 +1,528 @@
|
||||
Dumping EMC registers from BASE=0x7001B000
|
||||
-----------------------------------
|
||||
EMC_INTSTATUS_0 = 0x00000030
|
||||
EMC_INTMASK_0 = 0x00000000
|
||||
EMC_DBG_0 = 0x01000C00
|
||||
EMC_CFG_0 = 0xF3200000
|
||||
EMC_ADR_CFG_0 = 0x00000000
|
||||
EMC_REFCTRL_0 = 0x80000002
|
||||
EMC_PIN_0 = 0x00003101
|
||||
EMC_TIMING_CONTROL_0 = 0x00000001
|
||||
EMC_RC_0 = 0x000000B8
|
||||
EMC_RFC_0 = 0x0000036E
|
||||
EMC_RAS_0 = 0x0000007F
|
||||
EMC_RP_0 = 0x00000039
|
||||
EMC_R2W_0 = 0x00000035
|
||||
EMC_W2R_0 = 0x00000033
|
||||
EMC_R2P_0 = 0x00000010
|
||||
EMC_W2P_0 = 0x0000003B
|
||||
EMC_RD_RCD_0 = 0x00000039
|
||||
EMC_WR_RCD_0 = 0x00000039
|
||||
EMC_RRD_0 = 0x00000018
|
||||
EMC_REXT_0 = 0x0000001D
|
||||
EMC_WDV_0 = 0x00000012
|
||||
EMC_QUSE_0 = 0x0000002F
|
||||
EMC_QRST_0 = 0x00080005
|
||||
EMC_QSAFE_0 = 0x00000044
|
||||
EMC_RDV_0 = 0x00000049
|
||||
EMC_REFRESH_0 = 0x00002F7B
|
||||
EMC_BURST_REFRESH_NUM_0 = 0x00000000
|
||||
EMC_PDEX2WR_0 = 0x00000021
|
||||
EMC_PDEX2RD_0 = 0x00000021
|
||||
EMC_PCHG2PDEN_0 = 0x00000006
|
||||
EMC_ACT2PDEN_0 = 0x0000002C
|
||||
EMC_AR2PDEN_0 = 0x00000006
|
||||
EMC_RW2PDEN_0 = 0x00000049
|
||||
EMC_TXSR_0 = 0x00000385
|
||||
EMC_TCKE_0 = 0x0000001A
|
||||
EMC_TFAW_0 = 0x0000005E
|
||||
EMC_TRPAB_0 = 0x0000003F
|
||||
EMC_TCLKSTABLE_0 = 0x00000004
|
||||
EMC_TCLKSTOP_0 = 0x0000001F
|
||||
EMC_TREFBW_0 = 0x00002FBB
|
||||
EMC_TPPD_0 = 0x00000004
|
||||
EMC_ODT_WRITE_0 = 0x00000000
|
||||
EMC_PDEX2MRR_0 = 0x0000005C
|
||||
EMC_WEXT_0 = 0x00000019
|
||||
EMC_RFC_SLR_0 = 0x00000000
|
||||
EMC_MRS_WAIT_CNT2_0 = 0x0310002C
|
||||
EMC_MRS_WAIT_CNT_0 = 0x07FF003C
|
||||
EMC_MRS_0 = 0x00000000
|
||||
EMC_EMRS_0 = 0x00000000
|
||||
EMC_REF_0 = 0x80000000
|
||||
EMC_PRE_0 = 0x00000000
|
||||
EMC_NOP_0 = 0x00000000
|
||||
EMC_SELF_REF_0 = 0x00000000
|
||||
EMC_DPD_0 = 0x00000000
|
||||
EMC_MRW_0 = 0x00170040
|
||||
EMC_MRR_0 = 0x8012364C
|
||||
EMC_CMDQ_0 = 0x10004408
|
||||
EMC_MC2EMCQ_0 = 0x06000404
|
||||
EMC_FBIO_SPARE_0 = 0x00000012
|
||||
EMC_FBIO_CFG5_0 = 0x9160A00D
|
||||
EMC_FBIO_CFG6_0 = 0x00001010
|
||||
EMC_PDEX2CKE_0 = 0x00000004
|
||||
EMC_CKE2PDEN_0 = 0x0000001B
|
||||
EMC_CFG_RSV_0 = 0xFF00FF00
|
||||
EMC_ACPD_CONTROL_0 = 0x00000000
|
||||
EMC_MPC_0 = 0x0000004B
|
||||
EMC_EMRS2_0 = 0x00000000
|
||||
EMC_EMRS3_0 = 0x00000000
|
||||
EMC_MRW2_0 = 0x8802003F
|
||||
EMC_MRW3_0 = 0x8C0D0010
|
||||
EMC_MRW4_0 = 0xC0000000
|
||||
EMC_CLKEN_OVERRIDE_0 = 0x00000000
|
||||
EMC_R2R_0 = 0x00000000
|
||||
EMC_W2W_0 = 0x00000000
|
||||
EMC_EINPUT_0 = 0x0000000F
|
||||
EMC_EINPUT_DURATION_0 = 0x00000031
|
||||
EMC_PUTERM_EXTRA_0 = 0x00000001
|
||||
EMC_TCKESR_0 = 0x0000002F
|
||||
EMC_TPD_0 = 0x00000018
|
||||
EMC_AUTO_CAL_CONFIG_0 = 0x201A51D8
|
||||
EMC_AUTO_CAL_INTERVAL_0 = 0x001FFFFF
|
||||
EMC_AUTO_CAL_STATUS_0 = 0x1D190000
|
||||
EMC_REQ_CTRL_0 = 0x00000000
|
||||
EMC_EMC_STATUS_0 = 0x0B430035
|
||||
EMC_CFG_2_0 = 0x00110835
|
||||
EMC_CFG_DIG_DLL_0 = 0x002C03A9
|
||||
EMC_CFG_DIG_DLL_PERIOD_0 = 0x00008000
|
||||
EMC_DIG_DLL_STATUS_0 = 0x00000004
|
||||
EMC_CFG_DIG_DLL_1_0 = 0x000F3701
|
||||
EMC_RDV_MASK_0 = 0x0000004B
|
||||
EMC_WDV_MASK_0 = 0x00000012
|
||||
EMC_RDV_EARLY_MASK_0 = 0x00000049
|
||||
EMC_RDV_EARLY_0 = 0x00000047
|
||||
EMC_AUTO_CAL_CONFIG8_0 = 0x00880000
|
||||
EMC_ZCAL_INTERVAL_0 = 0x00064000
|
||||
EMC_ZCAL_WAIT_CNT_0 = 0x003F07FF
|
||||
EMC_ZCAL_MRW_CMD_0 = 0x8051004F
|
||||
EMC_ZQ_CAL_0 = 0x80000002
|
||||
EMC_XM2COMPPADCTRL3_0 = 0x00901000
|
||||
EMC_AUTO_CAL_VREF_SEL_0_0 = 0xC9AFBCBC
|
||||
EMC_AUTO_CAL_VREF_SEL_1_0 = 0x00009E3C
|
||||
EMC_XM2COMPPADCTRL_0 = 0x00000030
|
||||
EMC_FDPD_CTRL_DQ_0 = 0x8020221F
|
||||
EMC_FDPD_CTRL_CMD_0 = 0x0220F40F
|
||||
EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 = 0x00000000
|
||||
EMC_SCRATCH0_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU1_0 = 0x00000000
|
||||
EMC_PMACRO_BRICK_CTRL_RFU2_0 = 0x00000000
|
||||
EMC_CMD_MAPPING_CMD0_0_0 = 0x061B0504
|
||||
EMC_CMD_MAPPING_CMD0_1_0 = 0x1C070302
|
||||
EMC_CMD_MAPPING_CMD0_2_0 = 0x05252523
|
||||
EMC_CMD_MAPPING_CMD1_0_0 = 0x0A091D08
|
||||
EMC_CMD_MAPPING_CMD1_1_0 = 0x0D1E0B24
|
||||
EMC_CMD_MAPPING_CMD1_2_0 = 0x0326260C
|
||||
EMC_CMD_MAPPING_CMD2_0_0 = 0x231C1B02
|
||||
EMC_CMD_MAPPING_CMD2_1_0 = 0x05070403
|
||||
EMC_CMD_MAPPING_CMD2_2_0 = 0x02252506
|
||||
EMC_CMD_MAPPING_CMD3_0_0 = 0x0D1D0B0A
|
||||
EMC_CMD_MAPPING_CMD3_1_0 = 0x1E090C08
|
||||
EMC_CMD_MAPPING_CMD3_2_0 = 0x08262624
|
||||
EMC_CMD_MAPPING_BYTE_0 = 0x9A070624
|
||||
EMC_TR_TIMING_0_0 = 0x01186310
|
||||
EMC_TR_CTRL_0_0 = 0x00000020
|
||||
EMC_TR_CTRL_1_0 = 0x00000000
|
||||
EMC_SWITCH_BACK_CTRL_0 = 0x00000001
|
||||
EMC_TR_RDV_0 = 0x00000049
|
||||
EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 = 0x00000000
|
||||
EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 = 0x00000000
|
||||
EMC_AUTO_CAL_ = 0x3F1F080B
|
||||
EMC_SEL_DPD_CTRL_0 = 0x0004000C
|
||||
EMC_PRE_REFRESH_REQ_CNT_0 = 0x00000BDE
|
||||
EMC_DYN_SELF_REF_CONTROL_0 = 0x80005E17
|
||||
EMC_TXSRDLL_0 = 0x00000385
|
||||
EMC_CCFIFO_ADDR_0 = 0x80000000
|
||||
EMC_CCFIFO_DATA_0 = 0x00000000
|
||||
EMC_CCFIFO_STATUS_0 = 0x00000000
|
||||
EMC_TR_QPOP_0 = 0x0000003B
|
||||
EMC_TR_RDV_MASK_0 = 0x0000004B
|
||||
EMC_TR_QSAFE_0 = 0x00000044
|
||||
EMC_TR_QRST_0 = 0x00080005
|
||||
EMC_SWIZZLE_RANK0_BYTE0_0 = 0x76543201
|
||||
EMC_SWIZZLE_RANK0_BYTE1_0 = 0x65324710
|
||||
EMC_SWIZZLE_RANK0_BYTE2_0 = 0x25763410
|
||||
EMC_SWIZZLE_RANK0_BYTE3_0 = 0x25673401
|
||||
EMC_SWIZZLE_RANK1_BYTE0_0 = 0x32647501
|
||||
EMC_SWIZZLE_RANK1_BYTE1_0 = 0x34567201
|
||||
EMC_SWIZZLE_RANK1_BYTE2_0 = 0x56742310
|
||||
EMC_SWIZZLE_RANK1_BYTE3_0 = 0x67324501
|
||||
EMC_ISSUE_QRST_0 = 0x00000000
|
||||
EMC_PMC_SCRATCH1_0 = 0x4FAF9FFF
|
||||
EMC_PMC_SCRATCH2_0 = 0x7FFFFFFF
|
||||
EMC_PMC_SCRATCH3_0 = 0x4036D71F
|
||||
EMC_AUTO_CAL_CONFIG2_0 = 0x05500000
|
||||
EMC_AUTO_CAL_CONFIG3_0 = 0x00880000
|
||||
EMC_TR_DVFS_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CHANNEL_0 = 0xC1E00310
|
||||
EMC_IBDLY_0 = 0x1000001C
|
||||
EMC_OBDLY_0 = 0x10000002
|
||||
EMC_TXDSRVTTGEN_0 = 0x00000000
|
||||
EMC_WE_DURATION_0 = 0x0000000E
|
||||
EMC_WS_DURATION_0 = 0x00000008
|
||||
EMC_WEV_0 = 0x0000000E
|
||||
EMC_WSV_0 = 0x00000010
|
||||
EMC_CFG_3_0 = 0x00000040
|
||||
EMC_MRW5_0 = 0x00000000
|
||||
EMC_MRW6_0 = 0x8803F1F1
|
||||
EMC_MRW7_0 = 0xC803F1F1
|
||||
EMC_MRW8_0 = 0x880B0606
|
||||
EMC_MRW9_0 = 0x8C0E5D5D
|
||||
EMC_MRW10_0 = 0x880C5D5D
|
||||
EMC_MRW11_0 = 0xC80C5D5D
|
||||
EMC_MRW12_0 = 0x880E0E0B
|
||||
EMC_MRW13_0 = 0xC80E0000
|
||||
EMC_MRW14_0 = 0x88161414
|
||||
EMC_MRW15_0 = 0xC8161414
|
||||
EMC_CFG_SYNC_0 = 0x00000001
|
||||
EMC_FDPD_CTRL_CMD_NO_RAMP_0 = 0x00000001
|
||||
EMC_WDV_CHK_0 = 0x00000006
|
||||
EMC_CFG_PIPE_2_0 = 0x00000000
|
||||
EMC_CFG_PIPE_CLK_0 = 0x00000000
|
||||
EMC_CFG_PIPE_1_0 = 0x0FFF0000
|
||||
EMC_CFG_PIPE_0 = 0x0FFF0000
|
||||
EMC_QPOP_0 = 0x0000003B
|
||||
EMC_QUSE_WIDTH_0 = 0x0000000D
|
||||
EMC_PUTERM_WIDTH_0 = 0x80000000
|
||||
EMC_BGBIAS_CTL0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG7_0 = 0x00880000
|
||||
EMC_XM2COMPPADCTRL2_0 = 0x16001000
|
||||
EMC_COMP_PAD_SW_CTRL_0 = 0x738000F0
|
||||
EMC_REFCTRL2_0 = 0x00000000
|
||||
EMC_FBIO_CFG7_0 = 0x00003BFF
|
||||
EMC_DATA_BRLSHFT_0_0 = 0x00000492
|
||||
EMC_DATA_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_RFCPB_0 = 0x000001B7
|
||||
EMC_DQS_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_DQS_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_CMD_BRLSHFT_2_0 = 0x00000024
|
||||
EMC_CMD_BRLSHFT_3_0 = 0x00000024
|
||||
EMC_QUSE_BRLSHFT_0_0 = 0x00000000
|
||||
EMC_AUTO_CAL_CONFIG4_0 = 0x00880000
|
||||
EMC_AUTO_CAL_CONFIG5_0 = 0x00001220
|
||||
EMC_QUSE_BRLSHFT_1_0 = 0x00000000
|
||||
EMC_QUSE_BRLSHFT_2_0 = 0x00000000
|
||||
EMC_CCDMW_0 = 0x00000020
|
||||
EMC_QUSE_BRLSHFT_3_0 = 0x00000000
|
||||
EMC_FBIO_CFG8_0 = 0x0CF30000
|
||||
EMC_AUTO_CAL_CONFIG6_0 = 0x00880000
|
||||
EMC_PROTOBIST_CONFIG_ADR_1_0 = 0x30000000
|
||||
EMC_PROTOBIST_CONFIG_ADR_2_0 = 0x08000101
|
||||
EMC_PROTOBIST_MISC_0 = 0x00000000
|
||||
EMC_PROTOBIST_WDATA_LOWER_0 = 0x2A01A010
|
||||
EMC_PROTOBIST_WDATA_UPPER_0 = 0xC8200002
|
||||
EMC_PROTOBIST_RDATA_0 = 0x00000000
|
||||
EMC_DLL_CFG_0_0 = 0x1F136120
|
||||
EMC_DLL_CFG_1_0 = 0x00012014
|
||||
EMC_CONFIG_SAMPLE_DELAY_0 = 0x00000020
|
||||
EMC_CFG_UPDATE_0 = 0x70000301
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK0_5_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_0_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_1_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_2_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_3_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_4_0 = 0x00000000
|
||||
EMC_PMACRO_QUSE_DDLL_RANK1_5_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 = 0x0010001A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 = 0x001C000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 = 0x0022002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 = 0x0020002E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 = 0x0026002C
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 = 0x00240035
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 = 0x0010001A
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 = 0x001C000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 = 0x00080000
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 = 0x0000000D
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 = 0x0000000B
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 = 0x00000007
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 = 0x00000016
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 = 0x0004000E
|
||||
EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 = 0x00100000
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 = 0x00230029
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 = 0x0028002A
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 = 0x00220026
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 = 0x00200028
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 = 0x00200020
|
||||
EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 = 0x00200020
|
||||
EMC_PMACRO_AUTOCAL_CFG_0_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_1_0 = 0x04040404
|
||||
EMC_PMACRO_AUTOCAL_CFG_2_0 = 0x04040404
|
||||
EMC_PMACRO_TX_PWRD_0_0 = 0x10000000
|
||||
EMC_PMACRO_TX_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_PWRD_4_0 = 0x00400080
|
||||
EMC_PMACRO_TX_PWRD_5_0 = 0x00801004
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_0_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_1_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_2_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_3_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_4_0 = 0x00000000
|
||||
EMC_PMACRO_TX_SEL_CLK_SRC_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_BYPASS_0 = 0xEF000000
|
||||
EMC_PMACRO_DDLL_PWRD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PWRD_2_0 = 0x1C1C1C1C
|
||||
EMC_PMACRO_CMD_CTRL_0_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_1_0 = 0x00000000
|
||||
EMC_PMACRO_CMD_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x24242424
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x231E1C23
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000023
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x23242321
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x20241A1D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x0000001C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x28282A29
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x28282919
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000028
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x121C1F1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x1A1A150D
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000018
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x1D252022
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x1D221F1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000021
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x1F1E1E20
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x1E1D1E1C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x0000001C
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x32323232
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x3232292E
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x0000002B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x22231B1F
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x21202217
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x0000001B
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0_0 = 0x060A0A0A
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1_0 = 0x07010008
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0_0 = 0x05050305
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1_0 = 0x03050004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0_0 = 0x08080C11
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1_0 = 0x06070700
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2_0 = 0x00000006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0_0 = 0x00080E08
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1_0 = 0x08070200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2_0 = 0x00000002
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0_0 = 0x00070308
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1_0 = 0x03060409
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2_0 = 0x00000004
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0_0 = 0x0600030B
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1_0 = 0x01030105
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2_0 = 0x00000003
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0_0 = 0x03020302
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1_0 = 0x04020006
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0_0 = 0x04050103
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1_0 = 0x04040200
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2_0 = 0x00000001
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1_0 = 0x00000000
|
||||
EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQ_0_0 = 0x24202125
|
||||
EMC_PMACRO_IB_VREF_DQ_1_0 = 0x27241D22
|
||||
EMC_PMACRO_IB_VREF_DQ_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_VREF_DQS_0_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_1_0 = 0x29292929
|
||||
EMC_PMACRO_IB_VREF_DQS_2_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_LONG_CMD_0_0 = 0x001A001A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_1_0 = 0x00080008
|
||||
EMC_PMACRO_DDLL_LONG_CMD_2_0 = 0x000D000D
|
||||
EMC_PMACRO_DDLL_LONG_CMD_3_0 = 0x000E000E
|
||||
EMC_PMACRO_DDLL_LONG_CMD_4_0 = 0x0000001A
|
||||
EMC_PMACRO_DDLL_LONG_CMD_5_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_0_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_1_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_SHORT_CMD_2_0 = 0x00000000
|
||||
EMC_PMACRO_CFG_PM_GLOBAL_0_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_0_0 = 0x00090000
|
||||
EMC_PMACRO_VTTGEN_CTRL_1_0 = 0x00102000
|
||||
EMC_PMACRO_BG_BIAS_CTRL_0_0 = 0x00001000
|
||||
EMC_PMACRO_PAD_CFG_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_ZCTRL_0 = 0x00505050
|
||||
EMC_PMACRO_RX_TERM_0 = 0x080B080B
|
||||
EMC_PMACRO_CMD_TX_DRV_0 = 0x00001220
|
||||
EMC_PMACRO_CMD_PAD_RX_CTRL_0 = 0x06000000
|
||||
EMC_PMACRO_DATA_PAD_RX_CTRL_0 = 0x06060000
|
||||
EMC_PMACRO_CMD_RX_TERM_MODE_0 = 0x00002000
|
||||
EMC_PMACRO_DATA_RX_TERM_MODE_0 = 0x00000211
|
||||
EMC_PMACRO_CMD_PAD_TX_CTRL_0 = 0x40021084
|
||||
EMC_PMACRO_DATA_PAD_TX_CTRL_0 = 0x40021485
|
||||
EMC_PMACRO_COMMON_PAD_TX_CTRL_0 = 0x00000000
|
||||
EMC_PMACRO_DQ_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_CA_TX_DRV_0 = 0x1D191D19
|
||||
EMC_PMACRO_AUTOCAL_CFG_COMMON_0 = 0x0000081A
|
||||
EMC_PMACRO_DDLLCAL_CAL_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_DDLL_PERIODIC_OFFSET_0 = 0x00000000
|
||||
EMC_PMACRO_VTTGEN_CTRL_2_0 = 0x00000000
|
||||
EMC_PMACRO_IB_RXRT_0 = 0x00000078
|
||||
EMC_PMACRO_TRAINING_CTRL_0_0 = 0x00000008
|
||||
EMC_PMACRO_TRAINING_CTRL_1_0 = 0x00000008
|
||||
EMC_TRAINING_CMD_0 = 0x000000CC
|
||||
EMC_TRAINING_CTRL_0 = 0x00009080
|
||||
EMC_TRAINING_STATUS_0 = 0x00000000
|
||||
EMC_TRAINING_QUSE_CORS_CTRL_0 = 0x01124000
|
||||
EMC_TRAINING_QUSE_FINE_CTRL_0 = 0x01125B6A
|
||||
EMC_TRAINING_QUSE_CTRL_MISC_0 = 0x0F081000
|
||||
EMC_TRAINING_WRITE_FINE_CTRL_0 = 0x1114FC00
|
||||
EMC_TRAINING_WRITE_CTRL_MISC_0 = 0x07004300
|
||||
EMC_TRAINING_WRITE_VREF_CTRL_0 = 0x00102306
|
||||
EMC_TRAINING_READ_FINE_CTRL_0 = 0x1110FC00
|
||||
EMC_TRAINING_READ_CTRL_MISC_0 = 0x0F085300
|
||||
EMC_TRAINING_READ_VREF_CTRL_0 = 0x00104210
|
||||
EMC_TRAINING_CA_FINE_CTRL_0 = 0x0513801F
|
||||
EMC_TRAINING_CA_CTRL_MISC_0 = 0x1F101100
|
||||
EMC_TRAINING_CA_CTRL_MISC1_0 = 0x00000014
|
||||
EMC_TRAINING_CA_VREF_CTRL_0 = 0x00107240
|
||||
EMC_TRAINING_CA_TADR_CTRL_0 = 0x00028000
|
||||
EMC_TRAINING_SETTLE_0 = 0x07070404
|
||||
EMC_TRAINING_DEBUG_CTRL_0 = 0x00000000
|
||||
EMC_TRAINING_MPC_0 = 0x00000000
|
||||
EMC_TRAINING_PATRAM_CTRL_0 = 0x800000FF
|
||||
EMC_TRAINING_PATRAM_DQ_0 = 0x0F0F0F0F
|
||||
EMC_TRAINING_PATRAM_DMI_0 = 0x00000000
|
||||
EMC_TRAINING_VREF_SETTLE_0 = 0x00040320
|
||||
EMC_TRAINING_OPT_CA_VREF_0 = 0x00000000
|
||||
EMC_TRAINING_OPT_DQ_OB_VREF_0 = 0x00000E0B
|
||||
EMC_TRAINING_QUSE_VREF_CTRL_0 = 0x00105800
|
||||
288
timings/Mariko/AA/2133/mc/2133_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2133_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E6A271
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72703021
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x02930810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004A
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00600004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00600038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00600005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00600014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00600060
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00600016
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00600095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00600041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00600080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0060003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00600013
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000060
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00600090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00600004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000060
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080011
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00600013
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00600005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00600018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2166_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2166_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000F7B9B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x58681E41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80030080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000020
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00110B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713121
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00001020
|
||||
MC_ERR_SEC_ADR_0 = 0x02000000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004B
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005E0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005E0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005E0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005E0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005E005E
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005E0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005E0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005E0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005E0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005E003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005E0013
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005E
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005E0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005E0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005E0013
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005E0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005E0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2200_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2200_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD4B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77D4C531
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000008
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713222
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00040041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02110000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005D005D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005D0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005D0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005D0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2233_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2233_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01211200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7981FF41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000010
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000021
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120B10
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713322
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x001E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x003E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02123000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004E
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005B0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005B0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005B0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005B0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005B005B
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005B0015
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005B0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005B0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005B0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005B003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005B0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005B
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005B0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005B0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005B
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005B0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005B0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005B0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2266_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2266_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01011200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FF37F
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x4AF0EDF1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000010
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120B11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72713323
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00040041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02013000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000004F
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x005A0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x005A0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x005A0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x005A0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x005A005A
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x005A0014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x005A0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x005A0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x005A0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x005A003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x005A0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000005A
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x005A0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x005A0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000005A
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080010
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x005A0012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x005A0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x005A0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2300_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2300_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCFB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7ABA83D1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723423
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02022000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000050
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00590004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00590038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00590005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00590014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00590059
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00590014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00590095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00590041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00590080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0059003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00590012
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000059
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00590090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00590004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000059
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00590012
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00590005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00590018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2333_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2333_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD4B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7ABA6511
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000022
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723523
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80030080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02132810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000051
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00570004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00570038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00570005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00570014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00570057
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00570014
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00570095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00570041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00570080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0057003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00570011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000057
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00570090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00570004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000057
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00570011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00570005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00570018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2366_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2366_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x78694471
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000011
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000023
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00120C11
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723624
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80080080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000052
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00560004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00560038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00560005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00560014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00560056
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00560013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00560095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00560041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00560080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0056003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00560011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000056
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00560090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00560004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000056
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00560011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00560005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00560018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2400_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2400_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD7B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77CE85E1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80060080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72723625
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000040
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130010
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000053
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00550004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00550038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00550005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00550014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00550055
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00550013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00550095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00550041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00550080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0055003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00550011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000055
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00550090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00550004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000055
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00550011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00550005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00550018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2433_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2433_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E80541
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000009
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000024
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733725
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000610F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02132000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000055
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00540004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00540038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00540005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00540014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00540054
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00540013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00540095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00540041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00540080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0054003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00540011
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000054
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00540090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00540004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000054
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000F
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00540011
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00540005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00540018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2466_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2466_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD1B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E49471
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733826
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x001E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x003E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000056
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00530004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00530038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00530005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00530014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00530053
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00530013
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00530095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00530041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00530080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0053003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00530010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00530090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00530004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000053
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00530010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00530005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00530018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2500_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2500_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E6B271
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000012
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80030080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000025
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000C
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130C12
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733926
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02932800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000057
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00510004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00510038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00510005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00510014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00510051
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00510012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00510095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00510041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00510080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0051003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00510010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000051
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00510090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00510004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000051
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00510010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00510005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00510018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2533_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2533_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFDAB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E826A1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000012
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72733927
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00023070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000058
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00500004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00500038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00500005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00500014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00500050
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00500012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00500095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00500041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00500080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0050003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00500010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000050
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00500090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00500004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000050
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00500010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00500005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00500018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2566_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2566_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DD7551
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000026
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x00000019
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00130D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743A27
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02930000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000059
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_RING1_PTSA_RATE_0 = 0x0000035C
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003F
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_JPG_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_USBX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x0000003F
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x0000003F
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003F
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003F
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x0000003F
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003F
|
||||
MC_HOST_PTSA_MAX_0 = 0x0000003F
|
||||
MC_SAX_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003F
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003F
|
||||
MC_MSE_PTSA_MAX_0 = 0x0000003F
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004F0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004F0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000018
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004F0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004F0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004F004F
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004F0012
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004F0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004F0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004F0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004F003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x0080009B
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004F0010
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004F
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004F0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004F0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004F
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00800065
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000E
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004F0010
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004F0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004F0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00800024
|
||||
288
timings/Mariko/AA/2133/mc/2600_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2600_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD1B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7B210471
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0000000C
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x00000006
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x00000007
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000018
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000A
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x05060000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x000D080C
|
||||
MC_EMEM_ARB_MISC0_0 = 0x726C2419
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C181000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063090
|
||||
MC_ERR_SEC_ADR_0 = 0x08130850
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000037
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000230
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000445
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x00000010
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00800038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00800095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00800041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0080003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000080
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00800090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000080
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x00080016
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x00800019
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00800018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2633_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2633_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x68372880
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD8B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x784C7621
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000013
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02030000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004D0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004D0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004D0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004D0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004D004D
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004D0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004D0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004D0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004D0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004D003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004D000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004D
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004D0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004D0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004D
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004D000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004D0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004D0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2666_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2666_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E5A541
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000014
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x800D0080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000A
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000027
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001A
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000013
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140D13
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72743C28
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000041
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80030080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005D
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000D
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004C0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004C0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004C0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004C0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004C004C
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004C0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004C0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004C0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004C0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004C003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004C000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004C
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004C0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004C0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004C
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004C000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004C0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004C0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2700_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2700_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FF9DB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x0B948741
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000014
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000028
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001B
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140D14
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72753D29
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80020080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005E
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004B0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004B0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004B0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004B0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004B004B
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004B0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004B0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00990041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004B0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004B003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004B000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004B
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00800090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004B0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004B
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0099001E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004B0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004B0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2733_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2733_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DEB341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000014
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000029
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001B
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E14
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72753E2A
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C111000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000230B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000005F
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004A0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004A0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004A0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004A0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004A004A
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004A0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004A0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004A0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004A0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004A003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004A000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004A
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004A0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004A0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004A
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004A000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004A0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004A0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2766_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2766_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x11210200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E71141
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000014
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x00000029
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001C
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E14
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72753F2A
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630B0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000060
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000446
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x004A0004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x004A0038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x004A0005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x004A0014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x004A004A
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x004A0011
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x004A0095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x004A0041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x004A0080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x004A003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x004A000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x0000004A
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x004A0090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x004A0004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x0000004A
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x004A000F
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x004A0005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x004A0018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2800_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2800_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E18341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000015
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002A
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001C
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000014
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E15
|
||||
MC_EMEM_ARB_MISC0_0 = 0x72753F2B
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02112810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000061
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00490004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00490038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00490005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00490014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00490049
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00490010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00490095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00490041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00490080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0049003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0049000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000049
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00490090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00490004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000049
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000D
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0049000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00490005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00490018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2833_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2833_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E5D341
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000015
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002A
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001C
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00140E15
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7276402B
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x800E0080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x0A003000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000063
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00480004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00480038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00480005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00480014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00480048
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00480010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00480095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00480041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00480080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0048003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0048000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000048
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00480090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00480004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000048
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0048000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00480005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00480018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2866_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2866_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD0B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E42421
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000015
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000B
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002B
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001D
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150E15
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7276412C
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000400C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80040080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000064
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00470004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00470038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00470005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00470014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00470047
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00470010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00470095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00470041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00470080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0047003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0047000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000047
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00470090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00470004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000047
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0047000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00470005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00470018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2900_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2900_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFD0B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E8E401
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000015
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002B
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001D
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000D
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x06070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150E15
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7276422C
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80030080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00001060
|
||||
MC_ERR_SEC_ADR_0 = 0x02023000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000065
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00460004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00460038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00460005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00460014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00460046
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00460010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00460095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00460041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00460080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0046003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0046000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000046
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00460090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00460004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000046
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0046000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00460005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00460018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2933_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2933_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFBDB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x31050F41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000016
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002C
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001D
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000015
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150E16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7276422D
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x42130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000066
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000363
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00450004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00450038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00450005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00450014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00450045
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00450010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00990095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00450041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00450080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0045003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0045000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000045
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00450090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00450004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000045
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0045000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00450005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00450018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/2966_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/2966_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC9B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77EA0261
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000016
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002C
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7257432D
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000230F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000067
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00450004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00450038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00450005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00450014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00450045
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x00450010
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00450095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00450041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00450080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0045003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0045000E
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000045
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00450090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00450004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000045
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0045000E
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00450005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00450018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3000_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3000_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x19211200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFE4B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7A43E911
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000016
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002C
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7277442D
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0F
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000400C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02910810
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x00000068
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00440004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00440038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00440005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00440014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00440044
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0044000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00440095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00440041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00440080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0044003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0044000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000044
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00440090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00440004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000044
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0044000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00440005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00440018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3033_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3033_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFC8B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77D7A221
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x0C000016
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00150F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7277452E
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C1
|
||||
MC_ERR_VPR_ADR_0 = 0x0C191000
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000010E0
|
||||
MC_ERR_SEC_ADR_0 = 0x02003000
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006A
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00430004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00430038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00430005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00430014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00430043
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0043000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00430095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00430041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00430080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0043003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0043000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000043
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00430090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00430004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000043
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0043000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00430005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00430018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3066_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3066_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCEB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77E1F3B1
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x00000017
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80000080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000016
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000003
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00160F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7277452E
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80010080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x000630F0
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006B
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00420004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00420038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00420005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00420014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00420042
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0042000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00420095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00420041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00420080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0042003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0042000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000042
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00420090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00420004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000042
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000C
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0042000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00420005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00420018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3100_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3100_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x7FFFFFE0
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFB5B
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x7A3C0D41
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x04000017
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80020080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000C
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00160F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7258462E
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x000000C0
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130100
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006C
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x00000C63
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00420038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00800005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00800014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00800080
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0080001D
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00420095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00800041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00420080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0080003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0042000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000042
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00420090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00420004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000042
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000B
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0042000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00420005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00420018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
288
timings/Mariko/AA/2133/mc/3133_mc.txt
Normal file
288
timings/Mariko/AA/2133/mc/3133_mc.txt
Normal file
@@ -0,0 +1,288 @@
|
||||
Dumping MC registers from BASE=0x70019000
|
||||
-----------------------------------
|
||||
MC_ERR_ADR_0 = 0x01011200
|
||||
MC_SMMU_CONFIG_0 = 0xFFFFFFFF
|
||||
MC_SMMU_TLB_CONFIG_0 = 0x30000030
|
||||
MC_SMMU_PTC_CONFIG_0 = 0x2800003F
|
||||
MC_SMMU_PTB_ASID_0 = 0x0000000C
|
||||
MC_SMMU_PTB_DATA_0 = 0xE00FF80C
|
||||
MC_SMMU_TLB_FLUSH_0 = 0x000FFCCB
|
||||
MC_SMMU_PTC_FLUSH_0 = 0x77DD8331
|
||||
MC_EMEM_CFG_0 = 0x00001000
|
||||
MC_EMEM_ROW_WIDTH = 0x00000000
|
||||
MC_EMEM_ADR_CFG_DEV0_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_DEV1_0 = 0x00080302
|
||||
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 = 0xFFFF2400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_0_0 = 0x6E574400
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_1_0 = 0x39722800
|
||||
MC_EMEM_ADR_CFG_BANK_MASK_2_0 = 0x4B9C1000
|
||||
MC_SECURITY_CFG0_0 = 0xFFFFFFFF
|
||||
MC_SECURITY_CFG1_0 = 0xFFFFFFFF
|
||||
MC_EMEM_ARB_CFG_0 = 0x08000017
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_0 = 0x80010080
|
||||
MC_EMEM_ARB_TIMING_RCD_0 = 0x0000000D
|
||||
MC_EMEM_ARB_TIMING_RP_0 = 0x0000000E
|
||||
MC_EMEM_ARB_TIMING_RC_0 = 0x0000002D
|
||||
MC_EMEM_ARB_TIMING_RAS_0 = 0x0000001E
|
||||
MC_EMEM_ARB_TIMING_FAW_0 = 0x00000017
|
||||
MC_EMEM_ARB_TIMING_RRD_0 = 0x00000005
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE_0 = 0x00000004
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE_0 = 0x00000011
|
||||
MC_EMEM_ARB_TIMING_R2R_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_W2W_0 = 0x00000001
|
||||
MC_EMEM_ARB_TIMING_R2W_0 = 0x0000000F
|
||||
MC_EMEM_ARB_TIMING_W2R_0 = 0x0000000E
|
||||
MC_EMEM_ARB_DA_TURNS_0 = 0x07070000
|
||||
MC_EMEM_ARB_DA_COVERS_0 = 0x00160F16
|
||||
MC_EMEM_ARB_MISC0_0 = 0x7258472E
|
||||
C_EMEM_ARB_MISC1_0 = 0x70000F0E
|
||||
MC_EMEM_ARB_MISC2_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING1_THROTTLE_0 = 0x001F0000
|
||||
MC_EMEM_ARB_RING3_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_OVERRIDE_0 = 0x10000000
|
||||
MC_EMEM_ARB_RSV_0 = 0xFF00FF00
|
||||
MC_CLKEN_OVERRIDE_0 = 0x00008000
|
||||
MC_TIMING_CONTROL_0 = 0x00000001
|
||||
MC_STAT_CONTROL_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_0 = 0x000E0900
|
||||
MC_CLIENT_HOTRESET_STATUS_0 = 0x002E8900
|
||||
MC_EMEM_ARB_ISOCHRONOUS_0_0 = 0x0023007E
|
||||
MC_EMEM_ARB_ISOCHRONOUS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_3_0 = 0x00080000
|
||||
MC_EMEM_ARB_HYSTERESIS_0_0 = 0x0003007E
|
||||
MC_EMEM_ARB_HYSTERESIS_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_2_0 = 0x04000000
|
||||
MC_EMEM_ARB_HYSTERESIS_3_0 = 0x00080000
|
||||
MC_SMMU_AFI_ASID_0 = 0x8000000B
|
||||
MC_SMMU_AVPC_ASID_0 = 0x80000002
|
||||
MC_SMMU_DC_ASID_0 = 0x80000005
|
||||
MC_SMMU_DCB_ASID_0 = 0x80000006
|
||||
MC_SMMU_HC_ASID_0 = 0x80000000
|
||||
MC_SMMU_HDA_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVENC_ASID_0 = 0x80000000
|
||||
MC_SMMU_NV_ASID_0 = 0x00000000
|
||||
MC_SMMU_NV2_ASID_0 = 0x00000000
|
||||
MC_SMMU_PPCS_ASID_0 = 0x80000003
|
||||
MC_SMMU_SATA_ASID_0 = 0x00000000
|
||||
MC_SMMU_VI_ASID_0 = 0x00000000
|
||||
MC_SMMU_VIC_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_HOST_ASID_0 = 0x80000000
|
||||
MC_SMMU_XUSB_DEV_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_PPCS1_ASID_0 = 0x80000003
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 = 0xE4FACB43
|
||||
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 = 0x0600FED3
|
||||
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 = 0x00008000
|
||||
MC_DISPLAY_SNAP_RING_0 = 0x00000000
|
||||
MC_ERR_VPR_STATUS_0 = 0x00000040
|
||||
MC_ERR_VPR_ADR_0 = 0x0C1D1020
|
||||
MC_IRAM_REG_CTRL_0 = 0x00000001
|
||||
MC_EMEM_CFG_ACCESS_CTRL_0 = 0x00000001
|
||||
MC_TZ_SECURITY_CTRL_0 = 0x00000000
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 = 0x80000080
|
||||
MC_SEC_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_SEC_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_ERR_SEC_STATUS_0 = 0x00063070
|
||||
MC_ERR_SEC_ADR_0 = 0x02130800
|
||||
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 = 0x0000001F
|
||||
MC_STUTTER_CONTROL_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 = 0x00000000
|
||||
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 = 0x80008041
|
||||
MC_EMEM_ARB_TIMING_RFCPB_0 = 0x0000006D
|
||||
MC_EMEM_ARB_TIMING_CCDMW_0 = 0x00000008
|
||||
MC_EMEM_ARB_REFPB_HP_CTRL_0 = 0x000A1020
|
||||
MC_EMEM_ARB_REFPB_BANK_CTRL_0 = 0x80001028
|
||||
MC_EMEM_ARB_OVERRIDE_1_0 = 0x00000000
|
||||
MC_CLIENT_HOTRESET_CTRL_1_0 = 0x00000122
|
||||
MC_CLIENT_HOTRESET_STATUS_1_0 = 0x00000122
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 = 0x2A800000
|
||||
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 = 0x00000002
|
||||
MC_MTS_CARVEOUT_BOM_0 = 0xFFF00000
|
||||
MC_MTS_CARVEOUT_SIZE_MB_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_MTS_CARVEOUT_REG_CTRL_0 = 0x00000000
|
||||
MC_SMMU_PTC_FLUSH_1_0 = 0x00000001
|
||||
MC_SECURITY_CFG3_0 = 0xFFFFFFFF
|
||||
MC_EMEM_BANK_SWIZZLE_CFG0_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG1_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG2_0 = 0x00000000
|
||||
MC_EMEM_BANK_SWIZZLE_CFG3_0 = 0x00000000
|
||||
MC_SEC_CARVEOUT_ADR_HI_0 = 0x00000000
|
||||
MC_SMMU_DC1_ASID_0 = 0x80000005
|
||||
MC_SMMU_SDMMC1A_ASID_0 = 0x8000000C
|
||||
MC_SMMU_SDMMC2A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC3A_ASID_0 = 0x00000000
|
||||
MC_SMMU_SDMMC4A_ASID_0 = 0x00000000
|
||||
MC_SMMU_ISP2B_ASID_0 = 0x80000003
|
||||
MC_SMMU_GPU_ASID_0 = 0x00000000
|
||||
MC_SMMU_GPUB_ASID_0 = 0x8A090807
|
||||
MC_SMMU_PPCS2_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVDEC_ASID_0 = 0x80000000
|
||||
MC_SMMU_APE_ASID_0 = 0x80000004
|
||||
MC_SMMU_SE_ASID_0 = 0x80000003
|
||||
MC_SMMU_NVJPG_ASID_0 = 0x80000000
|
||||
MC_SMMU_HC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_SE1_ASID_0 = 0x80000003
|
||||
MC_SMMU_AXIAP_ASID_0 = 0x00000000
|
||||
MC_SMMU_ETR_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB_ASID_0 = 0x80000000
|
||||
MC_SMMU_TSEC1_ASID_0 = 0x00000000
|
||||
MC_SMMU_TSECB1_ASID_0 = 0x00000000
|
||||
MC_SMMU_NVDEC1_ASID_0 = 0x00000000
|
||||
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 = 0x00000000
|
||||
MC_EMEM_ARB_HYSTERESIS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_ISOCHRONOUS_4_0 = 0x00000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_0_0 = 0x10000000
|
||||
MC_EMEM_ARB_DHYSTERESIS_1_0 = 0x00000800
|
||||
MC_EMEM_ARB_DHYSTERESIS_2_0 = 0x030340D0
|
||||
MC_EMEM_ARB_DHYSTERESIS_3_0 = 0xC3043000
|
||||
MC_EMEM_ARB_DHYSTERESIS_4_0 = 0x00000300
|
||||
MC_EMEM_ARB_DHYST_CTRL_0 = 0x00000002
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 = 0x0000001A
|
||||
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 = 0x0000001A
|
||||
MC_DA_CONFIG0_0 = 0x00000001
|
||||
MC_AHB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AUD_PTSA_MIN_0 = 0x0000003B
|
||||
MC_MLL_MPCORER_PTSA_RATE_0 = 0x00000115
|
||||
MC_RING2_PTSA_RATE_0 = 0x0000000C
|
||||
MC_USBD_PTSA_RATE_0 = 0x00000000
|
||||
MC_USBX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MAX_0 = 0x00000000
|
||||
MC_JPG_PTSA_RATE_0 = 0x00000000
|
||||
MC_DIS_PTSA_MIN_0 = 0x0000003B
|
||||
MC_AVP_PTSA_MAX_0 = 0x00000000
|
||||
MC_AVP_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MIN_0 = 0x0000003B
|
||||
MC_DIS_PTSA_MAX_0 = 0x0000001F
|
||||
MC_SD_PTSA_MAX_0 = 0x00000000
|
||||
MC_MSE_PTSA_RATE_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_MAX_0 = 0x00000000
|
||||
MC_ISP_PTSA_RATE_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MIN_0 = 0x0000003B
|
||||
MC_RING2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_RATE_0 = 0x00000000
|
||||
MC_HOST_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MLL_MPCORER_PTSA_MAX_0 = 0x00000004
|
||||
MC_SD_PTSA_MIN_0 = 0x0000003E
|
||||
MC_RING1_PTSA_RATE_0 = 0x00000362
|
||||
MC_JPG_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HDAPC_PTSA_MIN_0 = 0x0000003E
|
||||
MC_AVP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_JPG_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DFD_PTSA_MAX_0 = 0x0000003F
|
||||
MC_VICPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_MAX_0 = 0x00000000
|
||||
MC_VICPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SDM_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_RATE_0 = 0x00000000
|
||||
MC_PCX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_MIN_0 = 0x0000003E
|
||||
MC_GK2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_PCX_PTSA_RATE_0 = 0x00000000
|
||||
MC_RING1_PTSA_MAX_0 = 0x0000001F
|
||||
MC_HDAPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_MLL_MPCORER_PTSA_MIN_0 = 0x0000003C
|
||||
MC_GK2_PTSA_MAX_0 = 0x00000000
|
||||
MC_AUD_PTSA_MAX_0 = 0x0000001F
|
||||
MC_GK2_PTSA_RATE_0 = 0x00000000
|
||||
MC_ISP_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_RATE_0 = 0x00000447
|
||||
MC_VE2_PTSA_MAX_0 = 0x00000000
|
||||
MC_DFD_PTSA_MIN_0 = 0x0000003F
|
||||
MC_FTOP_PTSA_RATE_0 = 0x0000001F
|
||||
MC_A9AVPPC_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_USBX_PTSA_MAX_0 = 0x00000000
|
||||
MC_DIS_PTSA_RATE_0 = 0x0000000B
|
||||
MC_USBD_PTSA_MAX_0 = 0x00000000
|
||||
MC_A9AVPPC_PTSA_MAX_0 = 0x00000010
|
||||
MC_USBX_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MAX_0 = 0x00000000
|
||||
MC_HDAPC_PTSA_MAX_0 = 0x00000000
|
||||
MC_SD_PTSA_RATE_0 = 0x00000000
|
||||
MC_DFD_PTSA_RATE_0 = 0x00000000
|
||||
MC_FTOP_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_RATE_0 = 0x00000000
|
||||
MC_SMMU_SMMU_PTSA_MAX_0 = 0x00000001
|
||||
MC_RING2_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SDM_PTSA_MIN_0 = 0x0000003E
|
||||
MC_APB_PTSA_RATE_0 = 0x00000000
|
||||
MC_MSE_PTSA_MIN_0 = 0x0000003E
|
||||
MC_HOST_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE_PTSA_RATE_0 = 0x00000000
|
||||
MC_AHB_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MIN_0 = 0x0000003E
|
||||
MC_SMMU_SMMU_PTSA_MIN_0 = 0x00000001
|
||||
MC_ISP_PTSA_MIN_0 = 0x0000003B
|
||||
MC_HOST_PTSA_MAX_0 = 0x00000000
|
||||
MC_SAX_PTSA_MAX_0 = 0x00000000
|
||||
MC_VE_PTSA_MIN_0 = 0x0000003B
|
||||
MC_GK_PTSA_MIN_0 = 0x0000003E
|
||||
MC_MSE_PTSA_MAX_0 = 0x00000000
|
||||
MC_DISB_PTSA_MAX_0 = 0x0000001F
|
||||
MC_DISB_PTSA_MIN_0 = 0x0000003B
|
||||
MC_SMMU_SMMU_PTSA_RATE_0 = 0x00000000
|
||||
MC_VE2_PTSA_RATE_0 = 0x00000000
|
||||
MC_GK_PTSA_RATE_0 = 0x00000000
|
||||
MC_PTSA_GRANT_DECREMENT_0 = 0x000017FF
|
||||
MC_LATENCY_ALLOWANCE_AVPC_0_0 = 0x00410004
|
||||
MC_LATENCY_ALLOWANCE_AXIAP_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_XUSB_1_0 = 0x00410038
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_0_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 = 0x00410005
|
||||
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 = 0x00410014
|
||||
MC_LATENCY_ALLOWANCE_ISP2_0_0 = 0x0000002C
|
||||
MC_LATENCY_ALLOWANCE_SE_0_0 = 0x0080002E
|
||||
MC_LATENCY_ALLOWANCE_ISP2_1_0 = 0x00410041
|
||||
MC_LATENCY_ALLOWANCE_DC_0_0 = 0x001E00FF
|
||||
MC_LATENCY_ALLOWANCE_VIC_0_0 = 0x0041000F
|
||||
MC_LATENCY_ALLOWANCE_DCB_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_NVDEC_0_0 = 0x00410095
|
||||
MC_LATENCY_ALLOWANCE_DCB_2_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_TSEC_0_0 = 0x00410041
|
||||
MC_LATENCY_ALLOWANCE_DC_2_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_PPCS_1_0 = 0x00410080
|
||||
MC_LATENCY_ALLOWANCE_XUSB_0_0 = 0x0041003D
|
||||
MC_LATENCY_ALLOWANCE_PPCS_0_0 = 0x00340049
|
||||
MC_LATENCY_ALLOWANCE_TSECB_0_0 = 0x00FF009D
|
||||
MC_LATENCY_ALLOWANCE_AFI_0_0 = 0x00FF0073
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_DC_1_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_APE_0_0 = 0x008000FF
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_A9AVP_0_0 = 0x00800004
|
||||
MC_LATENCY_ALLOWANCE_GPU2_0_0 = 0x0041000D
|
||||
MC_LATENCY_ALLOWANCE_DCB_0_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_HC_1_0 = 0x00000041
|
||||
MC_LATENCY_ALLOWANCE_SDMMC_0_0 = 0x00410090
|
||||
MC_LATENCY_ALLOWANCE_NVJPG_0_0 = 0x00800023
|
||||
MC_LATENCY_ALLOWANCE_PTC_0_0 = 0x00000000
|
||||
MC_LATENCY_ALLOWANCE_ETR_0_0 = 0x008000FF
|
||||
MC_LATENCY_ALLOWANCE_MPCORE_0_0 = 0x00410004
|
||||
MC_LATENCY_ALLOWANCE_VI2_0_0 = 0x00000041
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 = 0x001E001E
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 = 0x001E001E
|
||||
MC_LATENCY_ALLOWANCE_SATA_0_0 = 0x00FF00CB
|
||||
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_HC_0_0 = 0x0008000B
|
||||
MC_LATENCY_ALLOWANCE_DC_3_0 = 0x0000001E
|
||||
MC_LATENCY_ALLOWANCE_GPU_0_0 = 0x0041000D
|
||||
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 = 0x00410005
|
||||
MC_LATENCY_ALLOWANCE_ISP2B_1_0 = 0x00FF00FF
|
||||
MC_LATENCY_ALLOWANCE_NVENC_0_0 = 0x00410018
|
||||
MC_LATENCY_ALLOWANCE_HDA_0_0 = 0x00FF0024
|
||||
Reference in New Issue
Block a user