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readme; ignore EmcDvbTable

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This commit is contained in:
KazushiM
2021-11-21 21:31:00 +08:00
parent 92a16bd307
commit 3279aab56c
3 changed files with 15 additions and 25 deletions
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13
Source/Atmosphere/ldr_oc_patch.hpp
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@@ -126,6 +126,9 @@ namespace pcv {
};
/* EMC */
// DvbTable is all about frequency scaling along with CPU core voltage, no need to care about this for now.
// constexpr u32 EmcDvbTableOffsets[] =
// {
// 0xFFFFFFFF,
@@ -175,8 +178,8 @@ namespace pcv {
// 0x1428AC 23 #0x14
// 0x1428B0 12500 #0x18 // voltage step
// 0x1428B4 600000 #0x1C
// 0x1428B8 1125000 #0x20 // min voltage, default voltage for Erista EMC
// 0x1428BC 1125000 #0x24 // max voltage, default voltage for Erista EMC
// 0x1428B8 1125000 #0x20 // min voltage, default Vddq for Erista EMC
// 0x1428BC 1125000 #0x24 // max voltage, default Vddq for Erista EMC
// 0x1428C0 0 #0x28
// 0x1428C4 0 #0x2C
@@ -190,12 +193,10 @@ namespace pcv {
// in hekate/bdk/power/max77812.h:
// #define MAX77812_REG_M3_VOUT 0x25 // DRAM on PHASE211.
// What about DRAM on PHASE31?
// 3 outputs (CPU/GPU/DRAM) from max77812. Does PHASE31 mode exist?
// If so, read/query max77812 pmic via i2c for voltage info in hekate and get DRAM reg on PHASE31.
// max77812 document: https://datasheets.maximintegrated.com/en/ds/MAX77812.pdf
// See if we can read/query max77812 pmic via i2c for voltage info in fusee/hekate
// TODO: investigate why frequencies lower than 1331 MHz cannot be set
constexpr u32 EmcFreqOffsets[][30] = {
{ 0xD7C60, 0xD7C68, 0xD7C70, 0xD7C78, 0xD7C80, 0xD7C88, 0xD7C90, 0xD7C98, 0xD7CA0, 0xD7CA8, 0xE1800, 0xEEFA0, 0xF2478, 0xFE284, 0x10A304, 0x10D7DC, 0x110A40, 0x113CA4, 0x116F08, 0x11A16C, 0x11D3D0, 0x120634, 0x123898, 0x126AFC, 0x129D60, 0x12CFC4, 0x130228, 0x13BFE0, 0x140D00, 0x140D50, },