Revert "hoc-clk: add live vdd2, live boost clock and basic pwm dimming"
This reverts commit 15b7df8ef1.
This commit is contained in:
souldbminersmwc
@@ -1,55 +0,0 @@
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/*
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* Copyright (c) Atmosphère-NX
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*
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||||
* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
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||||
*
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||||
* This program is distributed in the hope it will be useful, but WITHOUT
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||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
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||||
*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours/common.hpp>
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#include <vapours/assert.hpp>
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#include <vapours/literals.hpp>
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#include <vapours/util.hpp>
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#include <vapours/results.hpp>
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#include <vapours/reg.hpp>
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#define AHB_ARBC(x) (0x6000c000 + x)
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#define AHB_ARBITRATION_DISABLE (0x004)
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#define AHB_ARBITRATION_PRIORITY_CTRL (0x008)
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#define AHB_MASTER_SWID (0x018)
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#define AHB_MASTER_SWID_1 (0x038)
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#define AHB_GIZMO_TZRAM (0x054)
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#define AHB_ARBITRATION_XBAR_CTRL (0x0E0)
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#define AHB_AHB_SPARE_REG (0x110)
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#define AHB_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AHB_, NAME)
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#define AHB_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AHB_, NAME, VALUE)
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#define AHB_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (AHB_, NAME, ENUM)
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#define AHB_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(AHB_, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
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#define DEFINE_AHB_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (AHB_, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_AHB_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE)
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#define DEFINE_AHB_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
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#define DEFINE_AHB_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
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#define DEFINE_AHB_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AHB_, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_COP, 1, ENABLE, DISABLE);
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DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_AHBDMA, 5, ENABLE, DISABLE);
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DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB, 6, ENABLE, DISABLE);
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DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_DISABLE_USB2, 18, ENABLE, DISABLE);
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DEFINE_AHB_REG_BIT_ENUM(ARBITRATION_XBAR_CTRL_MEM_INIT_DONE, 16, NOT_DONE, DONE);
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DEFINE_AHB_REG(AHB_SPARE_REG_CSITE_PADMACRO3_TRIM_SEL, 0, 5);
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DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_OBS_OVERRIDE_EN, 5, DISABLE, ENABLE);
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DEFINE_AHB_REG_BIT_ENUM(AHB_SPARE_REG_APB2JTAG_OVERRIDE_EN, 6, DISABLE, ENABLE);
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DEFINE_AHB_REG(AHB_SPARE_REG_AHB_SPARE_REG, 12, 32-12);
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@@ -1,150 +0,0 @@
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/*
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* Copyright (c) Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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||||
* under the terms and conditions of the GNU General Public License,
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||||
* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <vapours/common.hpp>
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#include <vapours/assert.hpp>
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#include <vapours/literals.hpp>
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#include <vapours/util.hpp>
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#include <vapours/results.hpp>
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#include <vapours/reg.hpp>
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#define APB_MISC_PP_CONFIG_CTL (0x024)
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#define APB_MISC_PP_PINMUX_GLOBAL_0 (0x040)
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#define APB_MISC_GP_ASDBGREG (0x810)
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#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL (0xA98)
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#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL (0xA9C)
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#define APB_MISC_GP_SDMMC2_PAD_CFGPADCTRL (0xA9C)
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#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL (0xAB4)
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#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL (0xABC)
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/* Mariko only */
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#define APB_MISC_GP_DSI_PAD_CONTROL (0xAC0)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 (0xc00)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 (0xc04)
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#define APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 (0xc08)
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#define APB_MISC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (APB_MISC, NAME)
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#define APB_MISC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (APB_MISC, NAME, VALUE)
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#define APB_MISC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (APB_MISC, NAME, ENUM)
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#define APB_MISC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(APB_MISC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
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#define DEFINE_APB_MISC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (APB_MISC, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_APB_MISC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (APB_MISC, NAME, __OFFSET__, ZERO, ONE)
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#define DEFINE_APB_MISC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (APB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
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#define DEFINE_APB_MISC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(APB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
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#define DEFINE_APB_MISC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (APB_MISC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
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DEFINE_APB_MISC_REG_BIT_ENUM(PP_CONFIG_CTL_JTAG, 6, DISABLE, ENABLE);
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DEFINE_APB_MISC_REG_BIT_ENUM(PP_CONFIG_CTL_TBE, 7, DISABLE, ENABLE);
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DEFINE_APB_MISC_REG(GP_ASDBGREG_CFG2TMC_RAM_SVOP_PDP, 24, 2);
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DEFINE_APB_MISC_REG (GP_SDMMC1_PAD_CFGPADCTRL_CFG2TMC_SDMMC1_PAD_CAL_DRVDN, 12, 7);
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DEFINE_APB_MISC_REG (GP_SDMMC1_PAD_CFGPADCTRL_CFG2TMC_SDMMC1_PAD_CAL_DRVUP, 20, 7);
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DEFINE_APB_MISC_REG (GP_SDMMC1_PAD_CFGPADCTRL_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWR, 28, 2);
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DEFINE_APB_MISC_REG (GP_SDMMC1_PAD_CFGPADCTRL_CFG2TMC_SDMMC1_CLK_CFG_CAL_DRVDN_SLWF, 30, 2);
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DEFINE_APB_MISC_REG_BIT_ENUM(GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_E_SCH, 0, DISABLE, ENABLE);
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DEFINE_APB_MISC_REG (GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_DRVDN_COMP, 2, 6);
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DEFINE_APB_MISC_REG (GP_EMMC2_PAD_CFGPADCTRL_CFG2TMC_EMMC2_PAD_DRVUP_COMP, 8, 6);
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DEFINE_APB_MISC_REG (GP_EMMC2_PAD_CFGPADCTRL_MISC2PMC_EMMC2_ALL_PARK, 14, 13);
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DEFINE_APB_MISC_REG (GP_SDMMC2_PAD_CFGPADCTRL_CFG2TMC_SDMMC2_PAD_CAL_DRVDN, 12, 7);
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DEFINE_APB_MISC_REG (GP_SDMMC2_PAD_CFGPADCTRL_CFG2TMC_SDMMC2_PAD_CAL_DRVUP, 20, 7);
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DEFINE_APB_MISC_REG_BIT_ENUM(GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_E_SCH, 0, DISABLE, ENABLE);
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DEFINE_APB_MISC_REG (GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVDN_COMP, 2, 6);
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DEFINE_APB_MISC_REG (GP_EMMC4_PAD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DRVUP_COMP, 8, 6);
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DEFINE_APB_MISC_REG (GP_EMMC4_PAD_CFGPADCTRL_MISC2PMC_EMMC4_ALL_PARK, 14, 13);
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DEFINE_APB_MISC_REG(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_CMD_PUPD_PULLU, 1, 1);
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DEFINE_APB_MISC_REG(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_CLK_PUPD_PULLD, 2, 1);
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DEFINE_APB_MISC_REG(GP_EMMC4_PAD_PUPD_CFGPADCTRL_CFG2TMC_EMMC4_PAD_DQS_PUPD_PULLD, 22, 1);
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#define DEFINE_SLAVE_SECURITY_REG(RINDEX, INDEX, NAME) DEFINE_APB_MISC_REG_BIT_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, INDEX, DISABLE, ENABLE)
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DEFINE_SLAVE_SECURITY_REG(0, 29, STM);
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DEFINE_SLAVE_SECURITY_REG(0, 24, CEC);
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DEFINE_SLAVE_SECURITY_REG(0, 23, ATOMICS);
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DEFINE_SLAVE_SECURITY_REG(0, 22, LA);
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DEFINE_SLAVE_SECURITY_REG(0, 21, HDA);
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DEFINE_SLAVE_SECURITY_REG(0, 20, SATA);
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DEFINE_SLAVE_SECURITY_REG(0, 16, KFUSE);
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DEFINE_SLAVE_SECURITY_REG(0, 15, FUSE);
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DEFINE_SLAVE_SECURITY_REG(0, 14, SE);
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DEFINE_SLAVE_SECURITY_REG(0, 13, PMC);
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DEFINE_SLAVE_SECURITY_REG(0, 11, RTC);
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DEFINE_SLAVE_SECURITY_REG(0, 10, CSITE);
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DEFINE_SLAVE_SECURITY_REG(0, 9, QSPI);
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DEFINE_SLAVE_SECURITY_REG(0, 8, PWM);
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DEFINE_SLAVE_SECURITY_REG(0, 6, DTV);
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DEFINE_SLAVE_SECURITY_REG(0, 4, APE);
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DEFINE_SLAVE_SECURITY_REG(0, 3, PINMUX_AUX);
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DEFINE_SLAVE_SECURITY_REG(0, 2, SATA_AUX);
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DEFINE_SLAVE_SECURITY_REG(0, 1, MISC_REGS);
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DEFINE_SLAVE_SECURITY_REG(1, 31, I2C6);
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DEFINE_SLAVE_SECURITY_REG(1, 30, DVC);
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DEFINE_SLAVE_SECURITY_REG(1, 29, I2C4);
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DEFINE_SLAVE_SECURITY_REG(1, 28, I2C3);
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DEFINE_SLAVE_SECURITY_REG(1, 27, I2C2);
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DEFINE_SLAVE_SECURITY_REG(1, 26, I2C1);
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DEFINE_SLAVE_SECURITY_REG(1, 25, SPI6);
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DEFINE_SLAVE_SECURITY_REG(1, 24, SPI5);
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DEFINE_SLAVE_SECURITY_REG(1, 23, SPI4);
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DEFINE_SLAVE_SECURITY_REG(1, 22, SPI3);
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DEFINE_SLAVE_SECURITY_REG(1, 21, SPI2);
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DEFINE_SLAVE_SECURITY_REG(1, 20, SPI1);
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DEFINE_SLAVE_SECURITY_REG(1, 15, UART_D);
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DEFINE_SLAVE_SECURITY_REG(1, 14, UART_C);
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DEFINE_SLAVE_SECURITY_REG(1, 13, UART_B);
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DEFINE_SLAVE_SECURITY_REG(1, 12, UART_A);
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DEFINE_SLAVE_SECURITY_REG(1, 11, EMCB);
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DEFINE_SLAVE_SECURITY_REG(1, 10, MCB);
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DEFINE_SLAVE_SECURITY_REG(1, 9, EMC1);
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DEFINE_SLAVE_SECURITY_REG(1, 8, MC1);
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DEFINE_SLAVE_SECURITY_REG(1, 5, EMC0);
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DEFINE_SLAVE_SECURITY_REG(1, 4, MC0);
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DEFINE_SLAVE_SECURITY_REG(2, 21, FEK);
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DEFINE_SLAVE_SECURITY_REG(2, 20, PKA1);
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DEFINE_SLAVE_SECURITY_REG(2, 19, SE2);
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DEFINE_SLAVE_SECURITY_REG(2, 16, DVFS);
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DEFINE_SLAVE_SECURITY_REG(2, 15, MIPI_CAL);
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DEFINE_SLAVE_SECURITY_REG(2, 14, XUSB_PADCTL);
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DEFINE_SLAVE_SECURITY_REG(2, 13, XUSB_DEV);
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DEFINE_SLAVE_SECURITY_REG(2, 12, XUSB_HOST);
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DEFINE_SLAVE_SECURITY_REG(2, 11, APB2JTAG);
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DEFINE_SLAVE_SECURITY_REG(2, 10, SOC_THERM);
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DEFINE_SLAVE_SECURITY_REG(2, 9, DP2);
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DEFINE_SLAVE_SECURITY_REG(2, 8, DDS);
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DEFINE_SLAVE_SECURITY_REG(2, 7, MIPIBIF);
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DEFINE_SLAVE_SECURITY_REG(2, 3, SDMMC4);
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DEFINE_SLAVE_SECURITY_REG(2, 2, SDMMC3);
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DEFINE_SLAVE_SECURITY_REG(2, 1, SDMMC2);
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DEFINE_SLAVE_SECURITY_REG(2, 0, SDMMC1);
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#undef DEFINE_SLAVE_SECURITY_REG
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#define SLAVE_SECURITY_REG_BITS_ENUM(RINDEX, NAME, ENUM) APB_MISC_REG_BITS_ENUM(SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG##RINDEX##_##NAME##_SECURITY_EN, ENUM)
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@@ -1,117 +0,0 @@
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/*
|
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* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
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#include <vapours/common.hpp>
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#include <vapours/assert.hpp>
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#include <vapours/literals.hpp>
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#include <vapours/util.hpp>
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#include <vapours/results.hpp>
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#include <vapours/reg.hpp>
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#define AVP_CACHE_ADDR(n) (0x50040000 + n)
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#define AVP_CACHE_CONFIG (0x000)
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#define AVP_CACHE_LOCK (0x004)
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#define AVP_CACHE_SIZE (0x00C)
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#define AVP_CACHE_LFSR (0x010)
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#define AVP_CACHE_TAG_STATUS (0x014)
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#define AVP_CACHE_CLKEN_OVERRIDE (0x018)
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#define AVP_CACHE_MAINT_0 (0x020)
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#define AVP_CACHE_MAINT_1 (0x024)
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#define AVP_CACHE_MAINT_2 (0x028)
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#define AVP_CACHE_INT_MASK (0x040)
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#define AVP_CACHE_INT_CLEAR (0x044)
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#define AVP_CACHE_INT_RAW_EVENT (0x048)
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#define AVP_CACHE_INT_STATUS (0x04C)
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#define AVP_CACHE_RB_CFG (0x080)
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#define AVP_CACHE_WB_CFG (0x084)
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#define AVP_CACHE_MMU_FALLBACK_ENTRY (0x0A0)
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#define AVP_CACHE_MMU_SHADOW_COPY_MASK_0 (0x0A4)
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#define AVP_CACHE_MMU_CFG (0x0AC)
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#define AVP_CACHE_MMU_CMD (0x0B0)
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#define AVP_CACHE_MMU_ABORT_STAT (0x0B4)
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#define AVP_CACHE_MMU_ABORT_ADDR (0x0B8)
|
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#define AVP_CACHE_MMU_ACTIVE_ENTRIES (0x0BC)
|
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|
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#define AVP_CACHE_MMU_SHADOW_ENTRY_0_MIN_ADDR (0x400)
|
||||
#define AVP_CACHE_MMU_SHADOW_ENTRY_0_MAX_ADDR (0x404)
|
||||
#define AVP_CACHE_MMU_SHADOW_ENTRY_0_CFG (0x408)
|
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#define AVP_CACHE_MMU_SHADOW_ENTRY_1_MIN_ADDR (0x410)
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#define AVP_CACHE_MMU_SHADOW_ENTRY_1_MAX_ADDR (0x414)
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#define AVP_CACHE_MMU_SHADOW_ENTRY_1_CFG (0x418)
|
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|
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#define AVP_CACHE_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (AVP_CACHE, NAME)
|
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#define AVP_CACHE_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (AVP_CACHE, NAME, VALUE)
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#define AVP_CACHE_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (AVP_CACHE, NAME, ENUM)
|
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#define AVP_CACHE_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(AVP_CACHE, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
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#define DEFINE_AVP_CACHE_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (AVP_CACHE, NAME, __OFFSET__, __WIDTH__)
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#define DEFINE_AVP_CACHE_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (AVP_CACHE, NAME, __OFFSET__, ZERO, ONE)
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#define DEFINE_AVP_CACHE_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (AVP_CACHE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_AVP_CACHE_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(AVP_CACHE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_AVP_CACHE_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (AVP_CACHE, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(CONFIG_ENABLE_CACHE, 0, FALSE, TRUE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(CONFIG_FORCE_WRITE_THROUGH, 3, FALSE, TRUE);
|
||||
DEFINE_AVP_CACHE_REG_TWO_BIT_ENUM(CONFIG_MMU_TAG_MODE, 8, PARALLEL, TAG_FIRST, MMU_FIRST, RSVD3);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(CONFIG_DISABLE_WB, 10, FALSE, TRUE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(CONFIG_DISABLE_RB, 11, FALSE, TRUE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(CONFIG_TAG_CHECK_ABORT_ON_ERROR, 14, FALSE, TRUE);
|
||||
|
||||
DEFINE_AVP_CACHE_REG(MAINT_2_OPCODE, 0, 8);
|
||||
DEFINE_AVP_CACHE_REG(MAINT_2_WAY_BITMAP, 8, 4);
|
||||
|
||||
enum AVP_CACHE_MAINT_OPCODE : u32 {
|
||||
AVP_CACHE_MAINT_OPCODE_NOP = 0,
|
||||
|
||||
AVP_CACHE_MAINT_OPCODE_CLEAN_PHY = 1,
|
||||
AVP_CACHE_MAINT_OPCODE_INVALID_PHY = 2,
|
||||
AVP_CACHE_MAINT_OPCODE_CLEAN_INVALID_PHY = 3,
|
||||
|
||||
AVP_CACHE_MAINT_OPCODE_CLEAN_LINE = 9,
|
||||
AVP_CACHE_MAINT_OPCODE_INVALID_LINE = 10,
|
||||
AVP_CACHE_MAINT_OPCODE_CLEAN_INVALID_LINE = 11,
|
||||
|
||||
AVP_CACHE_MAINT_OPCODE_CLEAN_WAY = 17,
|
||||
AVP_CACHE_MAINT_OPCODE_INVALID_WAY = 18,
|
||||
AVP_CACHE_MAINT_OPCODE_CLEAN_INVALID_WAY = 19,
|
||||
};
|
||||
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(INT_CLEAR_MAINTENANCE_DONE, 0, FALSE, TRUE);
|
||||
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(INT_RAW_EVENT_MAINTENANCE_DONE, 0, FALSE, TRUE);
|
||||
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(INT_STATUS_MAINTENANCE_DONE, 0, FALSE, TRUE);
|
||||
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_FALLBACK_ENTRY_CACHED, 0, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_FALLBACK_ENTRY_EXE_ENA, 1, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_FALLBACK_ENTRY_RD_ENA, 2, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_FALLBACK_ENTRY_WR_ENA, 3, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_CFG_BLOCK_MAIN_ENTRY_WR, 0, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_CFG_SEQ_ENA, 1, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_CFG_TLB_ENA, 2, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_CFG_SEQ_CHECK_ALL_ENTRIES, 3, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_CFG_ABORT_MODE, 4, STORE_FIRST, STORE_LAST);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(MMU_CFG_CLR_ABORT, 5, NOP, CLEAN);
|
||||
|
||||
DEFINE_AVP_CACHE_REG_TWO_BIT_ENUM(MMU_CMD_CMD, 0, NOP, INIT, COPY_SHADOW, RSVD3);
|
||||
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(SHADOW_ENTRY_CFG_CACHED, 0, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(SHADOW_ENTRY_CFG_EXE_ENA, 1, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(SHADOW_ENTRY_CFG_RD_ENA, 2, DISABLE, ENABLE);
|
||||
DEFINE_AVP_CACHE_REG_BIT_ENUM(SHADOW_ENTRY_CFG_WR_ENA, 3, DISABLE, ENABLE);
|
||||
@@ -1,499 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
/* Clock source enums. */
|
||||
#define CLK_RST_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (CLK_RST_CONTROLLER, NAME)
|
||||
#define CLK_RST_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (CLK_RST_CONTROLLER, NAME, VALUE)
|
||||
#define CLK_RST_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (CLK_RST_CONTROLLER, NAME, ENUM)
|
||||
#define CLK_RST_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(CLK_RST_CONTROLLER, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_CLK_RST_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (CLK_RST_CONTROLLER, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_CLK_RST_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_CLK_RST_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_CLK_RST_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (CLK_RST_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
|
||||
#define CLK_RST_CONTROLLER_RST_SOURCE (0x000)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY (0x020)
|
||||
#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER (0x024)
|
||||
#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY (0x028)
|
||||
#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER (0x02C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE (0x030)
|
||||
#define CLK_RST_CONTROLLER_MISC_CLK_ENB (0x048)
|
||||
#define CLK_RST_CONTROLLER_OSC_CTRL (0x050)
|
||||
#define CLK_RST_CONTROLLER_PLLC_BASE (0x080)
|
||||
#define CLK_RST_CONTROLLER_PLLC_OUT (0x084)
|
||||
#define CLK_RST_CONTROLLER_PLLC_MISC (0x088)
|
||||
#define CLK_RST_CONTROLLER_PLLC_MISC1 (0x08C)
|
||||
#define CLK_RST_CONTROLLER_PLLM_BASE (0x090)
|
||||
#define CLK_RST_CONTROLLER_PLLM_MISC1 (0x098)
|
||||
#define CLK_RST_CONTROLLER_PLLM_MISC2 (0x09C)
|
||||
#define CLK_RST_CONTROLLER_PLLD_BASE (0x0D0)
|
||||
#define CLK_RST_CONTROLLER_PLLD_MISC1 (0x0D8)
|
||||
#define CLK_RST_CONTROLLER_PLLD_MISC (0x0DC)
|
||||
#define CLK_RST_CONTROLLER_PLLX_BASE (0x0E0)
|
||||
#define CLK_RST_CONTROLLER_PLLX_MISC (0x0E4)
|
||||
#define CLK_RST_CONTROLLER_CCLKG_BURST_POLICY (0x368)
|
||||
#define CLK_RST_CONTROLLER_SUPER_CCLKG_DIVIDER (0x36C)
|
||||
#define CLK_RST_CONTROLLER_CCLKLP_BURST_POLICY (0x370)
|
||||
#define CLK_RST_CONTROLLER_SUPER_CCLKLP_DIVIDER (0x374)
|
||||
#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 (0x388)
|
||||
#define CLK_RST_CONTROLLER_PLLX_MISC1 (0x510)
|
||||
#define CLK_RST_CONTROLLER_PLLX_MISC2 (0x514)
|
||||
#define CLK_RST_CONTROLLER_PLLX_MISC3 (0x518)
|
||||
#define CLK_RST_CONTROLLER_SPARE_REG0 (0x55C)
|
||||
#define CLK_RST_CONTROLLER_PLLC4_BASE (0x5A4)
|
||||
#define CLK_RST_CONTROLLER_PLLC_MISC2 (0x5D0)
|
||||
#define CLK_RST_CONTROLLER_PLLMB_BASE (0x5E8)
|
||||
#define CLK_RST_CONTROLLER_PLLMB_MISC1 (0x5EC)
|
||||
|
||||
/* Mariko. */
|
||||
#define CLK_RST_CONTROLLER_PLLM_SS_CFG (0x774)
|
||||
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL1 (0x778)
|
||||
#define CLK_RST_CONTROLLER_PLLM_SS_CTRL2 (0x77C)
|
||||
#define CLK_RST_CONTROLLER_PLLMB_SS_CFG (0x780)
|
||||
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL1 (0x784)
|
||||
#define CLK_RST_CONTROLLER_PLLMB_SS_CTRL2 (0x788)
|
||||
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA (0x0F8)
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB (0x0FC)
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC (0x3A0)
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD (0x3A4)
|
||||
#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE (0x554)
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_IDLE_SOURCE, 0, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_RUN_SOURCE, 4, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_IRQ_SOURCE, 8, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(SCLK_BURST_POLICY_SWAKEUP_FIQ_SOURCE, 12, CLKM, PLLC_OUT1, PLLC4_OUT3PLLP_OUT4, PLLP_OUT0, PLLP_OUT2, PLLC4_OUT1PLLC_OUT0, CLK_SCLKS, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_IRQ, 24, NOP, BURST);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_IRQ, 25, NOP, BURST);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SCLK_BURST_POLICY_CPU_AUTO_SWAKEUP_FROM_FIQ, 26, NOP, BURST);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SCLK_BURST_POLICY_COP_AUTO_SWAKEUP_FROM_FIQ, 27, NOP, BURST);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(SCLK_BURST_POLICY_SYS_STATE, 28, STDBY, IDLE, RUN, RSVD3, IRQ, RSVD5, RSVD6, RSVD7, FIQ, RSVD9, RSVD10, RSVD11, RSVD12, RSVD13, RSVD14, RSVD15);
|
||||
|
||||
DEFINE_CLK_RST_REG(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIVIDEND, 8, 8);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIS_FROM_CPU_IRQ, 24, NOP, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIS_FROM_COP_IRQ, 25, NOP, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIS_FROM_CPU_FIQ, 26, NOP, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_SCLK_DIVIDER_SUPER_SDIV_DIS_FROM_COP_FIQ, 27, NOP, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_SCLK_DIVIDER_SUPER_SDIV_ENB, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SYSTEM_RATE_APB_RATE, 0, 2);
|
||||
DEFINE_CLK_RST_REG(CLK_SYSTEM_RATE_PCLK_DIS, 3, 1);
|
||||
DEFINE_CLK_RST_REG(CLK_SYSTEM_RATE_AHB_RATE, 4, 2);
|
||||
DEFINE_CLK_RST_REG(CLK_SYSTEM_RATE_HCLK_DIS, 7, 1);
|
||||
|
||||
DEFINE_CLK_RST_REG(MISC_CLK_ENB_CFG_ALL_VISIBLE, 28, 1);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(OSC_CTRL_XOE, 0, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG(OSC_CTRL_XOFS, 4, 6);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(OSC_CTRL_OSC_FREQ, 28, OSC13, OSC16P8, RSVD2, RSVD3, OSC19P2, OSC38P4, RSVD6, RSVD7, OSC12, OSC48, RSVD10, RSVD11, OSC26, RSVD13, RSVD14, RSVD15);
|
||||
|
||||
DEFINE_CLK_RST_REG(PLLC_BASE_PLLC_DIVM, 0, 8);
|
||||
DEFINE_CLK_RST_REG(PLLC_BASE_PLLC_DIVN, 10, 8);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_BASE_PLLC_LOCK, 27, NOT_LOCK, LOCK);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_BASE_PLLC_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_BASE_PLLC_ENABLE, 30, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_BASE_PLLC_BYPASS, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_OUT_PLLC_OUT1_RSTN, 0, RESET_ENABLE, RESET_DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_OUT_PLLC_OUT1_CLKEN, 1, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG(PLLC_OUT_PLLC_OUT1_RATIO, 8, 8);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC_OUT_PLLC_OUT1_DIV_BYP, 16, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVM, 0, 8);
|
||||
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVN, 8, 8);
|
||||
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVP, 20, 5);
|
||||
DEFINE_CLK_RST_REG(PLLM_BASE_PLLM_DIVP_B01, 20, 1);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_LOCK, 27, NOT_LOCK, LOCK);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_ENABLE, 30, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_BASE_PLLM_BYPASSPLL, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLM_MISC2_PLLM_EN_LCKDET, 4, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_CSI_CLK_SRC, 23, BRICK, PLL_D);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_ENABLE, 30, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLD_BASE_PLLD_BYPASS, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_LOCK, 27, NOT_LOCK, LOCK);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_REF_DIS, 29, REF_ENABLE, REF_DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_BASE_PLLX_ENABLE, 30, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLX_MISC_PLLX_LOCK_ENABLE, 18, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIVIDEND, 8, 8);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_IRQ, 24, NO_IMPACT, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_IRQ, 25, NO_IMPACT, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_CPU_FIQ, 26, NO_IMPACT, DISABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_DIS_FROM_COP_FIQ, 27, NO_IMPACT, DISABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKG_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(SUPER_CCLKLP_DIVIDER_SUPER_CDIV_ENB, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_IDLE_SOURCE, 0, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_RUN_SOURCE, 4, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_IRQ_SOURCE, 8, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CWAKEUP_FIQ_SOURCE, 12, CLKM, RSVD1, CLKS, RSVD3, PLLP_OUT0, PLLP_OUT4, RSVD6, RSVD7, PLLX_OUT0_LJ, DVFS_CPU_CLK, RSVD10, RSVD11, RSVD12, RSVD13, PLLX_OUT0, DVFS_CPU_CLK_LJ);
|
||||
DEFINE_CLK_RST_REG_FOUR_BIT_ENUM(CCLK_BURST_POLICY_CPU_STATE, 28, STDBY, IDLE, RUN, RSVD3, IRQ, RSVD5, RSVD6, RSVD7, FIQ, RSVD9, RSVD10, RSVD11, RSVD12, RSVD13, RSVD14, RSVD15);
|
||||
|
||||
DEFINE_CLK_RST_REG(CPU_SOFTRST_CTRL2_CAR2PMC_CPU_ACK_WIDTH, 0, 12);
|
||||
|
||||
DEFINE_CLK_RST_REG(PLLX_MISC3_PLLX_IDDQ, 3, 1);
|
||||
|
||||
DEFINE_CLK_RST_REG_TWO_BIT_ENUM(SPARE_REG0_CLK_M_DIVISOR, 2, CLK_M_DIVISOR1, CLK_M_DIVISOR2, CLK_M_DIVISOR3, CLK_M_DIVISOR4);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_IDDQ, 18, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_LOCK, 27, NOT_LOCK, LOCK_FEQ_AND_PHASE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLC4_BASE_PLLC4_ENABLE, 30, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVM, 0, 8);
|
||||
DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVN, 8, 8);
|
||||
DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVP, 20, 5);
|
||||
DEFINE_CLK_RST_REG(PLLMB_BASE_PLLMB_DIVP_B01, 20, 1);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_LOCK, 27, NOT_LOCK, LOCK);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(PLLMB_BASE_PLLMB_ENABLE, 30, DISABLE, ENABLE);
|
||||
|
||||
/* RST_DEVICES */
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_L (0x004)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_H (0x008)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_U (0x00C)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_X (0x28C)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_Y (0x2A4)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_V (0x358)
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES_W (0x35C)
|
||||
|
||||
/* CLK_OUT_ENB */
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L (0x010)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H (0x014)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U (0x018)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X (0x280)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y (0x298)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_V (0x360)
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W (0x364)
|
||||
|
||||
/* CLK_SOURCE */
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM (0x110)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 (0x124)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 (0x128)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 (0x138)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_VI (0x148)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 (0x150)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 (0x154)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 (0x164)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA (0x178)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB (0x17C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X (0x180)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 (0x198)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC (0x19C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC (0x1A0)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 (0x1B8)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 (0x1BC)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE (0x1D4)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC (0x1F4)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT (0x3B4)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 (0x3C4)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON (0x3E8)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 (0x410)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_SE (0x42C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP (0x620)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_REF (0x62C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_DVFS_SOC (0x630)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 (0x65C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL (0x664)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL (0x66C)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM (0x694)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC (0x6A0)
|
||||
#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_SAFE (0x724)
|
||||
|
||||
/* RST_DEV_*_SET */
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_L_SET (0x300)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_H_SET (0x308)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_U_SET (0x310)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_V_SET (0x430)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_W_SET (0x438)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_X_SET (0x290)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_Y_SET (0x2A8)
|
||||
|
||||
/* RST_DEV_*_CLR */
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_L_CLR (0x304)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_H_CLR (0x30C)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_U_CLR (0x314)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_V_CLR (0x434)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_W_CLR (0x43C)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_X_CLR (0x294)
|
||||
#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR (0x2AC)
|
||||
|
||||
/* CLK_ENB_*_SET */
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_L_SET (0x320)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_H_SET (0x328)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_U_SET (0x330)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_V_SET (0x440)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_W_SET (0x448)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_X_SET (0x284)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET (0x29C)
|
||||
|
||||
/* CLK_ENB_*_CLR */
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR (0x324)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR (0x32C)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR (0x334)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR (0x288)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR (0x2A0)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR (0x444)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR (0x44C)
|
||||
|
||||
/* RST_*_INDEX */
|
||||
#define CLK_RST_CONTROLLER_RST_I2C1_INDEX (0x0C)
|
||||
#define CLK_RST_CONTROLLER_RST_I2C2_INDEX (0x16)
|
||||
#define CLK_RST_CONTROLLER_RST_I2C3_INDEX (0x03)
|
||||
#define CLK_RST_CONTROLLER_RST_I2C4_INDEX (0x07)
|
||||
#define CLK_RST_CONTROLLER_RST_I2C5_INDEX (0x0F)
|
||||
#define CLK_RST_CONTROLLER_RST_I2C6_INDEX (0x06)
|
||||
|
||||
#define CLK_RST_CONTROLLER_RST_PWM_INDEX (0x11)
|
||||
|
||||
#define CLK_RST_CONTROLLER_RST_UARTA_INDEX (0x06)
|
||||
#define CLK_RST_CONTROLLER_RST_UARTB_INDEX (0x07)
|
||||
#define CLK_RST_CONTROLLER_RST_UARTC_INDEX (0x17)
|
||||
|
||||
#define CLK_RST_CONTROLLER_RST_ACTMON_INDEX (0x17)
|
||||
|
||||
/* CLK_ENB_*_INDEX */
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_I2C1_INDEX (0x0C)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_I2C2_INDEX (0x16)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_I2C3_INDEX (0x03)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_I2C4_INDEX (0x07)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_I2C5_INDEX (0x0F)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_I2C6_INDEX (0x06)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_PWM_INDEX (0x11)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_UARTA_INDEX (0x06)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_UARTB_INDEX (0x07)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_UARTC_INDEX (0x17)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_ACTMON_INDEX (0x17)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_DVFS_INDEX (0x1B)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_TZRAM_INDEX (0x1E)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_CACHE2_INDEX (0x1F)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_CRAM2_INDEX (0x18)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_SE_INDEX (0x1F)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_CSITE_INDEX (0x09)
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_HOST1X_INDEX (0x1C)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_TSEC_INDEX (0x13)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_SOR0_INDEX (0x16)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_SOR1_INDEX (0x17)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_SOR_SAFE_INDEX (0x1E)
|
||||
#define CLK_RST_CONTROLLER_CLK_ENB_KFUSE_INDEX (0x08)
|
||||
|
||||
/* RST_CPUG_CMPLX_* */
|
||||
#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET (0x450)
|
||||
#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR (0x454)
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ARC_CLK_OVR_ON, 19, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSEC_CLK_OVR_ON, 20, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TSECB_CLK_OVR_ON, 21, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_ISPB_CLK_OVR_ON, 22, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_TZRAM_CLK_OVR_ON, 23, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_QSPI_CLK_OVR_ON, 24, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_A9AVP_CLK_OVR_ON, 26, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_MPCORE_MSELECT_CLK_OVR_ON, 27, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC1_LEGACY_TMCLK_OVR_ON, 28, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC2_LEGACY_TMCLK_OVR_ON, 29, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC3_LEGACY_TMCLK_OVR_ON, 30, OFF, ON);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(LVL2_CLK_GATE_OVRD_SDMMC4_LEGACY_TMCLK_OVR_ON, 31, OFF, ON);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_CLK_SOURCE, 29, 3);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C1_I2C1_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_I2C1_I2C1_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_I2C5_I2C5_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_I2C5_I2C5_CLK_DIVISOR, 0, 8);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SDMMC1_SDMMC1_CLK_SRC, 29, PLLP_OUT0, PLLA_OUT, PLLC_OUT0, PLLC4_OUT2, PLLM_OUT0, PLLE_OUT0, CLK_M, PLLC4_OUT0);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SDMMC2_SDMMC2_CLK_SRC, 29, PLLP_OUT0, PLLC4_OUT2_LJ, PLLC4_OUT0_LJ, PLLC4_OUT2, PLLC4_OUT1, PLLC4_OUT1_LJ, CLK_M, PLLC4_OUT0);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SDMMC4_SDMMC4_CLK_SRC, 29, PLLP_OUT0, PLLC4_OUT2_LJ, PLLC4_OUT0_LJ, PLLC4_OUT2, PLLC4_OUT1, PLLC4_OUT1_LJ, CLK_M, PLLC4_OUT0);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SDMMC3_SDMMC3_CLK_SRC, 29, PLLP_OUT0, PLLA_OUT, PLLC_OUT0, PLLC4_OUT2, PLLC4_OUT1, PLLE_OUT0, CLK_M, PLLC4_OUT0);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SDMMCX_SDMMCX_CLK_SRC, 29, PLLP_OUT0, _RSVD1_, _RSVD2_, PLLC4_OUT2, _RSVD4_, _RSVD5_, CLK_M, PLLC4_OUT0);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SDMMC24_SDMMC24_CLK_SRC, 29, PLLP_OUT0, PLLC4_OUT2_LJ, PLLC4_OUT0_LJ, PLLC4_OUT2, PLLC4_OUT1, PLLC4_OUT1_LJ, CLK_M, PLLC4_OUT0);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_SDMMC1_SDMMC1_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_SDMMC2_SDMMC2_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_SDMMC4_SDMMC4_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_SDMMC3_SDMMC3_CLK_DIVISOR, 0, 8);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTA_UARTA_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTB_UARTB_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UARTC_UARTC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_VI_VI_CLK_SRC, 29, RESERVED0, PLLC2_OUT0, PLLC_OUT, PLLC3_OUT0, PLLP_OUT0, CLK_M, PLLA1_OUT0, PLLC4_OUT0);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_HOST1X_HOST1X_CLK_SRC, 29, PLLC4_OUT1, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLP_OUT0, CLK_M, PLLA_OUT0, PLLC4_OUT0);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_EMC_EMC_2X_CLK_SRC, 29, PLLM_OUT0, PLLC_OUT0, PLLP_OUT0, CLK_M, PLLM_UD, PLLMB_UD, PLLMB_OUT0, PLLP_UD);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_NVENC_NVENC_CLK_SRC, 29, RESERVED0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, PLLP_OUT0, RESERVED5, PLLA1_OUT0, CLK_M);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_CSITE_CSITE_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, PLLREFE_OUT1, PLLA1_OUT0, CLK_M, PLLC4_OUT0);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_TSEC_TSEC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, RESERVED4, PLLA1_OUT0, CLK_M, PLLC4_OUT0);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SE_SE_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC3_OUT0, RSVD4, PLLA1_OUT0, CLK_M, PLLC4_OUT0);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_SOURCE_SE_CLK_LOCK, 8, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_SOURCE_SOR1_SOR1_CLK_SEL0, 14, MUX, SOR1_BRICK_OUTPUT);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_SOURCE_SOR1_SOR1_CLK_SEL1, 15, SAFE_CLOCK, SOR1_CLOCK_SWITCH);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_SOR1_SOR1_CLK_SRC, 29, PLLP_OUT0, RESERVED1, PLLD_OUT0, RESERVED3, RESERVED4, PLLD2_OUT0, CLK_M, RESERVED7);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_MSELECT_MSELECT_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT2, PLLC4_OUT1, CLK_S, CLK_M, PLLC4_OUT0);
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_MSELECT_MSELECT_CLK_DIVISOR, 0, 8);
|
||||
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_ACTMON_ACTMON_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, CLK_S, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DSIA_LP_DSIA_LP_CLK_SRC, 29, PLLP_OUT0, RSVD1, PLLC_OUT0, PLLC4_OUT0, PLLC4_OUT1, PLLC4_OUT2, CLK_M, RSVD7);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_REF_DVFS_REF_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_REF_DVFS_REF_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_DVFS_SOC_DVFS_SOC_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_DVFS_SOC_DVFS_SOC_CLK_SRC, 29, PLLP_OUT0, PLLC2_OUT0, PLLC_OUT0, PLLC4_OUT0, RESERVED4, PLLC4_OUT1, CLK_M, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_UART_FST_MIPI_CAL_UART_FST_MIPI_CAL_CLK_SRC, 29, PLLP_OUT3, PLLC_OUT0, PLLC2_OUT0_2, RSVD3, PLLC2_OUT0_4, RSVD5, CLK_M, RSVD7);
|
||||
|
||||
DEFINE_CLK_RST_REG(CLK_SOURCE_LEGACY_TM_CLK_DIVISOR, 0, 8);
|
||||
DEFINE_CLK_RST_REG_THREE_BIT_ENUM(CLK_SOURCE_LEGACY_TM_CLK_SRC, 29, PLLP_OUT3, PLLC_OUT0, PLLC2_OUT0, CLK_M, PLLP_OUT0, PLLC4_OUT0, PLLC4_OUT1, PLLC4_OUT2);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_SET_SET_COP_RST, 1, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_L_CLR_CLR_COP_RST, 1, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET0, 0, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET1, 1, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET2, 2, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CPURESET3, 3, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET0, 16, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET1, 17, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET2, 18, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_CORERESET3, 19, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_L2RESET, 24, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_NONCPURESET, 29, DISABLE, ENABLE);
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_CPUG_CMPLX_CLR_CLR_PRESETDBG, 30, DISABLE, ENABLE);
|
||||
|
||||
/* TODO: Actually include all devices. */
|
||||
#define CLK_RST_FOREACH_DEVICE(HANDLER) \
|
||||
HANDLER(L, CPU, 0, 0) \
|
||||
HANDLER(L, RTC, 0, 4) \
|
||||
HANDLER(L, TMR, 0, 5) \
|
||||
HANDLER(L, GPIO, 0, 8) \
|
||||
HANDLER(L, SDMMC2, 0, 9) \
|
||||
HANDLER(L, SDMMC1, 0, 14) \
|
||||
HANDLER(L, SDMMC4, 0, 15) \
|
||||
HANDLER(L, USBD, 0, 22) \
|
||||
HANDLER(L, DISP1, 0, 27) \
|
||||
HANDLER(L, HOST1X, 0, 28) \
|
||||
HANDLER(L, CACHE2, 0, 31) \
|
||||
HANDLER(H, MEM, 1, 0) \
|
||||
HANDLER(H, AHBDMA, 1, 1) \
|
||||
HANDLER(H, APBDMA, 1, 2) \
|
||||
HANDLER(H, PMC, 1, 6) \
|
||||
HANDLER(H, FUSE, 1, 7) \
|
||||
HANDLER(H, KFUSE, 1, 8) \
|
||||
HANDLER(H, I2C5, 1, 15) \
|
||||
HANDLER(H, DSI, 1, 16) \
|
||||
HANDLER(H, MIPI_CAL, 1, 24) \
|
||||
HANDLER(H, EMC, 1, 25) \
|
||||
HANDLER(H, USB2, 1, 26) \
|
||||
HANDLER(U, SDMMC3, 2, 5) \
|
||||
HANDLER(U, CSITE, 2, 9) \
|
||||
HANDLER(U, IRAMA, 2, 20) \
|
||||
HANDLER(U, IRAMB, 2, 21) \
|
||||
HANDLER(U, IRAMC, 2, 22) \
|
||||
HANDLER(U, IRAMD, 2, 23) \
|
||||
HANDLER(U, CRAM2, 2, 24) \
|
||||
HANDLER(V, CPUG, 3, 0) \
|
||||
HANDLER(V, MSELECT, 3, 3) \
|
||||
HANDLER(V, AHUB, 3, 10) \
|
||||
HANDLER(V, APB2APE, 3, 11) \
|
||||
HANDLER(V, SPDIF_DOUBLER, 3, 22) \
|
||||
HANDLER(V, ACTMON, 3, 23) \
|
||||
HANDLER(V, TZRAM, 3, 30) \
|
||||
HANDLER(V, SE, 3, 31) \
|
||||
HANDLER(W, PCIERX0, 4, 2) \
|
||||
HANDLER(W, PCIERX1, 4, 3) \
|
||||
HANDLER(W, PCIERX2, 4, 4) \
|
||||
HANDLER(W, PCIERX3, 4, 5) \
|
||||
HANDLER(W, PCIERX4, 4, 6) \
|
||||
HANDLER(W, PCIERX5, 4, 7) \
|
||||
HANDLER(W, DSIA_LP, 4, 19) \
|
||||
HANDLER(W, ENTROPY, 4, 21) \
|
||||
HANDLER(W, DVFS, 4, 27) \
|
||||
HANDLER(W, MC1, 4, 30) \
|
||||
HANDLER(X, MC_CAPA, 5, 7) \
|
||||
HANDLER(X, MC_CBPA, 5, 8) \
|
||||
HANDLER(X, MC_CPU, 5, 9) \
|
||||
HANDLER(X, MC_BBC, 5, 10) \
|
||||
HANDLER(X, EMC_DLL, 5, 14) \
|
||||
HANDLER(X, UART_FST_MIPI_CAL, 5, 17) \
|
||||
HANDLER(X, VIC, 5, 18) \
|
||||
HANDLER(X, GPU, 5, 24) \
|
||||
HANDLER(X, DBGAPB, 5, 25) \
|
||||
HANDLER(X, PLLG_REF, 5, 29) \
|
||||
HANDLER(Y, LEGACY_TM, 6, 1) \
|
||||
HANDLER(Y, APE, 6, 6) \
|
||||
HANDLER(Y, MC_CCPA, 6, 8) \
|
||||
HANDLER(Y, MC_CDPA, 6, 9) \
|
||||
HANDLER(Y, PLLP_OUT_CPU, 6, 31)
|
||||
|
||||
#define CLK_RST_DEFINE_SET_CLR_REG(REGISTER, DEVICE, REGISTER_INDEX, DEVICE_INDEX) \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_SET_SET_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLR_CLR_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_OUT_ENB_##REGISTER##_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(CLK_ENB_##REGISTER##_CLK_ENB_##DEVICE, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_SET_SET_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_CLR_CLR_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEV_##REGISTER##_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE); \
|
||||
DEFINE_CLK_RST_REG_BIT_ENUM(RST_DEVICES_##REGISTER##_SWR_##DEVICE##_RST, DEVICE_INDEX, DISABLE, ENABLE);
|
||||
|
||||
CLK_RST_FOREACH_DEVICE(CLK_RST_DEFINE_SET_CLR_REG)
|
||||
|
||||
#undef CLK_RST_DEFINE_SET_CLR_REG
|
||||
|
||||
@@ -1,636 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define EMC_ADDRESS(x) (0x7001B000 + x)
|
||||
#define EMC0_ADDRESS(x) (0x7001E000 + x)
|
||||
#define EMC1_ADDRESS(x) (0x7001F000 + x)
|
||||
|
||||
#define EMC_INTSTATUS (0x000)
|
||||
#define EMC_DBG (0x008)
|
||||
#define EMC_CFG (0x00C)
|
||||
#define EMC_ADR_CFG (0x010)
|
||||
#define EMC_REFCTRL (0x020)
|
||||
#define EMC_PIN (0x024)
|
||||
#define EMC_TIMING_CONTROL (0x028)
|
||||
#define EMC_RC (0x02C)
|
||||
#define EMC_RFC (0x030)
|
||||
#define EMC_RAS (0x034)
|
||||
#define EMC_RP (0x038)
|
||||
#define EMC_R2W (0x03C)
|
||||
#define EMC_W2R (0x040)
|
||||
#define EMC_R2P (0x044)
|
||||
#define EMC_W2P (0x048)
|
||||
#define EMC_RD_RCD (0x04C)
|
||||
#define EMC_WR_RCD (0x050)
|
||||
#define EMC_RRD (0x054)
|
||||
#define EMC_REXT (0x058)
|
||||
#define EMC_WDV (0x05C)
|
||||
#define EMC_QUSE (0x060)
|
||||
#define EMC_QRST (0x064)
|
||||
#define EMC_QSAFE (0x068)
|
||||
#define EMC_RDV (0x06C)
|
||||
#define EMC_REFRESH (0x070)
|
||||
#define EMC_BURST_REFRESH_NUM (0x074)
|
||||
#define EMC_PDEX2WR (0x078)
|
||||
#define EMC_PDEX2RD (0x07C)
|
||||
#define EMC_PCHG2PDEN (0x080)
|
||||
#define EMC_ACT2PDEN (0x084)
|
||||
#define EMC_AR2PDEN (0x088)
|
||||
#define EMC_RW2PDEN (0x08C)
|
||||
#define EMC_TXSR (0x090)
|
||||
#define EMC_TCKE (0x094)
|
||||
#define EMC_TFAW (0x098)
|
||||
#define EMC_TRPAB (0x09C)
|
||||
#define EMC_TCLKSTABLE (0x0A0)
|
||||
#define EMC_TCLKSTOP (0x0A4)
|
||||
#define EMC_TREFBW (0x0A8)
|
||||
#define EMC_TPPD (0x0AC)
|
||||
#define EMC_ODT_WRITE (0x0B0)
|
||||
#define EMC_PDEX2MRR (0x0B4)
|
||||
#define EMC_WEXT (0x0B8)
|
||||
#define EMC_TRTM (0x0BC)
|
||||
#define EMC_RFC_SLR (0x0C0)
|
||||
#define EMC_MRS_WAIT_CNT2 (0x0C4)
|
||||
#define EMC_MRS_WAIT_CNT (0x0C8)
|
||||
#define EMC_MRS (0x0CC)
|
||||
#define EMC_EMRS (0x0D0)
|
||||
#define EMC_REF (0x0D4)
|
||||
#define EMC_NOP (0x0DC)
|
||||
#define EMC_SELF_REF (0x0E0)
|
||||
#define EMC_MRW (0x0E8)
|
||||
#define EMC_MRR (0x0EC)
|
||||
#define EMC_CMDQ (0x0F0)
|
||||
#define EMC_MC2EMCQ (0x0F4)
|
||||
#define EMC_TWTM (0x0F8)
|
||||
#define EMC_TRATM (0x0FC)
|
||||
#define EMC_FBIO_SPARE (0x100)
|
||||
#define EMC_FBIO_CFG5 (0x104)
|
||||
#define EMC_TWATM (0x108)
|
||||
#define EMC_TR2REF (0x10C)
|
||||
#define EMC_PMACRO_DATA_PI_CTRL (0x110)
|
||||
#define EMC_PMACRO_CMD_PI_CTRL (0x114)
|
||||
#define EMC_PDEX2CKE (0x118)
|
||||
#define EMC_CKE2PDEN (0x11C)
|
||||
#define EMC_CFG_RSV (0x120)
|
||||
#define EMC_ACPD_CONTROL (0x124)
|
||||
#define EMC_MPC (0x128)
|
||||
#define EMC_EMRS2 (0x12C)
|
||||
#define EMC_MRW2 (0x134)
|
||||
#define EMC_MRW3 (0x138)
|
||||
#define EMC_MRW3 (0x138)
|
||||
#define EMC_MRW4 (0x13C)
|
||||
#define EMC_CLKEN_OVERRIDE (0x140)
|
||||
#define EMC_R2R (0x144)
|
||||
#define EMC_W2W (0x148)
|
||||
#define EMC_EINPUT (0x14C)
|
||||
#define EMC_EINPUT_DURATION (0x150)
|
||||
#define EMC_PUTERM_EXTRA (0x154)
|
||||
#define EMC_TCKESR (0x158)
|
||||
#define EMC_TPD (0x15C)
|
||||
#define EMC_AUTO_CAL_CONFIG (0x2A4)
|
||||
#define EMC_AUTO_CAL_INTERVAL (0x2A8)
|
||||
#define EMC_REQ_CTRL (0x2B0)
|
||||
#define EMC_EMC_STATUS (0x2B4)
|
||||
#define EMC_CFG_2 (0x2B8)
|
||||
#define EMC_CFG_DIG_DLL (0x2BC)
|
||||
#define EMC_CFG_DIG_DLL_PERIOD (0x2C0)
|
||||
#define EMC_DIG_DLL_STATUS (0x2C4)
|
||||
#define EMC_CFG_DIG_DLL_1 (0x2C8)
|
||||
#define EMC_RDV_MASK (0x2CC)
|
||||
#define EMC_WDV_MASK (0x2D0)
|
||||
#define EMC_RDV_EARLY_MASK (0x2D4)
|
||||
#define EMC_RDV_EARLY (0x2D8)
|
||||
#define EMC_AUTO_CAL_CONFIG8 (0x2DC)
|
||||
#define EMC_ZCAL_INTERVAL (0x2E0)
|
||||
#define EMC_ZCAL_WAIT_CNT (0x2E4)
|
||||
#define EMC_ZCAL_MRW_CMD (0x2E8)
|
||||
#define EMC_ZQ_CAL (0x2EC)
|
||||
#define EMC_XM2COMPPADCTRL3 (0x2F4)
|
||||
#define EMC_AUTO_CAL_VREF_SEL_0 (0x2F8)
|
||||
#define EMC_AUTO_CAL_VREF_SEL_1 (0x300)
|
||||
#define EMC_XM2COMPPADCTRL (0x30C)
|
||||
#define EMC_FDPD_CTRL_DQ (0x310)
|
||||
#define EMC_FDPD_CTRL_CMD (0x314)
|
||||
#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD (0x318)
|
||||
#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD (0x31C)
|
||||
#define EMC_SCRATCH0 (0x324)
|
||||
#define EMC_PMACRO_BRICK_CTRL_RFU1 (0x330)
|
||||
#define EMC_PMACRO_BRICK_CTRL_RFU2 (0x334)
|
||||
#define EMC_CMD_MAPPING_CMD0_0 (0x380)
|
||||
#define EMC_CMD_MAPPING_CMD0_1 (0x384)
|
||||
#define EMC_CMD_MAPPING_CMD0_2 (0x388)
|
||||
#define EMC_CMD_MAPPING_CMD1_0 (0x38C)
|
||||
#define EMC_CMD_MAPPING_CMD1_1 (0x390)
|
||||
#define EMC_CMD_MAPPING_CMD1_2 (0x394)
|
||||
#define EMC_CMD_MAPPING_CMD2_0 (0x398)
|
||||
#define EMC_CMD_MAPPING_CMD2_1 (0x39C)
|
||||
#define EMC_CMD_MAPPING_CMD2_2 (0x3A0)
|
||||
#define EMC_CMD_MAPPING_CMD3_0 (0x3A4)
|
||||
#define EMC_CMD_MAPPING_CMD3_1 (0x3A8)
|
||||
#define EMC_CMD_MAPPING_CMD3_2 (0x3AC)
|
||||
#define EMC_CMD_MAPPING_BYTE (0x3B0)
|
||||
#define EMC_TR_TIMING_0 (0x3B4)
|
||||
#define EMC_TR_CTRL_0 (0x3B8)
|
||||
#define EMC_TR_CTRL_1 (0x3BC)
|
||||
#define EMC_SWITCH_BACK_CTRL (0x3C0)
|
||||
#define EMC_TR_RDV (0x3C4)
|
||||
#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE (0x3CC)
|
||||
#define EMC_SEL_DPD_CTRL (0x3D8)
|
||||
#define EMC_PRE_REFRESH_REQ_CNT (0x3DC)
|
||||
#define EMC_DYN_SELF_REF_CONTROL (0x3E0)
|
||||
#define EMC_TXSRDLL (0x3E4)
|
||||
#define EMC_CCFIFO_ADDR (0x3E8)
|
||||
#define EMC_CCFIFO_DATA (0x3EC)
|
||||
#define EMC_CCFIFO_STATUS (0x3F0)
|
||||
#define EMC_TR_QPOP (0x3F4)
|
||||
#define EMC_TR_RDV_MASK (0x3F8)
|
||||
#define EMC_TR_QSAFE (0x3FC)
|
||||
#define EMC_TR_QRST (0x400)
|
||||
#define EMC_SWIZZLE_RANK0_BYTE0 (0x404)
|
||||
#define EMC_SWIZZLE_RANK0_BYTE1 (0x408)
|
||||
#define EMC_SWIZZLE_RANK0_BYTE2 (0x40C)
|
||||
#define EMC_SWIZZLE_RANK0_BYTE3 (0x410)
|
||||
#define EMC_SWIZZLE_RANK1_BYTE0 (0x418)
|
||||
#define EMC_SWIZZLE_RANK1_BYTE1 (0x41C)
|
||||
#define EMC_SWIZZLE_RANK1_BYTE2 (0x420)
|
||||
#define EMC_SWIZZLE_RANK1_BYTE3 (0x424)
|
||||
#define EMC_ISSUE_QRST (0x428)
|
||||
#define EMC_AUTO_CAL_CONFIG9 (0x42C)
|
||||
#define EMC_PMC_SCRATCH1 (0x440)
|
||||
#define EMC_PMC_SCRATCH2 (0x444)
|
||||
#define EMC_PMC_SCRATCH3 (0x448)
|
||||
#define EMC_AUTO_CAL_CONFIG2 (0x458)
|
||||
#define EMC_AUTO_CAL_CONFIG3 (0x45C)
|
||||
#define EMC_TR_DVFS (0x460)
|
||||
#define EMC_AUTO_CAL_CHANNEL (0x464)
|
||||
#define EMC_IBDLY (0x468)
|
||||
#define EMC_OBDLY (0x46C)
|
||||
#define EMC_TXDSRVTTGEN (0x480)
|
||||
#define EMC_WE_DURATION (0x48C)
|
||||
#define EMC_WS_DURATION (0x490)
|
||||
#define EMC_WEV (0x494)
|
||||
#define EMC_WSV (0x498)
|
||||
#define EMC_CFG_3 (0x49C)
|
||||
#define EMC_MRW5 (0x4A0)
|
||||
#define EMC_MRW6 (0x4A4)
|
||||
#define EMC_MRW7 (0x4A8)
|
||||
#define EMC_MRW8 (0x4AC)
|
||||
#define EMC_MRW9 (0x4B0)
|
||||
#define EMC_MRW10 (0x4B4)
|
||||
#define EMC_MRW11 (0x4B8)
|
||||
#define EMC_MRW12 (0x4BC)
|
||||
#define EMC_MRW13 (0x4C0)
|
||||
#define EMC_MRW14 (0x4C4)
|
||||
#define EMC_MRW15 (0x4D0)
|
||||
#define EMC_CFG_SYNC (0x4D4)
|
||||
#define EMC_FDPD_CTRL_CMD_NO_RAMP (0x4D8)
|
||||
#define EMC_WDV_CHK (0x4E0)
|
||||
#define EMC_CFG_PIPE_2 (0x554)
|
||||
#define EMC_CFG_PIPE_CLK (0x558)
|
||||
#define EMC_CFG_PIPE_1 (0x55C)
|
||||
#define EMC_CFG_PIPE (0x560)
|
||||
#define EMC_QPOP (0x564)
|
||||
#define EMC_QUSE_WIDTH (0x568)
|
||||
#define EMC_PUTERM_WIDTH (0x56C)
|
||||
#define EMC_AUTO_CAL_CONFIG7 (0x574)
|
||||
#define EMC_XM2COMPPADCTRL2 (0x578)
|
||||
#define EMC_REFCTRL2 (0x580)
|
||||
#define EMC_FBIO_CFG7 (0x584)
|
||||
#define EMC_DATA_BRLSHFT_0 (0x588)
|
||||
#define EMC_DATA_BRLSHFT_1 (0x58C)
|
||||
#define EMC_RFCPB (0x590)
|
||||
#define EMC_DQS_BRLSHFT_0 (0x594)
|
||||
#define EMC_DQS_BRLSHFT_1 (0x598)
|
||||
#define EMC_CMD_BRLSHFT_0 (0x59C)
|
||||
#define EMC_CMD_BRLSHFT_1 (0x5A0)
|
||||
#define EMC_CMD_BRLSHFT_2 (0x5A4)
|
||||
#define EMC_CMD_BRLSHFT_3 (0x5A8)
|
||||
#define EMC_QUSE_BRLSHFT_0 (0x5AC)
|
||||
#define EMC_AUTO_CAL_CONFIG4 (0x5B0)
|
||||
#define EMC_AUTO_CAL_CONFIG5 (0x5B4)
|
||||
#define EMC_QUSE_BRLSHFT_1 (0x5B8)
|
||||
#define EMC_QUSE_BRLSHFT_2 (0x5BC)
|
||||
#define EMC_CCDMW (0x5C0)
|
||||
#define EMC_QUSE_BRLSHFT_3 (0x5C4)
|
||||
#define EMC_FBIO_CFG8 (0x5C8)
|
||||
#define EMC_AUTO_CAL_CONFIG6 (0x5CC)
|
||||
|
||||
/* Erista */
|
||||
#define EMC_DLL_CFG_0 (0x5E4)
|
||||
#define EMC_DLL_CFG_1 (0x5E8)
|
||||
|
||||
/* Mariko */
|
||||
#define EMC_PMACRO_DLL_CFG_0 (0x5E4)
|
||||
#define EMC_PMACRO_DLL_CFG_1 (0x5E8)
|
||||
#define EMC_PMACRO_DLL_CFG_2 (0x5F8)
|
||||
|
||||
#define EMC_CONFIG_SAMPLE_DELAY (0x5F0)
|
||||
#define EMC_CFG_UPDATE (0x5F4)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_0 (0x600)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_1 (0x604)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_2 (0x608)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_3 (0x60C)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_4 (0x610)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_5 (0x614)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_4 (0x630)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_5 (0x634)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_0 (0x620)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_1 (0x624)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_2 (0x628)
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_3 (0x62C)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 (0x640)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 (0x644)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 (0x648)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 (0x64C)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 (0x650)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 (0x654)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 (0x660)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 (0x664)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 (0x668)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 (0x66C)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 (0x670)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 (0x674)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 (0x680)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 (0x684)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 (0x688)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 (0x68C)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 (0x690)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 (0x694)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 (0x6A0)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 (0x6A4)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 (0x6A8)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 (0x6AC)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 (0x6B0)
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 (0x6B4)
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 (0x6C0)
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 (0x6C4)
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 (0x6C8)
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 (0x6CC)
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 (0x6E0)
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 (0x6E4)
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 (0x6E8)
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 (0x6EC)
|
||||
#define EMC_PMACRO_AUTOCAL_CFG_0 (0x700)
|
||||
#define EMC_PMACRO_AUTOCAL_CFG_1 (0x704)
|
||||
#define EMC_PMACRO_AUTOCAL_CFG_2 (0x708)
|
||||
#define EMC_PMACRO_TX_PWRD_0 (0x720)
|
||||
#define EMC_PMACRO_TX_PWRD_1 (0x724)
|
||||
#define EMC_PMACRO_TX_PWRD_2 (0x728)
|
||||
#define EMC_PMACRO_TX_PWRD_3 (0x72C)
|
||||
#define EMC_PMACRO_TX_PWRD_4 (0x730)
|
||||
#define EMC_PMACRO_TX_PWRD_5 (0x734)
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_0 (0x740)
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_1 (0x744)
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_3 (0x74C)
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_2 (0x748)
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_4 (0x750)
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_5 (0x754)
|
||||
#define EMC_PMACRO_DDLL_BYPASS (0x760)
|
||||
#define EMC_PMACRO_DDLL_PWRD_0 (0x770)
|
||||
#define EMC_PMACRO_DDLL_PWRD_1 (0x774)
|
||||
#define EMC_PMACRO_DDLL_PWRD_2 (0x778)
|
||||
#define EMC_PMACRO_CMD_CTRL_0 (0x780)
|
||||
#define EMC_PMACRO_CMD_CTRL_1 (0x784)
|
||||
#define EMC_PMACRO_CMD_CTRL_2 (0x788)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 (0x800)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 (0x804)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 (0x808)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 (0x80C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 (0x810)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 (0x814)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 (0x818)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 (0x81C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 (0x820)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 (0x824)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 (0x828)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 (0x82C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 (0x830)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 (0x834)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 (0x838)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 (0x83C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 (0x840)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 (0x844)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 (0x848)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 (0x84C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 (0x850)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 (0x854)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 (0x858)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 (0x85C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 (0x860)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 (0x864)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 (0x868)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 (0x86C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 (0x870)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 (0x874)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 (0x878)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 (0x87C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 (0x880)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 (0x884)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 (0x888)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 (0x88C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 (0x890)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 (0x894)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 (0x898)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 (0x89C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 (0x8A0)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 (0x8A4)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 (0x8A8)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 (0x8AC)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 (0x8B0)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 (0x8B4)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 (0x8B8)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 (0x8BC)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 (0x900)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 (0x904)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 (0x908)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 (0x90C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 (0x910)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 (0x914)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 (0x918)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 (0x91C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 (0x920)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 (0x924)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 (0x928)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 (0x92C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 (0x930)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 (0x934)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 (0x938)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 (0x93C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 (0x940)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 (0x944)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 (0x948)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 (0x94C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 (0x950)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 (0x954)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 (0x958)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 (0x95C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 (0x960)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 (0x964)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 (0x968)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 (0x96C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 (0x970)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 (0x974)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 (0x978)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 (0x97C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 (0x980)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 (0x984)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 (0x988)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 (0x98C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 (0x990)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 (0x994)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 (0x998)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 (0x99C)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 (0x9A0)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 (0x9A4)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 (0x9A8)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 (0x9AC)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 (0x9B0)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 (0x9B4)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 (0x9B8)
|
||||
#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 (0x9BC)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 (0xA00)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 (0xA04)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 (0xA08)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 (0xA10)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 (0xA14)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 (0xA18)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 (0xA20)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 (0xA24)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 (0xA28)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 (0xA30)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 (0xA34)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 (0xA38)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 (0xA40)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 (0xA44)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 (0xA48)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 (0xA50)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 (0xA54)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 (0xA58)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 (0xA60)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 (0xA64)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 (0xA68)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 (0xA70)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 (0xA74)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 (0xA78)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 (0xB00)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 (0xB04)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 (0xB08)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 (0xB10)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 (0xB14)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 (0xB18)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 (0xB20)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 (0xB24)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 (0xB28)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 (0xB30)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 (0xB34)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 (0xB38)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 (0xB40)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 (0xB44)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 (0xB48)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 (0xB50)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 (0xB54)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 (0xB58)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 (0xB60)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 (0xB64)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 (0xB68)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 (0xB70)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 (0xB74)
|
||||
#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 (0xB78)
|
||||
#define EMC_PMACRO_IB_VREF_DQ_0 (0xBE0)
|
||||
#define EMC_PMACRO_IB_VREF_DQ_1 (0xBE4)
|
||||
#define EMC_PMACRO_IB_VREF_DQS_0 (0xBF0)
|
||||
#define EMC_PMACRO_IB_VREF_DQS_1 (0xBF4)
|
||||
#define EMC_PMACRO_DDLL_LONG_CMD_0 (0xC00)
|
||||
#define EMC_PMACRO_DDLL_LONG_CMD_1 (0xC04)
|
||||
#define EMC_PMACRO_DDLL_LONG_CMD_2 (0xC08)
|
||||
#define EMC_PMACRO_DDLL_LONG_CMD_3 (0xC0C)
|
||||
#define EMC_PMACRO_DDLL_LONG_CMD_4 (0xC10)
|
||||
#define EMC_PMACRO_DDLL_SHORT_CMD_0 (0xC20)
|
||||
#define EMC_PMACRO_DDLL_SHORT_CMD_1 (0xC24)
|
||||
#define EMC_PMACRO_DDLL_SHORT_CMD_2 (0xC28)
|
||||
#define EMC_PMACRO_CFG_PM_GLOBAL_0 (0xC30)
|
||||
#define EMC_PMACRO_VTTGEN_CTRL_0 (0xC34)
|
||||
#define EMC_PMACRO_VTTGEN_CTRL_1 (0xC38)
|
||||
#define EMC_PMACRO_BG_BIAS_CTRL_0 (0xC3C)
|
||||
#define EMC_PMACRO_PAD_CFG_CTRL (0xC40)
|
||||
#define EMC_PMACRO_ZCTRL (0xC44)
|
||||
#define EMC_PMACRO_RX_TERM (0xC48)
|
||||
#define EMC_PMACRO_CMD_TX_DRV (0xC4C)
|
||||
#define EMC_PMACRO_CMD_PAD_RX_CTRL (0xC50)
|
||||
#define EMC_PMACRO_DATA_PAD_RX_CTRL (0xC54)
|
||||
#define EMC_PMACRO_CMD_RX_TERM_MODE (0xC58)
|
||||
#define EMC_PMACRO_DATA_RX_TERM_MODE (0xC5C)
|
||||
#define EMC_PMACRO_CMD_PAD_TX_CTRL (0xC60)
|
||||
#define EMC_PMACRO_DATA_PAD_TX_CTRL (0xC64)
|
||||
#define EMC_PMACRO_COMMON_PAD_TX_CTRL (0xC68)
|
||||
#define EMC_PMACRO_DSR_VTTGEN_CTRL_0 (0xC6C)
|
||||
#define EMC_PMACRO_DQ_TX_DRV (0xC70)
|
||||
#define EMC_PMACRO_CA_TX_DRV (0xC74)
|
||||
#define EMC_PMACRO_AUTOCAL_CFG_COMMON (0xC78)
|
||||
#define EMC_PMACRO_BRICK_MAPPING_0 (0xC80)
|
||||
#define EMC_PMACRO_BRICK_MAPPING_1 (0xC84)
|
||||
#define EMC_PMACRO_BRICK_MAPPING_2 (0xC88)
|
||||
#define EMC_PMACRO_DDLL_PERIODIC_OFFSET (0xCE8)
|
||||
#define EMC_PMACRO_VTTGEN_CTRL_2 (0xCF0)
|
||||
#define EMC_PMACRO_IB_RXRT (0xCF4)
|
||||
#define EMC_PMACRO_TRAINING_CTRL_0 (0xCF8)
|
||||
#define EMC_PMACRO_TRAINING_CTRL_1 (0xCFC)
|
||||
#define EMC_PMACRO_DIG_DLL_STATUS_0 (0xD20)
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_0 (0xD40)
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_1 (0xD44)
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_2 (0xD48)
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_3 (0xD4C)
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_4 (0xD50)
|
||||
#define EMC_PMACRO_PERBIT_FGCG_CTRL_5 (0xD54)
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_0 (0xD60)
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_1 (0xD64)
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_2 (0xD68)
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_3 (0xD6C)
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_4 (0xD70)
|
||||
#define EMC_PMACRO_PERBIT_RFU_CTRL_5 (0xD74)
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_0 (0xD80)
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_1 (0xD84)
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_2 (0xD88)
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_3 (0xD8C)
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_4 (0xD90)
|
||||
#define EMC_PMACRO_PERBIT_RFU1_CTRL_5 (0xD94)
|
||||
#define EMC_TRAINING_CMD (0xE00)
|
||||
#define EMC_TRAINING_CTRL (0xE04)
|
||||
#define EMC_TRAINING_STATUS (0xE08)
|
||||
#define EMC_TRAINING_QUSE_CORS_CTRL (0xE0C)
|
||||
#define EMC_TRAINING_QUSE_FINE_CTRL (0xE10)
|
||||
#define EMC_TRAINING_QUSE_CTRL_MISC (0xE14)
|
||||
#define EMC_TRAINING_WRITE_FINE_CTRL (0xE18)
|
||||
#define EMC_TRAINING_WRITE_CTRL_MISC (0xE1C)
|
||||
#define EMC_TRAINING_WRITE_VREF_CTRL (0xE20)
|
||||
#define EMC_TRAINING_READ_FINE_CTRL (0xE24)
|
||||
#define EMC_TRAINING_READ_CTRL_MISC (0xE28)
|
||||
#define EMC_TRAINING_READ_VREF_CTRL (0xE2C)
|
||||
#define EMC_TRAINING_CA_FINE_CTRL (0xE30)
|
||||
#define EMC_TRAINING_CA_CTRL_MISC (0xE34)
|
||||
#define EMC_TRAINING_CA_CTRL_MISC1 (0xE38)
|
||||
#define EMC_TRAINING_CA_VREF_CTRL (0xE3C)
|
||||
#define EMC_TRAINING_SETTLE (0xE44)
|
||||
#define EMC_TRAINING_MPC (0xE5C)
|
||||
#define EMC_TRAINING_PATRAM_CTRL (0xE60)
|
||||
#define EMC_TRAINING_PATRAM_DQ (0xE64)
|
||||
#define EMC_TRAINING_PATRAM_DMI (0xE68)
|
||||
#define EMC_TRAINING_VREF_SETTLE (0xE6C)
|
||||
#define EMC_TRAINING_RW_OFFSET_IB_BYTE0 (0xE98)
|
||||
#define EMC_TRAINING_RW_OFFSET_IB_BYTE1 (0xE9C)
|
||||
#define EMC_TRAINING_RW_OFFSET_IB_BYTE2 (0xEA0)
|
||||
#define EMC_TRAINING_RW_OFFSET_IB_BYTE3 (0xEA4)
|
||||
#define EMC_TRAINING_RW_OFFSET_IB_MISC (0xEA8)
|
||||
#define EMC_TRAINING_RW_OFFSET_OB_BYTE0 (0xEAC)
|
||||
#define EMC_TRAINING_RW_OFFSET_OB_BYTE1 (0xEB0)
|
||||
#define EMC_TRAINING_RW_OFFSET_OB_BYTE2 (0xEB4)
|
||||
#define EMC_TRAINING_RW_OFFSET_OB_BYTE3 (0xEB8)
|
||||
#define EMC_TRAINING_RW_OFFSET_OB_MISC (0xEBC)
|
||||
#define EMC_TRAINING_OPT_CA_VREF (0xEC0)
|
||||
#define EMC_TRAINING_OPT_DQ_OB_VREF (0xEC4)
|
||||
#define EMC_TRAINING_QUSE_VREF_CTRL (0xED0)
|
||||
#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 (0xED4)
|
||||
#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 (0xED8)
|
||||
|
||||
|
||||
#define EMC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (EMC, NAME)
|
||||
#define EMC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (EMC, NAME, VALUE)
|
||||
#define EMC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (EMC, NAME, ENUM)
|
||||
#define EMC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(EMC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_EMC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (EMC, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_EMC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (EMC, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_EMC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_EMC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_EMC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (EMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(DBG_WRITE_MUX, 1, ASSEMBLY, ACTIVE);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(CFG_DYN_SELF_REF, 28, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(CFG_DRAM_ACPD, 29, NO_POWERDOWN, ACTIVE_POWERDOWN);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(ADR_CFG_EMEM_NUMDEV, 0, N1, N2);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(TIMING_CONTROL_TIMING_UPDATE, 0, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(SELF_REF_SELF_REF_CMD, 0, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(SELF_REF_ACTIVE_SELF_REF, 8, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(SELF_REF_SREF_DEV_SELECTN, 30, BOTH, DEV1, DEV0, RESERVED);
|
||||
|
||||
DEFINE_EMC_REG(MRW_OP, 0, 8);
|
||||
DEFINE_EMC_REG(MRW_MA, 16, 8);
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(MRW_CNT, 26, SHORT, LONG, EXT1, EXT2);
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(MRW_DEV_SELECTN, 30, BOTH, DEV1, DEV0, RESERVED);
|
||||
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(FBIO_CFG5_DRAM_TYPE, 0, DDR4, LPDDR4, LPDDR2, DDR2);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL, 9, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL, 10, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(AUTO_CAL_CONFIG_AUTO_CAL_START, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_EMC_REG(REQ_CTRL_STALL_ALL_READS, 0, 1);
|
||||
DEFINE_EMC_REG(REQ_CTRL_STALL_ALL_WRITES, 1, 1);
|
||||
|
||||
DEFINE_EMC_REG_TWO_BIT_ENUM(EMC_STATUS_DRAM_IN_SELF_REFRESH, 8, DISABLED, DEV0_ENABLED, DEV1_ENABLED, BOTH_ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(EMC_STATUS_DRAM_DEV0_IN_SELF_REFRESH, 8, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(EMC_STATUS_NO_OUTSTANDING_TRANSACTIONS, 2, WAITING, COMPLETED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(EMC_STATUS_TIMING_UPDATE_STALLED, 23, DONE, BUSY);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(CFG_DIG_DLL_CFG_DLL_EN, 0, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG(ZCAL_INTERVAL_LO, 0, 10);
|
||||
DEFINE_EMC_REG(ZCAL_INTERVAL_HI, 10, 14);
|
||||
|
||||
DEFINE_EMC_REG(PMC_SCRATCH3_DDR_CNTRL, 0, 19);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMC_SCRATCH3_WEAK_BIAS, 30, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(FBIO_CFG7_CH0_ENABLE, 1, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(FBIO_CFG7_CH1_ENABLE, 2, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0, 16, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1, 17, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2, 18, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3, 19, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4, 20, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5, 21, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6, 22, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7, 23, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD0, 24, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD1, 25, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD2, 26, DISABLE, ENABLE);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD3, 27, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_ENABLED, 0, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_TRAIN_QPOP, 1, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_RX_E_DIRECT_ZI, 2, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR, 3, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_0_CH0_TRAINING_DRV_DQS, 4, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_ENABLED, 0, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_TRAIN_QPOP, 1, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_RX_E_DIRECT_ZI, 2, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR, 3, DISABLED, ENABLED);
|
||||
DEFINE_EMC_REG_BIT_ENUM(PMACRO_TRAINING_CTRL_1_CH1_TRAINING_DRV_DQS, 4, DISABLED, ENABLED);
|
||||
|
||||
@@ -1,33 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define EVP_CPU_RESET_VECTOR (0x100)
|
||||
|
||||
#define EVP_COP_RESET_VECTOR (0x200)
|
||||
#define EVP_COP_UNDEF_VECTOR (0x204)
|
||||
#define EVP_COP_SWI_VECTOR (0x208)
|
||||
#define EVP_COP_PREFETCH_ABORT_VECTOR (0x20C)
|
||||
#define EVP_COP_DATA_ABORT_VECTOR (0x210)
|
||||
#define EVP_COP_RSVD_VECTOR (0x214)
|
||||
#define EVP_COP_IRQ_VECTOR (0x218)
|
||||
#define EVP_COP_FIQ_VECTOR (0x21C)
|
||||
@@ -1,83 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define FLOW_CTLR_RAM_REPAIR (0x040)
|
||||
#define FLOW_CTLR_FLOW_DBG_QUAL (0x050)
|
||||
#define FLOW_CTLR_CC4_HVC_CONTROL (0x060)
|
||||
#define FLOW_CTLR_CC4_RETENTION_CONTROL (0x064)
|
||||
#define FLOW_CTLR_CC4_HVC_RETRY (0x08C)
|
||||
#define FLOW_CTLR_L2FLUSH_CONTROL (0x094)
|
||||
#define FLOW_CTLR_BPMP_CLUSTER_CONTROL (0x098)
|
||||
|
||||
|
||||
#define FLOW_CTLR_CPU0_CSR (0x008)
|
||||
#define FLOW_CTLR_CPU1_CSR (0x018)
|
||||
#define FLOW_CTLR_CPU2_CSR (0x020)
|
||||
#define FLOW_CTLR_CPU3_CSR (0x028)
|
||||
|
||||
#define FLOW_CTLR_HALT_CPU0_EVENTS (0x000)
|
||||
#define FLOW_CTLR_HALT_CPU1_EVENTS (0x014)
|
||||
#define FLOW_CTLR_HALT_CPU2_EVENTS (0x01C)
|
||||
#define FLOW_CTLR_HALT_CPU3_EVENTS (0x024)
|
||||
#define FLOW_CTLR_HALT_COP_EVENTS (0x004)
|
||||
|
||||
#define FLOW_CTLR_CC4_CORE0_CTRL (0x06C)
|
||||
#define FLOW_CTLR_CC4_CORE1_CTRL (0x070)
|
||||
#define FLOW_CTLR_CC4_CORE2_CTRL (0x074)
|
||||
#define FLOW_CTLR_CC4_CORE3_CTRL (0x078)
|
||||
|
||||
#define FLOW_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (FLOW_CTLR, NAME)
|
||||
#define FLOW_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (FLOW_CTLR, NAME, VALUE)
|
||||
#define FLOW_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (FLOW_CTLR, NAME, ENUM)
|
||||
#define FLOW_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(FLOW_CTLR, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_FLOW_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (FLOW_CTLR, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_FLOW_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_FLOW_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_FLOW_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_FLOW_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (FLOW_CTLR, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_ENABLE, 0, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG(CPUN_CSR_WAIT_WFI_BITMAP, 8, 4);
|
||||
DEFINE_FLOW_REG_TWO_BIT_ENUM(CPUN_CSR_ENABLE_EXT, 12, POWERGATE_CPU_ONLY, POWERGATE_BOTH_CPU_NONCPU, POWERGATE_CPU_TURNOFF_CPURAIL, PG_EMULATION);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_EVENT_FLAG, 14, FALSE, TRUE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(CPUN_CSR_INTR_FLAG, 15, FALSE, TRUE);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_CPUN_EVENTS_GIC_FIQN, 8, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_CPUN_EVENTS_GIC_IRQN, 9, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_CPUN_EVENTS_LIC_FIQN, 10, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_CPUN_EVENTS_LIC_IRQN, 11, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_FLOW_REG_THREE_BIT_ENUM(HALT_CPUN_EVENTS_FLOW_MODE, 29, NONE, RUN_AND_INT, WAITEVENT, WAITEVENT_AND_INT, STOP_UNTIL_IRQ, STOP_UNTIL_EVENT_AND_IRQ, RESERVED6, RESERVED7);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(HALT_COP_EVENTS_JTAG, 28, DISABLED, ENABLED);
|
||||
DEFINE_FLOW_REG_THREE_BIT_ENUM(HALT_COP_EVENTS_MODE, 29, FLOW_MODE_NONE, FLOW_MODE_RUN_AND_INT, FLOW_MODE_STOP, FLOW_MODE_STOP_AND_INT, FLOW_MODE_STOP_UNTIL_IRQ, FLOW_MODE_STOP_UNTIL_IRQ_AND_INT, FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ, RESERVED7);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(FLOW_DBG_QUAL_FIQ2CCPLEX_ENABLE, 28, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(RAM_REPAIR_REQ, 0, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(RAM_REPAIR_STS, 1, REQUESTED, DONE);
|
||||
|
||||
DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER, 0, FAST, SLOW);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_CLUSTER_SWITCH_ENABLE, 1, DISABLE, ENABLE);
|
||||
DEFINE_FLOW_REG_BIT_ENUM(BPMP_CLUSTER_CONTROL_ACTIVE_CLUSTER_LOCK, 2, DISABLE, ENABLE);
|
||||
@@ -1,137 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define I2C_I2C_CNFG (0x000)
|
||||
#define I2C_I2C_CMD_ADDR0 (0x004)
|
||||
#define I2C_I2C_CMD_DATA1 (0x00C)
|
||||
#define I2C_I2C_STATUS (0x01C)
|
||||
#define I2C_PACKET_TRANSFER_STATUS (0x058)
|
||||
#define I2C_FIFO_CONTROL (0x05C)
|
||||
#define I2C_FIFO_STATUS (0x060)
|
||||
#define I2C_INTERRUPT_MASK_REGISTER (0x064)
|
||||
#define I2C_INTERRUPT_STATUS_REGISTER (0x068)
|
||||
#define I2C_CLK_DIVISOR_REGISTER (0x06C)
|
||||
#define I2C_BUS_CLEAR_CONFIG (0x084)
|
||||
#define I2C_BUS_CLEAR_STATUS (0x088)
|
||||
#define I2C_CONFIG_LOAD (0x08C)
|
||||
#define I2C_INTERFACE_TIMING_0 (0x094)
|
||||
#define I2C_INTERFACE_TIMING_1 (0x098)
|
||||
#define I2C_HS_INTERFACE_TIMING_0 (0x094)
|
||||
#define I2C_HS_INTERFACE_TIMING_1 (0x098)
|
||||
|
||||
#define I2C_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (I2C, NAME)
|
||||
#define I2C_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (I2C, NAME, VALUE)
|
||||
#define I2C_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (I2C, NAME, ENUM)
|
||||
#define I2C_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(I2C, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_I2C_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (I2C, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_I2C_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (I2C, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_I2C_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (I2C, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_I2C_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(I2C, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_I2C_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (I2C, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
/* I2C_CNFG */
|
||||
DEFINE_I2C_REG(I2C_CNFG_LENGTH, 1, 3);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_CMD1, 6, WRITE, READ);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_SEND, 9, NOP, GO);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_PACKET_MODE_EN, 10, NOP, GO);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_CNFG_NEW_MASTER_FSM, 11, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_THREE_BIT_ENUM(I2C_CNFG_DEBOUNCE_CNT, 12, NO_DEBOUNCE, DEBOUNCE_2T, DEBOUNCE_4T, DEBOUNCE_6T, DEBOUNCE_8T, DEBOUNCE_10T, DEBOUNCE_12T, DEBOUNCE_14T);
|
||||
|
||||
/* I2C_CMD_ADDR0 */
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_CMD_ADDR0_7BIT_RW, 0, WRITE, READ);
|
||||
DEFINE_I2C_REG(I2C_CMD_ADDR0_7BIT_ADDR, 1, 7);
|
||||
|
||||
/* I2C_STATUS */
|
||||
DEFINE_I2C_REG_FOUR_BIT_ENUM(I2C_STATUS_CMD1_STAT, 0, SL1_XFER_SUCCESSFUL, SL1_NOACK_FOR_BYTE1, SL1_NOACK_FOR_BYTE2, SL1_NOACK_FOR_BYTE3, SL1_NOACK_FOR_BYTE4, SL1_NOACK_FOR_BYTE5, SL1_NOACK_FOR_BYTE6, SL1_NOACK_FOR_BYTE7, SL1_NOACK_FOR_BYTE8, SL1_NOACK_FOR_BYTE9, SL1_NOACK_FOR_BYTE10, RESERVED11, RESERVED12, RESERVED13, RESERVED14, RESERVED15);
|
||||
DEFINE_I2C_REG_FOUR_BIT_ENUM(I2C_STATUS_CMD2_STAT, 4, SL2_XFER_SUCCESSFUL, SL2_NOACK_FOR_BYTE1, SL2_NOACK_FOR_BYTE2, SL2_NOACK_FOR_BYTE3, SL2_NOACK_FOR_BYTE4, SL2_NOACK_FOR_BYTE5, SL2_NOACK_FOR_BYTE6, SL2_NOACK_FOR_BYTE7, SL2_NOACK_FOR_BYTE8, SL2_NOACK_FOR_BYTE9, SL2_NOACK_FOR_BYTE10, RESERVED11, RESERVED12, RESERVED13, RESERVED14, RESERVED15);
|
||||
DEFINE_I2C_REG_BIT_ENUM(I2C_STATUS_BUSY, 8, NOT_BUSY, BUSY);
|
||||
|
||||
/* PACKET_TRANSFER_STATUS */
|
||||
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_CONTROLLER_BUSY, 0, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_ARB_LOST, 1, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_NOACK_FOR_DATA, 2, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(PACKET_TRANSFER_STATUS_NOACK_FOR_ADDR, 3, UNSET, SET);
|
||||
|
||||
/* FIFO_CONTROL */
|
||||
DEFINE_I2C_REG_BIT_ENUM(FIFO_CONTROL_RX_FIFO_FLUSH, 0, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(FIFO_CONTROL_TX_FIFO_FLUSH, 1, UNSET, SET);
|
||||
|
||||
DEFINE_I2C_REG_TWO_BIT_ENUM(FIFO_CONTROL_FIFO_FLUSH, 0, RX_UNSET_TX_UNSET, RX_SET_TX_UNSET, RX_UNSET_TX_SET, RX_SET_TX_SET);
|
||||
|
||||
DEFINE_I2C_REG(FIFO_CONTROL_RX_FIFO_TRIG, 2, 3);
|
||||
DEFINE_I2C_REG(FIFO_CONTROL_TX_FIFO_TRIG, 5, 3);
|
||||
|
||||
/* FIFO_STATUS */
|
||||
DEFINE_I2C_REG(FIFO_STATUS_RX_FIFO_FULL_CNT, 0, 4);
|
||||
DEFINE_I2C_REG(FIFO_STATUS_TX_FIFO_EMPTY_CNT, 4, 4);
|
||||
|
||||
/* INTERRUPT_MASK_REGISTER */
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_RFIFO_DATA_REQ_INT_EN, 0, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_TFIFO_DATA_REQ_INT_EN, 1, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_ARB_LOST_INT_EN, 2, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_NOACK_INT_EN, 3, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_RFIFO_UNF_INT_EN, 4, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_TFIFO_OVF_INT_EN, 5, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_ALL_PACKETS_XFER_COMPLETE_INT_EN, 6, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_MASK_REGISTER_PACKET_XFER_COMPLETE_INT_EN, 7, DISABLE, ENABLE);
|
||||
|
||||
/* INTERRUPT_STATUS_REGISTER */
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_RFIFO_DATA_REQ, 0, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_TFIFO_DATA_REQ, 1, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_ARB_LOST, 2, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_NOACK, 3, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_RFIFO_UNF, 4, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_TFIFO_OVF, 5, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_ALL_PACKETS_XFER_COMPLETE, 6, UNSET, SET);
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_PACKET_XFER_COMPLETE, 7, UNSET, SET);
|
||||
|
||||
DEFINE_I2C_REG_BIT_ENUM(INTERRUPT_STATUS_REGISTER_BUS_CLEAR_DONE, 11, UNSET, SET);
|
||||
|
||||
/* CLK_DIVISOR_REGISTER */
|
||||
DEFINE_I2C_REG(CLK_DIVISOR_REGISTER_HSMODE, 0, 16);
|
||||
DEFINE_I2C_REG(CLK_DIVISOR_REGISTER_STD_FAST_MODE, 16, 16);
|
||||
|
||||
/* BUS_CLEAR_CONFIG */
|
||||
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_CONFIG_BC_ENABLE, 0, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_CONFIG_BC_TERMINATE, 1, THRESHOLD, IMMEDIATE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_CONFIG_BC_STOP_COND, 2, NO_STOP, STOP);
|
||||
DEFINE_I2C_REG(BUS_CLEAR_CONFIG_BC_SCLK_THRESHOLD, 16, 8);
|
||||
|
||||
/* BUS_CLEAR_STATUS */
|
||||
DEFINE_I2C_REG_BIT_ENUM(BUS_CLEAR_STATUS_BC_STATUS, 0, NOT_CLEARED, CLEARED);
|
||||
|
||||
/* CONFIG_LOAD */
|
||||
DEFINE_I2C_REG_BIT_ENUM(CONFIG_LOAD_MSTR_CONFIG_LOAD, 0, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(CONFIG_LOAD_SLV_CONFIG_LOAD, 1, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG_BIT_ENUM(CONFIG_LOAD_TIMEOUT_CONFIG_LOAD, 2, DISABLE, ENABLE);
|
||||
DEFINE_I2C_REG(CONFIG_LOAD_RESERVED_BIT_5, 5, 1);
|
||||
|
||||
/* INTERFACE_TIMING_0 */
|
||||
DEFINE_I2C_REG(INTERFACE_TIMING_0_TLOW, 0, 6);
|
||||
DEFINE_I2C_REG(INTERFACE_TIMING_0_THIGH, 8, 6);
|
||||
|
||||
/* HS_INTERFACE_TIMING_0 */
|
||||
DEFINE_I2C_REG(HS_INTERFACE_TIMING_0_HS_TLOW, 0, 6);
|
||||
DEFINE_I2C_REG(HS_INTERFACE_TIMING_0_HS_THIGH, 8, 6);
|
||||
|
||||
@@ -1,52 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define I2S_REG(x) (0x702d1000 + x)
|
||||
|
||||
|
||||
#define I2S0_I2S_CG (0x088)
|
||||
#define I2S0_I2S_CTRL (0x0A0)
|
||||
#define I2S1_I2S_CG (0x188)
|
||||
#define I2S1_I2S_CTRL (0x1A0)
|
||||
#define I2S2_I2S_CG (0x288)
|
||||
#define I2S2_I2S_CTRL (0x2A0)
|
||||
#define I2S3_I2S_CG (0x388)
|
||||
#define I2S3_I2S_CTRL (0x3A0)
|
||||
#define I2S4_I2S_CG (0x488)
|
||||
#define I2S4_I2S_CTRL (0x4A0)
|
||||
|
||||
#define I2S_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (I2S, NAME)
|
||||
#define I2S_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (I2S, NAME, VALUE)
|
||||
#define I2S_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (I2S, NAME, ENUM)
|
||||
#define I2S_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(I2S, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_I2S_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (I2S, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_I2S_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (I2S, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_I2S_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (I2S, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_I2S_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(I2S, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_I2S_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (I2S, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
|
||||
DEFINE_I2S_REG_BIT_ENUM(I2S_CG_SLCG_ENABLE, 0, FALSE, TRUE);
|
||||
|
||||
DEFINE_I2S_REG_BIT_ENUM(I2S_CTRL_MASTER, 10, DISABLE, ENABLE);
|
||||
@@ -1,32 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define PRI_ICTLR(n) (0x60004000 + n)
|
||||
#define SEC_ICTLR(n) (0x60004100 + n)
|
||||
#define TRI_ICTLR(n) (0x60004200 + n)
|
||||
#define QUAD_ICTLR(n) (0x60004300 + n)
|
||||
#define PENTA_ICTLR(n) (0x60004400 + n)
|
||||
#define HEXA_ICTLR(n) (0x60004500 + n)
|
||||
|
||||
#define ICTLR_COP_IER_CLR (0x038)
|
||||
|
||||
@@ -1,579 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define MC_INTSTATUS (0x000)
|
||||
#define MC_INTMASK (0x004)
|
||||
#define MC_ERR_STATUS (0x008)
|
||||
#define MC_ERR_ADR (0x00C)
|
||||
#define MC_SMMU_CONFIG (0x010)
|
||||
#define MC_SMMU_PTB_ASID (0x01C)
|
||||
#define MC_SMMU_PTB_DATA (0x020)
|
||||
#define MC_SMMU_TLB_FLUSH (0x030)
|
||||
#define MC_SMMU_PTC_FLUSH_0 (0x034)
|
||||
#define MC_EMEM_CFG (0x050)
|
||||
#define MC_EMEM_ADR_CFG (0x054)
|
||||
#define MC_EMEM_ADR_CFG_DEV0 (0x058)
|
||||
#define MC_EMEM_ADR_CFG_DEV1 (0x05C)
|
||||
#define MC_EMEM_ADR_CFG_CHANNEL_MASK (0x060)
|
||||
#define MC_EMEM_ADR_CFG_BANK_MASK_0 (0x064)
|
||||
#define MC_EMEM_ADR_CFG_BANK_MASK_1 (0x068)
|
||||
#define MC_EMEM_ADR_CFG_BANK_MASK_2 (0x06C)
|
||||
#define MC_EMEM_ARB_CFG (0x090)
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ (0x094)
|
||||
#define MC_EMEM_ARB_TIMING_RCD (0x098)
|
||||
#define MC_EMEM_ARB_TIMING_RP (0x09C)
|
||||
#define MC_EMEM_ARB_TIMING_RC (0x0A0)
|
||||
#define MC_EMEM_ARB_TIMING_RAS (0x0A4)
|
||||
#define MC_EMEM_ARB_TIMING_FAW (0x0A8)
|
||||
#define MC_EMEM_ARB_TIMING_RRD (0x0AC)
|
||||
#define MC_EMEM_ARB_TIMING_RAP2PRE (0x0B0)
|
||||
#define MC_EMEM_ARB_TIMING_WAP2PRE (0x0B4)
|
||||
#define MC_EMEM_ARB_TIMING_R2R (0x0B8)
|
||||
#define MC_EMEM_ARB_TIMING_W2W (0x0BC)
|
||||
#define MC_EMEM_ARB_TIMING_R2W (0x0C0)
|
||||
#define MC_EMEM_ARB_TIMING_W2R (0x0C4)
|
||||
#define MC_EMEM_ARB_MISC2 (0x0C8)
|
||||
#define MC_EMEM_ARB_DA_TURNS (0x0D0)
|
||||
#define MC_EMEM_ARB_DA_COVERS (0x0D4)
|
||||
#define MC_EMEM_ARB_MISC0 (0x0D8)
|
||||
#define MC_EMEM_ARB_MISC1 (0x0DC)
|
||||
#define MC_EMEM_ARB_RING1_THROTTLE (0x0E0)
|
||||
#define MC_EMEM_ARB_OVERRIDE (0x0E8)
|
||||
#define MC_EMEM_ARB_RSV (0x0EC)
|
||||
#define MC_CLKEN_OVERRIDE (0x0F4)
|
||||
#define MC_TIMING_CONTROL_DBG (0x0F8)
|
||||
#define MC_TIMING_CONTROL (0x0FC)
|
||||
#define MC_CLIENT_HOTRESET_CTRL (0x200)
|
||||
#define MC_CLIENT_HOTRESET_STATUS (0x204)
|
||||
#define MC_SMMU_AFI_ASID (0x238)
|
||||
#define MC_SMMU_DC_ASID (0x240)
|
||||
#define MC_SMMU_DCB_ASID (0x244)
|
||||
#define MC_SMMU_HC_ASID (0x250)
|
||||
#define MC_SMMU_HDA_ASID (0x254)
|
||||
#define MC_SMMU_ISP2_ASID (0x258)
|
||||
#define MC_SMMU_MSENC_NVENC_ASID (0x264)
|
||||
#define MC_SMMU_NV_ASID (0x268)
|
||||
#define MC_SMMU_NV2_ASID (0x26C)
|
||||
#define MC_SMMU_PPCS_ASID (0x270)
|
||||
#define MC_SMMU_SATA_ASID (0x274)
|
||||
#define MC_SMMU_VI_ASID (0x280)
|
||||
#define MC_SMMU_VIC_ASID (0x284)
|
||||
#define MC_SMMU_XUSB_HOST_ASID (0x288)
|
||||
#define MC_SMMU_XUSB_DEV_ASID (0x28C)
|
||||
#define MC_SMMU_TSEC_ASID (0x294)
|
||||
#define MC_LATENCY_ALLOWANCE_AVPC_0 (0x2E4)
|
||||
#define MC_LATENCY_ALLOWANCE_DC_0 (0x2E8)
|
||||
#define MC_LATENCY_ALLOWANCE_DC_1 (0x2EC)
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_0 (0x2F4)
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_1 (0x2F8)
|
||||
#define MC_LATENCY_ALLOWANCE_HC_0 (0x310)
|
||||
#define MC_LATENCY_ALLOWANCE_HC_1 (0x314)
|
||||
#define MC_LATENCY_ALLOWANCE_MPCORE_0 (0x320)
|
||||
#define MC_LATENCY_ALLOWANCE_NVENC_0 (0x328)
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_0 (0x344)
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_1 (0x348)
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_0 (0x370)
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_1 (0x374)
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_0 (0x37C)
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_1 (0x380)
|
||||
#define MC_LATENCY_ALLOWANCE_TSEC_0 (0x390)
|
||||
#define MC_LATENCY_ALLOWANCE_VIC_0 (0x394)
|
||||
#define MC_LATENCY_ALLOWANCE_VI2_0 (0x398)
|
||||
#define MC_LATENCY_ALLOWANCE_GPU_0 (0x3AC)
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 (0x3B8)
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 (0x3BC)
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMC_0 (0x3C0)
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 (0x3C4)
|
||||
#define MC_LATENCY_ALLOWANCE_NVDEC_0 (0x3D8)
|
||||
#define MC_LATENCY_ALLOWANCE_GPU2_0 (0x3E8)
|
||||
#define MC_VIDEO_PROTECT_VPR_OVERRIDE (0x418)
|
||||
#define MC_DIS_PTSA_RATE (0x41C)
|
||||
#define MC_DIS_PTSA_MIN (0x420)
|
||||
#define MC_DIS_PTSA_MAX (0x424)
|
||||
#define MC_DISB_PTSA_RATE (0x428)
|
||||
#define MC_DISB_PTSA_MIN (0x42C)
|
||||
#define MC_DISB_PTSA_MAX (0x430)
|
||||
#define MC_VE_PTSA_RATE (0x434)
|
||||
#define MC_VE_PTSA_MIN (0x438)
|
||||
#define MC_VE_PTSA_MAX (0x43C)
|
||||
#define MC_MLL_MPCORER_PTSA_RATE (0x44C)
|
||||
#define MC_RING1_PTSA_RATE (0x47C)
|
||||
#define MC_RING1_PTSA_MIN (0x480)
|
||||
#define MC_RING1_PTSA_MAX (0x484)
|
||||
#define MC_PCX_PTSA_RATE (0x4AC)
|
||||
#define MC_PCX_PTSA_MIN (0x4B0)
|
||||
#define MC_PCX_PTSA_MAX (0x4B4)
|
||||
#define MC_MSE_PTSA_RATE (0x4C4)
|
||||
#define MC_MSE_PTSA_MIN (0x4C8)
|
||||
#define MC_MSE_PTSA_MAX (0x4CC)
|
||||
#define MC_AHB_PTSA_RATE (0x4DC)
|
||||
#define MC_AHB_PTSA_MIN (0x4E0)
|
||||
#define MC_AHB_PTSA_MAX (0x4E4)
|
||||
#define MC_APB_PTSA_RATE (0x4E8)
|
||||
#define MC_APB_PTSA_MIN (0x4EC)
|
||||
#define MC_APB_PTSA_MAX (0x4F0)
|
||||
#define MC_FTOP_PTSA_RATE (0x50C)
|
||||
#define MC_HOST_PTSA_RATE (0x518)
|
||||
#define MC_HOST_PTSA_MIN (0x51C)
|
||||
#define MC_HOST_PTSA_MAX (0x520)
|
||||
#define MC_USBX_PTSA_RATE (0x524)
|
||||
#define MC_USBX_PTSA_MIN (0x528)
|
||||
#define MC_USBX_PTSA_MAX (0x52C)
|
||||
#define MC_USBD_PTSA_RATE (0x530)
|
||||
#define MC_USBD_PTSA_MIN (0x534)
|
||||
#define MC_USBD_PTSA_MAX (0x538)
|
||||
#define MC_GK_PTSA_RATE (0x53C)
|
||||
#define MC_GK_PTSA_MIN (0x540)
|
||||
#define MC_GK_PTSA_MAX (0x544)
|
||||
#define MC_AUD_PTSA_RATE (0x548)
|
||||
#define MC_AUD_PTSA_MIN (0x54C)
|
||||
#define MC_AUD_PTSA_MAX (0x550)
|
||||
#define MC_VICPC_PTSA_RATE (0x554)
|
||||
#define MC_VICPC_PTSA_MIN (0x558)
|
||||
#define MC_VICPC_PTSA_MAX (0x55C)
|
||||
#define MC_JPG_PTSA_RATE (0x584)
|
||||
#define MC_JPG_PTSA_MIN (0x588)
|
||||
#define MC_JPG_PTSA_MAX (0x58C)
|
||||
#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 (0x590)
|
||||
#define MC_GK2_PTSA_RATE (0x610)
|
||||
#define MC_GK2_PTSA_MIN (0x614)
|
||||
#define MC_GK2_PTSA_MAX (0x618)
|
||||
#define MC_SDM_PTSA_RATE (0x61C)
|
||||
#define MC_SDM_PTSA_MIN (0x620)
|
||||
#define MC_SDM_PTSA_MAX (0x624)
|
||||
#define MC_HDAPC_PTSA_RATE (0x628)
|
||||
#define MC_HDAPC_PTSA_MIN (0x62C)
|
||||
#define MC_HDAPC_PTSA_MAX (0x630)
|
||||
#define MC_VIDEO_PROTECT_BOM (0x648)
|
||||
#define MC_EMEM_CFG_ACCESS_CTRL (0x664)
|
||||
#define MC_SEC_CARVEOUT_BOM (0x670)
|
||||
#define MC_SEC_CARVEOUT_SIZE_MB (0x674)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A (0x690)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB (0x694)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B (0x698)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB (0x69C)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C (0x6A0)
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB (0x6A4)
|
||||
#define MC_EMEM_ARB_TIMING_RFCPB (0x6C0)
|
||||
#define MC_EMEM_ARB_TIMING_CCDMW (0x6C4)
|
||||
#define MC_EMEM_ARB_REFPB_HP_CTRL (0x6F0)
|
||||
#define MC_EMEM_ARB_REFPB_BANK_CTRL (0x6F4)
|
||||
#define MC_UNTRANSLATED_REGION_CHECK (0x948)
|
||||
#define MC_PTSA_GRANT_DECREMENT (0x960)
|
||||
#define MC_EMEM_ARB_OVERRIDE_1 (0x968)
|
||||
#define MC_CLIENT_HOTRESET_CTRL_1 (0x970)
|
||||
#define MC_CLIENT_HOTRESET_STATUS_1 (0x974)
|
||||
#define MC_VIDEO_PROTECT_BOM_ADR_HI (0x978)
|
||||
#define MC_SMMU_PTC_FLUSH_1 (0x9B8)
|
||||
#define MC_SEC_CARVEOUT_ADR_HI (0x9D4)
|
||||
#define MC_DA_CONFIG0 (0x9DC)
|
||||
#define MC_SMMU_DC1_ASID (0xA88)
|
||||
#define MC_SMMU_SDMMC1A_ASID (0xA94)
|
||||
#define MC_SMMU_SDMMC2A_ASID (0xA98)
|
||||
#define MC_SMMU_SDMMC3A_ASID (0xA9C)
|
||||
#define MC_SMMU_SDMMC4A_ASID (0xAA0)
|
||||
#define MC_SMMU_ISP2B_ASID (0xAA4)
|
||||
#define MC_SMMU_GPU_ASID (0xAA8)
|
||||
#define MC_SMMU_GPUB_ASID (0xAAC)
|
||||
#define MC_SMMU_PPCS2_ASID (0xAB0)
|
||||
#define MC_SMMU_NVDEC_ASID (0xAB4)
|
||||
#define MC_SMMU_APE_ASID (0xAB8)
|
||||
#define MC_SMMU_SE_ASID (0xABC)
|
||||
#define MC_SMMU_NVJPG_ASID (0xAC0)
|
||||
#define MC_SMMU_HC1_ASID (0xAC4)
|
||||
#define MC_SMMU_SE1_ASID (0xAC8)
|
||||
#define MC_SMMU_AXIAP_ASID (0xACC)
|
||||
#define MC_SMMU_ETR_ASID (0xAD0)
|
||||
#define MC_SMMU_TSECB_ASID (0xAD4)
|
||||
#define MC_SMMU_TSEC1_ASID (0xAD8)
|
||||
#define MC_SMMU_TSECB1_ASID (0xADC)
|
||||
#define MC_SMMU_NVDEC1_ASID (0xAE0)
|
||||
#define MC_EMEM_ARB_DHYST_CTRL (0xBCC)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 (0xBD0)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 (0xBD4)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 (0xBD8)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 (0xBDC)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 (0xBE0)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 (0xBE4)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 (0xBE8)
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 (0xBEC)
|
||||
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS (0xC00)
|
||||
|
||||
|
||||
#define MC_SMMU_TLB_CONFIG (0x014)
|
||||
#define MC_SMMU_PTC_CONFIG (0x018)
|
||||
|
||||
#define MC_SMMU_AVPC_ASID (0x23C)
|
||||
#define MC_SMMU_PPCS1_ASID (0x298)
|
||||
|
||||
#define MC_SECURITY_CFG0 (0x070)
|
||||
#define MC_SECURITY_CFG1 (0x074)
|
||||
#define MC_SECURITY_CFG3 (0x9BC)
|
||||
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_0 (0x228)
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_1 (0x22C)
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_2 (0x230)
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_3 (0x234)
|
||||
#define MC_SMMU_TRANSLATION_ENABLE_4 (0xB98)
|
||||
|
||||
#define MC_SMMU_ASID_SECURITY (0x038)
|
||||
#define MC_SMMU_ASID_SECURITY_1 (0x03c)
|
||||
#define MC_SMMU_ASID_SECURITY_2 (0x9e0)
|
||||
#define MC_SMMU_ASID_SECURITY_3 (0x9e4)
|
||||
#define MC_SMMU_ASID_SECURITY_4 (0x9e8)
|
||||
#define MC_SMMU_ASID_SECURITY_5 (0x9ec)
|
||||
#define MC_SMMU_ASID_SECURITY_6 (0x9f0)
|
||||
#define MC_SMMU_ASID_SECURITY_7 (0x9f4)
|
||||
|
||||
#define MC_IRAM_BOM (0x65c)
|
||||
#define MC_IRAM_TOM (0x660)
|
||||
#define MC_IRAM_REG_CTRL (0x964)
|
||||
|
||||
#define MC_SEC_CARVEOUT_BOM (0x670)
|
||||
#define MC_SEC_CARVEOUT_SIZE_MB (0x674)
|
||||
#define MC_SEC_CARVEOUT_REG_CTRL (0x678)
|
||||
|
||||
#define MC_VIDEO_PROTECT_BOM (0x648)
|
||||
#define MC_VIDEO_PROTECT_SIZE_MB (0x64c)
|
||||
#define MC_VIDEO_PROTECT_REG_CTRL (0x650)
|
||||
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 (0x984)
|
||||
#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 (0x988)
|
||||
|
||||
#define MC_MTS_CARVEOUT_BOM (0x9a0)
|
||||
#define MC_MTS_CARVEOUT_SIZE_MB (0x9a4)
|
||||
#define MC_MTS_CARVEOUT_ADR_HI (0x9a8)
|
||||
#define MC_MTS_CARVEOUT_REG_CTRL (0x9ac)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT1_CFG0 (0xc08)
|
||||
#define MC_SECURITY_CARVEOUT1_BOM (0xc0c)
|
||||
#define MC_SECURITY_CARVEOUT1_BOM_HI (0xc10)
|
||||
#define MC_SECURITY_CARVEOUT1_SIZE_128KB (0xc14)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 (0xc18)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 (0xc1c)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 (0xc20)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 (0xc24)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 (0xc28)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 (0xc2c)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 (0xc30)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 (0xc34)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 (0xc38)
|
||||
#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 (0xc3c)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT2_CFG0 (0xc58)
|
||||
#define MC_SECURITY_CARVEOUT2_BOM (0xc5c)
|
||||
#define MC_SECURITY_CARVEOUT2_BOM_HI (0xc60)
|
||||
#define MC_SECURITY_CARVEOUT2_SIZE_128KB (0xc64)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 (0xc68)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 (0xc6c)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 (0xc70)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 (0xc74)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 (0xc78)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 (0xc7c)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 (0xc80)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 (0xc84)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 (0xc88)
|
||||
#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 (0xc8c)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT3_CFG0 (0xca8)
|
||||
#define MC_SECURITY_CARVEOUT3_BOM (0xcac)
|
||||
#define MC_SECURITY_CARVEOUT3_BOM_HI (0xcb0)
|
||||
#define MC_SECURITY_CARVEOUT3_SIZE_128KB (0xcb4)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 (0xcb8)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 (0xcbc)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 (0xcc0)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 (0xcc4)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 (0xcc8)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 (0xccc)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 (0xcd0)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 (0xcd4)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 (0xcd8)
|
||||
#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 (0xcdc)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT4_CFG0 (0xcf8)
|
||||
#define MC_SECURITY_CARVEOUT4_BOM (0xcfc)
|
||||
#define MC_SECURITY_CARVEOUT4_BOM_HI (0xd00)
|
||||
#define MC_SECURITY_CARVEOUT4_SIZE_128KB (0xd04)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 (0xd08)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 (0xd0c)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 (0xd10)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 (0xd14)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 (0xd18)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 (0xd1c)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 (0xd20)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 (0xd24)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 (0xd28)
|
||||
#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 (0xd2c)
|
||||
|
||||
#define MC_SECURITY_CARVEOUT5_CFG0 (0xd48)
|
||||
#define MC_SECURITY_CARVEOUT5_BOM (0xd4c)
|
||||
#define MC_SECURITY_CARVEOUT5_BOM_HI (0xd50)
|
||||
#define MC_SECURITY_CARVEOUT5_SIZE_128KB (0xd54)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 (0xd58)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 (0xd5c)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 (0xd60)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 (0xd64)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 (0xd68)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 (0xd6c)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 (0xd70)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 (0xd74)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 (0xd78)
|
||||
#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 (0xd7c)
|
||||
|
||||
#define MC_STAT_CONTROL (0x100)
|
||||
#define MC_STAT_EMC_CLOCK_LIMIT (0x108)
|
||||
#define MC_STAT_EMC_CLOCK_LIMIT_MSBS (0x10c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO (0x118)
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI (0x11c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_SPARE (0x124)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 (0x128)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 (0x12c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 (0x130)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 (0x134)
|
||||
#define MC_STAT_EMC_SET0_COUNT (0x138)
|
||||
#define MC_STAT_EMC_SET0_COUNT_MSBS (0x13c)
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO (0x158)
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI (0x15c)
|
||||
#define MC_STAT_EMC_FILTER_SET1_SPARE (0x164)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 (0x168)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 (0x16c)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 (0x170)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 (0x174)
|
||||
#define MC_STAT_EMC_SET1_COUNT (0x178)
|
||||
#define MC_STAT_EMC_SET1_COUNT_MSBS (0x17c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER (0xa20)
|
||||
#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER (0xa24)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 (0xb88)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 (0xb8c)
|
||||
#define MC_STAT_EMC_FILTER_SET0_CLIENT_5 (0xbc4)
|
||||
#define MC_STAT_EMC_FILTER_SET1_CLIENT_5 (0xbc8)
|
||||
|
||||
#define MC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MC, NAME)
|
||||
#define MC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MC, NAME, VALUE)
|
||||
#define MC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (MC, NAME, ENUM)
|
||||
#define MC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(MC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_MC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (MC, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_MC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (MC, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_MC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (MC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_MC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(MC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_MC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (MC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_CONFIG_SMMU_ENABLE, 0, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_TLB_CONFIG_TLB_ACTIVE_LINES, 0, 6);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_TLB_CONFIG_TLB_ROUND_ROBIN_ARBITRATION, 28, DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_TLB_CONFIG_TLB_HIT_UNDER_MISS, 29, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_PTC_CONFIG_PTC_INDEX_MAP, 0, 7);
|
||||
DEFINE_MC_REG(SMMU_PTC_CONFIG_PTC_REQ_LIMIT, 24, 4);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PTC_CONFIG_PTC_CACHE_ENABLE, 29, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_PTB_ASID_CURRENT_ASID, 0, 7);
|
||||
|
||||
DEFINE_MC_REG(SMMU_PTB_DATA_ASID_PDE_BASE, 0, 22);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PTB_DATA_ASID_NONSECURE, 29, DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PTB_DATA_ASID_WRITABLE, 30, DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PTB_DATA_ASID_READABLE, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_AVPC_ASID_AVPC_ASID, 0, 7);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_AVPC_ASID_AVPC_SMMU_ENABLE, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(SMMU_PPCS1_ASID_PPCS1_ASID, 0, 7);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_PPCS1_ASID_PPCS1_SMMU_ENABLE, 31, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_0, 0, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_1, 1, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_2, 2, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_3, 3, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_4, 4, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_5, 5, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_6, 6, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_7, 7, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_8, 8, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_9, 9, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_10, 10, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_11, 11, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_12, 12, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_13, 13, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_14, 14, NONSECURE, SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_SECURE_ASIDS_15, 15, NONSECURE, SECURE);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_0, 16, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_1, 17, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_2, 18, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_3, 19, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_4, 20, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_5, 21, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_6, 22, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_7, 23, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_8, 24, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_9, 25, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_10, 26, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_11, 27, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_12, 28, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_13, 29, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_14, 30, NONPROMOTING, PROMOTING);
|
||||
DEFINE_MC_REG_BIT_ENUM(SMMU_ASID_SECURITY_PROMOTING_ASIDS_15, 31, NONPROMOTING, PROMOTING);
|
||||
|
||||
DEFINE_MC_REG(SECURITY_CFG0_SECURITY_BOM, 20, 12);
|
||||
DEFINE_MC_REG(SECURITY_CFG1_SECURITY_SIZE, 0, 13);
|
||||
DEFINE_MC_REG(SECURITY_CFG3_SECURITY_BOM_HI, 0, 2);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SEC_CARVEOUT_REG_CTRL_SEC_CARVEOUT_WRITE_ACCESS, 0, ENABLED, DISABLED);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(VIDEO_PROTECT_REG_CTRL_VIDEO_PROTECT_WRITE_ACCESS, 0, ENABLED, DISABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(VIDEO_PROTECT_REG_CTRL_VIDEO_PROTECT_ALLOW_TZ_WRITE, 1, DISABLED, ENABLED);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(MTS_CARVEOUT_REG_CTRL_MTS_CARVEOUT_WRITE_ACCESS, 0, ENABLED, DISABLED);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_PROTECT_MODE, 0, LOCKBIT_SECURE, TZ_SECURE);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_LOCK_MODE, 1, UNLOCKED, LOCKED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_ADDRESS_TYPE, 2, ANY_ADDRESS, UNTRANSLATED_ONLY);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL0, 3, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL1, 4, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL2, 5, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_READ_ACCESS_LEVEL3, 6, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL0, 7, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL1, 8, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL2, 9, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_WRITE_ACCESS_LEVEL3, 10, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG(SECURITY_CARVEOUT_CFG0_APERTURE_ID, 11, 3);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL0, 14, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL1, 15, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL2, 16, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_READ_CHECK_ACCESS_LEVEL3, 17, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL0, 18, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL1, 19, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL2, 20, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_DISABLE_WRITE_CHECK_ACCESS_LEVEL3, 21, ENABLE_CHECKS, DISABLE_CHECKS);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_SEND_CFG_TO_GPU, 22, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_WR_EN, 23, DISABLED, BYPASS_CHECK);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_TZ_GLOBAL_RD_EN, 24, DISABLED, BYPASS_CHECK);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_ALLOW_APERTURE_ID_MISMATCH, 25, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_FORCE_APERTURE_ID_MATCH, 26, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(SECURITY_CARVEOUT_CFG0_IS_WPR, 27, DISABLED, ENABLED);
|
||||
|
||||
#define MC_CLIENT_ACCESS_NUM_CLIENTS 32
|
||||
|
||||
/* _ACCESS0 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_PTCR, ( 0 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0A, ( 1 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0AB, ( 2 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0B, ( 3 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0BB, ( 4 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0C, ( 5 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAY0CB, ( 6 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_AFIR, ( 14 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_AVPCARM7R, ( 15 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAYHC, ( 16 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_DISPLAYHCB, ( 17 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_HDAR, ( 21 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_HOST1XDMAR, ( 22 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_HOST1XR, ( 23 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_NVENCSRD, ( 28 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_PPCSAHBDMAR, ( 29 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_PPCSAHBSLVR, ( 30 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS0_SATAR, ( 31 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 0)), DISABLE, ENABLE);
|
||||
|
||||
/* _ACCESS1 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEBSEVR, ( 34 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEMBER, ( 35 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEMCER, ( 36 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDETPER, ( 37 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCORELPR, ( 38 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCORER, ( 39 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_NVENCSWR, ( 43 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_AFIW, ( 49 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_AVPCARM7W, ( 50 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_HDAW, ( 53 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_HOST1XW, ( 54 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCORELPW, ( 56 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_MPCOREW, ( 57 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_PPCSAHBDMAW, ( 59 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_PPCSAHBSLVW, ( 60 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_SATAW, ( 61 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEBSEVW, ( 62 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS1_VDEDBGW, ( 63 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 1)), DISABLE, ENABLE);
|
||||
|
||||
/* _ACCESS2 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_VDEMBEW, ( 64 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_VDETPMW, ( 65 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPRA, ( 68 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWA, ( 70 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWB, ( 71 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_HOSTR, ( 74 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_HOSTW, ( 75 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_DEVR, ( 76 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_XUSB_DEVW, ( 77 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPRAB, ( 78 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWAB, ( 80 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_ISPWBB, ( 81 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_TSECSRD, ( 84 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_TSECSWR, ( 85 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_A9AVPSCR, ( 86 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_A9AVPSCW, ( 87 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_GPUSRD, ( 88 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_GPUSWR, ( 89 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS2_DISPLAYT, ( 90 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 2)), DISABLE, ENABLE);
|
||||
|
||||
/* _ACCESS3 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCRA, ( 96 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCRAA, ( 97 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCR, ( 98 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCRAB, ( 99 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCWA, (100 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCWAA, (101 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCW, (102 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_SDMMCWAB, (103 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_VICSRD, (108 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_VICSWR, (109 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_VIW, (114 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_DISPLAYD, (115 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVDECSRD, (120 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVDECSWR, (121 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_APER, (122 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_APEW, (123 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVJPGSRD, (126 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS3_NVJPGSWR, (127 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 3)), DISABLE, ENABLE);
|
||||
|
||||
/* _ACCESS4 */
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_SESRD, (128 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_SESWR, (129 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_AXIAPR, (130 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_AXIAPW, (131 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_ETRR, (132 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_ETRW, (133 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_TSECRDB, (134 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_TSECWRB, (135 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_GPUSRD2, (136 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
DEFINE_MC_REG_BIT_ENUM(CLIENT_ACCESS4_GPUSWR2, (137 - (MC_CLIENT_ACCESS_NUM_CLIENTS * 4)), DISABLE, ENABLE);
|
||||
|
||||
DEFINE_MC_REG(IRAM_BOM_IRAM_BOM, 12, BITSIZEOF(u32) - 12);
|
||||
DEFINE_MC_REG(IRAM_TOM_IRAM_TOM, 12, BITSIZEOF(u32) - 12);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(IRAM_REG_CTRL_IRAM_CFG_WRITE_ACCESS, 0, ENABLED, DISABLED);
|
||||
|
||||
DEFINE_MC_REG_BIT_ENUM(UNTRANSLATED_REGION_CHECK_UNTRANSLATED_REGION_CHECK_ACCESS, 0, ENABLED, DISABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(UNTRANSLATED_REGION_CHECK_REQUIRE_UNTRANSLATED_CLIENTS_HIT_CARVEOUT, 8, DISABLED, ENABLED);
|
||||
DEFINE_MC_REG_BIT_ENUM(UNTRANSLATED_REGION_CHECK_REQUIRE_UNTRANSLATED_GPU_HIT_CARVEOUT, 9, DISABLED, ENABLED);
|
||||
@@ -1,53 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define MIPI_CAL_MIPI_CAL_CTRL (0x000)
|
||||
#define MIPI_CAL_CIL_MIPI_CAL_STATUS (0x008)
|
||||
#define MIPI_CAL_CILA_MIPI_CAL_CONFIG (0x014)
|
||||
#define MIPI_CAL_CILB_MIPI_CAL_CONFIG (0x018)
|
||||
#define MIPI_CAL_CILC_MIPI_CAL_CONFIG (0x01C)
|
||||
#define MIPI_CAL_CILD_MIPI_CAL_CONFIG (0x020)
|
||||
#define MIPI_CAL_CILE_MIPI_CAL_CONFIG (0x024)
|
||||
#define MIPI_CAL_CILF_MIPI_CAL_CONFIG (0x028)
|
||||
#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG (0x038)
|
||||
#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG (0x03C)
|
||||
#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG (0x040)
|
||||
#define MIPI_CAL_DSID_MIPI_CAL_CONFIG (0x044)
|
||||
#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 (0x058)
|
||||
#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 (0x05C)
|
||||
#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 (0x060)
|
||||
#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 (0x064)
|
||||
#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 (0x068)
|
||||
#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 (0x070)
|
||||
#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x074)
|
||||
|
||||
#define MIPI_CAL_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MIPI_CAL, NAME)
|
||||
#define MIPI_CAL_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MIPI_CAL, NAME, VALUE)
|
||||
#define MIPI_CAL_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (MIPI_CAL, NAME, ENUM)
|
||||
#define MIPI_CAL_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(MIPI_CAL, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_MIPI_CAL_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (MIPI_CAL, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_MIPI_CAL_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (MIPI_CAL, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_MIPI_CAL_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (MIPI_CAL, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_MIPI_CAL_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(MIPI_CAL, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_MIPI_CAL_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (MIPI_CAL, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
@@ -1,44 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define MSELECT(x) (0x50060000 + x)
|
||||
|
||||
#define MSELECT_CONFIG (0x000)
|
||||
|
||||
#define MSELECT_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (MSELECT, NAME)
|
||||
#define MSELECT_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (MSELECT, NAME, VALUE)
|
||||
#define MSELECT_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (MSELECT, NAME, ENUM)
|
||||
#define MSELECT_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(MSELECT, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_MSELECT_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (MSELECT, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_MSELECT_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (MSELECT, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_MSELECT_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (MSELECT, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_MSELECT_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(MSELECT, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_MSELECT_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (MSELECT, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_ERR_RESP_EN_SLAVE1, 24, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_ERR_RESP_EN_SLAVE2, 25, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE0, 27, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE1, 28, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE2, 29, DISABLE, ENABLE);
|
||||
DEFINE_MSELECT_REG_BIT_ENUM(CONFIG_WRAP_TO_INCR_SLAVE3, 30, DISABLE, ENABLE);
|
||||
@@ -1,28 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define PG_UP(x) (0x60000000 + x)
|
||||
|
||||
#define PG_UP_TAG (0x000)
|
||||
|
||||
#define PG_UP_TAG_PID_COP 0xAAAAAAAA
|
||||
@@ -1,105 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define PINMUX_AUX_SDMMC1_CLK (0x3000)
|
||||
#define PINMUX_AUX_SDMMC1_CMD (0x3004)
|
||||
#define PINMUX_AUX_SDMMC1_DAT3 (0x3008)
|
||||
#define PINMUX_AUX_SDMMC1_DAT2 (0x300C)
|
||||
#define PINMUX_AUX_SDMMC1_DAT1 (0x3010)
|
||||
#define PINMUX_AUX_SDMMC1_DAT0 (0x3014)
|
||||
|
||||
#define PINMUX_AUX_DMIC3_CLK (0x30B4)
|
||||
|
||||
#define PINMUX_AUX_GEN1_I2C_SCL (0x30BC)
|
||||
#define PINMUX_AUX_GEN1_I2C_SDA (0x30C0)
|
||||
#define PINMUX_AUX_PWR_I2C_SCL (0x30DC)
|
||||
#define PINMUX_AUX_PWR_I2C_SDA (0x30E0)
|
||||
|
||||
#define PINMUX_AUX_UART1_TX (0x30E4)
|
||||
#define PINMUX_AUX_UART1_RX (0x30E8)
|
||||
#define PINMUX_AUX_UART1_RTS (0x30EC)
|
||||
#define PINMUX_AUX_UART1_CTS (0x30F0)
|
||||
#define PINMUX_AUX_UART2_TX (0x30F4)
|
||||
#define PINMUX_AUX_UART2_RX (0x30F8)
|
||||
#define PINMUX_AUX_UART2_RTS (0x30FC)
|
||||
#define PINMUX_AUX_UART2_CTS (0x3100)
|
||||
#define PINMUX_AUX_UART3_TX (0x3104)
|
||||
#define PINMUX_AUX_UART3_RX (0x3108)
|
||||
#define PINMUX_AUX_UART3_RTS (0x310C)
|
||||
#define PINMUX_AUX_UART3_CTS (0x3110)
|
||||
#define PINMUX_AUX_DVFS_PWM (0x3184)
|
||||
#define PINMUX_AUX_NFC_EN (0x31D0)
|
||||
#define PINMUX_AUX_NFC_INT (0x31D4)
|
||||
#define PINMUX_AUX_CAM_FLASH_EN (0x31E8)
|
||||
#define PINMUX_AUX_LCD_BL_PWM (0x31FC)
|
||||
#define PINMUX_AUX_LCD_BL_EN (0x3200)
|
||||
#define PINMUX_AUX_LCD_RST (0x3204)
|
||||
#define PINMUX_AUX_GPIO_PA6 (0x3244)
|
||||
#define PINMUX_AUX_GPIO_PE6 (0x3248)
|
||||
#define PINMUX_AUX_GPIO_PH6 (0x3250)
|
||||
|
||||
|
||||
#define PINMUX_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (PINMUX, NAME)
|
||||
#define PINMUX_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (PINMUX, NAME, VALUE)
|
||||
#define PINMUX_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (PINMUX, NAME, ENUM)
|
||||
#define PINMUX_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(PINMUX, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_PINMUX_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (PINMUX, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_PINMUX_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (PINMUX, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_PINMUX_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (PINMUX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_PINMUX_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(PINMUX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_PINMUX_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (PINMUX, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_PUPD, 2, NONE, PULL_DOWN, PULL_UP, RSVD);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_TRISTATE, 4, PASSTHROUGH, TRISTATE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_PARK, 5, NORMAL, PARKED);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_INPUT, 6, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_LOCK, 7, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_LPDR, 8, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_OD, 11, DISABLE, ENABLE);
|
||||
DEFINE_PINMUX_REG_BIT_ENUM(AUX_E_SCHMT, 12, DISABLE, ENABLE);
|
||||
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_SDMMC1_CLK_PM, 0, SDMMC1, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_SDMMC1_CMD_PM, 0, SDMMC1, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_SDMMC1_DAT3_PM, 0, SDMMC1, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_SDMMC1_DAT2_PM, 0, SDMMC1, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_SDMMC1_DAT1_PM, 0, SDMMC1, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_SDMMC1_DAT0_PM, 0, SDMMC1, RSVD1, RSVD2, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_DMIC3_CLK_PM, 0, DMIC3, I2S5A, RSVD2, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GEN1_I2C_PM, 0, I2C1, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_PWR_I2C_PM, 0, I2CPMU, RSVD1, RSVD2, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_UART1_PM, 0, UARTA, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_UART2_PM, 0, UARTB, I2S4A, RSVD2, UART);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_UART3_PM, 0, UARTC, SPI4, RSVD2, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_DVFS_PWM_PM, 0, RSVD0, CLDVFS, SPI3, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_LCD_BL_PWM_PM, 0, DISPLAYA, PWM0, SOR0, RSVD3);
|
||||
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GPIO_PA6_PM, 0, SATA, RSVD1, RSVD2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GPIO_PE6_PM, 0, RSVD0, I2S5A, PWM2, RSVD3);
|
||||
DEFINE_PINMUX_REG_TWO_BIT_ENUM(AUX_GPIO_PH6_PM, 0, RSVD0, RSVD1, RSVD2, RSVD3);
|
||||
@@ -1,665 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define APBDEV_PMC_CNTRL (0x000)
|
||||
#define APBDEV_PMC_WAKE_MASK (0x00C)
|
||||
#define APBDEV_PMC_WAKE_LVL (0x010)
|
||||
#define APBDEV_PMC_WAKE_STATUS (0x014)
|
||||
#define APBDEV_PMC_DPD_PADS_ORIDE (0x01C)
|
||||
#define APBDEV_PMC_DPD_SAMPLE (0x020)
|
||||
#define APBDEV_PMC_DPD_ENABLE (0x024)
|
||||
#define APBDEV_PMC_CLAMP_STATUS (0x02C)
|
||||
#define APBDEV_PMC_PWRGATE_TOGGLE (0x030)
|
||||
#define APBDEV_PMC_REMOVE_CLAMPING_CMD (0x034)
|
||||
#define APBDEV_PMC_PWRGATE_STATUS (0x038)
|
||||
#define APBDEV_PMC_PWRGOOD_TIMER (0x03C)
|
||||
#define APBDEV_PMC_BLINK_TIMER (0x040)
|
||||
#define APBDEV_PMC_NO_IOPOWER (0x044)
|
||||
#define APBDEV_PMC_PWR_DET (0x048)
|
||||
#define APBDEV_PMC_AUTO_WAKE_LVL_MASK (0x0DC)
|
||||
#define APBDEV_PMC_WAKE_DELAY (0x0E0)
|
||||
#define APBDEV_PMC_PWR_DET_VAL (0x0E4)
|
||||
#define APBDEV_PMC_DDR_PWR (0x0E8)
|
||||
#define APBDEV_PMC_CRYPTO_OP (0x0F4)
|
||||
#define APBDEV_PMC_WAKE2_MASK (0x160)
|
||||
#define APBDEV_PMC_WAKE2_LVL (0x164)
|
||||
#define APBDEV_PMC_WAKE2_STATUS (0x168)
|
||||
#define APBDEV_PMC_AUTO_WAKE2_LVL_MASK (0x170)
|
||||
#define APBDEV_PMC_OSC_EDPD_OVER (0x1A4)
|
||||
#define APBDEV_PMC_CLK_OUT_CNTRL (0x1A8)
|
||||
#define APBDEV_PMC_RST_STATUS (0x1B4)
|
||||
#define APBDEV_PMC_IO_DPD_REQ (0x1B8)
|
||||
#define APBDEV_PMC_IO_DPD_STATUS (0x1BC)
|
||||
#define APBDEV_PMC_IO_DPD2_REQ (0x1C0)
|
||||
#define APBDEV_PMC_IO_DPD2_STATUS (0x1C4)
|
||||
#define APBDEV_PMC_SEL_DPD_TIM (0x1C8)
|
||||
#define APBDEV_PMC_VDDP_SEL (0x1CC)
|
||||
#define APBDEV_PMC_DDR_CFG (0x1D0)
|
||||
#define APBDEV_PMC_TSC_MULT (0x2B4)
|
||||
#define APBDEV_PMC_STICKY_BITS (0x2C0)
|
||||
#define APBDEV_PMC_WEAK_BIAS (0x2C8)
|
||||
#define APBDEV_PMC_REG_SHORT (0x2CC)
|
||||
#define APBDEV_PMC_GPU_RG_CNTRL (0x2D4)
|
||||
#define APBDEV_PMC_CNTRL2 (0x440)
|
||||
#define APBDEV_PMC_FUSE_CTRL (0x450)
|
||||
#define APBDEV_PMC_IO_DPD3_REQ (0x45C)
|
||||
#define APBDEV_PMC_IO_DPD3_STATUS (0x460)
|
||||
#define APBDEV_PMC_IO_DPD4_REQ (0x464)
|
||||
#define APBDEV_PMC_IO_DPD4_STATUS (0x468)
|
||||
#define APBDEV_PMC_SET_SW_CLAMP (0x47C)
|
||||
#define APBDEV_PMC_WAKE_DEBOUNCE_EN (0x4D8)
|
||||
#define APBDEV_PMC_DDR_CNTRL (0x4E4)
|
||||
|
||||
#define APBDEV_PMC_SEC_DISABLE (0x004)
|
||||
#define APBDEV_PMC_SEC_DISABLE2 (0x2C4)
|
||||
#define APBDEV_PMC_SEC_DISABLE3 (0x2D8)
|
||||
#define APBDEV_PMC_SEC_DISABLE4 (0x5B0)
|
||||
#define APBDEV_PMC_SEC_DISABLE5 (0x5B4)
|
||||
#define APBDEV_PMC_SEC_DISABLE6 (0x5B8)
|
||||
#define APBDEV_PMC_SEC_DISABLE7 (0x5BC)
|
||||
#define APBDEV_PMC_SEC_DISABLE8 (0x5C0)
|
||||
|
||||
/* Mariko. */
|
||||
#define APBDEV_PMC_TZRAM_PWR_CNTRL (0xBE8)
|
||||
#define APBDEV_PMC_TZRAM_SEC_DISABLE (0xBEC)
|
||||
#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE (0xBF0)
|
||||
|
||||
#define APBDEV_PMC_SCRATCH0 (0x050)
|
||||
#define APBDEV_PMC_SCRATCH1 (0x054)
|
||||
#define APBDEV_PMC_SCRATCH2 (0x058)
|
||||
#define APBDEV_PMC_SCRATCH3 (0x05C)
|
||||
#define APBDEV_PMC_SCRATCH4 (0x060)
|
||||
#define APBDEV_PMC_SCRATCH5 (0x064)
|
||||
#define APBDEV_PMC_SCRATCH6 (0x068)
|
||||
#define APBDEV_PMC_SCRATCH7 (0x06C)
|
||||
#define APBDEV_PMC_SCRATCH8 (0x070)
|
||||
#define APBDEV_PMC_SCRATCH9 (0x074)
|
||||
#define APBDEV_PMC_SCRATCH10 (0x078)
|
||||
#define APBDEV_PMC_SCRATCH11 (0x07C)
|
||||
#define APBDEV_PMC_SCRATCH12 (0x080)
|
||||
#define APBDEV_PMC_SCRATCH13 (0x084)
|
||||
#define APBDEV_PMC_SCRATCH14 (0x088)
|
||||
#define APBDEV_PMC_SCRATCH15 (0x08C)
|
||||
#define APBDEV_PMC_SCRATCH16 (0x090)
|
||||
#define APBDEV_PMC_SCRATCH17 (0x094)
|
||||
#define APBDEV_PMC_SCRATCH18 (0x098)
|
||||
#define APBDEV_PMC_SCRATCH19 (0x09C)
|
||||
#define APBDEV_PMC_SCRATCH20 (0x0A0)
|
||||
#define APBDEV_PMC_SCRATCH21 (0x0A4)
|
||||
#define APBDEV_PMC_SCRATCH22 (0x0A8)
|
||||
#define APBDEV_PMC_SCRATCH23 (0x0AC)
|
||||
#define APBDEV_PMC_SCRATCH24 (0x0FC)
|
||||
#define APBDEV_PMC_SCRATCH25 (0x100)
|
||||
#define APBDEV_PMC_SCRATCH26 (0x104)
|
||||
#define APBDEV_PMC_SCRATCH27 (0x108)
|
||||
#define APBDEV_PMC_SCRATCH28 (0x10C)
|
||||
#define APBDEV_PMC_SCRATCH29 (0x110)
|
||||
#define APBDEV_PMC_SCRATCH30 (0x114)
|
||||
#define APBDEV_PMC_SCRATCH31 (0x118)
|
||||
#define APBDEV_PMC_SCRATCH32 (0x11C)
|
||||
#define APBDEV_PMC_SCRATCH33 (0x120)
|
||||
#define APBDEV_PMC_SCRATCH34 (0x124)
|
||||
#define APBDEV_PMC_SCRATCH35 (0x128)
|
||||
#define APBDEV_PMC_SCRATCH36 (0x12C)
|
||||
#define APBDEV_PMC_SCRATCH37 (0x130)
|
||||
#define APBDEV_PMC_SCRATCH38 (0x134)
|
||||
#define APBDEV_PMC_SCRATCH39 (0x138)
|
||||
#define APBDEV_PMC_SCRATCH40 (0x13C)
|
||||
#define APBDEV_PMC_SCRATCH41 (0x140)
|
||||
#define APBDEV_PMC_SCRATCH42 (0x144)
|
||||
#define APBDEV_PMC_SCRATCH43 (0x22C)
|
||||
#define APBDEV_PMC_SCRATCH44 (0x230)
|
||||
#define APBDEV_PMC_SCRATCH45 (0x234)
|
||||
#define APBDEV_PMC_SCRATCH46 (0x238)
|
||||
#define APBDEV_PMC_SCRATCH47 (0x23C)
|
||||
#define APBDEV_PMC_SCRATCH48 (0x240)
|
||||
#define APBDEV_PMC_SCRATCH49 (0x244)
|
||||
#define APBDEV_PMC_SCRATCH50 (0x248)
|
||||
#define APBDEV_PMC_SCRATCH51 (0x24C)
|
||||
#define APBDEV_PMC_SCRATCH52 (0x250)
|
||||
#define APBDEV_PMC_SCRATCH53 (0x254)
|
||||
#define APBDEV_PMC_SCRATCH54 (0x258)
|
||||
#define APBDEV_PMC_SCRATCH55 (0x25C)
|
||||
#define APBDEV_PMC_SCRATCH56 (0x600)
|
||||
#define APBDEV_PMC_SCRATCH57 (0x604)
|
||||
#define APBDEV_PMC_SCRATCH58 (0x608)
|
||||
#define APBDEV_PMC_SCRATCH59 (0x60C)
|
||||
#define APBDEV_PMC_SCRATCH60 (0x610)
|
||||
#define APBDEV_PMC_SCRATCH61 (0x614)
|
||||
#define APBDEV_PMC_SCRATCH62 (0x618)
|
||||
#define APBDEV_PMC_SCRATCH63 (0x61C)
|
||||
#define APBDEV_PMC_SCRATCH64 (0x620)
|
||||
#define APBDEV_PMC_SCRATCH65 (0x624)
|
||||
#define APBDEV_PMC_SCRATCH66 (0x628)
|
||||
#define APBDEV_PMC_SCRATCH67 (0x62C)
|
||||
#define APBDEV_PMC_SCRATCH68 (0x630)
|
||||
#define APBDEV_PMC_SCRATCH69 (0x634)
|
||||
#define APBDEV_PMC_SCRATCH70 (0x638)
|
||||
#define APBDEV_PMC_SCRATCH71 (0x63C)
|
||||
#define APBDEV_PMC_SCRATCH72 (0x640)
|
||||
#define APBDEV_PMC_SCRATCH73 (0x644)
|
||||
#define APBDEV_PMC_SCRATCH74 (0x648)
|
||||
#define APBDEV_PMC_SCRATCH75 (0x64C)
|
||||
#define APBDEV_PMC_SCRATCH76 (0x650)
|
||||
#define APBDEV_PMC_SCRATCH77 (0x654)
|
||||
#define APBDEV_PMC_SCRATCH78 (0x658)
|
||||
#define APBDEV_PMC_SCRATCH79 (0x65C)
|
||||
#define APBDEV_PMC_SCRATCH80 (0x660)
|
||||
#define APBDEV_PMC_SCRATCH81 (0x664)
|
||||
#define APBDEV_PMC_SCRATCH82 (0x668)
|
||||
#define APBDEV_PMC_SCRATCH83 (0x66C)
|
||||
#define APBDEV_PMC_SCRATCH84 (0x670)
|
||||
#define APBDEV_PMC_SCRATCH85 (0x674)
|
||||
#define APBDEV_PMC_SCRATCH86 (0x678)
|
||||
#define APBDEV_PMC_SCRATCH87 (0x67C)
|
||||
#define APBDEV_PMC_SCRATCH88 (0x680)
|
||||
#define APBDEV_PMC_SCRATCH89 (0x684)
|
||||
#define APBDEV_PMC_SCRATCH90 (0x688)
|
||||
#define APBDEV_PMC_SCRATCH91 (0x68C)
|
||||
#define APBDEV_PMC_SCRATCH92 (0x690)
|
||||
#define APBDEV_PMC_SCRATCH93 (0x694)
|
||||
#define APBDEV_PMC_SCRATCH94 (0x698)
|
||||
#define APBDEV_PMC_SCRATCH95 (0x69C)
|
||||
#define APBDEV_PMC_SCRATCH96 (0x6A0)
|
||||
#define APBDEV_PMC_SCRATCH97 (0x6A4)
|
||||
#define APBDEV_PMC_SCRATCH98 (0x6A8)
|
||||
#define APBDEV_PMC_SCRATCH99 (0x6AC)
|
||||
#define APBDEV_PMC_SCRATCH100 (0x6B0)
|
||||
#define APBDEV_PMC_SCRATCH101 (0x6B4)
|
||||
#define APBDEV_PMC_SCRATCH102 (0x6B8)
|
||||
#define APBDEV_PMC_SCRATCH103 (0x6BC)
|
||||
#define APBDEV_PMC_SCRATCH104 (0x6C0)
|
||||
#define APBDEV_PMC_SCRATCH105 (0x6C4)
|
||||
#define APBDEV_PMC_SCRATCH106 (0x6C8)
|
||||
#define APBDEV_PMC_SCRATCH107 (0x6CC)
|
||||
#define APBDEV_PMC_SCRATCH108 (0x6D0)
|
||||
#define APBDEV_PMC_SCRATCH109 (0x6D4)
|
||||
#define APBDEV_PMC_SCRATCH110 (0x6D8)
|
||||
#define APBDEV_PMC_SCRATCH111 (0x6DC)
|
||||
#define APBDEV_PMC_SCRATCH112 (0x6E0)
|
||||
#define APBDEV_PMC_SCRATCH113 (0x6E4)
|
||||
#define APBDEV_PMC_SCRATCH114 (0x6E8)
|
||||
#define APBDEV_PMC_SCRATCH115 (0x6EC)
|
||||
#define APBDEV_PMC_SCRATCH116 (0x6F0)
|
||||
#define APBDEV_PMC_SCRATCH117 (0x6F4)
|
||||
#define APBDEV_PMC_SCRATCH118 (0x6F8)
|
||||
#define APBDEV_PMC_SCRATCH119 (0x6FC)
|
||||
#define APBDEV_PMC_SCRATCH120 (0x700)
|
||||
#define APBDEV_PMC_SCRATCH121 (0x704)
|
||||
#define APBDEV_PMC_SCRATCH122 (0x708)
|
||||
#define APBDEV_PMC_SCRATCH123 (0x70C)
|
||||
#define APBDEV_PMC_SCRATCH124 (0x710)
|
||||
#define APBDEV_PMC_SCRATCH125 (0x714)
|
||||
#define APBDEV_PMC_SCRATCH126 (0x718)
|
||||
#define APBDEV_PMC_SCRATCH127 (0x71C)
|
||||
#define APBDEV_PMC_SCRATCH128 (0x720)
|
||||
#define APBDEV_PMC_SCRATCH129 (0x724)
|
||||
#define APBDEV_PMC_SCRATCH130 (0x728)
|
||||
#define APBDEV_PMC_SCRATCH131 (0x72C)
|
||||
#define APBDEV_PMC_SCRATCH132 (0x730)
|
||||
#define APBDEV_PMC_SCRATCH133 (0x734)
|
||||
#define APBDEV_PMC_SCRATCH134 (0x738)
|
||||
#define APBDEV_PMC_SCRATCH135 (0x73C)
|
||||
#define APBDEV_PMC_SCRATCH136 (0x740)
|
||||
#define APBDEV_PMC_SCRATCH137 (0x744)
|
||||
#define APBDEV_PMC_SCRATCH138 (0x748)
|
||||
#define APBDEV_PMC_SCRATCH139 (0x74C)
|
||||
#define APBDEV_PMC_SCRATCH140 (0x750)
|
||||
#define APBDEV_PMC_SCRATCH141 (0x754)
|
||||
#define APBDEV_PMC_SCRATCH142 (0x758)
|
||||
#define APBDEV_PMC_SCRATCH143 (0x75C)
|
||||
#define APBDEV_PMC_SCRATCH144 (0x760)
|
||||
#define APBDEV_PMC_SCRATCH145 (0x764)
|
||||
#define APBDEV_PMC_SCRATCH146 (0x768)
|
||||
#define APBDEV_PMC_SCRATCH147 (0x76C)
|
||||
#define APBDEV_PMC_SCRATCH148 (0x770)
|
||||
#define APBDEV_PMC_SCRATCH149 (0x774)
|
||||
#define APBDEV_PMC_SCRATCH150 (0x778)
|
||||
#define APBDEV_PMC_SCRATCH151 (0x77C)
|
||||
#define APBDEV_PMC_SCRATCH152 (0x780)
|
||||
#define APBDEV_PMC_SCRATCH153 (0x784)
|
||||
#define APBDEV_PMC_SCRATCH154 (0x788)
|
||||
#define APBDEV_PMC_SCRATCH155 (0x78C)
|
||||
#define APBDEV_PMC_SCRATCH156 (0x790)
|
||||
#define APBDEV_PMC_SCRATCH157 (0x794)
|
||||
#define APBDEV_PMC_SCRATCH158 (0x798)
|
||||
#define APBDEV_PMC_SCRATCH159 (0x79C)
|
||||
#define APBDEV_PMC_SCRATCH160 (0x7A0)
|
||||
#define APBDEV_PMC_SCRATCH161 (0x7A4)
|
||||
#define APBDEV_PMC_SCRATCH162 (0x7A8)
|
||||
#define APBDEV_PMC_SCRATCH163 (0x7AC)
|
||||
#define APBDEV_PMC_SCRATCH164 (0x7B0)
|
||||
#define APBDEV_PMC_SCRATCH165 (0x7B4)
|
||||
#define APBDEV_PMC_SCRATCH166 (0x7B8)
|
||||
#define APBDEV_PMC_SCRATCH167 (0x7BC)
|
||||
#define APBDEV_PMC_SCRATCH168 (0x7C0)
|
||||
#define APBDEV_PMC_SCRATCH169 (0x7C4)
|
||||
#define APBDEV_PMC_SCRATCH170 (0x7C8)
|
||||
#define APBDEV_PMC_SCRATCH171 (0x7CC)
|
||||
#define APBDEV_PMC_SCRATCH172 (0x7D0)
|
||||
#define APBDEV_PMC_SCRATCH173 (0x7D4)
|
||||
#define APBDEV_PMC_SCRATCH174 (0x7D8)
|
||||
#define APBDEV_PMC_SCRATCH175 (0x7DC)
|
||||
#define APBDEV_PMC_SCRATCH176 (0x7E0)
|
||||
#define APBDEV_PMC_SCRATCH177 (0x7E4)
|
||||
#define APBDEV_PMC_SCRATCH178 (0x7E8)
|
||||
#define APBDEV_PMC_SCRATCH179 (0x7EC)
|
||||
#define APBDEV_PMC_SCRATCH180 (0x7F0)
|
||||
#define APBDEV_PMC_SCRATCH181 (0x7F4)
|
||||
#define APBDEV_PMC_SCRATCH182 (0x7F8)
|
||||
#define APBDEV_PMC_SCRATCH183 (0x7FC)
|
||||
#define APBDEV_PMC_SCRATCH184 (0x800)
|
||||
#define APBDEV_PMC_SCRATCH185 (0x804)
|
||||
#define APBDEV_PMC_SCRATCH186 (0x808)
|
||||
#define APBDEV_PMC_SCRATCH187 (0x80C)
|
||||
#define APBDEV_PMC_SCRATCH188 (0x810)
|
||||
#define APBDEV_PMC_SCRATCH189 (0x814)
|
||||
#define APBDEV_PMC_SCRATCH190 (0x818)
|
||||
#define APBDEV_PMC_SCRATCH191 (0x81C)
|
||||
#define APBDEV_PMC_SCRATCH192 (0x820)
|
||||
#define APBDEV_PMC_SCRATCH193 (0x824)
|
||||
#define APBDEV_PMC_SCRATCH194 (0x828)
|
||||
#define APBDEV_PMC_SCRATCH195 (0x82C)
|
||||
#define APBDEV_PMC_SCRATCH196 (0x830)
|
||||
#define APBDEV_PMC_SCRATCH197 (0x834)
|
||||
#define APBDEV_PMC_SCRATCH198 (0x838)
|
||||
#define APBDEV_PMC_SCRATCH199 (0x83C)
|
||||
#define APBDEV_PMC_SCRATCH200 (0x840)
|
||||
#define APBDEV_PMC_SCRATCH201 (0x844)
|
||||
#define APBDEV_PMC_SCRATCH202 (0x848)
|
||||
#define APBDEV_PMC_SCRATCH203 (0x84C)
|
||||
#define APBDEV_PMC_SCRATCH204 (0x850)
|
||||
#define APBDEV_PMC_SCRATCH205 (0x854)
|
||||
#define APBDEV_PMC_SCRATCH206 (0x858)
|
||||
#define APBDEV_PMC_SCRATCH207 (0x85C)
|
||||
#define APBDEV_PMC_SCRATCH208 (0x860)
|
||||
#define APBDEV_PMC_SCRATCH209 (0x864)
|
||||
#define APBDEV_PMC_SCRATCH210 (0x868)
|
||||
#define APBDEV_PMC_SCRATCH211 (0x86C)
|
||||
#define APBDEV_PMC_SCRATCH212 (0x870)
|
||||
#define APBDEV_PMC_SCRATCH213 (0x874)
|
||||
#define APBDEV_PMC_SCRATCH214 (0x878)
|
||||
#define APBDEV_PMC_SCRATCH215 (0x87C)
|
||||
#define APBDEV_PMC_SCRATCH216 (0x880)
|
||||
#define APBDEV_PMC_SCRATCH217 (0x884)
|
||||
#define APBDEV_PMC_SCRATCH218 (0x888)
|
||||
#define APBDEV_PMC_SCRATCH219 (0x88C)
|
||||
#define APBDEV_PMC_SCRATCH220 (0x890)
|
||||
#define APBDEV_PMC_SCRATCH221 (0x894)
|
||||
#define APBDEV_PMC_SCRATCH222 (0x898)
|
||||
#define APBDEV_PMC_SCRATCH223 (0x89C)
|
||||
#define APBDEV_PMC_SCRATCH224 (0x8A0)
|
||||
#define APBDEV_PMC_SCRATCH225 (0x8A4)
|
||||
#define APBDEV_PMC_SCRATCH226 (0x8A8)
|
||||
#define APBDEV_PMC_SCRATCH227 (0x8AC)
|
||||
#define APBDEV_PMC_SCRATCH228 (0x8B0)
|
||||
#define APBDEV_PMC_SCRATCH229 (0x8B4)
|
||||
#define APBDEV_PMC_SCRATCH230 (0x8B8)
|
||||
#define APBDEV_PMC_SCRATCH231 (0x8BC)
|
||||
#define APBDEV_PMC_SCRATCH232 (0x8C0)
|
||||
#define APBDEV_PMC_SCRATCH233 (0x8C4)
|
||||
#define APBDEV_PMC_SCRATCH234 (0x8C8)
|
||||
#define APBDEV_PMC_SCRATCH235 (0x8CC)
|
||||
#define APBDEV_PMC_SCRATCH236 (0x8D0)
|
||||
#define APBDEV_PMC_SCRATCH237 (0x8D4)
|
||||
#define APBDEV_PMC_SCRATCH238 (0x8D8)
|
||||
#define APBDEV_PMC_SCRATCH239 (0x8DC)
|
||||
#define APBDEV_PMC_SCRATCH240 (0x8E0)
|
||||
#define APBDEV_PMC_SCRATCH241 (0x8E4)
|
||||
#define APBDEV_PMC_SCRATCH242 (0x8E8)
|
||||
#define APBDEV_PMC_SCRATCH243 (0x8EC)
|
||||
#define APBDEV_PMC_SCRATCH244 (0x8F0)
|
||||
#define APBDEV_PMC_SCRATCH245 (0x8F4)
|
||||
#define APBDEV_PMC_SCRATCH246 (0x8F8)
|
||||
#define APBDEV_PMC_SCRATCH247 (0x8FC)
|
||||
#define APBDEV_PMC_SCRATCH248 (0x900)
|
||||
#define APBDEV_PMC_SCRATCH249 (0x904)
|
||||
#define APBDEV_PMC_SCRATCH250 (0x908)
|
||||
#define APBDEV_PMC_SCRATCH251 (0x90C)
|
||||
#define APBDEV_PMC_SCRATCH252 (0x910)
|
||||
#define APBDEV_PMC_SCRATCH253 (0x914)
|
||||
#define APBDEV_PMC_SCRATCH254 (0x918)
|
||||
#define APBDEV_PMC_SCRATCH255 (0x91C)
|
||||
#define APBDEV_PMC_SCRATCH256 (0x920)
|
||||
#define APBDEV_PMC_SCRATCH257 (0x924)
|
||||
#define APBDEV_PMC_SCRATCH258 (0x928)
|
||||
#define APBDEV_PMC_SCRATCH259 (0x92C)
|
||||
#define APBDEV_PMC_SCRATCH260 (0x930)
|
||||
#define APBDEV_PMC_SCRATCH261 (0x934)
|
||||
#define APBDEV_PMC_SCRATCH262 (0x938)
|
||||
#define APBDEV_PMC_SCRATCH263 (0x93C)
|
||||
#define APBDEV_PMC_SCRATCH264 (0x940)
|
||||
#define APBDEV_PMC_SCRATCH265 (0x944)
|
||||
#define APBDEV_PMC_SCRATCH266 (0x948)
|
||||
#define APBDEV_PMC_SCRATCH267 (0x94C)
|
||||
#define APBDEV_PMC_SCRATCH268 (0x950)
|
||||
#define APBDEV_PMC_SCRATCH269 (0x954)
|
||||
#define APBDEV_PMC_SCRATCH270 (0x958)
|
||||
#define APBDEV_PMC_SCRATCH271 (0x95C)
|
||||
#define APBDEV_PMC_SCRATCH272 (0x960)
|
||||
#define APBDEV_PMC_SCRATCH273 (0x964)
|
||||
#define APBDEV_PMC_SCRATCH274 (0x968)
|
||||
#define APBDEV_PMC_SCRATCH275 (0x96C)
|
||||
#define APBDEV_PMC_SCRATCH276 (0x970)
|
||||
#define APBDEV_PMC_SCRATCH277 (0x974)
|
||||
#define APBDEV_PMC_SCRATCH278 (0x978)
|
||||
#define APBDEV_PMC_SCRATCH279 (0x97C)
|
||||
#define APBDEV_PMC_SCRATCH280 (0x980)
|
||||
#define APBDEV_PMC_SCRATCH281 (0x984)
|
||||
#define APBDEV_PMC_SCRATCH282 (0x988)
|
||||
#define APBDEV_PMC_SCRATCH283 (0x98C)
|
||||
#define APBDEV_PMC_SCRATCH284 (0x990)
|
||||
#define APBDEV_PMC_SCRATCH285 (0x994)
|
||||
#define APBDEV_PMC_SCRATCH286 (0x998)
|
||||
#define APBDEV_PMC_SCRATCH287 (0x99C)
|
||||
#define APBDEV_PMC_SCRATCH288 (0x9A0)
|
||||
#define APBDEV_PMC_SCRATCH289 (0x9A4)
|
||||
#define APBDEV_PMC_SCRATCH290 (0x9A8)
|
||||
#define APBDEV_PMC_SCRATCH291 (0x9AC)
|
||||
#define APBDEV_PMC_SCRATCH292 (0x9B0)
|
||||
#define APBDEV_PMC_SCRATCH293 (0x9B4)
|
||||
#define APBDEV_PMC_SCRATCH294 (0x9B8)
|
||||
#define APBDEV_PMC_SCRATCH295 (0x9BC)
|
||||
#define APBDEV_PMC_SCRATCH296 (0x9C0)
|
||||
#define APBDEV_PMC_SCRATCH297 (0x9C4)
|
||||
#define APBDEV_PMC_SCRATCH298 (0x9C8)
|
||||
#define APBDEV_PMC_SCRATCH299 (0x9CC)
|
||||
|
||||
#define APBDEV_PMC_SECURE_SCRATCH0 (0x0B0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH1 (0x0B4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH2 (0x0B8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH3 (0x0BC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH4 (0x0C0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH5 (0x0C4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH6 (0x224)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH7 (0x228)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH8 (0x300)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH9 (0x304)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH10 (0x308)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH11 (0x30C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH12 (0x310)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH13 (0x314)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH14 (0x318)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH15 (0x31C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH16 (0x320)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH17 (0x324)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH18 (0x328)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH19 (0x32C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH20 (0x330)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH21 (0x334)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH22 (0x338)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH23 (0x33C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH24 (0x340)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH25 (0x344)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH26 (0x348)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH27 (0x34C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH28 (0x350)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH29 (0x354)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH30 (0x358)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH31 (0x35C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH32 (0x360)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH33 (0x364)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH34 (0x368)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH35 (0x36C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH36 (0x370)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH37 (0x374)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH38 (0x378)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH39 (0x37C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH40 (0x380)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH41 (0x384)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH42 (0x388)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH43 (0x38C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH44 (0x390)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH45 (0x394)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH46 (0x398)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH47 (0x39C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH48 (0x3A0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH49 (0x3A4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH50 (0x3A8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH51 (0x3AC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH52 (0x3B0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH53 (0x3B4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH54 (0x3B8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH55 (0x3BC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH56 (0x3C0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH57 (0x3C4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH58 (0x3C8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH59 (0x3CC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH60 (0x3D0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH61 (0x3D4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH62 (0x3D8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH63 (0x3DC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH64 (0x3E0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH65 (0x3E4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH66 (0x3E8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH67 (0x3EC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH68 (0x3F0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH69 (0x3F4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH70 (0x3F8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH71 (0x3FC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH72 (0x400)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH73 (0x404)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH74 (0x408)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH75 (0x40C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH76 (0x410)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH77 (0x414)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH78 (0x418)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH79 (0x41C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH80 (0xA98)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH81 (0xA9C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH82 (0xAA0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH83 (0xAA4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH84 (0xAA8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH85 (0xAAC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH86 (0xAB0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH87 (0xAB4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH88 (0xAB8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH89 (0xABC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH90 (0xAC0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH91 (0xAC4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH92 (0xAC8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH93 (0xACC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH94 (0xAD0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH95 (0xAD4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH96 (0xAD8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH97 (0xADC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH98 (0xAE0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH99 (0xAE4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH100 (0xAE8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH101 (0xAEC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH102 (0xAF0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH103 (0xAF4)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH104 (0xAF8)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH105 (0xAFC)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH106 (0xB00)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH107 (0xB04)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH108 (0xB08)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH109 (0xB0C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH110 (0xB10)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH111 (0xB14)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH112 (0xB18)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH113 (0xB1C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH114 (0xB20)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH115 (0xB24)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH116 (0xB28)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH117 (0xB2C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH118 (0xB30)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH119 (0xB34)
|
||||
|
||||
/* Mariko. */
|
||||
#define APBDEV_PMC_SECURE_SCRATCH120 (0xB38)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH121 (0xB3C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH122 (0xB40)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH123 (0xB44)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH124 (0xB68)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH125 (0xB6C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH126 (0xB70)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH127 (0xB74)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH128 (0xB78)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH129 (0xB7C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH130 (0xB80)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH131 (0xB84)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH132 (0xB88)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH133 (0xB8C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH134 (0xB90)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH135 (0xB94)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH136 (0xB98)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH137 (0xB9C)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH138 (0xBA0)
|
||||
#define APBDEV_PMC_SECURE_SCRATCH139 (0xBA4)
|
||||
|
||||
#define PMC_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (APBDEV_PMC, NAME)
|
||||
#define PMC_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (APBDEV_PMC, NAME, VALUE)
|
||||
#define PMC_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (APBDEV_PMC, NAME, ENUM)
|
||||
#define PMC_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(APBDEV_PMC, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_PMC_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (APBDEV_PMC, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_PMC_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_PMC_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_PMC_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_PMC_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (APBDEV_PMC, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(CNTRL_MAIN_RESET, 4, DISABLE, ENABLE)
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(DPD_SAMPLE_ON, 0, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_ON, 0, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(DPD_ENABLE_TSC_MULT_EN, 1, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_TOGGLE_START, 8, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG(PWRGATE_TOGGLE_PARTID, 0, 5);
|
||||
|
||||
enum APBDEV_PMC_PWRGATE_TOGGLE_PARTID : u8 {
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CRAIL = 0,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE = 2,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_PCX = 3,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_MPE = 6,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_SAX = 8,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE1 = 9,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE2 = 10,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE3 = 11,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_CE0 = 14,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_C0NC = 15,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_SOR = 17,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DIS = 18,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DISB = 19,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBA = 20,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBB = 21,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_XUSBC = 22,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VIC = 23,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_IRAM = 24,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_NVDEC = 25,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_NVJPG = 26,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_AUD = 27,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_DFD = 28,
|
||||
APBDEV_PMC_PWRGATE_TOGGLE_PARTID_VE2 = 29,
|
||||
};
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(REMOVE_CLAMPING_COMMAND_CRAIL, 0, DISABLE, ENABLE);
|
||||
|
||||
enum APBDEV_PMC_PWRGATE_STATUS_STATUS {
|
||||
APBDEV_PMC_PWRGATE_STATUS_STATUS_OFF = 0,
|
||||
APBDEV_PMC_PWRGATE_STATUS_STATUS_ON = 1,
|
||||
};
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CRAIL, 0, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE, 2, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_PCX, 3, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_MPE, 6, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_SAX, 8, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE1, 9, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE2, 10, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE3, 11, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_CE0, 14, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_C0NC, 15, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_SOR, 17, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DIS, 18, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DISB, 19, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_XUSBA, 20, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_XUSBB, 21, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_XUSBC, 22, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VIC, 23, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_IRAM, 24, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_NVDEC, 25, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_NVJPG, 26, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_AUD, 27, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_DFD, 28, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWRGATE_STATUS_VE2, 29, OFF, ON);
|
||||
|
||||
DEFINE_PMC_REG(PWRGATE_STATUS_CE123, 9, 3);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(NO_IOPOWER_SDMMC1, 12, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWR_DET_SDMMC1, 12, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(PWR_DET_VAL_SDMMC1, 12, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG(SET_SW_CLAMP_CRAIL, 0, 1);
|
||||
|
||||
DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3);
|
||||
DEFINE_PMC_REG_TWO_BIT_ENUM(IO_DPD2_REQ_CODE, 30, IDLE, DPD_OFF, DPD_ON, RESERVED3);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CRAIL, 0, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_TE, 1, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VE, 2, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_PCX, 3, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VDE, 4, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_MPE, 6, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_HEG, 7, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_SAX, 8, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE1, 9, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE2, 10, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE3, 11, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CELP, 12, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_CE0, 14, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_C0NC, 15, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_SOR, 17, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_C1NC, 16, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_DIS, 18, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_DISB, 19, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBA, 20, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBB, 21, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_XUSBC, 22, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_VIC, 23, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CLAMP_STATUS_IRAM, 24, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG(OSC_EDPD_OVER_XOFS, 1, 6);
|
||||
DEFINE_PMC_REG_BIT_ENUM(OSC_EDPD_OVER_OSC_CTRL_SELECT, 22, CAR, PMC);
|
||||
|
||||
DEFINE_PMC_REG(TSC_MULT_MULT_VAL, 0, 16);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_HDA_LPBK_DIS, 0, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(STICKY_BITS_JTAG_STS, 6, ENABLE, DISABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(CNTRL2_WAKE_DET_EN, 9, DISABLE, ENABLE);
|
||||
DEFINE_PMC_REG_BIT_ENUM(CNTRL2_HOLD_CKE_LOW_EN, 12, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(SEC_DISABLE2_WRITE21, 26, OFF, ON);
|
||||
|
||||
DEFINE_PMC_REG(TZRAM_PWR_CNTRL_TZRAM_SD, 0, 1);
|
||||
DEFINE_PMC_REG(TZRAM_PWR_CNTRL_TZRAM_SLCG_OVR, 1, 1);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(TZRAM_SEC_DISABLE_SD_WRITE, 0, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(TZRAM_SEC_DISABLE_SD_READ, 1, OFF, ON);
|
||||
|
||||
DEFINE_PMC_REG_BIT_ENUM(TZRAM_NON_SEC_DISABLE_SD_WRITE, 0, OFF, ON);
|
||||
DEFINE_PMC_REG_BIT_ENUM(TZRAM_NON_SEC_DISABLE_SD_READ, 1, OFF, ON);
|
||||
@@ -1,43 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define PWM_CONTROLLER_PWM_CHANNEL_OFFSET(channel) (0x10 * channel)
|
||||
|
||||
#define PWM_CONTROLLER_PWM_CSR (0x000)
|
||||
|
||||
|
||||
#define PWM_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (PWM_CONTROLLER, NAME)
|
||||
#define PWM_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (PWM_CONTROLLER, NAME, VALUE)
|
||||
#define PWM_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (PWM_CONTROLLER, NAME, ENUM)
|
||||
#define PWM_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(PWM_CONTROLLER, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_PWM_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (PWM_CONTROLLER, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_PWM_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (PWM_CONTROLLER, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_PWM_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (PWM_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_PWM_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(PWM_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_PWM_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (PWM_CONTROLLER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_PWM_REG(PWM_CSR_PFM, 0, 13);
|
||||
DEFINE_PWM_REG(PWM_CSR_PWM, 16, 15);
|
||||
DEFINE_PWM_REG_BIT_ENUM(PWM_CSR_ENB, 31, DISABLE, ENABLE);
|
||||
|
||||
@@ -1,52 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define SB_CSR (0x200)
|
||||
#define SB_PFCFG (0x208)
|
||||
#define SB_AA64_RESET_LOW (0x230)
|
||||
#define SB_AA64_RESET_HIGH (0x234)
|
||||
|
||||
|
||||
#define SB_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (SB, NAME)
|
||||
#define SB_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (SB, NAME, VALUE)
|
||||
#define SB_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (SB, NAME, ENUM)
|
||||
#define SB_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(SB, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_SB_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (SB, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_SB_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (SB, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_SB_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (SB, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_SB_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(SB, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_SB_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (SB, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_SECURE_BOOT_FLAG, 0, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_NS_RST_VEC_WR_DIS, 1, ENABLE, DISABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_PIROM_DISABLE, 4, ENABLE, DISABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_HANG, 6, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(CSR_SWDM_ENABLE, 7, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG(CSR_SWDM_FAIL_COUNT, 8, 4);
|
||||
DEFINE_SB_REG(CSR_COT_FAIL_COUNT, 12, 4);
|
||||
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_SPNIDEN, 0, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_SPIDEN, 1, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_NIDEN, 2, DISABLE, ENABLE);
|
||||
DEFINE_SB_REG_BIT_ENUM(PFCFG_DBGEN, 3, DISABLE, ENABLE);
|
||||
@@ -1,58 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define SYSCTR0_CNTCR (0x000)
|
||||
#define SYSCTR0_CNTCV0 (0x008)
|
||||
#define SYSCTR0_CNTCV1 (0x00C)
|
||||
#define SYSCTR0_CNTFID0 (0x020)
|
||||
#define SYSCTR0_CNTFID1 (0x024)
|
||||
|
||||
|
||||
#define SYSCTR0_COUNTERID4 (0xFD0)
|
||||
#define SYSCTR0_COUNTERID5 (0xFD4)
|
||||
#define SYSCTR0_COUNTERID6 (0xFD8)
|
||||
#define SYSCTR0_COUNTERID7 (0xFDC)
|
||||
#define SYSCTR0_COUNTERID0 (0xFE0)
|
||||
#define SYSCTR0_COUNTERID1 (0xFE4)
|
||||
#define SYSCTR0_COUNTERID2 (0xFE8)
|
||||
#define SYSCTR0_COUNTERID3 (0xFEC)
|
||||
#define SYSCTR0_COUNTERID8 (0xFF0)
|
||||
#define SYSCTR0_COUNTERID9 (0xFF4)
|
||||
#define SYSCTR0_COUNTERID10 (0xFF8)
|
||||
#define SYSCTR0_COUNTERID11 (0xFFC)
|
||||
|
||||
#define SYSCTR0_COUNTERID(n) SYSCTR0_COUNTERID##n
|
||||
|
||||
#define SYSCTR0_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (SYSCTR0, NAME)
|
||||
#define SYSCTR0_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (SYSCTR0, NAME, VALUE)
|
||||
#define SYSCTR0_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (SYSCTR0, NAME, ENUM)
|
||||
#define SYSCTR0_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(SYSCTR0, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_SYSCTR0_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (SYSCTR0, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_SYSCTR0_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (SYSCTR0, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_SYSCTR0_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (SYSCTR0, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_SYSCTR0_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(SYSCTR0, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_SYSCTR0_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (SYSCTR0, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_SYSCTR0_REG_BIT_ENUM(CNTCR_EN, 0, DISABLE, ENABLE);
|
||||
DEFINE_SYSCTR0_REG_BIT_ENUM(CNTCR_HDBG, 1, DISABLE, ENABLE);
|
||||
@@ -1,49 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) Atmosphère-NX
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
#pragma once
|
||||
#include <vapours/common.hpp>
|
||||
#include <vapours/assert.hpp>
|
||||
#include <vapours/literals.hpp>
|
||||
#include <vapours/util.hpp>
|
||||
#include <vapours/results.hpp>
|
||||
#include <vapours/reg.hpp>
|
||||
|
||||
#define TIMERUS_USEC_CFG (0x014)
|
||||
#define TIMER_SHARED_TIMER_SECURE_CFG (0x1A4)
|
||||
|
||||
#define TIMER_REG_BITS_MASK(NAME) REG_NAMED_BITS_MASK (TIMER, NAME)
|
||||
#define TIMER_REG_BITS_VALUE(NAME, VALUE) REG_NAMED_BITS_VALUE (TIMER, NAME, VALUE)
|
||||
#define TIMER_REG_BITS_ENUM(NAME, ENUM) REG_NAMED_BITS_ENUM (TIMER, NAME, ENUM)
|
||||
#define TIMER_REG_BITS_ENUM_SEL(NAME, __COND__, TRUE_ENUM, FALSE_ENUM) REG_NAMED_BITS_ENUM_SEL(TIMER, NAME, __COND__, TRUE_ENUM, FALSE_ENUM)
|
||||
|
||||
#define DEFINE_TIMER_REG(NAME, __OFFSET__, __WIDTH__) REG_DEFINE_NAMED_REG (TIMER, NAME, __OFFSET__, __WIDTH__)
|
||||
#define DEFINE_TIMER_REG_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE) REG_DEFINE_NAMED_BIT_ENUM (TIMER, NAME, __OFFSET__, ZERO, ONE)
|
||||
#define DEFINE_TIMER_REG_TWO_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE) REG_DEFINE_NAMED_TWO_BIT_ENUM (TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE)
|
||||
#define DEFINE_TIMER_REG_THREE_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN) REG_DEFINE_NAMED_THREE_BIT_ENUM(TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN)
|
||||
#define DEFINE_TIMER_REG_FOUR_BIT_ENUM(NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN) REG_DEFINE_NAMED_FOUR_BIT_ENUM (TIMER, NAME, __OFFSET__, ZERO, ONE, TWO, THREE, FOUR, FIVE, SIX, SEVEN, EIGHT, NINE, TEN, ELEVEN, TWELVE, THIRTEEN, FOURTEEN, FIFTEEN)
|
||||
|
||||
DEFINE_TIMER_REG(USEC_CFG_USEC_DIVISOR, 0, 8);
|
||||
DEFINE_TIMER_REG(USEC_CFG_USEC_DIVIDEND, 8, 8);
|
||||
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR5, 5, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR6, 6, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR7, 7, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_TMR8, 8, DISABLE, ENABLE);
|
||||
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT0, 12, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT1, 13, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT2, 14, DISABLE, ENABLE);
|
||||
DEFINE_TIMER_REG_BIT_ENUM(SHARED_TIMER_SECURE_CFG_WDT3, 15, DISABLE, ENABLE);
|
||||
Reference in New Issue
Block a user