sysclk: add live timings updates
This commit is contained in:
souldbminersmwc
@@ -38,6 +38,15 @@
|
||||
#include <display_refresh_rate.h>
|
||||
#include <stdio.h>
|
||||
#include <cstring>
|
||||
#include "emc_mc_defs.h"
|
||||
#include <notification.h>
|
||||
|
||||
#define MAX(A, B) std::max(A, B)
|
||||
#define MIN(A, B) std::min(A, B)
|
||||
#define CEIL(A) std::ceil(A)
|
||||
#define FLOOR(A) std::floor(A)
|
||||
#define ROUND(A) std::lround(A)
|
||||
|
||||
|
||||
#define FUSE_CPU_SPEEDO_0_CALIB 0x114
|
||||
//#define FUSE_CPU_SPEEDO_1_CALIB 0x12C
|
||||
@@ -875,3 +884,161 @@ std::uint32_t Board::GetVoltage(HocClkVoltage voltage)
|
||||
|
||||
return out > 0 ? out : 0;
|
||||
}
|
||||
|
||||
#define MC_REGISTER_BASE 0x70019000
|
||||
#define MC_REGISTER_REGION_SIZE 0x1000
|
||||
|
||||
#define EMC_REGISTER_BASE 0x7001b000
|
||||
#define EMC_REGISTER_REGION_SIZE 0x1000
|
||||
|
||||
#define GET_CYCLE_CEIL(PARAM) u32(CEIL(double(PARAM) / tCK_avg))
|
||||
|
||||
#define WRITE_REGISTER_EMC(TIMING_OFFSET, VALUE) \
|
||||
do { \
|
||||
args = {}; \
|
||||
args.X[0] = 0xF0000002; \
|
||||
args.X[1] = EMC_REGISTER_BASE + (TIMING_OFFSET); \
|
||||
args.X[2] = 0xFFFFFFFF; \
|
||||
args.X[3] = (VALUE); \
|
||||
svcCallSecureMonitor(&args); \
|
||||
} while (false)
|
||||
|
||||
#define WRITE_REGISTER_MC(TIMING_OFFSET, VALUE) \
|
||||
do { \
|
||||
args = {}; \
|
||||
args.X[0] = 0xF0000002; \
|
||||
args.X[1] = MC_REGISTER_BASE + (TIMING_OFFSET); \
|
||||
args.X[2] = 0xFFFFFFFF; \
|
||||
args.X[3] = (VALUE); \
|
||||
svcCallSecureMonitor(&args); \
|
||||
} while (false)
|
||||
|
||||
|
||||
// NOTE: needs patch to exosphere to expose emc region to secmon. MC does NOT need this patch
|
||||
|
||||
u32 tRCD_values[] = { 18, 17, 16, 15, 14, 13, 12, 11 };
|
||||
u32 tRP_values[] = { 18, 17, 16, 15, 14, 13, 12, 11 };
|
||||
u32 tRAS_values[] = { 42, 36, 34, 32, 30, 28, 26, 24, 22, 20 };
|
||||
double tRRD_values[] = { /*10.0,*/ 7.5, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0 }; /* 10.0 is used for <2133mhz; do we care? */
|
||||
u32 tRFC_values[] = { 140, 130, 120, 110, 100, 90, 80, 70, 60, 50, 40 };
|
||||
u32 tWTR_values[] = { 10, 9, 8, 7, 6, 5, 4, 3, 2, 1 };
|
||||
u32 tREFpb_values[] = { 3900, 5850, 7800, 11700, 15600, 99999 };
|
||||
|
||||
// Credit to Lightos for these timings!
|
||||
|
||||
|
||||
void Board::UpdateShadowRegs(u32 tRCD_i, u32 tRP_i, u32 tRAS_i, u32 tRRD_i, u32 tRFC_i, u32 tRTW_i, u32 tWTR_i, u32 tREFpb_i, u32 ramFreq, u32 rlAdd, u32 wlAdd, bool hpMode) {
|
||||
// timing stuff
|
||||
|
||||
SecmonArgs args = {};
|
||||
|
||||
constexpr double MC_ARB_DIV = 4.0;
|
||||
constexpr u32 MC_ARB_SFA = 2;
|
||||
|
||||
double tCK_avg = 1000'000.0 / ramFreq;
|
||||
u32 BL = 16;
|
||||
u32 RL = 28 + rlAdd;
|
||||
u32 WL = 14 + wlAdd;
|
||||
u32 RL_DBI = RL + 4;
|
||||
|
||||
u32 tRCD = tRCD_values[tRCD_i];
|
||||
u32 tRPpb = tRP_values[tRP_i];
|
||||
u32 tRAS = tRAS_values[tRAS_i];
|
||||
double tRRD = tRRD_values[tRRD_i];
|
||||
u32 tRFCpb = tRFC_values[tRFC_i];
|
||||
u32 tWTR = 10 - tWTR_values[tWTR_i];
|
||||
u32 tFAW = static_cast<u32>(tRRD * 4.0);
|
||||
|
||||
double tDQSCK_max = 3.5;
|
||||
u32 tWPRE = 2;
|
||||
|
||||
double tRPST = 0.5;
|
||||
|
||||
u32 tR2W = CEIL(RL_DBI + (tDQSCK_max / tCK_avg) + (BL / 2) - WL + tWPRE + FLOOR(tRPST) + 9.0) - (tRTW_i * 3);
|
||||
|
||||
u32 tRC = tRAS + tRPpb;
|
||||
u32 tRFCab = tRFCpb * 2;
|
||||
u32 tRPab = tRPpb + 3;
|
||||
|
||||
u32 tW2R = CEIL(MAX(WL + (0.010322547033278747 * (ramFreq / 1000.0)), (WL * -0.2067922202979121) + FLOOR(((RL_DBI * -0.1331159971685554) + WL) * 3.654131957826108)) - (tWTR / tCK_avg));
|
||||
|
||||
double tMMRI = tRCD + (tCK_avg * 3);
|
||||
double pdex2mrr = tMMRI + 10;
|
||||
u32 emc_cfg = hpMode ? 0x13200000 : 0xF3200000;
|
||||
|
||||
u32 refresh_raw = 0xFFFF;
|
||||
if (tREFpb_i != 6) {
|
||||
refresh_raw = CEIL(tREFpb_values[tREFpb_i] / tCK_avg) - 0x40;
|
||||
refresh_raw = MIN(refresh_raw, static_cast<u32>(0xFFFF));
|
||||
}
|
||||
|
||||
u32 trefbw = refresh_raw + 0x40;
|
||||
trefbw = MIN(trefbw, static_cast<u32>(0x3FFF));
|
||||
|
||||
u32 tR2P = 12 + (rlAdd / 2);
|
||||
u32 tW2P = (CEIL(WL * 1.7303) * 2) - 5;
|
||||
|
||||
double tXSR = (double) (tRFCab + 7.5);
|
||||
|
||||
args = {};
|
||||
args.X[0] = 0xF0000002;
|
||||
args.X[1] = EMC_REGISTER_BASE + EMC_INTSTATUS_0;
|
||||
svcCallSecureMonitor(&args);
|
||||
|
||||
if(args.X[1] == (EMC_REGISTER_BASE + EMC_INTSTATUS_0)) { // if param 1 is identical read failed, exosphere needs patch!
|
||||
writeNotification("Horizon OC\nExosphere not patched\nfor EMC r/w");
|
||||
return;
|
||||
}
|
||||
|
||||
// actually write the timings
|
||||
WRITE_REGISTER_EMC(EMC_CFG_0, emc_cfg);
|
||||
WRITE_REGISTER_EMC(EMC_RD_RCD_0, GET_CYCLE_CEIL(tRCD));
|
||||
WRITE_REGISTER_EMC(EMC_WR_RCD_0, GET_CYCLE_CEIL(tRCD));
|
||||
WRITE_REGISTER_EMC(EMC_RC_0, MIN(GET_CYCLE_CEIL(tRC), static_cast<u32>(0xB8)));
|
||||
WRITE_REGISTER_EMC(EMC_RAS_0, MIN(GET_CYCLE_CEIL(tRAS), static_cast<u32>(0x7F)));
|
||||
WRITE_REGISTER_EMC(EMC_RRD_0, GET_CYCLE_CEIL(tRRD));
|
||||
WRITE_REGISTER_EMC(EMC_RFCPB_0, GET_CYCLE_CEIL(tRFCpb));
|
||||
WRITE_REGISTER_EMC(EMC_RFC_0, GET_CYCLE_CEIL(tRFCab));
|
||||
WRITE_REGISTER_EMC(EMC_RP_0, GET_CYCLE_CEIL(tRPpb));
|
||||
WRITE_REGISTER_EMC(EMC_TRPAB_0, MIN(GET_CYCLE_CEIL(tRPab), static_cast<u32>(0x3F)));
|
||||
WRITE_REGISTER_EMC(EMC_R2W_0, tR2W);
|
||||
WRITE_REGISTER_EMC(EMC_W2R_0, tW2R);
|
||||
WRITE_REGISTER_EMC(EMC_REFRESH_0, refresh_raw);
|
||||
WRITE_REGISTER_EMC(EMC_PRE_REFRESH_REQ_CNT_0, refresh_raw / 4);
|
||||
WRITE_REGISTER_EMC(EMC_TREFBW_0, trefbw);
|
||||
WRITE_REGISTER_EMC(EMC_PDEX2MRR_0, GET_CYCLE_CEIL(pdex2mrr));
|
||||
WRITE_REGISTER_EMC(EMC_TXSR_0, MIN(GET_CYCLE_CEIL(tXSR), static_cast<u32>(0x3fe)));
|
||||
WRITE_REGISTER_EMC(EMC_TXSRDLL_0, MIN(GET_CYCLE_CEIL(tXSR), static_cast<u32>(0x3fe)));
|
||||
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_RCD_0, CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV) - 2);
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_RP_0, CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV) - 1);
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_RC_0, CEIL(GET_CYCLE_CEIL(tRC) / MC_ARB_DIV) - 1);
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_RAS_0, CEIL(GET_CYCLE_CEIL(tRAS) / MC_ARB_DIV) - 2);
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_FAW_0, CEIL(GET_CYCLE_CEIL(tFAW) / MC_ARB_DIV) - 1);
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_RRD_0, CEIL(GET_CYCLE_CEIL(tRRD) / MC_ARB_DIV) - 1);
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_RFCPB_0, CEIL(GET_CYCLE_CEIL(tRFCpb) / MC_ARB_DIV) - 1);
|
||||
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_R2W_0, CEIL(tR2W / MC_ARB_DIV) - 1 + MC_ARB_SFA);
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_W2R_0, CEIL(tW2R / MC_ARB_DIV) - 1 + MC_ARB_SFA);
|
||||
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_RAP2PRE_0, CEIL(tR2P / MC_ARB_DIV));
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_TIMING_WAP2PRE_0, CEIL(tW2P / MC_ARB_DIV) + MC_ARB_SFA);
|
||||
|
||||
u32 da_turns = 0;
|
||||
da_turns |= u8((CEIL(tR2W / MC_ARB_DIV) - 1 + MC_ARB_SFA) / 2) << 16;
|
||||
da_turns |= u8((CEIL(tW2R / MC_ARB_DIV) - 1 + MC_ARB_SFA) / 2) << 24;
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_DA_TURNS_0, da_turns);
|
||||
|
||||
u32 da_covers = 0;
|
||||
u8 r_cover = ((CEIL(tR2P / MC_ARB_DIV)) + (CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV) - 1) + (CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV) - 2)) / 2;
|
||||
u8 w_cover = ((CEIL(tW2P / MC_ARB_DIV) + MC_ARB_SFA) + (CEIL(GET_CYCLE_CEIL(tRPpb) / MC_ARB_DIV) - 1) + (CEIL(GET_CYCLE_CEIL(tRCD) / MC_ARB_DIV) - 2)) / 2;
|
||||
da_covers |= ((u32)(CEIL(GET_CYCLE_CEIL(tRC) / (u32)MC_ARB_DIV) - 1) / 2);
|
||||
da_covers |= (r_cover << 8);
|
||||
da_covers |= (w_cover << 16);
|
||||
|
||||
WRITE_REGISTER_MC(MC_EMEM_ARB_DA_COVERS_0, da_covers);
|
||||
// TODO: modify mc_emem_arb_misc0
|
||||
|
||||
WRITE_REGISTER_MC(MC_TIMING_CONTROL_0, 0x1); // update timing regs as they are shadowed
|
||||
WRITE_REGISTER_EMC(EMC_TIMING_CONTROL_0, 0x1);
|
||||
}
|
||||
|
||||
@@ -61,7 +61,7 @@ class Board
|
||||
static HorizonOCConsoleType GetConsoleType();
|
||||
static std::uint32_t GetVoltage(HocClkVoltage voltage);
|
||||
static u8 GetFanRotationLevel();
|
||||
|
||||
static void UpdateShadowRegs(u32 tRCD_i, u32 tRP_i, u32 tRAS_i, u32 tRRD_i, u32 tRFC_i, u32 tRTW_i, u32 tWTR_i, u32 tREFpb_i, u32 ramFreq, u32 rlAdd, u32 wlAdd, bool hpMode);
|
||||
protected:
|
||||
static void FetchHardwareInfos();
|
||||
static PcvModule GetPcvModule(SysClkModule sysclkModule);
|
||||
|
||||
@@ -36,6 +36,7 @@
|
||||
#include <i2c.h>
|
||||
#include "notification.h"
|
||||
#include <display_refresh_rate.h>
|
||||
#include <cstring>
|
||||
|
||||
#define HOSPPC_HAS_BOOST (hosversionAtLeast(7,0,0))
|
||||
bool isGovernorEnabled = false; // to avoid thread messes
|
||||
@@ -43,7 +44,8 @@ bool lastGovernorState = false;
|
||||
bool hasChanged = true;
|
||||
ClockManager *ClockManager::instance = NULL;
|
||||
Thread governorTHREAD;
|
||||
|
||||
u32 initialConfigValues[SysClkConfigValue_EnumMax]; // initial config. used for safety checks
|
||||
bool writeBootConfigValues = true; // do we write the initial config values?
|
||||
ClockManager *ClockManager::GetInstance()
|
||||
{
|
||||
return instance;
|
||||
@@ -85,7 +87,7 @@ ClockManager::ClockManager()
|
||||
this->lastCsvWriteNs = 0;
|
||||
|
||||
this->rnxSync = new ReverseNXSync;
|
||||
|
||||
memset(&initialConfigValues, 0, sizeof(initialConfigValues));
|
||||
if(this->config->GetConfigValue(HocClkConfigValue_KipEditing))
|
||||
this->GetKipData();
|
||||
threadCreate(
|
||||
@@ -105,7 +107,6 @@ ClockManager::ClockManager()
|
||||
this->context->speedos[HorizonOCSpeedo_CPU] = Board::getCPUSpeedo();
|
||||
this->context->speedos[HorizonOCSpeedo_GPU] = Board::getGPUSpeedo();
|
||||
this->context->speedos[HorizonOCSpeedo_SOC] = Board::getSOCSpeedo();
|
||||
|
||||
}
|
||||
|
||||
ClockManager::~ClockManager()
|
||||
@@ -372,7 +373,6 @@ void ClockManager::GovernorThread(void* arg)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void ClockManager::Tick()
|
||||
{
|
||||
std::scoped_lock lock{this->contextMutex};
|
||||
@@ -644,13 +644,13 @@ void ClockManager::SetRNXRTMode(ReverseNXMode mode)
|
||||
}
|
||||
|
||||
void ClockManager::SetKipData() {
|
||||
|
||||
if(Board::GetSocType() == SysClkSocType_Mariko) {
|
||||
if(I2c_BuckConverter_SetMvOut(&I2c_Mariko_DRAM_VDDQ, this->config->GetConfigValue(KipConfigValue_marikoEmcVddqVolt) / 1000)) {
|
||||
FileUtils::LogLine("[clock_manager] Failed set i2c vddq");
|
||||
writeNotification("Horizon OC\nFailed to write I2C\nwhile setting vddq");
|
||||
}
|
||||
}
|
||||
// TODO: figure out if this REALLY causes issues (i doubt it)
|
||||
// if(Board::GetSocType() == SysClkSocType_Mariko) {
|
||||
// if(R_FAILED(I2c_BuckConverter_SetMvOut(&I2c_Mariko_DRAM_VDDQ, this->config->GetConfigValue(KipConfigValue_marikoEmcVddqVolt) / 1000))) {
|
||||
// FileUtils::LogLine("[clock_manager] Failed set i2c vddq");
|
||||
// writeNotification("Horizon OC\nFailed to write I2C\nwhile setting vddq");
|
||||
// }
|
||||
// }
|
||||
CustomizeTable table;
|
||||
|
||||
if (!cust_read_and_cache(this->config->GetConfigValue(HocClkConfigValue_KipFileName) ? "sdmc:/atmosphere/kips/loader.kip" : "sdmc:/atmosphere/kips/hoc.kip", &table)) {
|
||||
@@ -725,16 +725,73 @@ void ClockManager::SetKipData() {
|
||||
|
||||
void ClockManager::GetKipData() {
|
||||
if(this->config->Refresh()) {
|
||||
SysClkConfigValueList configValues;
|
||||
this->config->GetConfigValues(&configValues);
|
||||
|
||||
CustomizeTable table;
|
||||
|
||||
|
||||
if (!cust_read_and_cache(this->config->GetConfigValue(HocClkConfigValue_KipFileName) ? "sdmc:/atmosphere/kips/loader.kip" : "sdmc:/atmosphere/kips/hoc.kip", &table)) {
|
||||
FileUtils::LogLine("[clock_manager] Failed to read KIP file for GetKipData");
|
||||
writeNotification("Horizon OC\nKip read failed");
|
||||
return;
|
||||
}
|
||||
|
||||
if(writeBootConfigValues) {
|
||||
writeBootConfigValues = false;
|
||||
|
||||
SysClkConfigValueList configValues;
|
||||
this->config->GetConfigValues(&configValues);
|
||||
initialConfigValues[KipConfigValue_mtcConf] = cust_get_mtc_conf(&table);
|
||||
initialConfigValues[KipConfigValue_hpMode] = cust_get_hp_mode(&table);
|
||||
|
||||
initialConfigValues[KipConfigValue_commonEmcMemVolt] = cust_get_common_emc_volt(&table);
|
||||
initialConfigValues[KipConfigValue_eristaEmcMaxClock] = cust_get_erista_emc_max(&table);
|
||||
initialConfigValues[KipConfigValue_marikoEmcMaxClock] = cust_get_mariko_emc_max(&table);
|
||||
initialConfigValues[KipConfigValue_marikoEmcVddqVolt] = cust_get_mariko_emc_vddq(&table);
|
||||
initialConfigValues[KipConfigValue_emcDvbShift] = cust_get_emc_dvb_shift(&table);
|
||||
|
||||
initialConfigValues[KipConfigValue_t1_tRCD] = cust_get_tRCD(&table);
|
||||
initialConfigValues[KipConfigValue_t2_tRP] = cust_get_tRP(&table);
|
||||
initialConfigValues[KipConfigValue_t3_tRAS] = cust_get_tRAS(&table);
|
||||
initialConfigValues[KipConfigValue_t4_tRRD] = cust_get_tRRD(&table);
|
||||
initialConfigValues[KipConfigValue_t5_tRFC] = cust_get_tRFC(&table);
|
||||
initialConfigValues[KipConfigValue_t6_tRTW] = cust_get_tRTW(&table);
|
||||
initialConfigValues[KipConfigValue_t7_tWTR] = cust_get_tWTR(&table);
|
||||
initialConfigValues[KipConfigValue_t8_tREFI] = cust_get_tREFI(&table);
|
||||
initialConfigValues[KipConfigValue_mem_burst_read_latency] = cust_get_burst_read_lat(&table);
|
||||
initialConfigValues[KipConfigValue_mem_burst_write_latency] = cust_get_burst_write_lat(&table);
|
||||
|
||||
initialConfigValues[KipConfigValue_eristaCpuUV] = cust_get_erista_cpu_uv(&table);
|
||||
initialConfigValues[KipConfigValue_eristaCpuVmin] = cust_get_eristaCpuVmin(&table);
|
||||
initialConfigValues[KipConfigValue_eristaCpuMaxVolt] = cust_get_erista_cpu_max_volt(&table);
|
||||
initialConfigValues[KipConfigValue_eristaCpuUnlock] = cust_get_eristaCpuUnlock(&table);
|
||||
|
||||
|
||||
initialConfigValues[KipConfigValue_marikoCpuUVLow] = cust_get_mariko_cpu_uv_low(&table);
|
||||
initialConfigValues[KipConfigValue_marikoCpuUVHigh] = cust_get_mariko_cpu_uv_high(&table);
|
||||
initialConfigValues[KipConfigValue_tableConf] = cust_get_table_conf(&table);
|
||||
initialConfigValues[KipConfigValue_marikoCpuLowVmin] = cust_get_mariko_cpu_low_vmin(&table);
|
||||
initialConfigValues[KipConfigValue_marikoCpuHighVmin] = cust_get_mariko_cpu_high_vmin(&table);
|
||||
initialConfigValues[KipConfigValue_marikoCpuMaxVolt] = cust_get_mariko_cpu_max_volt(&table);
|
||||
initialConfigValues[KipConfigValue_marikoGpuFullUnlock] = cust_get_marikoCpuMaxClock(&table) / 1000;
|
||||
initialConfigValues[KipConfigValue_eristaCpuBoostClock] = cust_get_erista_cpu_boost(&table) / 1000;
|
||||
initialConfigValues[KipConfigValue_marikoCpuBoostClock] = cust_get_mariko_cpu_boost(&table) / 1000;
|
||||
|
||||
initialConfigValues[KipConfigValue_eristaGpuUV] = cust_get_erista_gpu_uv(&table);
|
||||
initialConfigValues[KipConfigValue_eristaGpuVmin] = cust_get_erista_gpu_vmin(&table);
|
||||
initialConfigValues[KipConfigValue_marikoGpuUV] = cust_get_mariko_gpu_uv(&table);
|
||||
initialConfigValues[KipConfigValue_marikoGpuVmin] = cust_get_mariko_gpu_vmin(&table);
|
||||
initialConfigValues[KipConfigValue_marikoGpuVmax] = cust_get_mariko_gpu_vmax(&table);
|
||||
initialConfigValues[KipConfigValue_commonGpuVoltOffset] = cust_get_common_gpu_offset(&table);
|
||||
initialConfigValues[KipConfigValue_gpuSpeedo] = cust_get_gpu_speedo(&table);
|
||||
initialConfigValues[KipConfigValue_marikoGpuFullUnlock] = cust_get_mariko_gpu_unlock(&table);
|
||||
|
||||
for (int i = 0; i < 24; i++) {
|
||||
initialConfigValues[KipConfigValue_g_volt_76800 + i] = cust_get_mariko_gpu_volt(&table, i);
|
||||
}
|
||||
|
||||
for (int i = 0; i < 27; i++) {
|
||||
initialConfigValues[KipConfigValue_g_volt_e_76800 + i] = cust_get_erista_gpu_volt(&table, i);
|
||||
}
|
||||
}
|
||||
|
||||
configValues.values[KipConfigValue_mtcConf] = cust_get_mtc_conf(&table);
|
||||
configValues.values[KipConfigValue_hpMode] = cust_get_hp_mode(&table);
|
||||
@@ -807,4 +864,39 @@ void ClockManager::GetKipData() {
|
||||
FileUtils::LogLine("[clock_manager] Config refresh error in GetKipData!");
|
||||
writeNotification("Horizon OC\nConfig refresh failed");
|
||||
}
|
||||
}
|
||||
|
||||
void ClockManager::UpdateRamTimings() {
|
||||
if(!this->config->GetConfigValue(HocClkConfigValue_KipEditing))
|
||||
return;
|
||||
|
||||
CustomizeTable table;
|
||||
|
||||
if (!cust_read_and_cache(this->config->GetConfigValue(HocClkConfigValue_KipFileName) ? "sdmc:/atmosphere/kips/loader.kip" : "sdmc:/atmosphere/kips/hoc.kip", &table)) {
|
||||
FileUtils::LogLine("[clock_manager] Failed to read KIP file for GetKipData");
|
||||
writeNotification("Horizon OC\nKip read failed");
|
||||
return;
|
||||
}
|
||||
|
||||
if(this->config->GetConfigValue(KipConfigValue_marikoEmcMaxClock) != initialConfigValues[KipConfigValue_marikoEmcMaxClock] ||
|
||||
this->config->GetConfigValue(KipConfigValue_mem_burst_read_latency) != initialConfigValues[KipConfigValue_mem_burst_read_latency] ||
|
||||
this->config->GetConfigValue(KipConfigValue_mem_burst_write_latency) != initialConfigValues[KipConfigValue_mem_burst_write_latency]
|
||||
) {
|
||||
writeNotification("Horizon OC\nCritical values changed!\nUnable to write timings");
|
||||
return;
|
||||
}
|
||||
u32 t1_tRCD = this->config->GetConfigValue(KipConfigValue_t1_tRCD);
|
||||
u32 t2_tRP = this->config->GetConfigValue(KipConfigValue_t2_tRP);
|
||||
u32 t3_tRAS = this->config->GetConfigValue(KipConfigValue_t3_tRAS);
|
||||
u32 t4_tRRD = this->config->GetConfigValue(KipConfigValue_t4_tRRD);
|
||||
u32 t5_tRFC = this->config->GetConfigValue(KipConfigValue_t5_tRFC);
|
||||
u32 t6_tRTW = this->config->GetConfigValue(KipConfigValue_t6_tRTW);
|
||||
u32 t7_tWTR = this->config->GetConfigValue(KipConfigValue_t7_tWTR);
|
||||
u32 t8_tREFI = this->config->GetConfigValue(KipConfigValue_t8_tREFI);
|
||||
u64 ramFreq = this->config->GetConfigValue(KipConfigValue_marikoEmcMaxClock);
|
||||
u32 rlAdd = this->config->GetConfigValue(KipConfigValue_mem_burst_read_latency);
|
||||
u32 wlAdd = this->config->GetConfigValue(KipConfigValue_mem_burst_write_latency);
|
||||
bool hpMode = (bool)this->config->GetConfigValue(KipConfigValue_hpMode);
|
||||
|
||||
Board::UpdateShadowRegs(t1_tRCD, t2_tRP, t3_tRAS, t4_tRRD, t5_tRFC, t6_tRTW, t7_tWTR, t8_tREFI, ramFreq, rlAdd, wlAdd, hpMode);
|
||||
}
|
||||
@@ -62,6 +62,7 @@ class ClockManager
|
||||
void SetKipData();
|
||||
void GetKipData();
|
||||
static void GovernorThread(void* arg);
|
||||
void UpdateRamTimings();
|
||||
struct {
|
||||
std::uint32_t count;
|
||||
std::uint32_t list[SYSCLK_FREQ_LIST_MAX];
|
||||
|
||||
474
Source/sys-clk/sysmodule/src/emc_mc_defs.h
Normal file
474
Source/sys-clk/sysmodule/src/emc_mc_defs.h
Normal file
@@ -0,0 +1,474 @@
|
||||
#pragma once
|
||||
|
||||
#define EMC_INTSTATUS_0 0x0
|
||||
#define EMC_INTMASK_0 0x4
|
||||
#define EMC_DBG_0 0x8
|
||||
#define EMC_CFG_0 0xC
|
||||
#define EMC_ADR_CFG_0 0x10
|
||||
#define EMC_REFCTRL_0 0x20
|
||||
#define EMC_PIN_0 0x24
|
||||
#define EMC_TIMING_CONTROL_0 0x28
|
||||
#define EMC_RC_0 0x2C
|
||||
#define EMC_RFC_0 0x30
|
||||
#define EMC_RAS_0 0x34
|
||||
#define EMC_RP_0 0x38
|
||||
#define EMC_R2W_0 0x3C
|
||||
#define EMC_W2R_0 0x40
|
||||
#define EMC_R2P_0 0x44
|
||||
#define EMC_W2P_0 0x48
|
||||
#define EMC_RD_RCD_0 0x4C
|
||||
#define EMC_WR_RCD_0 0x50
|
||||
#define EMC_RRD_0 0x54
|
||||
#define EMC_REXT_0 0x58
|
||||
#define EMC_WDV_0 0x5C
|
||||
#define EMC_QUSE_0 0x60
|
||||
#define EMC_QRST_0 0x64
|
||||
#define EMC_QSAFE_0 0x68
|
||||
#define EMC_RDV_0 0x6C
|
||||
#define EMC_REFRESH_0 0x70
|
||||
#define EMC_BURST_REFRESH_NUM_0 0x74
|
||||
#define EMC_PDEX2WR_0 0x78
|
||||
#define EMC_PDEX2RD_0 0x7C
|
||||
#define EMC_PCHG2PDEN_0 0x80
|
||||
#define EMC_ACT2PDEN_0 0x84
|
||||
#define EMC_AR2PDEN_0 0x88
|
||||
#define EMC_RW2PDEN_0 0x8C
|
||||
#define EMC_TXSR_0 0x90
|
||||
#define EMC_TCKE_0 0x94
|
||||
#define EMC_TFAW_0 0x98
|
||||
#define EMC_TRPAB_0 0x9C
|
||||
#define EMC_TCLKSTABLE_0 0xA0
|
||||
#define EMC_TCLKSTOP_0 0xA4
|
||||
#define EMC_TREFBW_0 0xA8
|
||||
#define EMC_TPPD_0 0xAC
|
||||
#define EMC_ODT_WRITE_0 0xB0
|
||||
#define EMC_PDEX2MRR_0 0xB4
|
||||
#define EMC_WEXT_0 0xB8
|
||||
#define EMC_RFC_SLR_0 0xC0
|
||||
#define EMC_MRS_WAIT_CNT2_0 0xC4
|
||||
#define EMC_MRS_WAIT_CNT_0 0xC8
|
||||
#define EMC_MRS_0 0xCC
|
||||
#define EMC_EMRS_0 0xD0
|
||||
#define EMC_REF_0 0xD4
|
||||
#define EMC_PRE_0 0xD8
|
||||
#define EMC_NOP_0 0xDC
|
||||
#define EMC_SELF_REF_0 0xE0
|
||||
#define EMC_DPD_0 0xE4
|
||||
#define EMC_MRW_0 0xE8
|
||||
#define EMC_MRR_0 0xEC
|
||||
#define EMC_CMDQ_0 0xF0
|
||||
#define EMC_MC2EMCQ_0 0xF4
|
||||
#define EMC_FBIO_SPARE_0 0x100
|
||||
#define EMC_FBIO_CFG5_0 0x104
|
||||
#define EMC_FBIO_CFG6_0 0x114
|
||||
#define EMC_PDEX2CKE_0 0x118
|
||||
#define EMC_CKE2PDEN_0 0x11C
|
||||
#define EMC_CFG_RSV_0 0x120
|
||||
#define EMC_ACPD_CONTROL_0 0x124
|
||||
#define EMC_MPC_0 0x128
|
||||
#define EMC_EMRS2_0 0x12C
|
||||
#define EMC_EMRS3_0 0x130
|
||||
#define EMC_MRW2_0 0x134
|
||||
#define EMC_MRW3_0 0x138
|
||||
#define EMC_MRW4_0 0x13C
|
||||
#define EMC_CLKEN_OVERRIDE_0 0x140
|
||||
#define EMC_R2R_0 0x144
|
||||
#define EMC_W2W_0 0x148
|
||||
#define EMC_EINPUT_0 0x14C
|
||||
#define EMC_EINPUT_DURATION_0 0x150
|
||||
#define EMC_PUTERM_EXTRA_0 0x154
|
||||
#define EMC_TCKESR_0 0x158
|
||||
#define EMC_TPD_0 0x15C
|
||||
#define EMC_AUTO_CAL_CONFIG_0 0x2A4
|
||||
#define EMC_AUTO_CAL_INTERVAL_0 0x2A8
|
||||
#define EMC_AUTO_CAL_STATUS_0 0x2AC
|
||||
#define EMC_REQ_CTRL_0 0x2B0
|
||||
#define EMC_EMC_STATUS_0 0x2B4
|
||||
#define EMC_CFG_2_0 0x2B8
|
||||
#define EMC_CFG_DIG_DLL_0 0x2BC
|
||||
#define EMC_CFG_DIG_DLL_PERIOD_0 0x2C0
|
||||
#define EMC_DIG_DLL_STATUS_0 0x2C4
|
||||
#define EMC_CFG_DIG_DLL_1_0 0x2C8
|
||||
#define EMC_RDV_MASK_0 0x2CC
|
||||
#define EMC_WDV_MASK_0 0x2D0
|
||||
#define EMC_RDV_EARLY_MASK_0 0x2D4
|
||||
#define EMC_RDV_EARLY_0 0x2D8
|
||||
#define EMC_AUTO_CAL_CONFIG8_0 0x2DC
|
||||
#define EMC_ZCAL_INTERVAL_0 0x2E0
|
||||
#define EMC_ZCAL_WAIT_CNT_0 0x2E4
|
||||
#define EMC_ZCAL_MRW_CMD_0 0x2E8
|
||||
#define EMC_ZQ_CAL_0 0x2EC
|
||||
#define EMC_XM2COMPPADCTRL3_0 0x2F4
|
||||
#define EMC_AUTO_CAL_VREF_SEL_0_0 0x2F8
|
||||
#define EMC_AUTO_CAL_VREF_SEL_1_0 0x300
|
||||
#define EMC_XM2COMPPADCTRL_0 0x30C
|
||||
#define EMC_FDPD_CTRL_DQ_0 0x310
|
||||
#define EMC_FDPD_CTRL_CMD_0 0x314
|
||||
#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 0x318
|
||||
#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 0x31C
|
||||
#define EMC_SCRATCH0_0 0x324
|
||||
#define EMC_PMACRO_BRICK_CTRL_RFU1_0 0x330
|
||||
#define EMC_PMACRO_BRICK_CTRL_RFU2_0 0x334
|
||||
#define EMC_CMD_MAPPING_CMD0_0_0 0x380
|
||||
#define EMC_CMD_MAPPING_CMD0_1_0 0x384
|
||||
#define EMC_CMD_MAPPING_CMD0_2_0 0x388
|
||||
#define EMC_CMD_MAPPING_CMD1_0_0 0x38C
|
||||
#define EMC_CMD_MAPPING_CMD1_1_0 0x390
|
||||
#define EMC_CMD_MAPPING_CMD1_2_0 0x394
|
||||
#define EMC_CMD_MAPPING_CMD2_0_0 0x398
|
||||
#define EMC_CMD_MAPPING_CMD2_1_0 0x39C
|
||||
#define EMC_CMD_MAPPING_CMD2_2_0 0x3A0
|
||||
#define EMC_CMD_MAPPING_CMD3_0_0 0x3A4
|
||||
#define EMC_CMD_MAPPING_CMD3_1_0 0x3A8
|
||||
#define EMC_CMD_MAPPING_CMD3_2_0 0x3AC
|
||||
#define EMC_CMD_MAPPING_BYTE_0 0x3B0
|
||||
#define EMC_TR_TIMING_0_0 0x3B4
|
||||
#define EMC_TR_CTRL_0_0 0x3B8
|
||||
#define EMC_TR_CTRL_1_0 0x3BC
|
||||
#define EMC_SWITCH_BACK_CTRL_0 0x3C0
|
||||
#define EMC_TR_RDV_0 0x3C4
|
||||
#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 0x3C8
|
||||
#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 0x3CC
|
||||
#define EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 0x3D0
|
||||
#define EMC_AUTO_CAL_ 0x3D4
|
||||
#define EMC_SEL_DPD_CTRL_0 0x3D8
|
||||
#define EMC_PRE_REFRESH_REQ_CNT_0 0x3DC
|
||||
#define EMC_DYN_SELF_REF_CONTROL_0 0x3E0
|
||||
#define EMC_TXSRDLL_0 0x3E4
|
||||
#define EMC_CCFIFO_ADDR_0 0x3E8
|
||||
#define EMC_CCFIFO_DATA_0 0x3EC
|
||||
#define EMC_CCFIFO_STATUS_0 0x3F0
|
||||
#define EMC_TR_QPOP_0 0x3F4
|
||||
#define EMC_TR_RDV_MASK_0 0x3F8
|
||||
#define EMC_TR_QSAFE_0 0x3FC
|
||||
#define EMC_TR_QRST_0 0x400
|
||||
#define EMC_SWIZZLE_RANK0_BYTE0_0 0x404
|
||||
#define EMC_SWIZZLE_RANK0_BYTE1_0 0x408
|
||||
#define EMC_SWIZZLE_RANK0_BYTE2_0 0x40C
|
||||
#define EMC_SWIZZLE_RANK0_BYTE3_0 0x410
|
||||
#define EMC_SWIZZLE_RANK1_BYTE0_0 0x418
|
||||
#define EMC_SWIZZLE_RANK1_BYTE1_0 0x41C
|
||||
#define EMC_SWIZZLE_RANK1_BYTE2_0 0x420
|
||||
#define EMC_SWIZZLE_RANK1_BYTE3_0 0x424
|
||||
#define EMC_ISSUE_QRST_0 0x428
|
||||
#define EMC_PMC_SCRATCH1_0 0x440
|
||||
#define EMC_PMC_SCRATCH2_0 0x444
|
||||
#define EMC_PMC_SCRATCH3_0 0x448
|
||||
#define EMC_AUTO_CAL_CONFIG2_0 0x458
|
||||
#define EMC_AUTO_CAL_CONFIG3_0 0x45C
|
||||
#define EMC_TR_DVFS_0 0x460
|
||||
#define EMC_AUTO_CAL_CHANNEL_0 0x464
|
||||
#define EMC_IBDLY_0 0x468
|
||||
#define EMC_OBDLY_0 0x46C
|
||||
#define EMC_TXDSRVTTGEN_0 0x480
|
||||
#define EMC_WE_DURATION_0 0x48C
|
||||
#define EMC_WS_DURATION_0 0x490
|
||||
#define EMC_WEV_0 0x494
|
||||
#define EMC_WSV_0 0x498
|
||||
#define EMC_CFG_3_0 0x49C
|
||||
#define EMC_MRW5_0 0x4A0
|
||||
#define EMC_MRW6_0 0x4A4
|
||||
#define EMC_MRW7_0 0x4A8
|
||||
#define EMC_MRW8_0 0x4AC
|
||||
#define EMC_MRW9_0 0x4B0
|
||||
#define EMC_MRW10_0 0x4B4
|
||||
#define EMC_MRW11_0 0x4B8
|
||||
#define EMC_MRW12_0 0x4BC
|
||||
#define EMC_MRW13_0 0x4C0
|
||||
#define EMC_MRW14_0 0x4C4
|
||||
#define EMC_MRW15_0 0x4D0
|
||||
#define EMC_CFG_SYNC_0 0x4D4
|
||||
#define EMC_FDPD_CTRL_CMD_NO_RAMP_0 0x4D8
|
||||
#define EMC_WDV_CHK_0 0x4E0
|
||||
#define EMC_CFG_PIPE_2_0 0x554
|
||||
#define EMC_CFG_PIPE_CLK_0 0x558
|
||||
#define EMC_CFG_PIPE_1_0 0x55C
|
||||
#define EMC_CFG_PIPE_0 0x560
|
||||
#define EMC_QPOP_0 0x564
|
||||
#define EMC_QUSE_WIDTH_0 0x568
|
||||
#define EMC_PUTERM_WIDTH_0 0x56C
|
||||
#define EMC_BGBIAS_CTL0_0 0x570
|
||||
#define EMC_AUTO_CAL_CONFIG7_0 0x574
|
||||
#define EMC_XM2COMPPADCTRL2_0 0x578
|
||||
#define EMC_COMP_PAD_SW_CTRL_0 0x57C
|
||||
#define EMC_REFCTRL2_0 0x580
|
||||
#define EMC_FBIO_CFG7_0 0x584
|
||||
#define EMC_DATA_BRLSHFT_0_0 0x588
|
||||
#define EMC_DATA_BRLSHFT_1_0 0x58C
|
||||
#define EMC_RFCPB_0 0x590
|
||||
#define EMC_DQS_BRLSHFT_0_0 0x594
|
||||
#define EMC_DQS_BRLSHFT_1_0 0x598
|
||||
#define EMC_CMD_BRLSHFT_0_0 0x59C
|
||||
#define EMC_CMD_BRLSHFT_1_0 0x5A0
|
||||
#define EMC_CMD_BRLSHFT_2_0 0x5A4
|
||||
#define EMC_CMD_BRLSHFT_3_0 0x5A8
|
||||
#define EMC_QUSE_BRLSHFT_0_0 0x5AC
|
||||
#define EMC_AUTO_CAL_CONFIG4_0 0x5B0
|
||||
#define EMC_AUTO_CAL_CONFIG5_0 0x5B4
|
||||
#define EMC_QUSE_BRLSHFT_1_0 0x5B8
|
||||
#define EMC_QUSE_BRLSHFT_2_0 0x5BC
|
||||
#define EMC_CCDMW_0 0x5C0
|
||||
#define EMC_QUSE_BRLSHFT_3_0 0x5C4
|
||||
#define EMC_FBIO_CFG8_0 0x5C8
|
||||
#define EMC_AUTO_CAL_CONFIG6_0 0x5CC
|
||||
#define EMC_PROTOBIST_CONFIG_ADR_1_0 0x5D0
|
||||
#define EMC_PROTOBIST_CONFIG_ADR_2_0 0x5D4
|
||||
#define EMC_PROTOBIST_MISC_0 0x5D8
|
||||
#define EMC_PROTOBIST_WDATA_LOWER_0 0x5DC
|
||||
#define EMC_PROTOBIST_WDATA_UPPER_0 0x5E0
|
||||
#define EMC_PROTOBIST_RDATA_0 0x5EC
|
||||
#define EMC_DLL_CFG_0_0 0x5E4
|
||||
#define EMC_DLL_CFG_1_0 0x5E8
|
||||
#define EMC_CONFIG_SAMPLE_DELAY_0 0x5F0
|
||||
#define EMC_CFG_UPDATE_0 0x5F4
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_0_0 0x600
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_1_0 0x604
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_2_0 0x608
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_3_0 0x60C
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_4_0 0x610
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK0_5_0 0x614
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_0_0 0x620
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_1_0 0x624
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_2_0 0x628
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_3_0 0x62C
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_4_0 0x630
|
||||
#define EMC_PMACRO_QUSE_DDLL_RANK1_5_0 0x634
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 0x640
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 0x644
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 0x648
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 0x64C
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 0x650
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 0x654
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 0x660
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 0x664
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 0x668
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 0x66C
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 0x670
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 0x674
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 0x680
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 0x684
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 0x688
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 0x68C
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 0x690
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 0x694
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 0x6A0
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 0x6A4
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 0x6A8
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 0x6AC
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 0x6B0
|
||||
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 0x6B4
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 0x6C0
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 0x6C4
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 0x6C8
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 0x6CC
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 0x6D0
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 0x6D4
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 0x6E0
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 0x6E4
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 0x6E8
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 0x6EC
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 0x6F0
|
||||
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 0x6F4
|
||||
#define EMC_PMACRO_AUTOCAL_CFG_0_0 0x700
|
||||
#define EMC_PMACRO_AUTOCAL_CFG_1_0 0x704
|
||||
#define EMC_PMACRO_AUTOCAL_CFG_2_0 0x708
|
||||
#define EMC_PMACRO_TX_PWRD_0_0 0x720
|
||||
#define EMC_PMACRO_TX_PWRD_1_0 0x724
|
||||
#define EMC_PMACRO_TX_PWRD_2_0 0x728
|
||||
#define EMC_PMACRO_TX_PWRD_3_0 0x72C
|
||||
#define EMC_PMACRO_TX_PWRD_4_0 0x730
|
||||
#define EMC_PMACRO_TX_PWRD_5_0 0x734
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_0_0 0x740
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_1_0 0x744
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_2_0 0x748
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_3_0 0x74C
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_4_0 0x750
|
||||
#define EMC_PMACRO_TX_SEL_CLK_SRC_5_0 0x754
|
||||
#define EMC_PMACRO_DDLL_BYPASS_0 0x760
|
||||
#define EMC_PMACRO_DDLL_PWRD_0_0 0x770
|
||||
#define EMC_PMACRO_DDLL_PWRD_1_0 0x774
|
||||
#define EMC_PMACRO_DDLL_PWRD_2_0 0x778
|
||||
#define EMC_PMACRO_CMD_CTRL_0_0 0x780
|
||||
#define EMC_PMACRO_CMD_CTRL_1_0 0x784
|
||||
#define EMC_PMACRO_CMD_CTRL_2_0 0x788
|
||||
|
||||
#define MC_INTSTATUS_0 0x000
|
||||
#define MC_INTMASK_0 0x004
|
||||
#define MC_ERR_STATUS_0 0x008
|
||||
#define MC_ERR_ADR_0 0x00C
|
||||
#define MC_SMMU_CONFIG_0 0x010
|
||||
#define MC_SMMU_PTB_ASID_0 0x01C
|
||||
#define MC_SMMU_PTB_DATA_0 0x020
|
||||
#define MC_SMMU_TLB_FLUSH_0 0x030
|
||||
#define MC_SMMU_PTC_FLUSH_0_0 0x034
|
||||
#define MC_EMEM_CFG_0 0x050
|
||||
#define MC_EMEM_ADR_CFG_0 0x054
|
||||
#define MC_EMEM_ARB_CFG_0 0x090
|
||||
#define MC_EMEM_ARB_OUTSTANDING_REQ_0 0x094
|
||||
#define MC_EMEM_ARB_TIMING_RCD_0 0x098
|
||||
#define MC_EMEM_ARB_TIMING_RP_0 0x09C
|
||||
#define MC_EMEM_ARB_TIMING_RC_0 0x0A0
|
||||
#define MC_EMEM_ARB_TIMING_RAS_0 0x0A4
|
||||
#define MC_EMEM_ARB_TIMING_FAW_0 0x0A8
|
||||
#define MC_EMEM_ARB_TIMING_RRD_0 0x0AC
|
||||
#define MC_EMEM_ARB_TIMING_RAP2PRE_0 0x0B0
|
||||
#define MC_EMEM_ARB_TIMING_WAP2PRE_0 0x0B4
|
||||
#define MC_EMEM_ARB_TIMING_R2R_0 0x0B8
|
||||
#define MC_EMEM_ARB_TIMING_W2W_0 0x0BC
|
||||
#define MC_EMEM_ARB_TIMING_R2W_0 0x0C0
|
||||
#define MC_EMEM_ARB_TIMING_W2R_0 0x0C4
|
||||
#define MC_EMEM_ARB_MISC2_0 0x0C8
|
||||
#define MC_EMEM_ARB_DA_TURNS_0 0x0D0
|
||||
#define MC_EMEM_ARB_DA_COVERS_0 0x0D4
|
||||
#define MC_EMEM_ARB_MISC0_0 0x0D8
|
||||
#define MC_EMEM_ARB_MISC1_0 0x0DC
|
||||
#define MC_TIMING_CONTROL_0 0xFC
|
||||
#define MC_EMEM_ARB_RING1_THROTTLE_0 0x0E0
|
||||
#define MC_CLIENT_HOTRESET_CTRL_0 0x200
|
||||
#define MC_CLIENT_HOTRESET_STATUS_0 0x204
|
||||
#define MC_SMMU_AFI_ASID_0 0x238
|
||||
#define MC_SMMU_DC_ASID_0 0x240
|
||||
#define MC_SMMU_DCB_ASID_0 0x244
|
||||
#define MC_SMMU_HC_ASID_0 0x250
|
||||
#define MC_SMMU_HDA_ASID_0 0x254
|
||||
#define MC_SMMU_ISP2_ASID_0 0x258
|
||||
#define MC_SMMU_MSENC_NVENC_ASID_0 0x264
|
||||
#define MC_SMMU_NV_ASID_0 0x268
|
||||
#define MC_SMMU_NV2_ASID_0 0x26C
|
||||
#define MC_SMMU_PPCS_ASID_0 0x270
|
||||
#define MC_SMMU_SATA_ASID_0 0x274
|
||||
#define MC_SMMU_VI_ASID_0 0x280
|
||||
#define MC_SMMU_VIC_ASID_0 0x284
|
||||
#define MC_SMMU_XUSB_HOST_ASID_0 0x288
|
||||
#define MC_SMMU_XUSB_DEV_ASID_0 0x28C
|
||||
#define MC_SMMU_TSEC_ASID_0 0x294
|
||||
#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2E4
|
||||
#define MC_LATENCY_ALLOWANCE_DC_0 0x2E8
|
||||
#define MC_LATENCY_ALLOWANCE_DC_1 0x2EC
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_0 0x2F4
|
||||
#define MC_LATENCY_ALLOWANCE_DCB_1 0x2F8
|
||||
#define MC_LATENCY_ALLOWANCE_HC_0 0x310
|
||||
#define MC_LATENCY_ALLOWANCE_HC_1 0x314
|
||||
#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
|
||||
#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
|
||||
#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
|
||||
#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37C
|
||||
#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
|
||||
#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
|
||||
#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
|
||||
#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
|
||||
#define MC_LATENCY_ALLOWANCE_GPU_0 0x3AC
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3B8
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3BC
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3C0
|
||||
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3C4
|
||||
#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3D8
|
||||
#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3E8
|
||||
#define MC_DIS_PTSA_RATE_0 0x41C
|
||||
#define MC_DIS_PTSA_MIN_0 0x420
|
||||
#define MC_DIS_PTSA_MAX_0 0x424
|
||||
#define MC_DISB_PTSA_RATE_0 0x428
|
||||
#define MC_DISB_PTSA_MIN_0 0x42C
|
||||
#define MC_DISB_PTSA_MAX_0 0x430
|
||||
#define MC_VE_PTSA_RATE_0 0x434
|
||||
#define MC_VE_PTSA_MIN_0 0x438
|
||||
#define MC_VE_PTSA_MAX_0 0x43C
|
||||
#define MC_MLL_MPCORER_PTSA_RATE_0 0x44C
|
||||
#define MC_RING1_PTSA_RATE_0 0x47C
|
||||
#define MC_RING1_PTSA_MIN_0 0x480
|
||||
#define MC_RING1_PTSA_MAX_0 0x484
|
||||
#define MC_PCX_PTSA_RATE_0 0x4AC
|
||||
#define MC_PCX_PTSA_MIN_0 0x4B0
|
||||
#define MC_PCX_PTSA_MAX_0 0x4B4
|
||||
#define MC_MSE_PTSA_RATE_0 0x4C4
|
||||
#define MC_MSE_PTSA_MIN_0 0x4C8
|
||||
#define MC_MSE_PTSA_MAX_0 0x4CC
|
||||
#define MC_AHB_PTSA_RATE_0 0x4DC
|
||||
#define MC_AHB_PTSA_MIN_0 0x4E0
|
||||
#define MC_AHB_PTSA_MAX_0 0x4E4
|
||||
#define MC_APB_PTSA_RATE_0 0x4E8
|
||||
#define MC_APB_PTSA_MIN_0 0x4EC
|
||||
#define MC_APB_PTSA_MAX_0 0x4F0
|
||||
#define MC_FTOP_PTSA_RATE_0 0x50C
|
||||
#define MC_HOST_PTSA_RATE_0 0x518
|
||||
#define MC_HOST_PTSA_MIN_0 0x51C
|
||||
#define MC_HOST_PTSA_MAX_0 0x520
|
||||
#define MC_USBX_PTSA_RATE_0 0x524
|
||||
#define MC_USBX_PTSA_MIN_0 0x528
|
||||
#define MC_USBX_PTSA_MAX_0 0x52C
|
||||
#define MC_USBD_PTSA_RATE_0 0x530
|
||||
#define MC_USBD_PTSA_MIN_0 0x534
|
||||
#define MC_USBD_PTSA_MAX_0 0x538
|
||||
#define MC_GK_PTSA_RATE_0 0x53C
|
||||
#define MC_GK_PTSA_MIN_0 0x540
|
||||
#define MC_GK_PTSA_MAX_0 0x544
|
||||
#define MC_AUD_PTSA_RATE_0 0x548
|
||||
#define MC_AUD_PTSA_MIN_0 0x54C
|
||||
#define MC_AUD_PTSA_MAX_0 0x550
|
||||
#define MC_VICPC_PTSA_RATE_0 0x554
|
||||
#define MC_VICPC_PTSA_MIN_0 0x558
|
||||
#define MC_VICPC_PTSA_MAX_0 0x55C
|
||||
#define MC_JPG_PTSA_RATE_0 0x584
|
||||
#define MC_JPG_PTSA_MIN_0 0x588
|
||||
#define MC_JPG_PTSA_MAX_0 0x58C
|
||||
#define MC_GK2_PTSA_RATE_0 0x610
|
||||
#define MC_GK2_PTSA_MIN_0 0x614
|
||||
#define MC_GK2_PTSA_MAX_0 0x618
|
||||
#define MC_SDM_PTSA_RATE_0 0x61C
|
||||
#define MC_SDM_PTSA_MIN_0 0x620
|
||||
#define MC_SDM_PTSA_MAX_0 0x624
|
||||
#define MC_HDAPC_PTSA_RATE_0 0x628
|
||||
#define MC_HDAPC_PTSA_MIN_0 0x62C
|
||||
#define MC_HDAPC_PTSA_MAX_0 0x630
|
||||
#define MC_SEC_CARVEOUT_BOM_0 0x670
|
||||
#define MC_SEC_CARVEOUT_SIZE_MB_0 0x674
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 0x690
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 0x694
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 0x698
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 0x69C
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 0x6A0
|
||||
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 0x6A4
|
||||
#define MC_EMEM_ARB_TIMING_RFCPB_0 0x6C0
|
||||
#define MC_EMEM_ARB_TIMING_CCDMW_0 0x6C4
|
||||
#define MC_EMEM_ARB_REFPB_HP_CTRL_0 0x6F0
|
||||
#define MC_EMEM_ARB_REFPB_BANK_CTRL_0 0x6F4
|
||||
#define MC_PTSA_GRANT_DECREMENT_0 0x960
|
||||
#define MC_CLIENT_HOTRESET_CTRL_1 0x970
|
||||
#define MC_CLIENT_HOTRESET_STATUS_1 0x974
|
||||
#define MC_SMMU_PTC_FLUSH_1 0x9B8
|
||||
#define MC_SMMU_DC1_ASID_0 0xA88
|
||||
#define MC_SMMU_SDMMC1A_ASID_0 0xA94
|
||||
#define MC_SMMU_SDMMC2A_ASID_0 0xA98
|
||||
#define MC_SMMU_SDMMC3A_ASID_0 0xA9C
|
||||
#define MC_SMMU_SDMMC4A_ASID_0 0xAA0
|
||||
#define MC_SMMU_ISP2B_ASID_0 0xAA4
|
||||
#define MC_SMMU_GPU_ASID_0 0xAA8
|
||||
#define MC_SMMU_GPUB_ASID_0 0xAAC
|
||||
#define MC_SMMU_PPCS2_ASID_0 0xAB0
|
||||
#define MC_SMMU_NVDEC_ASID_0 0xAB4
|
||||
#define MC_SMMU_APE_ASID_0 0xAB8
|
||||
#define MC_SMMU_SE_ASID_0 0xABC
|
||||
#define MC_SMMU_NVJPG_ASID_0 0xAC0
|
||||
#define MC_SMMU_HC1_ASID_0 0xAC4
|
||||
#define MC_SMMU_SE1_ASID_0 0xAC8
|
||||
#define MC_SMMU_AXIAP_ASID_0 0xACC
|
||||
#define MC_SMMU_ETR_ASID_0 0xAD0
|
||||
#define MC_SMMU_TSECB_ASID_0 0xAD4
|
||||
#define MC_SMMU_TSEC1_ASID_0 0xAD8
|
||||
#define MC_SMMU_TSECB1_ASID_0 0xADC
|
||||
#define MC_SMMU_NVDEC1_ASID_0 0xAE0
|
||||
#define MC_EMEM_ARB_DHYST_CTRL_0 0xBCC
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xBD0
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xBD4
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xBD8
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xBDC
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xBE0
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xBE4
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xBE8
|
||||
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xBEC
|
||||
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_0 0xC00
|
||||
#define MC_SECURITY_CARVEOUT2_BOM_0 0xC5C
|
||||
#define MC_SECURITY_CARVEOUT3_BOM_0 0xCAC
|
||||
@@ -208,6 +208,12 @@ Result IpcService::ServiceHandlerFunc(void* arg, const IpcServerRequest* r, u8*
|
||||
if (r->data.size >= 0) {
|
||||
return ipcSrv->SetKipData();
|
||||
}
|
||||
break;
|
||||
case HocClkIpcCmd_UpdateEmcRegs:
|
||||
if (r->data.size >= 0) {
|
||||
return ipcSrv->UpdateEmcRegs();
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
return SYSCLK_ERROR(Generic);
|
||||
@@ -376,4 +382,8 @@ Result IpcService::GetKipData() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
Result IpcService::UpdateEmcRegs() {
|
||||
this->clockMgr->UpdateRamTimings();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -57,7 +57,7 @@ class IpcService
|
||||
Result SetReverseNXRTMode(ReverseNXMode mode);
|
||||
Result SetKipData();
|
||||
Result GetKipData();
|
||||
|
||||
Result UpdateEmcRegs();
|
||||
bool running;
|
||||
Thread thread;
|
||||
LockableMutex threadMutex;
|
||||
|
||||
Reference in New Issue
Block a user