pcv_erista: add experimental proper write timings
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@@ -82,11 +82,42 @@ namespace ams::ldr::hoc::pcv::erista {
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}
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}
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void CalculateMrw2() {
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static const u8 rlMapDBI[8] = {
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6, 12, 16, 22, 28, 32, 36, 40
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};
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static const u8 wlMapSetA[8] = {
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4, 6, 8, 10, 12, 14, 16, 18
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};
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u32 rlIndex = 0;
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u32 wlIndex = 0;
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for (u32 i = 0; i < std::size(rlMapDBI); ++i) {
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if (rlMapDBI[i] == 32) {
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rlIndex = i;
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break;
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}
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}
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for (u32 i = 0; i < std::size(wlMapSetA); ++i) {
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if (wlMapSetA[i] == WL) {
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wlIndex = i;
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break;
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}
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}
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/* DBI is always enabled. */
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mrw2 = static_cast<u8>(((rlIndex & 0x7) | ((wlIndex & 0x7) << 3) | ((0 & 0x1) << 6)));
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}
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void CalculateTimings(double tCK_avg, u32 freq) {
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RL = RL_1331;
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WL = WL_1331;
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HandleLatency(freq);
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CalculateMrw2();
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tR2P = CEIL((RL * 0.426) - 2.0);
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tR2W = FLOOR(FLOOR((5.0 / tCK_avg) + ((FLOOR(48.0 / WL) - 0.478) * 3.0)) / 1.501) + RL - (C.t6_tRTW * 3) + finetRTW;
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@@ -95,6 +126,14 @@ namespace ams::ldr::hoc::pcv::erista {
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tWTPDEN = CEIL(((1.803 / tCK_avg) + MAX(RL + (2.694 / tCK_avg), static_cast<double>(tW2P))) + (BL / 2));
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tW2R = FLOOR(MAX((5.020 / tCK_avg) + 1.130, WL - MAX(-CEIL(0.258 * (WL - RL)), 1.964)) * 1.964) + WL - CEIL(tWTR / tCK_avg) + finetWTR;
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wdv = WL;
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wsv = WL - 2;
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wev = 0xA + (WL - 14);
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u32 obdlyHigh = 3 / FLOOR(MIN(static_cast<double>(2), tCK_avg * (WL - 7)));
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u32 obdlyLow = MAX(WL - FLOOR((126.0 / CEIL(tCK_avg + 8.601))), 0.0);
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obdly = PACK_U32_NIBBLE_HIGH_BYTE_LOW(obdlyHigh, obdlyLow);
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pdex2rw = CEIL((CEIL(12.335 - tCK_avg) + (7.430 / tCK_avg) - CEIL(tCK_avg * 11.361)));
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tCLKSTOP = FLOOR(MIN(8.488 / tCK_avg, 23.0)) + 8.0;
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