diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/customize.cpp b/Source/Atmosphere/stratosphere/loader/source/oc/customize.cpp
index 9eb8956f..d77e2e55 100644
--- a/Source/Atmosphere/stratosphere/loader/source/oc/customize.cpp
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/customize.cpp
@@ -44,7 +44,7 @@ volatile CustomizeTable C = {
  *   Value should be divided evenly by 12'500.
  *   Not enabled by default.
  */
-.commonEmcMemVolt  = 0,
+.commonEmcMemVolt  = 1175000,
 
 /* Erista CPU:
  * - Max Voltage in mV
@@ -60,7 +60,7 @@ volatile CustomizeTable C = {
  *   - System instabilities
  *   - NAND corruption
  */
-.eristaEmcMaxClock = 1862400,
+.eristaEmcMaxClock = 2131200,
 
 /* Mariko CPU:
  * - Max Voltage in mV:
diff --git a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp
index 0df2a24a..ad5f8f15 100644
--- a/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp
+++ b/Source/Atmosphere/stratosphere/loader/source/oc/mtc_timing_value.hpp
@@ -103,15 +103,15 @@ namespace ams::ldr::oc {
     namespace pcv::erista {
         // tCK_avg (average clock period) in ns
         const double tCK_avg = 1000'000. / C.eristaEmcMaxClock;
-        const u32 WL = !TIMING_PRESET_SEVEN ? (C.eristaEmcMaxClock <= 2131200 ? 12 : 14) : tWL_values[TIMING_PRESET_SEVEN-1]; //?
-        const u32 RL = !TIMING_PRESET_SEVEN ? (C.eristaEmcMaxClock <= 2131200 ? 24 : 28) : WL*2; //?
+        const u32 WL = 16 - 2*TIMING_PRESET_SEVEN; //?
+        const u32 RL = 36 - 4*TIMING_PRESET_SEVEN; //?
 
         // minimum number of cycles from any read command to any write command, irrespective of bank
-        const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST));
+        const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST)) + 6;
         // Delay Time From WRITE-to-READ
-        const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg);
+        const u32 W2R = WL + BL/2 + 1 + CEIL(tWTR/tCK_avg) - 6;
         // write-to-precharge time for commands to the same bank in cycles
-        const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg);
+        const u32 WTP = WL + BL/2 + 1 + CEIL(tWR/tCK_avg) - 8;
         // #_of_rows per die for 8Gb density
         const u32 numOfRows = 65536;
         // {REFRESH, REFRESH_LO} = max[(tREF/#_of_rows) / (emc_clk_period) - 64, (tREF/#_of_rows) / (emc_clk_period) * 97%]
@@ -131,8 +131,8 @@ namespace ams::ldr::oc {
     namespace pcv::mariko {
         // tCK_avg (average clock period) in ns
         const double tCK_avg = 1000'000. / C.marikoEmcMaxClock;
-        const u32 WL = !TIMING_PRESET_SEVEN ? (C.marikoEmcMaxClock <= 2131200 ? 12 : 14) : tWL_values[TIMING_PRESET_SEVEN-1]; //?
-        const u32 RL = !TIMING_PRESET_SEVEN ? (C.marikoEmcMaxClock <= 2131200 ? 24 : 28) : WL*2; //?
+        const u32 WL = 14 - 2*TIMING_PRESET_SEVEN; //?
+        const u32 RL = 28 - 4*TIMING_PRESET_SEVEN; //?
 
         // minimum number of cycles from any read command to any write command, irrespective of bank
         const u32 R2W = CEIL (RL + CEIL(tDQSCK_max/tCK_avg) + BL/2 - WL + tWPRE + FLOOR(tRPST));
diff --git a/pages/src/main.ts b/pages/src/main.ts
index ab4fab55..6e4b7a4d 100644
--- a/pages/src/main.ts
+++ b/pages/src/main.ts
@@ -325,7 +325,7 @@ var AdvTable: Array<AdvEntry> = [
      "<b>5</b> : 12 - 4",
      "<b>6</b> : 8 - 4",],
      1,
-     [0,5],
+     [0,6],
      1,
   ),
   new AdvEntry(
@@ -385,19 +385,19 @@ var AdvTable: Array<AdvEntry> = [
   ),
   new AdvEntry(
     "ramTimingPresetSeven",
-    "Secondary RAM Timing Preset",
+    "Latency Decrement",
      CustPlatform.Mariko,
      4,
      ["WARNING: Unstable timings can corrupt your nand",
-     "Secondary Timing Preset for both AUTO_ADJ and CUSTOM_ADJ",
+     "Latency decrement for both AUTO_ADJ and CUSTOM_ADJ",
      "Values are : WL - RL",
-     "<b>0</b> : Do Not Adjust (2400Mhz: ??) (CUST_ADJ only)",
-     "<b>1</b> : 14 - 28", 
-     "<b>2</b> : 12 - 24", 
-     "<b>3</b> : 10 - 20",
-     "<b>4</b> : 8 - 16",
-     "<b>5</b> : 6 - 12",
-     "<b>6</b> : 4 - 8",],
+     "<b>0</b> : Default Latency",
+     "<b>1</b> : -2 - -4", 
+     "<b>2</b> : -4 - -8", 
+     "<b>3</b> : -6 - -12",
+     "<b>4</b> : -8 - -16",
+     "<b>5</b> : -10 - -20",
+     "<b>6</b> : -12 - -24",],
      1,
      [0,6],
      1,