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sysclk: refactoring

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This commit is contained in:
souldbminersmwc
2026-01-10 12:49:59 -05:00
parent c879ba985f
commit 00443343dc
10 changed files with 71 additions and 35 deletions
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24
Source/sys-clk/sysmodule/src/board.cpp
View File

@@ -39,7 +39,7 @@
#include <display_refresh_rate.h>
#include <stdio.h>
#include <cstring>
#include "emc_mc_defs.h"
#include <registers.h>
#include <notification.h>
#define MAX(A, B) std::max(A, B)
@@ -97,7 +97,7 @@ std::atomic<uint64_t> idletick3{systemtickfrequency};
u32 cpu0, cpu1, cpu2, cpu3, cpuAvg;
u16 cpuSpeedo0, cpuSpeedo2, socSpeedo0; // CPU, GPU, SOC
u16 cpuIDDQ, gpuIDDQ, socIDDQ;
u8 g_dramID = 0;
const char* Board::GetModuleName(SysClkModule module, bool pretty)
{
@@ -239,10 +239,10 @@ void Board::Initialize()
threadCreate(&gpuLThread, gpuLoadThread, NULL, NULL, 0x1000, 0x3F, -2);
threadStart(&gpuLThread);
threadCreate(&cpuCore0Thread, CheckCore, &idletick0, NULL, 0x1000, 0x10, 0);
threadCreate(&cpuCore1Thread, CheckCore, &idletick1, NULL, 0x1000, 0x10, 1);
threadCreate(&cpuCore2Thread, CheckCore, &idletick2, NULL, 0x1000, 0x10, 2);
threadCreate(&cpuCore3Thread, CheckCore, &idletick3, NULL, 0x1000, 0x10, 3);
threadCreate(&cpuCore0Thread, CheckCore, &idletick0, NULL, 0x500, 0x10, 0);
threadCreate(&cpuCore1Thread, CheckCore, &idletick1, NULL, 0x500, 0x10, 1);
threadCreate(&cpuCore2Thread, CheckCore, &idletick2, NULL, 0x500, 0x10, 2);
threadCreate(&cpuCore3Thread, CheckCore, &idletick3, NULL, 0x500, 0x10, 3);
threadCreate(&miscThread, miscThreadFunc, NULL, NULL, 0x1000, 0x3F, 3);
threadStart(&cpuCore0Thread);
@@ -266,6 +266,7 @@ void Board::Initialize()
DisplayRefresh_Initialize(&cfg);
}
FetchHardwareInfos();
}
@@ -767,16 +768,23 @@ HorizonOCConsoleType Board::GetConsoleType() {
return g_consoleType;
}
u8 Board::GetDramID() {
return g_dramID;
}
void Board::FetchHardwareInfos()
{
fuseReadSpeedos();
u64 sku = 0;
u64 sku = 0, dramID = 0;
Result rc = splInitialize();
ASSERT_RESULT_OK(rc, "splInitialize");
rc = splGetConfig(SplConfigItem_HardwareType, &sku);
ASSERT_RESULT_OK(rc, "splGetConfig");
rc = splGetConfig(SplConfigItem_DramId, &dramID);
ASSERT_RESULT_OK(rc, "splGetConfig");
splExit();
switch(sku)
@@ -792,6 +800,8 @@ void Board::FetchHardwareInfos()
}
g_consoleType = (HorizonOCConsoleType)sku;
g_dramID = (u8)dramID;
}
/*

1
Source/sys-clk/sysmodule/src/board.h
View File

@@ -61,6 +61,7 @@ class Board
static HorizonOCConsoleType GetConsoleType();
static std::uint32_t GetVoltage(HocClkVoltage voltage);
static u8 GetFanRotationLevel();
static u8 GetDramID();
static void UpdateShadowRegs(u32 tRCD_i, u32 tRP_i, u32 tRAS_i, u32 tRRD_i, u32 tRFC_i, u32 tRTW_i, u32 tWTR_i, u32 tREFpb_i, u32 ramFreq, u32 rlAdd, u32 wlAdd, bool hpMode);
protected:
static void FetchHardwareInfos();

52
Source/sys-clk/sysmodule/src/clock_manager.cpp
View File

@@ -107,13 +107,20 @@ ClockManager::ClockManager()
this->context->speedos[HorizonOCSpeedo_GPU] = Board::getGPUSpeedo();
this->context->speedos[HorizonOCSpeedo_SOC] = Board::getSOCSpeedo();
this->context->dramID = Board::GetDramID();
}
void ClockManager::FixCpuBug() {
Board::SetHz(SysClkModule_CPU, 1785000000); // this will just set to the max when kip is unloaded so idgaf
Board::SetHz(SysClkModule_CPU, 1887000000);
Board::SetHz(SysClkModule_CPU, 1963000000);
Board::SetHz(SysClkModule_CPU, 2091000000);
Board::SetHz(SysClkModule_CPU, 2193000000);
Board::SetHz(SysClkModule_CPU, 2295000000);
Board::SetHz(SysClkModule_CPU, 2397000000);
Board::SetHz(SysClkModule_CPU, 2499000000);
Board::SetHz(SysClkModule_CPU, 2601000000);
Board::SetHz(SysClkModule_CPU, 2703000000); // i am just replicating what the user would manually do to fix the bug. if 2703 is unstable it will reset to 1020 due to how fast this runs
Board::SetHz(SysClkModule_CPU, 1020000000);
ResetToStockClocks();
u32 targetHz = 0;
@@ -414,10 +421,6 @@ void ClockManager::Tick()
Result rc = apmExtGetCurrentPerformanceConfiguration(&mode);
ASSERT_RESULT_OK(rc, "apmExtGetCurrentPerformanceConfiguration");
if(this->config->GetConfigValue(HorizonOCConfigValue_BatteryChargeCurrent)) {
I2c_Bq24193_SetFastChargeCurrentLimit(this->config->GetConfigValue(HorizonOCConfigValue_BatteryChargeCurrent));
}
if(this->config->GetConfigValue(HocClkConfigValue_HandheldTDP) && opMode == AppletOperationMode_Handheld) {
if(Board::GetConsoleType() == HorizonOCConsoleType_Hoag) {
if(Board::GetPowerMw(SysClkPowerSensor_Now) < -(int)this->config->GetConfigValue(HocClkConfigValue_LiteTDPLimit)) {
@@ -456,6 +459,9 @@ void ClockManager::Tick()
if (this->RefreshContext() || this->config->Refresh())
{
if(this->config->GetConfigValue(HorizonOCConfigValue_BatteryChargeCurrent)) {
I2c_Bq24193_SetFastChargeCurrentLimit(this->config->GetConfigValue(HorizonOCConfigValue_BatteryChargeCurrent));
}
std::uint32_t targetHz = 0;
std::uint32_t maxHz = 0;
std::uint32_t nearestHz = 0;
@@ -965,25 +971,25 @@ void ClockManager::UpdateRamTimings() {
return;
}
if(this->config->GetConfigValue(KipConfigValue_marikoEmcMaxClock) != initialConfigValues[KipConfigValue_marikoEmcMaxClock] ||
this->config->GetConfigValue(KipConfigValue_mem_burst_read_latency) != initialConfigValues[KipConfigValue_mem_burst_read_latency] ||
this->config->GetConfigValue(KipConfigValue_mem_burst_write_latency) != initialConfigValues[KipConfigValue_mem_burst_write_latency]
) {
writeNotification("Horizon OC\nCritical values changed!\nUnable to write timings");
return;
}
u32 t1_tRCD = this->config->GetConfigValue(KipConfigValue_t1_tRCD);
u32 t2_tRP = this->config->GetConfigValue(KipConfigValue_t2_tRP);
u32 t3_tRAS = this->config->GetConfigValue(KipConfigValue_t3_tRAS);
u32 t4_tRRD = this->config->GetConfigValue(KipConfigValue_t4_tRRD);
u32 t5_tRFC = this->config->GetConfigValue(KipConfigValue_t5_tRFC);
u32 t6_tRTW = this->config->GetConfigValue(KipConfigValue_t6_tRTW);
u32 t7_tWTR = this->config->GetConfigValue(KipConfigValue_t7_tWTR);
u32 t8_tREFI = this->config->GetConfigValue(KipConfigValue_t8_tREFI);
u64 ramFreq = this->config->GetConfigValue(KipConfigValue_marikoEmcMaxClock);
u32 rlAdd = this->config->GetConfigValue(KipConfigValue_mem_burst_read_latency);
u32 wlAdd = this->config->GetConfigValue(KipConfigValue_mem_burst_write_latency);
bool hpMode = (bool)this->config->GetConfigValue(KipConfigValue_hpMode);
// if(this->config->GetConfigValue(KipConfigValue_marikoEmcMaxClock) != initialConfigValues[KipConfigValue_marikoEmcMaxClock] ||
// this->config->GetConfigValue(KipConfigValue_mem_burst_read_latency) != initialConfigValues[KipConfigValue_mem_burst_read_latency] ||
// this->config->GetConfigValue(KipConfigValue_mem_burst_write_latency) != initialConfigValues[KipConfigValue_mem_burst_write_latency]
// ) {
// writeNotification("Horizon OC\nCritical values changed!\nUnable to write timings");
// return;
// }
u32 t1_tRCD = initialConfigValues[KipConfigValue_t1_tRCD];
u32 t2_tRP = initialConfigValues[KipConfigValue_t2_tRP];
u32 t3_tRAS = initialConfigValues[KipConfigValue_t3_tRAS];
u32 t4_tRRD = initialConfigValues[KipConfigValue_t4_tRRD];
u32 t5_tRFC = initialConfigValues[KipConfigValue_t5_tRFC];
u32 t6_tRTW = initialConfigValues[KipConfigValue_t6_tRTW];
u32 t7_tWTR = initialConfigValues[KipConfigValue_t7_tWTR];
u32 t8_tREFI = initialConfigValues[KipConfigValue_t8_tREFI];
u64 ramFreq = initialConfigValues[KipConfigValue_marikoEmcMaxClock];
u32 rlAdd = initialConfigValues[KipConfigValue_mem_burst_read_latency];
u32 wlAdd = initialConfigValues[KipConfigValue_mem_burst_write_latency];
bool hpMode = (bool)initialConfigValues[KipConfigValue_hpMode];
Board::UpdateShadowRegs(t1_tRCD, t2_tRP, t3_tRAS, t4_tRRD, t5_tRFC, t6_tRTW, t7_tWTR, t8_tREFI, ramFreq, rlAdd, wlAdd, hpMode);
}

2
Source/sys-clk/sysmodule/src/clock_manager.h
View File

@@ -73,7 +73,7 @@ class ClockManager
void calculateGpuVmin(void);
protected:
bool IsAssignableHz(SysClkModule module, std::uint32_t hz);
std::uint32_t GetMaxAllowedHz(SysClkModule module, SysClkProfile profile);
inline std::uint32_t GetMaxAllowedHz(SysClkModule module, SysClkProfile profile);
std::uint32_t GetNearestHz(SysClkModule module, std::uint32_t inHz, std::uint32_t maxHz);
bool ConfigIntervalTimeout(SysClkConfigValue intervalMsConfigValue, std::uint64_t ns, std::uint64_t* lastLogNs);
void RefreshFreqTableRow(SysClkModule module);

492
Source/sys-clk/sysmodule/src/emc_mc_defs.h
View File

@@ -1,492 +0,0 @@
/*
* Copyright (c) Souldbminer and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#pragma once
#define EMC_INTSTATUS_0 0x0
#define EMC_INTMASK_0 0x4
#define EMC_DBG_0 0x8
#define EMC_CFG_0 0xC
#define EMC_ADR_CFG_0 0x10
#define EMC_REFCTRL_0 0x20
#define EMC_PIN_0 0x24
#define EMC_TIMING_CONTROL_0 0x28
#define EMC_RC_0 0x2C
#define EMC_RFC_0 0x30
#define EMC_RAS_0 0x34
#define EMC_RP_0 0x38
#define EMC_R2W_0 0x3C
#define EMC_W2R_0 0x40
#define EMC_R2P_0 0x44
#define EMC_W2P_0 0x48
#define EMC_RD_RCD_0 0x4C
#define EMC_WR_RCD_0 0x50
#define EMC_RRD_0 0x54
#define EMC_REXT_0 0x58
#define EMC_WDV_0 0x5C
#define EMC_QUSE_0 0x60
#define EMC_QRST_0 0x64
#define EMC_QSAFE_0 0x68
#define EMC_RDV_0 0x6C
#define EMC_REFRESH_0 0x70
#define EMC_BURST_REFRESH_NUM_0 0x74
#define EMC_PDEX2WR_0 0x78
#define EMC_PDEX2RD_0 0x7C
#define EMC_PCHG2PDEN_0 0x80
#define EMC_ACT2PDEN_0 0x84
#define EMC_AR2PDEN_0 0x88
#define EMC_RW2PDEN_0 0x8C
#define EMC_TXSR_0 0x90
#define EMC_TCKE_0 0x94
#define EMC_TFAW_0 0x98
#define EMC_TRPAB_0 0x9C
#define EMC_TCLKSTABLE_0 0xA0
#define EMC_TCLKSTOP_0 0xA4
#define EMC_TREFBW_0 0xA8
#define EMC_TPPD_0 0xAC
#define EMC_ODT_WRITE_0 0xB0
#define EMC_PDEX2MRR_0 0xB4
#define EMC_WEXT_0 0xB8
#define EMC_RFC_SLR_0 0xC0
#define EMC_MRS_WAIT_CNT2_0 0xC4
#define EMC_MRS_WAIT_CNT_0 0xC8
#define EMC_MRS_0 0xCC
#define EMC_EMRS_0 0xD0
#define EMC_REF_0 0xD4
#define EMC_PRE_0 0xD8
#define EMC_NOP_0 0xDC
#define EMC_SELF_REF_0 0xE0
#define EMC_DPD_0 0xE4
#define EMC_MRW_0 0xE8
#define EMC_MRR_0 0xEC
#define EMC_CMDQ_0 0xF0
#define EMC_MC2EMCQ_0 0xF4
#define EMC_FBIO_SPARE_0 0x100
#define EMC_FBIO_CFG5_0 0x104
#define EMC_FBIO_CFG6_0 0x114
#define EMC_PDEX2CKE_0 0x118
#define EMC_CKE2PDEN_0 0x11C
#define EMC_CFG_RSV_0 0x120
#define EMC_ACPD_CONTROL_0 0x124
#define EMC_MPC_0 0x128
#define EMC_EMRS2_0 0x12C
#define EMC_EMRS3_0 0x130
#define EMC_MRW2_0 0x134
#define EMC_MRW3_0 0x138
#define EMC_MRW4_0 0x13C
#define EMC_CLKEN_OVERRIDE_0 0x140
#define EMC_R2R_0 0x144
#define EMC_W2W_0 0x148
#define EMC_EINPUT_0 0x14C
#define EMC_EINPUT_DURATION_0 0x150
#define EMC_PUTERM_EXTRA_0 0x154
#define EMC_TCKESR_0 0x158
#define EMC_TPD_0 0x15C
#define EMC_AUTO_CAL_CONFIG_0 0x2A4
#define EMC_AUTO_CAL_INTERVAL_0 0x2A8
#define EMC_AUTO_CAL_STATUS_0 0x2AC
#define EMC_REQ_CTRL_0 0x2B0
#define EMC_EMC_STATUS_0 0x2B4
#define EMC_CFG_2_0 0x2B8
#define EMC_CFG_DIG_DLL_0 0x2BC
#define EMC_CFG_DIG_DLL_PERIOD_0 0x2C0
#define EMC_DIG_DLL_STATUS_0 0x2C4
#define EMC_CFG_DIG_DLL_1_0 0x2C8
#define EMC_RDV_MASK_0 0x2CC
#define EMC_WDV_MASK_0 0x2D0
#define EMC_RDV_EARLY_MASK_0 0x2D4
#define EMC_RDV_EARLY_0 0x2D8
#define EMC_AUTO_CAL_CONFIG8_0 0x2DC
#define EMC_ZCAL_INTERVAL_0 0x2E0
#define EMC_ZCAL_WAIT_CNT_0 0x2E4
#define EMC_ZCAL_MRW_CMD_0 0x2E8
#define EMC_ZQ_CAL_0 0x2EC
#define EMC_XM2COMPPADCTRL3_0 0x2F4
#define EMC_AUTO_CAL_VREF_SEL_0_0 0x2F8
#define EMC_AUTO_CAL_VREF_SEL_1_0 0x300
#define EMC_XM2COMPPADCTRL_0 0x30C
#define EMC_FDPD_CTRL_DQ_0 0x310
#define EMC_FDPD_CTRL_CMD_0 0x314
#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD_0 0x318
#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD_0 0x31C
#define EMC_SCRATCH0_0 0x324
#define EMC_PMACRO_BRICK_CTRL_RFU1_0 0x330
#define EMC_PMACRO_BRICK_CTRL_RFU2_0 0x334
#define EMC_CMD_MAPPING_CMD0_0_0 0x380
#define EMC_CMD_MAPPING_CMD0_1_0 0x384
#define EMC_CMD_MAPPING_CMD0_2_0 0x388
#define EMC_CMD_MAPPING_CMD1_0_0 0x38C
#define EMC_CMD_MAPPING_CMD1_1_0 0x390
#define EMC_CMD_MAPPING_CMD1_2_0 0x394
#define EMC_CMD_MAPPING_CMD2_0_0 0x398
#define EMC_CMD_MAPPING_CMD2_1_0 0x39C
#define EMC_CMD_MAPPING_CMD2_2_0 0x3A0
#define EMC_CMD_MAPPING_CMD3_0_0 0x3A4
#define EMC_CMD_MAPPING_CMD3_1_0 0x3A8
#define EMC_CMD_MAPPING_CMD3_2_0 0x3AC
#define EMC_CMD_MAPPING_BYTE_0 0x3B0
#define EMC_TR_TIMING_0_0 0x3B4
#define EMC_TR_CTRL_0_0 0x3B8
#define EMC_TR_CTRL_1_0 0x3BC
#define EMC_SWITCH_BACK_CTRL_0 0x3C0
#define EMC_TR_RDV_0 0x3C4
#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE_0 0x3C8
#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE_0 0x3CC
#define EMC_UNSTALL_RW_AFTER_CLKCHANGE_0 0x3D0
#define EMC_AUTO_CAL_ 0x3D4
#define EMC_SEL_DPD_CTRL_0 0x3D8
#define EMC_PRE_REFRESH_REQ_CNT_0 0x3DC
#define EMC_DYN_SELF_REF_CONTROL_0 0x3E0
#define EMC_TXSRDLL_0 0x3E4
#define EMC_CCFIFO_ADDR_0 0x3E8
#define EMC_CCFIFO_DATA_0 0x3EC
#define EMC_CCFIFO_STATUS_0 0x3F0
#define EMC_TR_QPOP_0 0x3F4
#define EMC_TR_RDV_MASK_0 0x3F8
#define EMC_TR_QSAFE_0 0x3FC
#define EMC_TR_QRST_0 0x400
#define EMC_SWIZZLE_RANK0_BYTE0_0 0x404
#define EMC_SWIZZLE_RANK0_BYTE1_0 0x408
#define EMC_SWIZZLE_RANK0_BYTE2_0 0x40C
#define EMC_SWIZZLE_RANK0_BYTE3_0 0x410
#define EMC_SWIZZLE_RANK1_BYTE0_0 0x418
#define EMC_SWIZZLE_RANK1_BYTE1_0 0x41C
#define EMC_SWIZZLE_RANK1_BYTE2_0 0x420
#define EMC_SWIZZLE_RANK1_BYTE3_0 0x424
#define EMC_ISSUE_QRST_0 0x428
#define EMC_PMC_SCRATCH1_0 0x440
#define EMC_PMC_SCRATCH2_0 0x444
#define EMC_PMC_SCRATCH3_0 0x448
#define EMC_AUTO_CAL_CONFIG2_0 0x458
#define EMC_AUTO_CAL_CONFIG3_0 0x45C
#define EMC_TR_DVFS_0 0x460
#define EMC_AUTO_CAL_CHANNEL_0 0x464
#define EMC_IBDLY_0 0x468
#define EMC_OBDLY_0 0x46C
#define EMC_TXDSRVTTGEN_0 0x480
#define EMC_WE_DURATION_0 0x48C
#define EMC_WS_DURATION_0 0x490
#define EMC_WEV_0 0x494
#define EMC_WSV_0 0x498
#define EMC_CFG_3_0 0x49C
#define EMC_MRW5_0 0x4A0
#define EMC_MRW6_0 0x4A4
#define EMC_MRW7_0 0x4A8
#define EMC_MRW8_0 0x4AC
#define EMC_MRW9_0 0x4B0
#define EMC_MRW10_0 0x4B4
#define EMC_MRW11_0 0x4B8
#define EMC_MRW12_0 0x4BC
#define EMC_MRW13_0 0x4C0
#define EMC_MRW14_0 0x4C4
#define EMC_MRW15_0 0x4D0
#define EMC_CFG_SYNC_0 0x4D4
#define EMC_FDPD_CTRL_CMD_NO_RAMP_0 0x4D8
#define EMC_WDV_CHK_0 0x4E0
#define EMC_CFG_PIPE_2_0 0x554
#define EMC_CFG_PIPE_CLK_0 0x558
#define EMC_CFG_PIPE_1_0 0x55C
#define EMC_CFG_PIPE_0 0x560
#define EMC_QPOP_0 0x564
#define EMC_QUSE_WIDTH_0 0x568
#define EMC_PUTERM_WIDTH_0 0x56C
#define EMC_BGBIAS_CTL0_0 0x570
#define EMC_AUTO_CAL_CONFIG7_0 0x574
#define EMC_XM2COMPPADCTRL2_0 0x578
#define EMC_COMP_PAD_SW_CTRL_0 0x57C
#define EMC_REFCTRL2_0 0x580
#define EMC_FBIO_CFG7_0 0x584
#define EMC_DATA_BRLSHFT_0_0 0x588
#define EMC_DATA_BRLSHFT_1_0 0x58C
#define EMC_RFCPB_0 0x590
#define EMC_DQS_BRLSHFT_0_0 0x594
#define EMC_DQS_BRLSHFT_1_0 0x598
#define EMC_CMD_BRLSHFT_0_0 0x59C
#define EMC_CMD_BRLSHFT_1_0 0x5A0
#define EMC_CMD_BRLSHFT_2_0 0x5A4
#define EMC_CMD_BRLSHFT_3_0 0x5A8
#define EMC_QUSE_BRLSHFT_0_0 0x5AC
#define EMC_AUTO_CAL_CONFIG4_0 0x5B0
#define EMC_AUTO_CAL_CONFIG5_0 0x5B4
#define EMC_QUSE_BRLSHFT_1_0 0x5B8
#define EMC_QUSE_BRLSHFT_2_0 0x5BC
#define EMC_CCDMW_0 0x5C0
#define EMC_QUSE_BRLSHFT_3_0 0x5C4
#define EMC_FBIO_CFG8_0 0x5C8
#define EMC_AUTO_CAL_CONFIG6_0 0x5CC
#define EMC_PROTOBIST_CONFIG_ADR_1_0 0x5D0
#define EMC_PROTOBIST_CONFIG_ADR_2_0 0x5D4
#define EMC_PROTOBIST_MISC_0 0x5D8
#define EMC_PROTOBIST_WDATA_LOWER_0 0x5DC
#define EMC_PROTOBIST_WDATA_UPPER_0 0x5E0
#define EMC_PROTOBIST_RDATA_0 0x5EC
#define EMC_DLL_CFG_0_0 0x5E4
#define EMC_DLL_CFG_1_0 0x5E8
#define EMC_CONFIG_SAMPLE_DELAY_0 0x5F0
#define EMC_CFG_UPDATE_0 0x5F4
#define EMC_PMACRO_QUSE_DDLL_RANK0_0_0 0x600
#define EMC_PMACRO_QUSE_DDLL_RANK0_1_0 0x604
#define EMC_PMACRO_QUSE_DDLL_RANK0_2_0 0x608
#define EMC_PMACRO_QUSE_DDLL_RANK0_3_0 0x60C
#define EMC_PMACRO_QUSE_DDLL_RANK0_4_0 0x610
#define EMC_PMACRO_QUSE_DDLL_RANK0_5_0 0x614
#define EMC_PMACRO_QUSE_DDLL_RANK1_0_0 0x620
#define EMC_PMACRO_QUSE_DDLL_RANK1_1_0 0x624
#define EMC_PMACRO_QUSE_DDLL_RANK1_2_0 0x628
#define EMC_PMACRO_QUSE_DDLL_RANK1_3_0 0x62C
#define EMC_PMACRO_QUSE_DDLL_RANK1_4_0 0x630
#define EMC_PMACRO_QUSE_DDLL_RANK1_5_0 0x634
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_0 0x640
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_0 0x644
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_0 0x648
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_0 0x64C
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_0 0x650
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_0 0x654
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_0 0x660
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_0 0x664
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_0 0x668
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_0 0x66C
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4_0 0x670
#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5_0 0x674
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0_0 0x680
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1_0 0x684
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2_0 0x688
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3_0 0x68C
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4_0 0x690
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5_0 0x694
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0_0 0x6A0
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1_0 0x6A4
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2_0 0x6A8
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3_0 0x6AC
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4_0 0x6B0
#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5_0 0x6B4
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0_0 0x6C0
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1_0 0x6C4
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2_0 0x6C8
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3_0 0x6CC
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4_0 0x6D0
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5_0 0x6D4
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0_0 0x6E0
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1_0 0x6E4
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2_0 0x6E8
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3_0 0x6EC
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4_0 0x6F0
#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5_0 0x6F4
#define EMC_PMACRO_AUTOCAL_CFG_0_0 0x700
#define EMC_PMACRO_AUTOCAL_CFG_1_0 0x704
#define EMC_PMACRO_AUTOCAL_CFG_2_0 0x708
#define EMC_PMACRO_TX_PWRD_0_0 0x720
#define EMC_PMACRO_TX_PWRD_1_0 0x724
#define EMC_PMACRO_TX_PWRD_2_0 0x728
#define EMC_PMACRO_TX_PWRD_3_0 0x72C
#define EMC_PMACRO_TX_PWRD_4_0 0x730
#define EMC_PMACRO_TX_PWRD_5_0 0x734
#define EMC_PMACRO_TX_SEL_CLK_SRC_0_0 0x740
#define EMC_PMACRO_TX_SEL_CLK_SRC_1_0 0x744
#define EMC_PMACRO_TX_SEL_CLK_SRC_2_0 0x748
#define EMC_PMACRO_TX_SEL_CLK_SRC_3_0 0x74C
#define EMC_PMACRO_TX_SEL_CLK_SRC_4_0 0x750
#define EMC_PMACRO_TX_SEL_CLK_SRC_5_0 0x754
#define EMC_PMACRO_DDLL_BYPASS_0 0x760
#define EMC_PMACRO_DDLL_PWRD_0_0 0x770
#define EMC_PMACRO_DDLL_PWRD_1_0 0x774
#define EMC_PMACRO_DDLL_PWRD_2_0 0x778
#define EMC_PMACRO_CMD_CTRL_0_0 0x780
#define EMC_PMACRO_CMD_CTRL_1_0 0x784
#define EMC_PMACRO_CMD_CTRL_2_0 0x788
#define MC_INTSTATUS_0 0x000
#define MC_INTMASK_0 0x004
#define MC_ERR_STATUS_0 0x008
#define MC_ERR_ADR_0 0x00C
#define MC_SMMU_CONFIG_0 0x010
#define MC_SMMU_PTB_ASID_0 0x01C
#define MC_SMMU_PTB_DATA_0 0x020
#define MC_SMMU_TLB_FLUSH_0 0x030
#define MC_SMMU_PTC_FLUSH_0_0 0x034
#define MC_EMEM_CFG_0 0x050
#define MC_EMEM_ADR_CFG_0 0x054
#define MC_EMEM_ARB_CFG_0 0x090
#define MC_EMEM_ARB_OUTSTANDING_REQ_0 0x094
#define MC_EMEM_ARB_TIMING_RCD_0 0x098
#define MC_EMEM_ARB_TIMING_RP_0 0x09C
#define MC_EMEM_ARB_TIMING_RC_0 0x0A0
#define MC_EMEM_ARB_TIMING_RAS_0 0x0A4
#define MC_EMEM_ARB_TIMING_FAW_0 0x0A8
#define MC_EMEM_ARB_TIMING_RRD_0 0x0AC
#define MC_EMEM_ARB_TIMING_RAP2PRE_0 0x0B0
#define MC_EMEM_ARB_TIMING_WAP2PRE_0 0x0B4
#define MC_EMEM_ARB_TIMING_R2R_0 0x0B8
#define MC_EMEM_ARB_TIMING_W2W_0 0x0BC
#define MC_EMEM_ARB_TIMING_R2W_0 0x0C0
#define MC_EMEM_ARB_TIMING_W2R_0 0x0C4
#define MC_EMEM_ARB_MISC2_0 0x0C8
#define MC_EMEM_ARB_DA_TURNS_0 0x0D0
#define MC_EMEM_ARB_DA_COVERS_0 0x0D4
#define MC_EMEM_ARB_MISC0_0 0x0D8
#define MC_EMEM_ARB_MISC1_0 0x0DC
#define MC_TIMING_CONTROL_0 0xFC
#define MC_EMEM_ARB_RING1_THROTTLE_0 0x0E0
#define MC_CLIENT_HOTRESET_CTRL_0 0x200
#define MC_CLIENT_HOTRESET_STATUS_0 0x204
#define MC_SMMU_AFI_ASID_0 0x238
#define MC_SMMU_DC_ASID_0 0x240
#define MC_SMMU_DCB_ASID_0 0x244
#define MC_SMMU_HC_ASID_0 0x250
#define MC_SMMU_HDA_ASID_0 0x254
#define MC_SMMU_ISP2_ASID_0 0x258
#define MC_SMMU_MSENC_NVENC_ASID_0 0x264
#define MC_SMMU_NV_ASID_0 0x268
#define MC_SMMU_NV2_ASID_0 0x26C
#define MC_SMMU_PPCS_ASID_0 0x270
#define MC_SMMU_SATA_ASID_0 0x274
#define MC_SMMU_VI_ASID_0 0x280
#define MC_SMMU_VIC_ASID_0 0x284
#define MC_SMMU_XUSB_HOST_ASID_0 0x288
#define MC_SMMU_XUSB_DEV_ASID_0 0x28C
#define MC_SMMU_TSEC_ASID_0 0x294
#define MC_LATENCY_ALLOWANCE_AVPC_0 0x2E4
#define MC_LATENCY_ALLOWANCE_DC_0 0x2E8
#define MC_LATENCY_ALLOWANCE_DC_1 0x2EC
#define MC_LATENCY_ALLOWANCE_DCB_0 0x2F4
#define MC_LATENCY_ALLOWANCE_DCB_1 0x2F8
#define MC_LATENCY_ALLOWANCE_HC_0 0x310
#define MC_LATENCY_ALLOWANCE_HC_1 0x314
#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320
#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328
#define MC_LATENCY_ALLOWANCE_PPCS_0 0x344
#define MC_LATENCY_ALLOWANCE_PPCS_1 0x348
#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370
#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374
#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37C
#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380
#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390
#define MC_LATENCY_ALLOWANCE_VIC_0 0x394
#define MC_LATENCY_ALLOWANCE_VI2_0 0x398
#define MC_LATENCY_ALLOWANCE_GPU_0 0x3AC
#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3B8
#define MC_LATENCY_ALLOWANCE_SDMMCAA_0 0x3BC
#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3C0
#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3C4
#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3D8
#define MC_LATENCY_ALLOWANCE_GPU2_0 0x3E8
#define MC_DIS_PTSA_RATE_0 0x41C
#define MC_DIS_PTSA_MIN_0 0x420
#define MC_DIS_PTSA_MAX_0 0x424
#define MC_DISB_PTSA_RATE_0 0x428
#define MC_DISB_PTSA_MIN_0 0x42C
#define MC_DISB_PTSA_MAX_0 0x430
#define MC_VE_PTSA_RATE_0 0x434
#define MC_VE_PTSA_MIN_0 0x438
#define MC_VE_PTSA_MAX_0 0x43C
#define MC_MLL_MPCORER_PTSA_RATE_0 0x44C
#define MC_RING1_PTSA_RATE_0 0x47C
#define MC_RING1_PTSA_MIN_0 0x480
#define MC_RING1_PTSA_MAX_0 0x484
#define MC_PCX_PTSA_RATE_0 0x4AC
#define MC_PCX_PTSA_MIN_0 0x4B0
#define MC_PCX_PTSA_MAX_0 0x4B4
#define MC_MSE_PTSA_RATE_0 0x4C4
#define MC_MSE_PTSA_MIN_0 0x4C8
#define MC_MSE_PTSA_MAX_0 0x4CC
#define MC_AHB_PTSA_RATE_0 0x4DC
#define MC_AHB_PTSA_MIN_0 0x4E0
#define MC_AHB_PTSA_MAX_0 0x4E4
#define MC_APB_PTSA_RATE_0 0x4E8
#define MC_APB_PTSA_MIN_0 0x4EC
#define MC_APB_PTSA_MAX_0 0x4F0
#define MC_FTOP_PTSA_RATE_0 0x50C
#define MC_HOST_PTSA_RATE_0 0x518
#define MC_HOST_PTSA_MIN_0 0x51C
#define MC_HOST_PTSA_MAX_0 0x520
#define MC_USBX_PTSA_RATE_0 0x524
#define MC_USBX_PTSA_MIN_0 0x528
#define MC_USBX_PTSA_MAX_0 0x52C
#define MC_USBD_PTSA_RATE_0 0x530
#define MC_USBD_PTSA_MIN_0 0x534
#define MC_USBD_PTSA_MAX_0 0x538
#define MC_GK_PTSA_RATE_0 0x53C
#define MC_GK_PTSA_MIN_0 0x540
#define MC_GK_PTSA_MAX_0 0x544
#define MC_AUD_PTSA_RATE_0 0x548
#define MC_AUD_PTSA_MIN_0 0x54C
#define MC_AUD_PTSA_MAX_0 0x550
#define MC_VICPC_PTSA_RATE_0 0x554
#define MC_VICPC_PTSA_MIN_0 0x558
#define MC_VICPC_PTSA_MAX_0 0x55C
#define MC_JPG_PTSA_RATE_0 0x584
#define MC_JPG_PTSA_MIN_0 0x588
#define MC_JPG_PTSA_MAX_0 0x58C
#define MC_GK2_PTSA_RATE_0 0x610
#define MC_GK2_PTSA_MIN_0 0x614
#define MC_GK2_PTSA_MAX_0 0x618
#define MC_SDM_PTSA_RATE_0 0x61C
#define MC_SDM_PTSA_MIN_0 0x620
#define MC_SDM_PTSA_MAX_0 0x624
#define MC_HDAPC_PTSA_RATE_0 0x628
#define MC_HDAPC_PTSA_MIN_0 0x62C
#define MC_HDAPC_PTSA_MAX_0 0x630
#define MC_SEC_CARVEOUT_BOM_0 0x670
#define MC_SEC_CARVEOUT_SIZE_MB_0 0x674
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 0x690
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 0x694
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 0x698
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 0x69C
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 0x6A0
#define MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 0x6A4
#define MC_EMEM_ARB_TIMING_RFCPB_0 0x6C0
#define MC_EMEM_ARB_TIMING_CCDMW_0 0x6C4
#define MC_EMEM_ARB_REFPB_HP_CTRL_0 0x6F0
#define MC_EMEM_ARB_REFPB_BANK_CTRL_0 0x6F4
#define MC_PTSA_GRANT_DECREMENT_0 0x960
#define MC_CLIENT_HOTRESET_CTRL_1 0x970
#define MC_CLIENT_HOTRESET_STATUS_1 0x974
#define MC_SMMU_PTC_FLUSH_1 0x9B8
#define MC_SMMU_DC1_ASID_0 0xA88
#define MC_SMMU_SDMMC1A_ASID_0 0xA94
#define MC_SMMU_SDMMC2A_ASID_0 0xA98
#define MC_SMMU_SDMMC3A_ASID_0 0xA9C
#define MC_SMMU_SDMMC4A_ASID_0 0xAA0
#define MC_SMMU_ISP2B_ASID_0 0xAA4
#define MC_SMMU_GPU_ASID_0 0xAA8
#define MC_SMMU_GPUB_ASID_0 0xAAC
#define MC_SMMU_PPCS2_ASID_0 0xAB0
#define MC_SMMU_NVDEC_ASID_0 0xAB4
#define MC_SMMU_APE_ASID_0 0xAB8
#define MC_SMMU_SE_ASID_0 0xABC
#define MC_SMMU_NVJPG_ASID_0 0xAC0
#define MC_SMMU_HC1_ASID_0 0xAC4
#define MC_SMMU_SE1_ASID_0 0xAC8
#define MC_SMMU_AXIAP_ASID_0 0xACC
#define MC_SMMU_ETR_ASID_0 0xAD0
#define MC_SMMU_TSECB_ASID_0 0xAD4
#define MC_SMMU_TSEC1_ASID_0 0xAD8
#define MC_SMMU_TSECB1_ASID_0 0xADC
#define MC_SMMU_NVDEC1_ASID_0 0xAE0
#define MC_EMEM_ARB_DHYST_CTRL_0 0xBCC
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xBD0
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xBD4
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xBD8
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xBDC
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xBE0
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xBE4
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xBE8
#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xBEC
#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_0 0xC00
#define MC_SECURITY_CARVEOUT2_BOM_0 0xC5C
#define MC_SECURITY_CARVEOUT3_BOM_0 0xCAC

2
Source/sys-clk/sysmodule/src/file_utils.h
View File

@@ -35,7 +35,7 @@
#include <sysclk.h>
#define FILE_CONFIG_DIR "/config/" TARGET
#define FILE_FLAG_CHECK_INTERVAL_NS 5000000000ULL
#define FILE_FLAG_CHECK_INTERVAL_NS (10000ULL * 1000000000ULL)
#define FILE_CONTEXT_CSV_PATH FILE_CONFIG_DIR "/context.csv"
#define FILE_LOG_FLAG_PATH FILE_CONFIG_DIR "/log.flag"
#define FILE_LOG_FILE_PATH FILE_CONFIG_DIR "/log.txt"