155 lines
4.9 KiB
C++
155 lines
4.9 KiB
C++
/*
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* Copyright (c) NVIDIA
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*
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* Copyright (c) Souldbminer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "gm20b.hpp"
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#include "../mapping/mem_map.hpp"
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namespace gm20b {
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u64 gpu_base = 0;
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#define GPU_PA 0x57000000
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#define GPU_SIZE 0x1000000
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#define GPU_TRIM_SYS_GPCPLL_CFG 0x00
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#define GPU_TRIM_SYS_GPCPLL_COEFF 0x04
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#define GPU_TRIM_SYS_GPCPLL_CFG3 0x0C
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#define GPU_TRIM_SYS_GPCPLL_DVFS1 0x14
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#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x1C
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#define GPU_TRIM_SYS_SEL_VCO 0x2C
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#define GPU_TRIM_SYS_GPC2CLK_OUT 0x250
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#define GPC_BCAST(x) (*(volatile u32 *)(gpu_base + 0x132800ul + (x)))
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#define GPU_TRIM_SYS_GPCPLL(x) (*(volatile u32 *)(gpu_base + 0x137000ul + (x)))
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#define GPC_BCAST_GPCPLL_DVFS2 0x20
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#define GPC_BCAST_NDIV_SLOWDOWN_DBG 0xa0
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#define GPCPLL_CFG_ENABLE BIT(0)
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#define GPCPLL_CFG_IDDQ BIT(1)
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#define GPCPLL_CFG_SYNC_MODE BIT(2)
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#define GPCPLL_CFG_LOCK BIT(17)
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#define GPCPLL_CFG2_SDM_DIN_MASK 0x000000FFu
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#define GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x007FFF00u
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#define GPCPLL_CFG2_STEPA_SHIFT 24
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#define GPCPLL_CFG2_STEPA_MASK 0xFF000000u
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#define GPCPLL_CFG3_STEPB_SHIFT 16
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#define GPCPLL_CFG3_STEPB_MASK 0x00FF0000u
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#define GPCPLL_DVFS0_DFS_COEFF_MASK 0x0000007Fu
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#define NDIV_SLOWDOWN_SLOWDOWN_USING_PLL BIT(22)
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#define NDIV_SLOWDOWN_EN_DYNRAMP BIT(23)
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#define DYNRAMP_DONE_SYNCED BIT(24)
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#define GPCPLL_DVFS2_DFS_EXT_STROBE BIT(16)
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#define RAMP_TIMEOUT_US 500
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static inline void _gpu_mask(u32 reg, u32 mask, u32 val) {
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u32 tmp = GPU_TRIM_SYS_GPCPLL(reg);
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GPU_TRIM_SYS_GPCPLL(reg) = (tmp & ~mask) | (val & mask);
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(void)GPU_TRIM_SYS_GPCPLL(reg);
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}
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static inline void _gbc_mask(u32 reg, u32 mask, u32 val) {
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u32 tmp = GPC_BCAST(reg);
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GPC_BCAST(reg) = (tmp & ~mask) | (val & mask);
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(void)GPC_BCAST(reg);
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}
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static void _clk_setup_slide() {
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_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2,
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GPCPLL_CFG2_STEPA_MASK,
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0x04u << GPCPLL_CFG2_STEPA_SHIFT);
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_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG3,
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GPCPLL_CFG3_STEPB_MASK,
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0x05u << GPCPLL_CFG3_STEPB_SHIFT);
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}
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static bool _gpu_pllg_slide(u32 new_divn) {
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u32 coeff = GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF);
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u32 cur_divn = (coeff >> 8) & 0xFF;
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if (new_divn == cur_divn)
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return true;
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_clk_setup_slide();
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_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN,
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NDIV_SLOWDOWN_SLOWDOWN_USING_PLL,
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NDIV_SLOWDOWN_SLOWDOWN_USING_PLL);
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_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_NEW_MASK, 0);
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coeff = (coeff & ~(0xFFu << 8)) | (new_divn << 8);
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usleep(1);
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GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF) = coeff;
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usleep(1);
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_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN,
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NDIV_SLOWDOWN_EN_DYNRAMP,
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NDIV_SLOWDOWN_EN_DYNRAMP);
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int ramp_timeout = RAMP_TIMEOUT_US;
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bool success = false;
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do {
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usleep(1);
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ramp_timeout--;
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if (GPC_BCAST(GPC_BCAST_NDIV_SLOWDOWN_DBG) & DYNRAMP_DONE_SYNCED) {
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success = true;
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break;
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}
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} while (ramp_timeout > 0);
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if (success) {
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_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_MASK, 0);
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}
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_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN,
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NDIV_SLOWDOWN_SLOWDOWN_USING_PLL | NDIV_SLOWDOWN_EN_DYNRAMP,
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0);
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(void)GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN);
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return success;
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}
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bool setClock(u32 khz) {
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if (!gpu_base)
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QueryMemoryMapping(&gpu_base, GPU_PA, GPU_SIZE);
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const u32 osc_khz = 38400; // PLL Hz
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u32 coeff = GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF);
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u32 divm = coeff & 0xFF;
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u32 divp = (coeff >> 16) & 0x3F;
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if (divm == 0 || divp == 0)
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return false;
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u32 new_divn = (u64)khz * divm * divp * 2 / osc_khz;
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// L4T clamps the registers here for some reason, do that
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if (new_divn < 8) new_divn = 8;
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if (new_divn > 255) new_divn = 255;
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return _gpu_pllg_slide(new_divn);
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}
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} |