153 lines
5.0 KiB
C++
153 lines
5.0 KiB
C++
/*
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* Copyright (c) 2019-2025 CTCaer
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* Copyright (c) Souldbminer, Lightos and Horizon OC Contributors
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#pragma once
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#include "regs.hpp"
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// NOTE: MMU won't allow access to gpu address space (smmu carveout issue?)
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namespace bpmpMmu {
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constexpr u32 CacheBase = 0x50040000;
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constexpr u32 CacheConfig = 0x000;
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constexpr u32 CfgEnableCache = (1u << 0);
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constexpr u32 CfgForceWriteThrough = (1u << 3);
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constexpr u32 CfgMmuTagModeShift = 8;
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constexpr u32 TagModeParallel = 0;
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constexpr u32 CfgTagChkAbrtOnErr = (1u << 14);
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constexpr u32 MaintReq = 0x028;
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constexpr u32 MaintReqWayBitmapAll = (0xFu << 8);
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constexpr u32 IntClear = 0x044;
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constexpr u32 IntRawEvent = 0x048;
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constexpr u32 IntMaintDone = (1u << 0);
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constexpr u32 MmuFallbackEntry = 0x0A0;
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constexpr u32 MmuShadowCopyMask = 0x0A4;
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constexpr u32 MmuCfg = 0x0AC;
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constexpr u32 MmuCfgSeqEn = (1u << 1);
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constexpr u32 MmuCfgTlbEn = (1u << 2);
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constexpr u32 MmuCfgAbortStoreLast = (1u << 4);
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constexpr u32 MmuCmd = 0x0B0;
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constexpr u32 MmuCmdInit = 1;
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constexpr u32 MmuCmdCopyShadow = 2;
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constexpr u32 ShadowEntryBase = CacheBase + 0x400;
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constexpr u32 MmuEnCached = (1u << 0);
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constexpr u32 MmuEnExec = (1u << 1);
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constexpr u32 MmuEnRead = (1u << 2);
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constexpr u32 MmuEnWrite = (1u << 3);
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constexpr u32 MaintCleanInvalidWay = 19;
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constexpr u32 MaintInvalidWay = 18;
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constexpr u32 CacheLineSize = 0x20;
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constexpr u32 DramStart = 0x80000000;
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constexpr u32 IramBase = 0x40000000;
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constexpr u32 IramEnd = 0x4003FFFF;
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struct MmuEntry {
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u32 startAddr;
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u32 endAddr;
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u32 attr;
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};
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constexpr MmuEntry Entries[] = {
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{ DramStart, 0xFFFFFFFF, MmuEnRead | MmuEnWrite | MmuEnExec | MmuEnCached },
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{ IramBase, IramEnd, MmuEnRead | MmuEnWrite | MmuEnExec | MmuEnCached },
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};
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inline u32 AlignUp(u32 x, u32 a) {
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return (x + a - 1) & ~(a - 1);
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}
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inline u32 AlignDown(u32 x, u32 a) {
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return x & ~(a - 1);
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}
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inline void Maintenance(u32 op, bool force) {
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if (!force && !(MMIO32(CacheBase + CacheConfig) & CfgEnableCache)) {
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return;
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}
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MMIO32(CacheBase + IntClear) = IntMaintDone;
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// Blocking operation.
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MMIO32(CacheBase + MaintReq) = MaintReqWayBitmapAll | op;
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while (!(MMIO32(CacheBase + IntRawEvent) & IntMaintDone))
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;
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MMIO32(CacheBase + IntClear) = MMIO32(CacheBase + IntRawEvent);
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}
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inline void SetEntry(u32 idx, const MmuEntry &entry) {
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MMIO32(ShadowEntryBase + sizeof(u32) * 4 * idx + 0x0) = AlignUp(entry.startAddr, CacheLineSize);
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MMIO32(ShadowEntryBase + sizeof(u32) * 4 * idx + 0x4) = AlignDown(entry.endAddr, CacheLineSize);
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MMIO32(ShadowEntryBase + sizeof(u32) * 4 * idx + 0x8) = entry.attr;
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MMIO32(CacheBase + MmuShadowCopyMask) |= (1u << idx);
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}
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inline void Enable() {
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if (MMIO32(CacheBase + CacheConfig) & CfgEnableCache) {
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return;
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}
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// Init BPMP MMU.
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MMIO32(CacheBase + MmuCmd) = MmuCmdInit;
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MMIO32(CacheBase + MmuFallbackEntry) = MmuEnRead | MmuEnWrite | MmuEnExec; // RWX for non-defined regions.
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MMIO32(CacheBase + MmuCfg) = MmuCfgSeqEn | MmuCfgTlbEn | MmuCfgAbortStoreLast;
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// Init BPMP MMU entries.
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MMIO32(CacheBase + MmuShadowCopyMask) = 0;
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for (u32 idx = 0; idx < sizeof(Entries) / sizeof(Entries[0]); idx++) {
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SetEntry(idx, Entries[idx]);
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}
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MMIO32(CacheBase + MmuCmd) = MmuCmdCopyShadow;
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// Invalidate cache.
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Maintenance(MaintInvalidWay, true);
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// Enable cache.
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MMIO32(CacheBase + CacheConfig) = CfgEnableCache | CfgForceWriteThrough |
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(TagModeParallel << CfgMmuTagModeShift) | CfgTagChkAbrtOnErr;
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// HW bug. Invalidate cache again.
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Maintenance(MaintInvalidWay, false);
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}
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inline void Disable() {
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if (!(MMIO32(CacheBase + CacheConfig) & CfgEnableCache)) {
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return;
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}
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// Clean and invalidate cache.
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Maintenance(MaintCleanInvalidWay, false);
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// Disable cache.
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MMIO32(CacheBase + CacheConfig) = 0;
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}
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} // namespace bpmpMmu
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