diff --git a/Source/hoc-clk/sysmodule/src/soc/registers.h b/Source/hoc-clk/sysmodule/src/soc/registers.h index 6a2f3564..8e2be21d 100644 --- a/Source/hoc-clk/sysmodule/src/soc/registers.h +++ b/Source/hoc-clk/sysmodule/src/soc/registers.h @@ -3849,154 +3849,154 @@ #define GPU_TOP_DEVICE_INFO_DATA_FAULT_ID_FIELDMASK 0x00000001 #define GPU_TOP_DEVICE_INFO_DATA_FAULT_ID_VALID_V 0x00000001 -#define TRIM_SYS_GPCPLL_CFG 0x00137000 -#define TRIM_SYS_GPCPLL_CFG_ENABLE_MASK 0x00000001 -#define TRIM_SYS_GPCPLL_CFG_ENABLE_SHIFT 0x00000000 -#define TRIM_SYS_GPCPLL_CFG_ENABLE_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_CFG_ENABLE_NO_F 0x00000000 -#define TRIM_SYS_GPCPLL_CFG_ENABLE_YES_F 0x00000001 -#define TRIM_SYS_GPCPLL_CFG_IDDQ_MASK 0x00000002 -#define TRIM_SYS_GPCPLL_CFG_IDDQ_SHIFT 0x00000001 -#define TRIM_SYS_GPCPLL_CFG_IDDQ_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON_V 0x00000000 -#define TRIM_SYS_GPCPLL_CFG_SYNC_MODE_MASK 0x00000004 -#define TRIM_SYS_GPCPLL_CFG_SYNC_MODE_SHIFT 0x00000002 -#define TRIM_SYS_GPCPLL_CFG_SYNC_MODE_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE_F 0x00000004 -#define TRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE_F 0x00000000 -#define TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_MASK 0x00000010 -#define TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_SHIFT 0x00000004 -#define TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON_F 0x00000000 -#define TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF_F 0x00000010 -#define TRIM_SYS_GPCPLL_CFG_PLL_LOCK_SHIFT 0x00000011 -#define TRIM_SYS_GPCPLL_CFG_PLL_LOCK_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_CFG_PLL_LOCK_TRUE_F 0x00020000 -#define TRIM_SYS_GPCPLL_COEFF 0x00137004 -#define TRIM_SYS_GPCPLL_COEFF_MDIV_SHIFT 0x00000000 -#define TRIM_SYS_GPCPLL_COEFF_MDIV_FIELDMASK 0x000000ff -#define TRIM_SYS_GPCPLL_COEFF_MDIV_MASK 0x000000ff -#define TRIM_SYS_GPCPLL_COEFF_NDIV_SHIFT 0x00000008 -#define TRIM_SYS_GPCPLL_COEFF_NDIV_FIELDMASK 0x000000ff -#define TRIM_SYS_GPCPLL_COEFF_NDIV_MASK 0x0000ff00 -#define TRIM_SYS_GPCPLL_COEFF_PLDIV_SHIFT 0x00000010 -#define TRIM_SYS_GPCPLL_COEFF_PLDIV_FIELDMASK 0x0000003f -#define TRIM_SYS_GPCPLL_COEFF_PLDIV_MASK 0x003f0000 -#define TRIM_SYS_SEL_VCO 0x00137100 -#define TRIM_SYS_SEL_VCO_GPC2CLK_OUT_MASK 0x00000001 -#define TRIM_SYS_SEL_VCO_GPC2CLK_OUT_SHIFT 0x00000000 -#define TRIM_SYS_SEL_VCO_GPC2CLK_OUT_FIELDMASK 0x00000001 -#define TRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT_V 0x00000000 -#define TRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT_F 0x00000000 -#define TRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS_F 0x00000000 -#define TRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO_F 0x00000001 -#define TRIM_SYS_GPC2CLK_OUT 0x00137250 -#define TRIM_SYS_GPC2CLK_OUT_BYPDIV_SIZE 0x00000006 -#define TRIM_SYS_GPC2CLK_OUT_BYPDIV_SHIFT 0x00000000 -#define TRIM_SYS_GPC2CLK_OUT_BYPDIV_FIELDMASK 0x0000003f -#define TRIM_SYS_GPC2CLK_OUT_BYPDIV_MASK 0x0000003f -#define TRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31_F 0x0000003c -#define TRIM_SYS_GPC2CLK_OUT_VCODIV_SIZE 0x00000006 -#define TRIM_SYS_GPC2CLK_OUT_VCODIV_SHIFT 0x00000008 -#define TRIM_SYS_GPC2CLK_OUT_VCODIV_FIELDMASK 0x0000003f -#define TRIM_SYS_GPC2CLK_OUT_VCODIV_MASK 0x00003f00 -#define TRIM_SYS_GPC2CLK_OUT_VCODIV_BY1_F 0x00000000 -#define TRIM_SYS_GPC2CLK_OUT_SDIV14_MASK 0x80000000 -#define TRIM_SYS_GPC2CLK_OUT_SDIV14_SHIFT 0x0000001f -#define TRIM_SYS_GPC2CLK_OUT_SDIV14_FIELDMASK 0x00000001 -#define TRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE_F 0x80000000 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG__BASE 0x00134124 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG__STRIDE 0x00000200 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x00134124 + (i) * 0x00000200) -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS_SHIFT 0x00000000 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS_FIELDMASK 0x00003fff -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED_F 0x00010000 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED_F 0x00100000 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED_F 0x01000000 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT__BASE 0x00134128 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT__STRIDE 0x00000200 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x00134128 + (i) * 0x00000200) -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE_SHIFT 0x00000000 -#define TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE_FIELDMASK 0x000fffff -#define TRIM_SYS_GPCPLL_CFG2 0x0013700c -#define TRIM_SYS_GPCPLL_CFG2_SDM_DIN_SHIFT 0x00000000 -#define TRIM_SYS_GPCPLL_CFG2_SDM_DIN_FIELDMASK 0x000000ff -#define TRIM_SYS_GPCPLL_CFG2_SDM_DIN_MASK 0x000000ff -#define TRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW_SHIFT 0x00000008 -#define TRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW_FIELDMASK 0x000000ff -#define TRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x0000ff00 -#define TRIM_SYS_GPCPLL_CFG2_PLL_STEPA_SHIFT 0x00000018 -#define TRIM_SYS_GPCPLL_CFG2_PLL_STEPA_FIELDMASK 0x000000ff -#define TRIM_SYS_GPCPLL_CFG2_PLL_STEPA_MASK 0xff000000 -#define TRIM_SYS_GPCPLL_CFG3 0x00137018 -#define TRIM_SYS_GPCPLL_CFG3_VCO_CTRL_SHIFT 0x00000000 -#define TRIM_SYS_GPCPLL_CFG3_VCO_CTRL_FIELDMASK 0x000001ff -#define TRIM_SYS_GPCPLL_CFG3_VCO_CTRL_MASK 0x000001ff -#define TRIM_SYS_GPCPLL_CFG3_PLL_STEPB_SHIFT 0x00000010 -#define TRIM_SYS_GPCPLL_CFG3_PLL_STEPB_FIELDMASK 0x000000ff -#define TRIM_SYS_GPCPLL_CFG3_PLL_STEPB_MASK 0x00ff0000 -#define TRIM_SYS_GPCPLL_CFG3_DFS_TESTOUT_SHIFT 0x00000018 -#define TRIM_SYS_GPCPLL_CFG3_DFS_TESTOUT_FIELDMASK 0x0000007f -#define TRIM_SYS_GPCPLL_DVFS0 0x00137010 -#define TRIM_SYS_GPCPLL_DVFS0_DFS_COEFF_SHIFT 0x00000000 -#define TRIM_SYS_GPCPLL_DVFS0_DFS_COEFF_FIELDMASK 0x0000007f -#define TRIM_SYS_GPCPLL_DVFS0_DFS_COEFF_MASK 0x0000007f -#define TRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX_SHIFT 0x00000008 -#define TRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX_FIELDMASK 0x0000007f -#define TRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX_MASK 0x00007f00 -#define TRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET_SHIFT 0x00000010 -#define TRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET_FIELDMASK 0x0000003f -#define TRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET_MASK 0x003f0000 -#define TRIM_SYS_GPCPLL_DVFS0_MODE_MASK 0x10000000 -#define TRIM_SYS_GPCPLL_DVFS0_MODE_SHIFT 0x0000001c -#define TRIM_SYS_GPCPLL_DVFS0_MODE_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_DVFS0_MODE_DVFSPLL_F 0x00000000 -#define TRIM_SYS_GPCPLL_DVFS1 0x00137014 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_DET_SHIFT 0x00000000 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_DET_FIELDMASK 0x0000007f -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_DET_MASK 0x0000007f -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_STRB_MASK 0x00000080 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_STRB_SHIFT 0x00000007 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_STRB_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_CAL_SHIFT 0x00000008 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_CAL_FIELDMASK 0x0000007f -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_CAL_MASK 0x00007f00 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_SEL_MASK 0x00008000 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_SEL_SHIFT 0x0000000f -#define TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_SEL_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_CTRL_SHIFT 0x00000010 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_CTRL_FIELDMASK 0x00000fff -#define TRIM_SYS_GPCPLL_DVFS1_DFS_CTRL_MASK 0x0fff0000 -#define TRIM_SYS_GPCPLL_DVFS1_EN_SDM_MASK 0x10000000 -#define TRIM_SYS_GPCPLL_DVFS1_EN_SDM_SHIFT 0x0000001c -#define TRIM_SYS_GPCPLL_DVFS1_EN_SDM_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_DVFS1_EN_DFS_MASK 0x20000000 -#define TRIM_SYS_GPCPLL_DVFS1_EN_DFS_SHIFT 0x0000001d -#define TRIM_SYS_GPCPLL_DVFS1_EN_DFS_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_DVFS1_EN_DFS_CAL_MASK 0x40000000 -#define TRIM_SYS_GPCPLL_DVFS1_EN_DFS_CAL_SHIFT 0x0000001e -#define TRIM_SYS_GPCPLL_DVFS1_EN_DFS_CAL_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_DVFS1_DFS_CAL_DONE_SHIFT 0x0000001f -#define TRIM_SYS_GPCPLL_DVFS1_DFS_CAL_DONE_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_DVFS2 0x00137020 -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x0013701c -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_MASK 0x00400000 -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 0x00000016 -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_YES_F 0x00400000 -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_NO_F 0x00000000 -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_MASK 0x80000000 -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 0x0000001f -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_FIELDMASK 0x00000001 -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_YES_F 0x80000000 -#define TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_NO_F 0x00000000 -#define TRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG 0x001328a0 -#define TRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 0x00000018 -#define TRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_FIELDMASK 0x00000001 -#define TRIM_GPC_BCAST_GPCPLL_DVFS2 0x00132820 -#define TRIM_SYS_BYPASSCTRL 0x00137340 -#define TRIM_SYS_BYPASSCTRL_GPCPLL_MASK 0x00000001 -#define TRIM_SYS_BYPASSCTRL_GPCPLL_SHIFT 0x00000000 -#define TRIM_SYS_BYPASSCTRL_GPCPLL_FIELDMASK 0x00000001 -#define TRIM_SYS_BYPASSCTRL_GPCPLL_BYPASSCLK_F 0x00000001 -#define TRIM_SYS_BYPASSCTRL_GPCPLL_VCO_F 0x00000000 \ No newline at end of file +#define GPU_TRIM_SYS_GPCPLL_CFG 0x00137000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_MASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_NO_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENABLE_YES_F 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_IDDQ_MASK 0x00000002 +#define GPU_TRIM_SYS_GPCPLL_CFG_IDDQ_SHIFT 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_IDDQ_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON_V 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_MASK 0x00000004 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_SHIFT 0x00000002 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE_F 0x00000004 +#define GPU_TRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_MASK 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_SHIFT 0x00000004 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_ON_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG_ENB_LCKDET_POWER_OFF_F 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_CFG_PLL_LOCK_SHIFT 0x00000011 +#define GPU_TRIM_SYS_GPCPLL_CFG_PLL_LOCK_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_CFG_PLL_LOCK_TRUE_F 0x00020000 +#define GPU_TRIM_SYS_GPCPLL_COEFF 0x00137004 +#define GPU_TRIM_SYS_GPCPLL_COEFF_MDIV_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_COEFF_MDIV_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_COEFF_MDIV_MASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_COEFF_NDIV_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPCPLL_COEFF_NDIV_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_COEFF_NDIV_MASK 0x0000ff00 +#define GPU_TRIM_SYS_GPCPLL_COEFF_PLDIV_SHIFT 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_COEFF_PLDIV_FIELDMASK 0x0000003f +#define GPU_TRIM_SYS_GPCPLL_COEFF_PLDIV_MASK 0x003f0000 +#define GPU_TRIM_SYS_SEL_VCO 0x00137100 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_MASK 0x00000001 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_SHIFT 0x00000000 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT_V 0x00000000 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_INIT_F 0x00000000 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_BYPASS_F 0x00000000 +#define GPU_TRIM_SYS_SEL_VCO_GPC2CLK_OUT_VCO_F 0x00000001 +#define GPU_TRIM_SYS_GPC2CLK_OUT 0x00137250 +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_SIZE 0x00000006 +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_FIELDMASK 0x0000003f +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_MASK 0x0000003f +#define GPU_TRIM_SYS_GPC2CLK_OUT_BYPDIV_BY31_F 0x0000003c +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_SIZE 0x00000006 +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_FIELDMASK 0x0000003f +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_MASK 0x00003f00 +#define GPU_TRIM_SYS_GPC2CLK_OUT_VCODIV_BY1_F 0x00000000 +#define GPU_TRIM_SYS_GPC2CLK_OUT_SDIV14_MASK 0x80000000 +#define GPU_TRIM_SYS_GPC2CLK_OUT_SDIV14_SHIFT 0x0000001f +#define GPU_TRIM_SYS_GPC2CLK_OUT_SDIV14_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPC2CLK_OUT_SDIV14_INDIV4_MODE_F 0x80000000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG__BASE 0x00134124 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG__STRIDE 0x00000200 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG(i) (0x00134124 + (i) * 0x00000200) +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS_SHIFT 0x00000000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_NOOFIPCLKS_FIELDMASK 0x00003fff +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_WRITE_EN_ASSERTED_F 0x00010000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_ENABLE_ASSERTED_F 0x00100000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED_F 0x01000000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT__BASE 0x00134128 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT__STRIDE 0x00000200 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT(i) (0x00134128 + (i) * 0x00000200) +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE_SHIFT 0x00000000 +#define GPU_TRIM_GPC_CLK_CNTR_NCGPCCLK_CNT_VALUE_FIELDMASK 0x000fffff +#define GPU_TRIM_SYS_GPCPLL_CFG2 0x0013700c +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_MASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x0000ff00 +#define GPU_TRIM_SYS_GPCPLL_CFG2_PLL_STEPA_SHIFT 0x00000018 +#define GPU_TRIM_SYS_GPCPLL_CFG2_PLL_STEPA_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG2_PLL_STEPA_MASK 0xff000000 +#define GPU_TRIM_SYS_GPCPLL_CFG3 0x00137018 +#define GPU_TRIM_SYS_GPCPLL_CFG3_VCO_CTRL_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_CFG3_VCO_CTRL_FIELDMASK 0x000001ff +#define GPU_TRIM_SYS_GPCPLL_CFG3_VCO_CTRL_MASK 0x000001ff +#define GPU_TRIM_SYS_GPCPLL_CFG3_PLL_STEPB_SHIFT 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_CFG3_PLL_STEPB_FIELDMASK 0x000000ff +#define GPU_TRIM_SYS_GPCPLL_CFG3_PLL_STEPB_MASK 0x00ff0000 +#define GPU_TRIM_SYS_GPCPLL_CFG3_DFS_TESTOUT_SHIFT 0x00000018 +#define GPU_TRIM_SYS_GPCPLL_CFG3_DFS_TESTOUT_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS0 0x00137010 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_COEFF_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_COEFF_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_COEFF_MASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DET_MAX_MASK 0x00007f00 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET_SHIFT 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET_FIELDMASK 0x0000003f +#define GPU_TRIM_SYS_GPCPLL_DVFS0_DFS_DC_OFFSET_MASK 0x003f0000 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_MODE_MASK 0x10000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_MODE_SHIFT 0x0000001c +#define GPU_TRIM_SYS_GPCPLL_DVFS0_MODE_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS0_MODE_DVFSPLL_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1 0x00137014 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_DET_SHIFT 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_DET_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_DET_MASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_STRB_MASK 0x00000080 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_STRB_SHIFT 0x00000007 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_STRB_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_CAL_SHIFT 0x00000008 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_CAL_FIELDMASK 0x0000007f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_CAL_MASK 0x00007f00 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_SEL_MASK 0x00008000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_SEL_SHIFT 0x0000000f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_EXT_SEL_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CTRL_SHIFT 0x00000010 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CTRL_FIELDMASK 0x00000fff +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CTRL_MASK 0x0fff0000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_SDM_MASK 0x10000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_SDM_SHIFT 0x0000001c +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_SDM_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_MASK 0x20000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_SHIFT 0x0000001d +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_CAL_MASK 0x40000000 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_CAL_SHIFT 0x0000001e +#define GPU_TRIM_SYS_GPCPLL_DVFS1_EN_DFS_CAL_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CAL_DONE_SHIFT 0x0000001f +#define GPU_TRIM_SYS_GPCPLL_DVFS1_DFS_CAL_DONE_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_DVFS2 0x00137020 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x0013701c +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_MASK 0x00400000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 0x00000016 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_YES_F 0x00400000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_NO_F 0x00000000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_MASK 0x80000000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 0x0000001f +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_YES_F 0x80000000 +#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_NO_F 0x00000000 +#define GPU_TRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG 0x001328a0 +#define GPU_TRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 0x00000018 +#define GPU_TRIM_GPC_BCAST_GPCPLL_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_FIELDMASK 0x00000001 +#define GPU_TRIM_GPC_BCAST_GPCPLL_DVFS2 0x00132820 +#define GPU_TRIM_SYS_BYPASSCTRL 0x00137340 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_MASK 0x00000001 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_SHIFT 0x00000000 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_FIELDMASK 0x00000001 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_BYPASSCLK_F 0x00000001 +#define GPU_TRIM_SYS_BYPASSCTRL_GPCPLL_VCO_F 0x00000000 \ No newline at end of file