real freqs + ram load on bpmp
gpu freq is excluded due to smmu issue (carveout?)
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@@ -1,297 +0,0 @@
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/*
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* Copyright (c) 2020-2023 CTCaer
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* Copyright (c) 2023 p-sam
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* Copyright (c) 2023 Lineon
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* Copyright (c) 2026 Souldbminer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "t210.h"
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#define WAIT_NS 1000000000UL
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#define usleep(x) svcSleepThread(1000UL * x)
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#define GPU_TRIM_SYS_GPCPLL_COEFF 0x4
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#define GPU_TRIM_SYS_GPCPLL(x) (*(volatile u32 *)(g_gpu_base + 0x137000ul + (x)))
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#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL 0x60
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#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS 0x64
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#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
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#define CLK_RST_CONTROLLER_RST_DEVICES_X 0x28C
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/*! PTO_CLK_CNT */
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#define PTO_REF_CLK_WIN_CFG_MASK 0xF
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#define PTO_REF_CLK_WIN_CFG_16P 0xF
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#define PTO_CNT_EN BIT(9)
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#define PTO_CNT_RST BIT(10)
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#define PTO_CLK_ENABLE BIT(13)
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#define PTO_SRC_SEL_SHIFT 14
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#define PTO_SRC_SEL_MASK 0x1FF
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#define PTO_DIV_SEL_MASK (3 << 23)
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#define PTO_DIV_SEL_GATED (0 << 23)
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#define PTO_DIV_SEL_DIV1 (1 << 23)
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#define PTO_DIV_SEL_DIV2_RISING (2 << 23)
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#define PTO_DIV_SEL_DIV2_FALLING (3 << 23)
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#define PTO_DIV_SEL_CPU_EARLY (0 << 23)
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#define PTO_DIV_SEL_CPU_LATE (1 << 23)
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#define PTO_CLK_CNT_BUSY BIT(31)
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#define PTO_CLK_CNT 0xFFFFFF
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#define CLK_PTO_CCLK_G_DIV2 0x13
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#define CLK_PTO_EMC 0x24
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#define CLOCK(x) (*(volatile u32 *)(g_clk_base + (x)))
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/* Actmon Global registers */
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#define ACTMON_GLB_STATUS 0x0
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#define ACTMON_MCCPU_MON_ACT BIT(8)
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#define ACTMON_MCALL_MON_ACT BIT(9)
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#define ACTMON_CPU_FREQ_MON_ACT BIT(10)
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#define ACTMON_BPMP_MON_ACT BIT(14)
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#define ACTMON_CPU_MON_ACT BIT(15)
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#define ACTMON_GLB_PERIOD_CTRL 0x4
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#define ACTMON_GLB_PERIOD_USEC BIT(8)
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#define ACTMON_GLB_PERIOD_SAMPLE(n) (((n) - 1) & 0xFF)
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/* Actmon Device Registers */
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#define ACTMON_DEV_SIZE 0x40
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/* Actmon CTRL */
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#define ACTMON_DEV_CTRL_K_VAL(k) (((k) & 7) << 10)
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#define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18)
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#define ACTMON_DEV_CTRL_ENB BIT(31)
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#define ACTMON_PERIOD_MS 20
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#define DEV_COUNT_WEIGHT 1024
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#define ACTMON_BASE (g_act_base + 0x800)
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#define ACTMON_DEV_BASE (ACTMON_BASE + 0x80)
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#define ACTMON(x) (*(volatile u32 *)(ACTMON_BASE + (x)))
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typedef enum _actmon_dev_t {
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ACTMON_DEV_CPU,
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ACTMON_DEV_BPMP,
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ACTMON_DEV_AHB,
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ACTMON_DEV_APB,
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ACTMON_DEV_CPU_FREQ,
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ACTMON_DEV_MC_ALL,
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ACTMON_DEV_MC_CPU,
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ACTMON_DEV_NUM,
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} actmon_dev_t;
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typedef struct _actmon_dev_reg_t {
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vu32 ctrl;
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vu32 upper_wnark;
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vu32 lower_wmark;
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vu32 init_avg;
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vu32 avg_upper_wmark;
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vu32 avg_lower_wmark;
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vu32 count_weight;
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vu32 count;
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vu32 avg_count;
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vu32 intr_status;
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vu32 ctrl2;
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vu32 rsvd[5];
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} actmon_dev_reg_t;
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static uintptr_t g_clk_base = 0;
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static uintptr_t g_gpu_base = 0;
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static uintptr_t g_act_base = 0;
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static u64 g_update_ticks = 0;
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static u32 g_cpu_freq = 0;
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static u32 g_gpu_freq = 0;
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static u32 g_mem_freq = 0;
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static u32 g_emc_lall = 0;
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static u32 g_emc_lcpu = 0;
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static u32 g_emc_bw_all = 0;
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static u32 g_emc_bw_cpu = 0;
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static u32 g_emc_bw_gpu = 0;
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static u32 _clock_get_dev_freq(u32 id, u32 multiplier) {
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const u32 pto_win = 16;
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const u32 pto_osc = 32768;
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u32 val = ((id & PTO_SRC_SEL_MASK) << PTO_SRC_SEL_SHIFT) | PTO_DIV_SEL_DIV1 | PTO_CLK_ENABLE | (pto_win - 1);
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CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val;
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(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
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usleep(2);
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CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val | PTO_CNT_RST;
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(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
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usleep(2);
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CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val;
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(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
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usleep(2);
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CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val | PTO_CNT_EN;
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(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
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usleep((1000000ULL * pto_win / pto_osc) + 12 + 2); // 502 us.
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while (CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS) & PTO_CLK_CNT_BUSY)
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;
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u32 cnt = CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS) & PTO_CLK_CNT;
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CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = 0;
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(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
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usleep(2);
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u32 freq_khz = (u64)cnt * multiplier * pto_osc / pto_win;
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return freq_khz;
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}
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static void _actmon_dev_enable(actmon_dev_t dev, u32 freq, u32 weight) {
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actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
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regs->init_avg = (u32)freq * ACTMON_PERIOD_MS / 2;
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regs->count_weight = weight;
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regs->ctrl = ACTMON_DEV_CTRL_ENB | ACTMON_DEV_CTRL_ENB_PERIODIC | ACTMON_DEV_CTRL_K_VAL(3); // 8 samples average.
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}
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static u32 _actmon_dev_get_count_avg(actmon_dev_t dev) {
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actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
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return regs->avg_count;
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}
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static inline Result _svcQueryMemoryMappingFallback(u64 *virtaddr, u64 physaddr, u64 size) {
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if (hosversionAtLeast(10, 0, 0)) {
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u64 out_size;
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return svcQueryMemoryMapping(virtaddr, &out_size, physaddr, size);
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} else {
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return svcLegacyQueryIoMapping(virtaddr, physaddr, size);
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}
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}
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static void _clock_update_freqs(void) {
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u64 ticks = armGetSystemTick();
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if (armTicksToNs(ticks - g_update_ticks) <= WAIT_NS) {
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return;
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}
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g_update_ticks = ticks;
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if (!g_clk_base) {
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_svcQueryMemoryMappingFallback(&g_clk_base, 0x60006000ul, 0x1000);
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}
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if (!g_clk_base) {
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return;
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}
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g_mem_freq = _clock_get_dev_freq(CLK_PTO_EMC, 1);
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g_cpu_freq = _clock_get_dev_freq(CLK_PTO_CCLK_G_DIV2, 2);
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if (!g_gpu_base) {
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_svcQueryMemoryMappingFallback(&g_gpu_base, 0x57000000ul, 0x1000000);
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}
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if (!g_gpu_base) {
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return;
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}
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bool gpu_enabled = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) & BIT(24)) && !(CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_X) & BIT(24));
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if (!gpu_enabled) {
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return;
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}
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if (!g_act_base) {
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_svcQueryMemoryMappingFallback(&g_act_base, 0x6000C000ul, 0x1000);
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}
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if (!g_act_base) {
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return;
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}
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const u32 osc = 38400000;
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u32 coeff = GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF);
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u32 divm = coeff & 0xFF;
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u32 divn = (coeff >> 8) & 0xFF;
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u32 divp = (coeff >> 16) & 0x3F;
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g_gpu_freq = osc * divn / (divm * divp) / 2;
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u32 emc_freq = g_mem_freq / 1000;
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// Check if actmon is disabled
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if (!(ACTMON(ACTMON_GLB_STATUS) & ACTMON_MCALL_MON_ACT)) {
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ACTMON(ACTMON_GLB_PERIOD_CTRL) = ACTMON_GLB_PERIOD_SAMPLE(ACTMON_PERIOD_MS);
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_actmon_dev_enable(ACTMON_DEV_MC_ALL, emc_freq, 256 * 4);
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}
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// Check if actmon is disabled
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if (!(ACTMON(ACTMON_GLB_STATUS) & ACTMON_MCCPU_MON_ACT))
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_actmon_dev_enable(ACTMON_DEV_MC_CPU, emc_freq, 256 * 4);
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// Get 1000 -> 100.0.
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g_emc_lall = (u64)_actmon_dev_get_count_avg(ACTMON_DEV_MC_ALL) * 10 * 100 / (emc_freq * ACTMON_PERIOD_MS);
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g_emc_lcpu = (u64)_actmon_dev_get_count_avg(ACTMON_DEV_MC_CPU) * 10 * 100 / (emc_freq * ACTMON_PERIOD_MS);
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// TODO: use PLL instead of actmon
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// Avoid floating point arithematic
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g_emc_bw_all = (u64)emc_freq * 16 * g_emc_lall / 1000000;
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g_emc_bw_cpu = (u64)emc_freq * 16 * g_emc_lcpu / 1000000;
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// Not 100% accurate but should be enough
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g_emc_bw_gpu = g_emc_bw_all - g_emc_bw_cpu;
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}
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u32 t210ClkCpuFreq(void) {
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_clock_update_freqs();
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return g_cpu_freq;
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}
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u32 t210ClkMemFreq(void) {
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_clock_update_freqs();
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return g_mem_freq;
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}
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u32 t210ClkGpuFreq(void) {
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_clock_update_freqs();
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return g_gpu_freq;
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}
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u32 t210EmcLoadAll() {
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_clock_update_freqs();
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return g_emc_lall;
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}
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u32 t210EmcLoadCpu() {
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_clock_update_freqs();
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return g_emc_lcpu;
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}
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u32 t210EmcBwAll() {
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_clock_update_freqs();
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return g_emc_bw_all;
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}
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u32 t210EmcBwCpu() {
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_clock_update_freqs();
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return g_emc_bw_cpu;
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}
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u32 t210EmcBwGpu() {
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_clock_update_freqs();
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return g_emc_bw_gpu;
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}
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u32 t210EmcBwPeak() {
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_clock_update_freqs();
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return ((u64)g_mem_freq * 16) / 1000000;
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}
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@@ -1,47 +0,0 @@
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/*
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* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/* --------------------------------------------------------------------------
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* "THE BEER-WARE LICENSE" (Revision 42):
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* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
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* wrote this file. As long as you retain this notice you can do whatever you
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* want with this stuff. If you meet any of us some day, and you think this
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* stuff is worth it, you can buy us a beer in return. - The sys-clk authors
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* --------------------------------------------------------------------------
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <switch.h>
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u32 t210ClkCpuFreq(void);
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u32 t210ClkMemFreq(void);
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u32 t210ClkGpuFreq(void);
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u32 t210EmcLoadAll(void);
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u32 t210EmcLoadCpu(void);
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u32 t210EmcBwAll(void);
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u32 t210EmcBwCpu(void);
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u32 t210EmcBwGpu(void);
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u32 t210EmcBwPeak(void);
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#ifdef __cplusplus
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}
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#endif
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