real freqs + ram load on bpmp
gpu freq is excluded due to smmu issue (carveout?)
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@@ -0,0 +1,99 @@
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/*
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* Copyright (c) Souldbminer, Lightos and Horizon OC Contributors
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#pragma once
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#include "freq.hpp"
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#include "regs.hpp"
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#include <hocclk/bpmp.h>
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namespace actmon {
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constexpr u32 ActmonBase = 0x6000C800;
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constexpr u32 ActmonDevBase = ActmonBase + 0x80;
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constexpr u32 ActmonDevSize = 0x40;
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constexpr u32 ActmonGlbStatus = 0x0;
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constexpr u32 ActmonGlbPeriodCtrl = 0x4;
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constexpr u32 ActmonMccpuMonAct = (1u << 8);
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constexpr u32 ActmonMcallMonAct = (1u << 9);
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constexpr u32 ActmonDevCtrlKVal3 = (3u << 10);
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constexpr u32 ActmonDevCtrlEnbPeriodic = (1u << 18);
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constexpr u32 ActmonDevCtrlEnb = (1u << 31);
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constexpr u32 ActmonPeriodMs = 20;
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enum ActmonDev : u32 {
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DevCpu = 0,
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DevBpmp,
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DevAhb,
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DevApb,
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DevCpuFreq,
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DevMcAll,
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DevMcCpu,
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};
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constexpr u32 DevCtrl = 0x00;
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constexpr u32 DevInitAvg = 0x0C;
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constexpr u32 DevCountWeight = 0x18;
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constexpr u32 DevAvgCount = 0x20;
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inline u32 DevReg(ActmonDev dev, u32 off) {
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return ActmonDevBase + (static_cast<u32>(dev) * ActmonDevSize) + off;
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}
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inline void EnableDev(ActmonDev dev, u32 freqKhz, u32 weight) {
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MMIO32(DevReg(dev, DevInitAvg)) = freqKhz * ActmonPeriodMs / 2;
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MMIO32(DevReg(dev, DevCountWeight)) = weight;
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MMIO32(DevReg(dev, DevCtrl)) = ActmonDevCtrlEnb | ActmonDevCtrlEnbPeriodic | ActmonDevCtrlKVal3;
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}
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inline void Init() {
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const u32 emcFreqKhz = static_cast<u32>(freq::MeasurePtoFreqHz(freq::ClkPtoEmc, 1) / 1000);
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if (!(MMIO32(ActmonBase + ActmonGlbStatus) & ActmonMcallMonAct)) {
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MMIO32(ActmonBase + ActmonGlbPeriodCtrl) = (ActmonPeriodMs - 1) & 0xFF;
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EnableDev(DevMcAll, emcFreqKhz, 256 * 4);
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}
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if (!(MMIO32(ActmonBase + ActmonGlbStatus) & ActmonMccpuMonAct)) {
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EnableDev(DevMcCpu, emcFreqKhz, 256 * 4);
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}
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}
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inline void Update(HocClkBpmpSharedInfo &info) {
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const u32 emcFreqKhz = info.freqMem;
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if (emcFreqKhz == 0) {
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return;
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}
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const u32 avgAll = MMIO32(DevReg(DevMcAll, DevAvgCount));
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const u32 avgCpu = MMIO32(DevReg(DevMcCpu, DevAvgCount));
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// Get 1000 -> 100.0.
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info.emcLoadAll = static_cast<u32>((static_cast<u64>(avgAll) * 10 * 100) / (emcFreqKhz * ActmonPeriodMs));
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info.emcLoadCpu = static_cast<u32>((static_cast<u64>(avgCpu) * 10 * 100) / (emcFreqKhz * ActmonPeriodMs));
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info.emcBwAll = static_cast<u32>((static_cast<u64>(emcFreqKhz) * 16 * info.emcLoadAll) / 1000000);
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info.emcBwCpu = static_cast<u32>((static_cast<u64>(emcFreqKhz) * 16 * info.emcLoadCpu) / 1000000);
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// Not 100% accurate but should be enough.
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info.emcBwGpu = (info.emcBwAll > info.emcBwCpu) ? (info.emcBwAll - info.emcBwCpu) : 0;
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}
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} // namespace actmon
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@@ -0,0 +1,152 @@
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/*
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* Copyright (c) 2019-2025 CTCaer
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* Copyright (c) Souldbminer, Lightos and Horizon OC Contributors
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#pragma once
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#include "regs.hpp"
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// NOTE: MMU won't allow access to gpu address space (smmu carveout issue?)
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namespace bpmpMmu {
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constexpr u32 CacheBase = 0x50040000;
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constexpr u32 CacheConfig = 0x000;
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constexpr u32 CfgEnableCache = (1u << 0);
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constexpr u32 CfgForceWriteThrough = (1u << 3);
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constexpr u32 CfgMmuTagModeShift = 8;
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constexpr u32 TagModeParallel = 0;
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constexpr u32 CfgTagChkAbrtOnErr = (1u << 14);
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constexpr u32 MaintReq = 0x028;
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constexpr u32 MaintReqWayBitmapAll = (0xFu << 8);
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constexpr u32 IntClear = 0x044;
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constexpr u32 IntRawEvent = 0x048;
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constexpr u32 IntMaintDone = (1u << 0);
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constexpr u32 MmuFallbackEntry = 0x0A0;
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constexpr u32 MmuShadowCopyMask = 0x0A4;
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constexpr u32 MmuCfg = 0x0AC;
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constexpr u32 MmuCfgSeqEn = (1u << 1);
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constexpr u32 MmuCfgTlbEn = (1u << 2);
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constexpr u32 MmuCfgAbortStoreLast = (1u << 4);
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constexpr u32 MmuCmd = 0x0B0;
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constexpr u32 MmuCmdInit = 1;
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constexpr u32 MmuCmdCopyShadow = 2;
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constexpr u32 ShadowEntryBase = CacheBase + 0x400;
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constexpr u32 MmuEnCached = (1u << 0);
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constexpr u32 MmuEnExec = (1u << 1);
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constexpr u32 MmuEnRead = (1u << 2);
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constexpr u32 MmuEnWrite = (1u << 3);
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constexpr u32 MaintCleanInvalidWay = 19;
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constexpr u32 MaintInvalidWay = 18;
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constexpr u32 CacheLineSize = 0x20;
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constexpr u32 DramStart = 0x80000000;
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constexpr u32 IramBase = 0x40000000;
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constexpr u32 IramEnd = 0x4003FFFF;
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struct MmuEntry {
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u32 startAddr;
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u32 endAddr;
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u32 attr;
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};
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constexpr MmuEntry Entries[] = {
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{ DramStart, 0xFFFFFFFF, MmuEnRead | MmuEnWrite | MmuEnExec | MmuEnCached },
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{ IramBase, IramEnd, MmuEnRead | MmuEnWrite | MmuEnExec | MmuEnCached },
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};
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inline u32 AlignUp(u32 x, u32 a) {
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return (x + a - 1) & ~(a - 1);
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}
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inline u32 AlignDown(u32 x, u32 a) {
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return x & ~(a - 1);
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}
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inline void Maintenance(u32 op, bool force) {
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if (!force && !(MMIO32(CacheBase + CacheConfig) & CfgEnableCache)) {
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return;
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}
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MMIO32(CacheBase + IntClear) = IntMaintDone;
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// Blocking operation.
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MMIO32(CacheBase + MaintReq) = MaintReqWayBitmapAll | op;
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while (!(MMIO32(CacheBase + IntRawEvent) & IntMaintDone))
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;
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MMIO32(CacheBase + IntClear) = MMIO32(CacheBase + IntRawEvent);
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}
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inline void SetEntry(u32 idx, const MmuEntry &entry) {
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MMIO32(ShadowEntryBase + sizeof(u32) * 4 * idx + 0x0) = AlignUp(entry.startAddr, CacheLineSize);
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MMIO32(ShadowEntryBase + sizeof(u32) * 4 * idx + 0x4) = AlignDown(entry.endAddr, CacheLineSize);
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MMIO32(ShadowEntryBase + sizeof(u32) * 4 * idx + 0x8) = entry.attr;
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MMIO32(CacheBase + MmuShadowCopyMask) |= (1u << idx);
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}
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inline void Enable() {
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if (MMIO32(CacheBase + CacheConfig) & CfgEnableCache) {
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return;
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}
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// Init BPMP MMU.
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MMIO32(CacheBase + MmuCmd) = MmuCmdInit;
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MMIO32(CacheBase + MmuFallbackEntry) = MmuEnRead | MmuEnWrite | MmuEnExec; // RWX for non-defined regions.
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MMIO32(CacheBase + MmuCfg) = MmuCfgSeqEn | MmuCfgTlbEn | MmuCfgAbortStoreLast;
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// Init BPMP MMU entries.
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MMIO32(CacheBase + MmuShadowCopyMask) = 0;
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for (u32 idx = 0; idx < sizeof(Entries) / sizeof(Entries[0]); idx++) {
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SetEntry(idx, Entries[idx]);
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}
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MMIO32(CacheBase + MmuCmd) = MmuCmdCopyShadow;
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// Invalidate cache.
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Maintenance(MaintInvalidWay, true);
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// Enable cache.
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MMIO32(CacheBase + CacheConfig) = CfgEnableCache | CfgForceWriteThrough |
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(TagModeParallel << CfgMmuTagModeShift) | CfgTagChkAbrtOnErr;
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// HW bug. Invalidate cache again.
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Maintenance(MaintInvalidWay, false);
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}
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inline void Disable() {
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if (!(MMIO32(CacheBase + CacheConfig) & CfgEnableCache)) {
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return;
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}
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// Clean and invalidate cache.
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Maintenance(MaintCleanInvalidWay, false);
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// Disable cache.
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MMIO32(CacheBase + CacheConfig) = 0;
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}
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} // namespace bpmpMmu
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@@ -0,0 +1,79 @@
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/*
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* Copyright (c) Souldbminer, Lightos and Horizon OC Contributors
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#pragma once
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#include "regs.hpp"
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#include <hocclk/bpmp.h>
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namespace freq {
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constexpr u32 CarBase = 0x60006000;
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constexpr u32 CarPtoClkCntCntl = 0x60;
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constexpr u32 CarPtoClkCntStatus = 0x64;
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constexpr u32 PtoCntEn = (1u << 9);
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constexpr u32 PtoCntRst = (1u << 10);
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constexpr u32 PtoClkEnable = (1u << 13);
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constexpr u32 PtoSrcSelShift = 14;
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constexpr u32 PtoDivSelDiv1 = (1u << 23);
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constexpr u32 PtoClkCntBusy = (1u << 31);
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constexpr u32 PtoClkCntMask = 0xFFFFFF;
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constexpr u32 ClkPtoCclkGDiv2 = 0x13;
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constexpr u32 ClkPtoEmc = 0x24;
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inline u64 MeasurePtoFreqHz(u32 srcId, u32 multiplier) {
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constexpr u32 win = 16;
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constexpr u32 osc = 32768;
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const u32 val = (srcId << PtoSrcSelShift) | PtoDivSelDiv1 | PtoClkEnable | (win - 1);
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MMIO32(CarBase + CarPtoClkCntCntl) = val;
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(void)MMIO32(CarBase + CarPtoClkCntCntl);
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usleep(2);
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MMIO32(CarBase + CarPtoClkCntCntl) = val | PtoCntRst;
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(void)MMIO32(CarBase + CarPtoClkCntCntl);
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usleep(2);
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MMIO32(CarBase + CarPtoClkCntCntl) = val;
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(void)MMIO32(CarBase + CarPtoClkCntCntl);
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usleep(2);
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MMIO32(CarBase + CarPtoClkCntCntl) = val | PtoCntEn;
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(void)MMIO32(CarBase + CarPtoClkCntCntl);
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usleep((1000000u * win / osc) + 12 + 2); // 502us
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while (MMIO32(CarBase + CarPtoClkCntStatus) & PtoClkCntBusy)
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;
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const u32 cnt = MMIO32(CarBase + CarPtoClkCntStatus) & PtoClkCntMask;
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MMIO32(CarBase + CarPtoClkCntCntl) = 0;
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(void)MMIO32(CarBase + CarPtoClkCntCntl);
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usleep(2);
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return (static_cast<u64>(cnt) * multiplier * osc) / win;
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}
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inline void Update(HocClkBpmpSharedInfo &info) {
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info.freqMem = static_cast<u32>(MeasurePtoFreqHz(ClkPtoEmc, 1) / 1000);
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info.freqCpu = static_cast<u32>(MeasurePtoFreqHz(ClkPtoCclkGDiv2, 2) / 1000);
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}
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} // namespace freq
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@@ -18,6 +18,9 @@
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#include <stdio.h>
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#include <string.h>
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#include "actmon.hpp"
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#include "bpmp_mmu.hpp"
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#include "freq.hpp"
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#include "libc_platform.hpp"
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#include "regs.hpp"
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#include "sensors.hpp"
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@@ -34,6 +37,10 @@ namespace {
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void MainLoop(HocClkBpmpSharedInfo &info) {
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for (;;) {
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if (info.exitRequested) {
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break;
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}
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const u32 temp1 = MMIO32(SocthermBase + SocthermSensorTemp1);
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const u32 temp2 = MMIO32(SocthermBase + SocthermSensorTemp2);
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@@ -42,11 +49,23 @@ void MainLoop(HocClkBpmpSharedInfo &info) {
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info.tempMem = TranslateSocthermTemp(static_cast<u16>(temp2 >> 16));
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info.tempPllx = TranslateSocthermTemp(static_cast<u16>(temp2));
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msleep(500);
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freq::Update(info);
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actmon::Update(info);
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msleep(250);
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}
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/* Deinit MMU otherwise sleep will fatal. */
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bpmpMmu::Disable();
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info.magic = 0x0;
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for (;;)
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;
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}
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extern "C" void main() {
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bpmpMmu::Enable();
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InitializeLibc();
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printf("[hoc-bpmpfw]: Starting bpmpfw\n");
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@@ -54,6 +73,9 @@ extern "C" void main() {
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HocClkBpmpSharedInfo &info = SharedInfo();
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memset(&info, 0, sizeof(info));
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info.status = 0;
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actmon::Init();
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info.magic = HOCCLK_BPMP_MAGIC; // written last
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/* If the main loop exits then it is a panic or invalid state */
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