perfect ram timings

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souldbminersmwc committed 2026-07-29 19:06:10 -04:00
1 parent 119099984d
commit b093b32b29
5 files changed
+35 -5

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@@ -113,7 +113,7 @@ namespace ams::ldr::hoc {
const std::array<u32, 8> tRCD_values = { 18, 17, 16, 15, 14, 13, 12, 11 };
const std::array<u32, 8> tRP_values = { 18, 17, 16, 15, 14, 13, 12, 11 };
const std::array<u32, 10> tRAS_values = { 42, 36, 34, 32, 30, 28, 26, 24, 22, 20 };
const std::array<double, 7> tRRD_values = { /*10.0,*/ 7.5, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0 }; /* 10.0 is used for <2133mhz; do we care? 8gb uses 7.5 tRRD on >=1331. */
const std::array<double, 8> tRRD_values = { 10.0, 7.5, 6.0, 5.0, 4.0, 3.0, 2.0, 1.0 };
const std::array<u32, 11> tRFC_values = { 140, 130, 120, 110, 100, 90, 80, 70, 60, 50, 40 };
const std::array<u32, 10> tWTR_values = { 10, 9, 8, 7, 6, 5, 4, 3, 2, 1 };
const std::array<u32, 6> tREFpb_values = { 3900, 5850, 7800, 11700, 15600, 99999 };
@@ -15,18 +15,42 @@
*/
#include <stratosphere.hpp>
#include "../pcv.hpp"
#include "../../mtc_timing_value.hpp"
#include "timing_tables.hpp"
namespace ams::ldr::hoc::pcv::mariko {
double GetMaxTrrd(u32 freq) {
DramId id = GetDramId();
if (freq >= 1866'000) {
return 7.5;
}
switch (id) {
case HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE ... IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE:
case IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE:
case HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE:
case IOWA_8GB_SAMSUNG_K4UBE3D4AA_MGCL:
case HOAG_8GB_SAMSUNG_K4UBE3D4AA_MGCL:
case AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL:
case IOWA_4GB_MICRON_MT53E512M32D1NP_046_WTB ... AULA_4GB_MICRON_MT53E512M32D1NP_046_WTB:
return 7.5;
default:
break;
}
return 10.0;
}
void GetRext(u32 freq) {
if (auto r = FindRext(freq)) {
rext = r->rext;
return;
}
/* > 3200 */
/* Fallback */
rext = 0x1E;
}
@@ -46,9 +70,10 @@ namespace ams::ldr::hoc::pcv::mariko {
}
void AutoLatency(volatile u32 &latency, u32 freq, u32 latencyStep) {
if (freq > 1600'000 && freq <= 1896'000) { /* 1866tRWL */
if (freq > 1600'000 && freq <= 1866'000) { /* 1866tRWL */
latency += latencyStep * 2;
} else { /* 2133tRWL */
// Note: JEDEC/Datasheet mandates 2133 for >1866, even if <2133
latency += latencyStep * 3;
}
}
@@ -139,7 +164,7 @@ namespace ams::ldr::hoc::pcv::mariko {
tRCD = tRCD_values[lowFreq ? C.low_t1_tRCD : C.t1_tRCD];
tRPpb = tRP_values[lowFreq ? C.low_t2_tRP : C.t2_tRP];
tRAS = tRAS_values[lowFreq ? C.low_t3_tRAS : C.t3_tRAS];
tRRD = tRRD_values[lowFreq ? C.low_t4_tRRD : C.t4_tRRD];
tRRD = MIN(tRRD_values[lowFreq ? C.low_t4_tRRD : C.t4_tRRD], GetMaxTrrd(freq));
tRFCpb = tRFC_values[lowFreq ? C.low_t5_tRFC : C.t5_tRFC];
u32 tRTW = lowFreq ? C.low_t6_tRTW : C.t6_tRTW;
@@ -26,6 +26,8 @@
namespace ams::ldr::hoc::pcv::mariko {
DramId GetDramId();
void MtcGenerateFreqTables();
Result MemFreqMtcTable(u32 *ptr);
Result MemFreqDvbTable(u32 *ptr);