hocclk: format code
use clang format file provided for optimal formatting
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@@ -21,67 +21,67 @@
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*/
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#include <notification.h>
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#include "../mapping/mem_map.hpp"
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#include "../file/file_utils.hpp"
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#include "tsensor_common.hpp"
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#include "../mapping/mem_map.hpp"
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#include "aotag.hpp"
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#include "tsensor_common.hpp"
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namespace tsensor {
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#define PMC_BASE 0x7000E400
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#define TEGRA_FUSE_CP_REV_0_3 (3)
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#define FUSE_CP_REV 0x190
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#define PMC_BASE 0x7000E400
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#define TEGRA_FUSE_CP_REV_0_3 (3)
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#define FUSE_CP_REV 0x190
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namespace {
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u64 fuseVa = 0;
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u64 fuseVa = 0;
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bool wasInit = false;
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}
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} // namespace
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#define REG_SET(r, mask, value) \
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((r & ~(mask##_MASK)) | ((value<<(mask##_POS_START)) & mask##_MASK))
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#define REG_SET(r, mask, value) ((r & ~(mask##_MASK)) | ((value << (mask##_POS_START)) & mask##_MASK))
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#define REG_GET(r, mask) \
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((r & mask##_MASK) >> mask##_POS_START)
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#define REG_GET(r, mask) ((r & mask##_MASK) >> mask##_POS_START)
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#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
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#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
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static const TSensorFuse tegra_aotag_fuse = {
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.fuse_base_cp_mask = 0x3ff << 11,
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.fuse_base_cp_shift = 11,
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.fuse_base_ft_mask = (u32)0x7ff << 21,
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.fuse_base_ft_shift = 21,
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.fuse_shift_ft_mask = 0x1f << 6,
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.fuse_shift_ft_shift = 6,
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.fuse_base_cp_mask = 0x3ff << 11,
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.fuse_base_cp_shift = 11,
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.fuse_base_ft_mask = (u32)0x7ff << 21,
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.fuse_base_ft_shift = 21,
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.fuse_shift_ft_mask = 0x1f << 6,
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.fuse_shift_ft_shift = 6,
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.fuse_spare_realignment = 0,
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};
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static TSensorConfig tegra_aotag_config = {
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.tall = 76,
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.tiddq_en = 1,
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.ten_count = 16,
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.pdiv = 8,
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.pdiv_ate = 8,
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.tsample = 9,
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.tall = 76,
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.tiddq_en = 1,
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.ten_count = 16,
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.pdiv = 8,
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.pdiv_ate = 8,
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.tsample = 9,
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.tsample_ate = 39,
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};
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static TSensorConfig tegra210b01_aotag_config = {
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.tall = 76,
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.tiddq_en = 1,
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.ten_count = 16,
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.pdiv = 12,
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.pdiv_ate = 6,
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.tsample = 19,
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.tall = 76,
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.tiddq_en = 1,
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.ten_count = 16,
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.pdiv = 12,
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.pdiv_ate = 6,
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.tsample = 19,
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.tsample_ate = 39,
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};
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static const FuseCorrCoeff tegra_aotag_coeff = {
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.alpha = 1063200,
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.beta = -6749000,
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.beta = -6749000,
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};
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static const FuseCorrCoeff tegra210b01_aotag_coeff = {
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.alpha = 991100,
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.beta = 1096200,
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.beta = 1096200,
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};
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struct aotag_sensor_info_t {
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@@ -99,32 +99,32 @@ namespace tsensor {
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static aotag_platform_data tegra210_plat_data = {
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.config = &tegra_aotag_config,
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.coeff = &tegra_aotag_coeff,
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.coeff = &tegra_aotag_coeff,
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};
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static aotag_platform_data tegra210b01_plat_data = {
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.config = &tegra210b01_aotag_config,
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.coeff = &tegra210b01_aotag_coeff,
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.coeff = &tegra210b01_aotag_coeff,
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};
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aotag_sensor_info_t aotag_sensor_info = {
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.config = NULL,
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.fuse = NULL,
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.coeff = NULL,
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.config = NULL,
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.fuse = NULL,
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.coeff = NULL,
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.therm_a = 0,
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.therm_b = 0,
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};
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aotag_sensor_info_t *info = &aotag_sensor_info;
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aotag_sensor_info_t *info = &aotag_sensor_info;
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aotag_platform_data *pdata = NULL;
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u32 ReadPmcReg(unsigned long offset) {
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SecmonArgs args = {};
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args.X[0] = 0xF0000002;
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args.X[1] = PMC_BASE + offset;
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args.X[0] = 0xF0000002;
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args.X[1] = PMC_BASE + offset;
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svcCallSecureMonitor(&args);
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if (args.X[1] == (PMC_BASE + offset)) { // if param 1 is identical read failed
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if (args.X[1] == (PMC_BASE + offset)) { // if param 1 is identical read failed
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return 0;
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}
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@@ -133,21 +133,21 @@ namespace tsensor {
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void WritePmcReg(u32 value, unsigned long offset) {
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SecmonArgs args = {};
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args.X[0] = 0xF0000002;
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args.X[1] = PMC_BASE + offset;
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args.X[2] = 0xFFFFFFFF;
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args.X[3] = (value);
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args.X[0] = 0xF0000002;
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args.X[1] = PMC_BASE + offset;
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args.X[2] = 0xFFFFFFFF;
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args.X[3] = (value);
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svcCallSecureMonitor(&args);
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}
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static inline void SetBit(unsigned long nr, volatile void *addr) {
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int *m = ((int *) addr) + (nr >> 5);
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*m |= 1 << (nr & 31);
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int *m = ((int *)addr) + (nr >> 5);
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*m |= 1 << (nr & 31);
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}
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static inline void ClearBit(unsigned long nr, volatile void *addr) {
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int *m = ((int *) addr) + (nr >> 5);
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*m &= ~(1 << (nr & 31));
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int *m = ((int *)addr) + (nr >> 5);
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*m &= ~(1 << (nr & 31));
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}
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void InitializeAotag(bool isMariko) {
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@@ -156,7 +156,7 @@ namespace tsensor {
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if (isMariko) {
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// u32 major, minor, rev;
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pdata = &tegra210b01_plat_data;
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pdata = &tegra210b01_plat_data;
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info->config = &tegra210b01_aotag_config;
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// tegra_fuse_readl(FUSE_CP_REV, &rev);
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// minor = rev & 0x1f;
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@@ -166,10 +166,10 @@ namespace tsensor {
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// }
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} else {
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info->config = &tegra_aotag_config;
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pdata = &tegra210_plat_data;
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pdata = &tegra210_plat_data;
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}
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info->fuse = &tegra_aotag_fuse;
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info->fuse = &tegra_aotag_fuse;
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info->coeff = pdata->coeff;
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aotag_sensor_info_t *ps_info = &aotag_sensor_info;
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@@ -215,18 +215,18 @@ namespace tsensor {
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}
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u32 regval = 0, abs = 0, fraction = 0, valid = 0, sign = 0;
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s32 temp = 0;
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regval = ReadPmcReg(PMC_TSENSOR_STATUS1);
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valid = REG_GET(regval, STATUS1_TEMP_VALID);
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s32 temp = 0;
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regval = ReadPmcReg(PMC_TSENSOR_STATUS1);
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valid = REG_GET(regval, STATUS1_TEMP_VALID);
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if (!valid) {
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return -125;
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}
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abs = REG_GET(regval, STATUS1_TEMP_ABS);
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abs = REG_GET(regval, STATUS1_TEMP_ABS);
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fraction = REG_GET(regval, STATUS1_TEMP_FRAC);
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sign = REG_GET(regval, STATUS1_TEMP_SIGN);
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temp = (abs * 1000) + (fraction * 500);
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sign = REG_GET(regval, STATUS1_TEMP_SIGN);
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temp = (abs * 1000) + (fraction * 500);
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if (sign) {
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temp = (-1) * (temp);
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}
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@@ -238,4 +238,4 @@ namespace tsensor {
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return wasInit;
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}
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}
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} // namespace tsensor
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@@ -21,136 +21,118 @@
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namespace tsensor {
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#define MASK(start, end) \
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(((0xFFFFFFFF)<<start) & (u32)(((u64)1<<(end+1))-1))
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#define MASK(start, end) (((0xFFFFFFFF) << start) & (u32)(((u64)1 << (end + 1)) - 1))
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#define MAX_THRESHOLD_TEMP (127000)
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#define MIN_THRESHOLD_TEMP (-127000)
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#define MAX_THRESHOLD_TEMP (127000)
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#define MIN_THRESHOLD_TEMP (-127000)
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/*
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* Register definitions
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*/
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#define TSENSOR_COMMON_FUSE_ADDR (0x280)
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/*
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* Register definitions
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*/
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#define TSENSOR_COMMON_FUSE_ADDR (0x280)
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// NVIDIA driver uses 1D4 here but its incorrect.
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// I guess that's what happens when you vibecode your AOTAG driver (jk)
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#define AOTAG_FUSE_ADDR (0x2D4)
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// NVIDIA driver uses 1D4 here but its incorrect.
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// I guess that's what happens when you vibecode your AOTAG driver (jk)
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#define AOTAG_FUSE_ADDR (0x2D4)
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#define PMC_R_OBS_AOTAG (0x017)
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#define PMC_R_OBS_AOTAG_CAPTURE (0x017)
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#define PMC_RST_STATUS (0x1B4)
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#define PMC_DIRECT_THERMTRIP_CFG (0x474)
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#define PMC_R_OBS_AOTAG (0x017)
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#define PMC_R_OBS_AOTAG_CAPTURE (0x017)
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#define PMC_RST_STATUS (0x1B4)
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#define PMC_DIRECT_THERMTRIP_CFG (0x474)
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#define PMC_AOTAG_CFG (0x484)
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#define CFG_DISABLE_CLK_POS (0)
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#define CFG_SW_TRIGGER_POS (2)
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#define CFG_USE_EXT_TRIGGER_POS (3)
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#define CFG_ENABLE_SW_DEBUG_POS (4)
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#define CFG_TAG_EN_POS (5)
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#define CFG_THERMTRIP_EN_POS (6)
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#define PMC_AOTAG_CFG (0x484)
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#define CFG_DISABLE_CLK_POS (0)
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#define CFG_SW_TRIGGER_POS (2)
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#define CFG_USE_EXT_TRIGGER_POS (3)
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#define CFG_ENABLE_SW_DEBUG_POS (4)
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#define CFG_TAG_EN_POS (5)
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#define CFG_THERMTRIP_EN_POS (6)
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#define PMC_AOTAG_THRESH1_CFG (0x488)
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#define PMC_AOTAG_THRESH2_CFG (0x48C)
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#define PMC_AOTAG_THRESH3_CFG (0x490)
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#define THRESH3_CFG_POS_START (0)
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#define THRESH3_CFG_POS_END (14)
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#define THRESH3_CFG_MASK (MASK(THRESH3_CFG_POS_START,\
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THRESH3_CFG_POS_END))
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#define PMC_AOTAG_STATUS (0x494)
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#define PMC_AOTAG_SECURITY (0x498)
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#define PMC_AOTAG_THRESH1_CFG (0x488)
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#define PMC_AOTAG_THRESH2_CFG (0x48C)
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#define PMC_AOTAG_THRESH3_CFG (0x490)
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#define THRESH3_CFG_POS_START (0)
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#define THRESH3_CFG_POS_END (14)
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#define THRESH3_CFG_MASK (MASK(THRESH3_CFG_POS_START, THRESH3_CFG_POS_END))
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#define PMC_AOTAG_STATUS (0x494)
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#define PMC_AOTAG_SECURITY (0x498)
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#define PMC_TSENSOR_CONFIG0 (0x49C)
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#define CONFIG0_STOP_POS (0)
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#define CONFIG0_RO_SEL_POS (1)
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#define CONFIG0_STATUS_CLR_POS (5)
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#define CONFIG0_TALL_POS_START (8)
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#define CONFIG0_TALL_POS_END (27)
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#define CONFIG0_TALL_SIZE (CONFIG0_TALL_POS_END - \
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CONFIG0_TALL_POS + 1)
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#define CONFIG0_TALL_MASK (MASK(CONFIG0_TALL_POS_START, \
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CONFIG0_TALL_POS_END))
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#define PMC_TSENSOR_CONFIG0 (0x49C)
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#define CONFIG0_STOP_POS (0)
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#define CONFIG0_RO_SEL_POS (1)
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#define CONFIG0_STATUS_CLR_POS (5)
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#define CONFIG0_TALL_POS_START (8)
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#define CONFIG0_TALL_POS_END (27)
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#define CONFIG0_TALL_SIZE (CONFIG0_TALL_POS_END - CONFIG0_TALL_POS + 1)
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#define CONFIG0_TALL_MASK (MASK(CONFIG0_TALL_POS_START, CONFIG0_TALL_POS_END))
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#define PMC_TSENSOR_CONFIG1 (0x4A0)
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#define CONFIG1_TEMP_ENABLE_POS (31)
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#define CONFIG1_TEN_COUNT_POS_START (24)
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#define CONFIG1_TEN_COUNT_POS_END (29)
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#define CONFIG1_TEN_COUNT_MASK (MASK(CONFIG1_TEN_COUNT_POS_START, \
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CONFIG1_TEN_COUNT_POS_END))
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#define CONFIG1_TIDDQ_EN_POS_START (15)
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#define CONFIG1_TIDDQ_EN_POS_END (20)
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#define CONFIG1_TIDDQ_EN_MASK (MASK(CONFIG1_TIDDQ_EN_POS_START, \
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CONFIG1_TIDDQ_EN_POS_END))
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#define CONFIG1_TSAMPLE_POS_START (0)
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#define CONFIG1_TSAMPLE_POS_END (9)
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#define CONFIG1_TSAMPLE_MASK (MASK(CONFIG1_TSAMPLE_POS_START, \
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CONFIG1_TSAMPLE_POS_END))
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#define PMC_TSENSOR_CONFIG1 (0x4A0)
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#define CONFIG1_TEMP_ENABLE_POS (31)
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#define CONFIG1_TEN_COUNT_POS_START (24)
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#define CONFIG1_TEN_COUNT_POS_END (29)
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#define CONFIG1_TEN_COUNT_MASK (MASK(CONFIG1_TEN_COUNT_POS_START, CONFIG1_TEN_COUNT_POS_END))
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#define CONFIG1_TIDDQ_EN_POS_START (15)
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#define CONFIG1_TIDDQ_EN_POS_END (20)
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#define CONFIG1_TIDDQ_EN_MASK (MASK(CONFIG1_TIDDQ_EN_POS_START, CONFIG1_TIDDQ_EN_POS_END))
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#define CONFIG1_TSAMPLE_POS_START (0)
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#define CONFIG1_TSAMPLE_POS_END (9)
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#define CONFIG1_TSAMPLE_MASK (MASK(CONFIG1_TSAMPLE_POS_START, CONFIG1_TSAMPLE_POS_END))
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#define PMC_TSENSOR_CONFIG2 (0x4A4)
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#define CONFIG2_THERM_A_POS_START (16)
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#define CONFIG2_THERM_A_POS_END (31)
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#define CONFIG2_THERM_A_MASK (MASK(CONFIG2_THERM_A_POS_START, \
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CONFIG2_THERM_A_POS_END))
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#define PMC_TSENSOR_CONFIG2 (0x4A4)
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#define CONFIG2_THERM_A_POS_START (16)
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#define CONFIG2_THERM_A_POS_END (31)
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#define CONFIG2_THERM_A_MASK (MASK(CONFIG2_THERM_A_POS_START, CONFIG2_THERM_A_POS_END))
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#define CONFIG2_THERM_B_POS_START (0)
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#define CONFIG2_THERM_B_POS_END (15)
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#define CONFIG2_THERM_B_MASK (MASK(CONFIG2_THERM_B_POS_START, \
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CONFIG2_THERM_B_POS_END))
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#define CONFIG2_THERM_B_POS_START (0)
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#define CONFIG2_THERM_B_POS_END (15)
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#define CONFIG2_THERM_B_MASK (MASK(CONFIG2_THERM_B_POS_START, CONFIG2_THERM_B_POS_END))
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#define PMC_TSENSOR_STATUS0 (0x4A8)
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#define STATUS0_CAPTURE_VALID_POS (31)
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#define STATUS0_CAPTURE_POS_START (0)
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#define STATUS0_CAPTURE_POS_END (15)
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#define STATUS0_CAPTURE_MASK (MASK(STATUS0_CAPTURE_POS_START, \
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STATUS0_CAPTURE_POS_END))
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#define PMC_TSENSOR_STATUS0 (0x4A8)
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#define STATUS0_CAPTURE_VALID_POS (31)
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#define STATUS0_CAPTURE_POS_START (0)
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#define STATUS0_CAPTURE_POS_END (15)
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#define STATUS0_CAPTURE_MASK (MASK(STATUS0_CAPTURE_POS_START, STATUS0_CAPTURE_POS_END))
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#define PMC_TSENSOR_STATUS1 (0x4AC)
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#define STATUS1_TEMP_POS (31)
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#define STATUS1_TEMP_POS_START (0)
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#define STATUS1_TEMP_POS_END (15)
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#define STATUS1_TEMP_MASK (MASK(STATUS1_TEMP_POS_START, \
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STATUS1_TEMP_POS_END))
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#define PMC_TSENSOR_STATUS1 (0x4AC)
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#define STATUS1_TEMP_POS (31)
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#define STATUS1_TEMP_POS_START (0)
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#define STATUS1_TEMP_POS_END (15)
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#define STATUS1_TEMP_MASK (MASK(STATUS1_TEMP_POS_START, STATUS1_TEMP_POS_END))
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#define STATUS1_TEMP_VALID_POS_START (31)
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#define STATUS1_TEMP_VALID_POS_END (31)
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#define STATUS1_TEMP_VALID_MASK (MASK(STATUS1_TEMP_VALID_POS_START, \
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STATUS1_TEMP_VALID_POS_END))
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#define STATUS1_TEMP_VALID_POS_START (31)
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#define STATUS1_TEMP_VALID_POS_END (31)
|
||||
#define STATUS1_TEMP_VALID_MASK (MASK(STATUS1_TEMP_VALID_POS_START, STATUS1_TEMP_VALID_POS_END))
|
||||
|
||||
#define STATUS1_TEMP_ABS_POS_START (8)
|
||||
#define STATUS1_TEMP_ABS_POS_END (15)
|
||||
#define STATUS1_TEMP_ABS_MASK (MASK(STATUS1_TEMP_ABS_POS_START, \
|
||||
STATUS1_TEMP_ABS_POS_END))
|
||||
#define STATUS1_TEMP_ABS_POS_START (8)
|
||||
#define STATUS1_TEMP_ABS_POS_END (15)
|
||||
#define STATUS1_TEMP_ABS_MASK (MASK(STATUS1_TEMP_ABS_POS_START, STATUS1_TEMP_ABS_POS_END))
|
||||
|
||||
#define STATUS1_TEMP_FRAC_POS_START (7)
|
||||
#define STATUS1_TEMP_FRAC_POS_END (7)
|
||||
#define STATUS1_TEMP_FRAC_MASK (MASK(STATUS1_TEMP_FRAC_POS_START, \
|
||||
STATUS1_TEMP_FRAC_POS_END))
|
||||
#define STATUS1_TEMP_FRAC_POS_START (7)
|
||||
#define STATUS1_TEMP_FRAC_POS_END (7)
|
||||
#define STATUS1_TEMP_FRAC_MASK (MASK(STATUS1_TEMP_FRAC_POS_START, STATUS1_TEMP_FRAC_POS_END))
|
||||
|
||||
#define STATUS1_TEMP_SIGN_POS_START (0)
|
||||
#define STATUS1_TEMP_SIGN_POS_END (0)
|
||||
#define STATUS1_TEMP_SIGN_MASK (MASK(STATUS1_TEMP_SIGN_POS_START, \
|
||||
STATUS1_TEMP_SIGN_POS_END))
|
||||
#define STATUS1_TEMP_SIGN_POS_START (0)
|
||||
#define STATUS1_TEMP_SIGN_POS_END (0)
|
||||
#define STATUS1_TEMP_SIGN_MASK (MASK(STATUS1_TEMP_SIGN_POS_START, STATUS1_TEMP_SIGN_POS_END))
|
||||
|
||||
#define PMC_TSENSOR_STATUS2 (0x4B0)
|
||||
#define PMC_TSENSOR_PDIV0 (0x4B4)
|
||||
#define TSENSOR_PDIV_POS_START (12)
|
||||
#define TSENSOR_PDIV_POS_END (15)
|
||||
#define TSENSOR_PDIV_MASK (MASK(TSENSOR_PDIV_POS_START, \
|
||||
TSENSOR_PDIV_POS_END))
|
||||
#define PMC_TSENSOR_STATUS2 (0x4B0)
|
||||
#define PMC_TSENSOR_PDIV0 (0x4B4)
|
||||
#define TSENSOR_PDIV_POS_START (12)
|
||||
#define TSENSOR_PDIV_POS_END (15)
|
||||
#define TSENSOR_PDIV_MASK (MASK(TSENSOR_PDIV_POS_START, TSENSOR_PDIV_POS_END))
|
||||
|
||||
#define PMC_AOTAG_INTR_EN (0x4B8)
|
||||
#define PMC_AOTAG_INTR_DIS (0x4BC)
|
||||
#define PMC_AOTAG_INTR_EN (0x4B8)
|
||||
#define PMC_AOTAG_INTR_DIS (0x4BC)
|
||||
|
||||
#define AOTAG_FUSE_CALIB_CP_POS_START (0)
|
||||
#define AOTAG_FUSE_CALIB_CP_POS_END (12)
|
||||
#define AOTAG_FUSE_CALIB_CP_MASK (MASK(AOTAG_FUSE_CALIB_CP_POS_START, \
|
||||
AOTAG_FUSE_CALIB_CP_POS_END))
|
||||
#define AOTAG_FUSE_CALIB_CP_POS_START (0)
|
||||
#define AOTAG_FUSE_CALIB_CP_POS_END (12)
|
||||
#define AOTAG_FUSE_CALIB_CP_MASK (MASK(AOTAG_FUSE_CALIB_CP_POS_START, AOTAG_FUSE_CALIB_CP_POS_END))
|
||||
|
||||
#define AOTAG_FUSE_CALIB_FT_POS_START (13)
|
||||
#define AOTAG_FUSE_CALIB_FT_POS_END (25)
|
||||
#define AOTAG_FUSE_CALIB_FT_MASK (MASK(AOTAG_FUSE_CALIB_FT_POS_START, \
|
||||
AOTAG_FUSE_CALIB_FT_POS_END))
|
||||
#define AOTAG_FUSE_CALIB_FT_POS_START (13)
|
||||
#define AOTAG_FUSE_CALIB_FT_POS_END (25)
|
||||
#define AOTAG_FUSE_CALIB_FT_MASK (MASK(AOTAG_FUSE_CALIB_FT_POS_START, AOTAG_FUSE_CALIB_FT_POS_END))
|
||||
|
||||
void InitializeAotag(bool isMariko);
|
||||
s32 ReadAotag();
|
||||
bool IsInitialized();
|
||||
}
|
||||
} // namespace tsensor
|
||||
@@ -1,8 +1,8 @@
|
||||
/*
|
||||
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
|
||||
*
|
||||
*
|
||||
* Copyright (c) CtCaer
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
@@ -20,8 +20,7 @@
|
||||
#include "bq24193.hpp"
|
||||
|
||||
namespace bq24193 {
|
||||
static u8 bq24193_get_reg(u8 reg)
|
||||
{
|
||||
static u8 bq24193_get_reg(u8 reg) {
|
||||
u8 out;
|
||||
I2cRead_OutU8(I2cDevice_Bq24193, reg, &out);
|
||||
return out;
|
||||
@@ -30,4 +29,4 @@ namespace bq24193 {
|
||||
u8 regVal = bq24193_get_reg(BQ24193_FaultReg);
|
||||
return regVal & BQ24193_FAULT_THERM_MASK;
|
||||
}
|
||||
}
|
||||
} // namespace bq24193
|
||||
@@ -1,8 +1,8 @@
|
||||
/*
|
||||
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
|
||||
*
|
||||
*
|
||||
* Copyright (c) CtCaer
|
||||
*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
@@ -17,106 +17,108 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include "../board/board.hpp"
|
||||
#include <i2c.h>
|
||||
|
||||
#include "../board/board.hpp"
|
||||
#include "../i2c/i2cDrv.h"
|
||||
|
||||
|
||||
namespace bq24193 {
|
||||
#define BQ24193_I2C_ADDR 0x6B
|
||||
#define BQ24193_I2C_ADDR 0x6B
|
||||
|
||||
// REG 0 masks.
|
||||
#define BQ24193_INCONFIG_INLIMIT_MASK (7<<0)
|
||||
#define BQ24193_INCONFIG_VINDPM_MASK 0x78
|
||||
#define BQ24193_INCONFIG_HIZ_EN_MASK (1<<7)
|
||||
// REG 0 masks.
|
||||
#define BQ24193_INCONFIG_INLIMIT_MASK (7 << 0)
|
||||
#define BQ24193_INCONFIG_VINDPM_MASK 0x78
|
||||
#define BQ24193_INCONFIG_HIZ_EN_MASK (1 << 7)
|
||||
|
||||
// REG 1 masks.
|
||||
#define BQ24193_PORCONFIG_BOOST_MASK (1<<0)
|
||||
#define BQ24193_PORCONFIG_SYSMIN_MASK (7<<1) // 3000uV HOS default.
|
||||
#define BQ24193_PORCONFIG_CHGCONFIG_MASK (3<<4)
|
||||
#define BQ24193_PORCONFIG_CHGCONFIG_CHARGER_EN (1<<4)
|
||||
#define BQ24193_PORCONFIG_I2CWATCHDOG_MASK (1<<6)
|
||||
#define BQ24193_PORCONFIG_RESET_MASK (1<<7)
|
||||
// REG 1 masks.
|
||||
#define BQ24193_PORCONFIG_BOOST_MASK (1 << 0)
|
||||
#define BQ24193_PORCONFIG_SYSMIN_MASK (7 << 1) // 3000uV HOS default.
|
||||
#define BQ24193_PORCONFIG_CHGCONFIG_MASK (3 << 4)
|
||||
#define BQ24193_PORCONFIG_CHGCONFIG_CHARGER_EN (1 << 4)
|
||||
#define BQ24193_PORCONFIG_I2CWATCHDOG_MASK (1 << 6)
|
||||
#define BQ24193_PORCONFIG_RESET_MASK (1 << 7)
|
||||
|
||||
// REG 2 masks.
|
||||
#define BQ24193_CHRGCURR_20PCT_MASK (1<<0)
|
||||
#define BQ24193_CHRGCURR_ICHG_MASK 0xFC
|
||||
// REG 2 masks.
|
||||
#define BQ24193_CHRGCURR_20PCT_MASK (1 << 0)
|
||||
#define BQ24193_CHRGCURR_ICHG_MASK 0xFC
|
||||
|
||||
// REG 3 masks.
|
||||
#define BQ24193_PRECHRG_ITERM 0x0F
|
||||
#define BQ24193_PRECHRG_IPRECHG 0xF0
|
||||
// REG 3 masks.
|
||||
#define BQ24193_PRECHRG_ITERM 0x0F
|
||||
#define BQ24193_PRECHRG_IPRECHG 0xF0
|
||||
|
||||
// REG 4 masks.
|
||||
#define BQ24193_CHRGVOLT_VTHRES (1<<0)
|
||||
#define BQ24193_CHRGVOLT_BATTLOW (1<<1)
|
||||
#define BQ24193_CHRGVOLT_VREG 0xFC
|
||||
// REG 4 masks.
|
||||
#define BQ24193_CHRGVOLT_VTHRES (1 << 0)
|
||||
#define BQ24193_CHRGVOLT_BATTLOW (1 << 1)
|
||||
#define BQ24193_CHRGVOLT_VREG 0xFC
|
||||
|
||||
// REG 5 masks.
|
||||
#define BQ24193_CHRGTERM_ISET_MASK (1<<0)
|
||||
#define BQ24193_CHRGTERM_CHGTIMER_MASK (3<<1)
|
||||
#define BQ24193_CHRGTERM_ENTIMER_MASK (1<<3)
|
||||
#define BQ24193_CHRGTERM_WATCHDOG_MASK (3<<4)
|
||||
#define BQ24193_CHRGTERM_TERM_ST_MASK (1<<6)
|
||||
#define BQ24193_CHRGTERM_TERM_EN_MASK (1<<7)
|
||||
// REG 5 masks.
|
||||
#define BQ24193_CHRGTERM_ISET_MASK (1 << 0)
|
||||
#define BQ24193_CHRGTERM_CHGTIMER_MASK (3 << 1)
|
||||
#define BQ24193_CHRGTERM_ENTIMER_MASK (1 << 3)
|
||||
#define BQ24193_CHRGTERM_WATCHDOG_MASK (3 << 4)
|
||||
#define BQ24193_CHRGTERM_TERM_ST_MASK (1 << 6)
|
||||
#define BQ24193_CHRGTERM_TERM_EN_MASK (1 << 7)
|
||||
|
||||
// REG 6 masks.
|
||||
#define BQ24193_IRTHERMAL_THERM_MASK (3<<0)
|
||||
#define BQ24193_IRTHERMAL_VCLAMP_MASK (7<<2)
|
||||
#define BQ24193_IRTHERMAL_BATTCOMP_MASK (7<<5)
|
||||
// REG 6 masks.
|
||||
#define BQ24193_IRTHERMAL_THERM_MASK (3 << 0)
|
||||
#define BQ24193_IRTHERMAL_VCLAMP_MASK (7 << 2)
|
||||
#define BQ24193_IRTHERMAL_BATTCOMP_MASK (7 << 5)
|
||||
|
||||
// REG 7 masks.
|
||||
#define BQ24193_MISC_INT_MASK (3<<0)
|
||||
#define BQ24193_MISC_VSET_MASK (1<<4)
|
||||
#define BQ24193_MISC_BATFET_DI_MASK (1<<5)
|
||||
#define BQ24193_MISC_TMR2X_EN_MASK (1<<6)
|
||||
#define BQ24193_MISC_DPDM_EN_MASK (1<<7)
|
||||
// REG 7 masks.
|
||||
#define BQ24193_MISC_INT_MASK (3 << 0)
|
||||
#define BQ24193_MISC_VSET_MASK (1 << 4)
|
||||
#define BQ24193_MISC_BATFET_DI_MASK (1 << 5)
|
||||
#define BQ24193_MISC_TMR2X_EN_MASK (1 << 6)
|
||||
#define BQ24193_MISC_DPDM_EN_MASK (1 << 7)
|
||||
|
||||
// REG 8 masks.
|
||||
#define BQ24193_STATUS_VSYS_MASK (1<<0)
|
||||
#define BQ24193_STATUS_THERM_MASK (1<<1)
|
||||
#define BQ24193_STATUS_PG_MASK (1<<2)
|
||||
#define BQ24193_STATUS_DPM_MASK (1<<3)
|
||||
#define BQ24193_STATUS_CHRG_MASK (3<<4)
|
||||
#define BQ24193_STATUS_VBUS_MASK (3<<6)
|
||||
// REG 8 masks.
|
||||
#define BQ24193_STATUS_VSYS_MASK (1 << 0)
|
||||
#define BQ24193_STATUS_THERM_MASK (1 << 1)
|
||||
#define BQ24193_STATUS_PG_MASK (1 << 2)
|
||||
#define BQ24193_STATUS_DPM_MASK (1 << 3)
|
||||
#define BQ24193_STATUS_CHRG_MASK (3 << 4)
|
||||
#define BQ24193_STATUS_VBUS_MASK (3 << 6)
|
||||
|
||||
// REG 9 masks.
|
||||
#define BQ24193_FAULT_THERM_MASK (7<<0)
|
||||
#define BQ24193_FAULT_BATT_OVP_MASK (1<<3)
|
||||
#define BQ24193_FAULT_CHARGE_MASK (3<<4)
|
||||
#define BQ24193_FAULT_BOOST_MASK (1<<6)
|
||||
#define BQ24193_FAULT_WATCHDOG_MASK (1<<7)
|
||||
// REG 9 masks.
|
||||
#define BQ24193_FAULT_THERM_MASK (7 << 0)
|
||||
#define BQ24193_FAULT_BATT_OVP_MASK (1 << 3)
|
||||
#define BQ24193_FAULT_CHARGE_MASK (3 << 4)
|
||||
#define BQ24193_FAULT_BOOST_MASK (1 << 6)
|
||||
#define BQ24193_FAULT_WATCHDOG_MASK (1 << 7)
|
||||
|
||||
// REG A masks.
|
||||
#define BQ24193_VENDORPART_DEV_MASK (3<<0)
|
||||
#define BQ24193_VENDORPART_PN_MASK (7<<3)
|
||||
// REG A masks.
|
||||
#define BQ24193_VENDORPART_DEV_MASK (3 << 0)
|
||||
#define BQ24193_VENDORPART_PN_MASK (7 << 3)
|
||||
|
||||
enum BQ24193_reg {
|
||||
BQ24193_InputSource = 0x00,
|
||||
BQ24193_PORConfig = 0x01,
|
||||
BQ24193_ChrgCurr = 0x02,
|
||||
BQ24193_PreChrgTerm = 0x03,
|
||||
BQ24193_ChrgVolt = 0x04,
|
||||
BQ24193_ChrgTermTimer = 0x05,
|
||||
BQ24193_IRCompThermal = 0x06,
|
||||
BQ24193_Misc = 0x07,
|
||||
BQ24193_Status = 0x08,
|
||||
BQ24193_FaultReg = 0x09,
|
||||
BQ24193_VendorPart = 0x0A,
|
||||
BQ24193_InputSource = 0x00,
|
||||
BQ24193_PORConfig = 0x01,
|
||||
BQ24193_ChrgCurr = 0x02,
|
||||
BQ24193_PreChrgTerm = 0x03,
|
||||
BQ24193_ChrgVolt = 0x04,
|
||||
BQ24193_ChrgTermTimer = 0x05,
|
||||
BQ24193_IRCompThermal = 0x06,
|
||||
BQ24193_Misc = 0x07,
|
||||
BQ24193_Status = 0x08,
|
||||
BQ24193_FaultReg = 0x09,
|
||||
BQ24193_VendorPart = 0x0A,
|
||||
};
|
||||
|
||||
enum BQ24193_reg_prop {
|
||||
BQ24193_InputVoltageLimit, // REG 0.
|
||||
BQ24193_InputCurrentLimit, // REG 0.
|
||||
BQ24193_SystemMinimumVoltage, // REG 1.
|
||||
BQ24193_FastChargeCurrentLimit, // REG 2.
|
||||
BQ24193_ChargeVoltageLimit, // REG 4.
|
||||
BQ24193_RechargeThreshold, // REG 4.
|
||||
BQ24193_ThermalRegulation, // REG 6.
|
||||
BQ24193_ChargeStatus, // REG 8.
|
||||
BQ24193_TempStatus, // REG 9.
|
||||
BQ24193_DevID, // REG A.
|
||||
BQ24193_ProductNumber, // REG A.
|
||||
BQ24193_InputVoltageLimit, // REG 0.
|
||||
BQ24193_InputCurrentLimit, // REG 0.
|
||||
BQ24193_SystemMinimumVoltage, // REG 1.
|
||||
BQ24193_FastChargeCurrentLimit, // REG 2.
|
||||
BQ24193_ChargeVoltageLimit, // REG 4.
|
||||
BQ24193_RechargeThreshold, // REG 4.
|
||||
BQ24193_ThermalRegulation, // REG 6.
|
||||
BQ24193_ChargeStatus, // REG 8.
|
||||
BQ24193_TempStatus, // REG 9.
|
||||
BQ24193_DevID, // REG A.
|
||||
BQ24193_ProductNumber, // REG A.
|
||||
};
|
||||
// 0: Normal, 2: Warm, 3: Cool, 5: Cold, 6: Hot.
|
||||
// 0: Normal, 2: Warm, 3: Cool, 5: Cold, 6: Hot.
|
||||
enum BQ24193_Temp {
|
||||
BQ24193_Temp_Normal = 0,
|
||||
BQ24193_Temp_Warm = 2,
|
||||
@@ -125,5 +127,4 @@ namespace bq24193 {
|
||||
BQ24193_Temp_Hot = 6,
|
||||
};
|
||||
u8 getBQTemp();
|
||||
}
|
||||
|
||||
} // namespace bq24193
|
||||
@@ -20,169 +20,171 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#include <switch.h>
|
||||
#include <hocclk.h>
|
||||
#include <switch.h>
|
||||
|
||||
#include "../board/board.hpp"
|
||||
#include "../file/file_utils.hpp"
|
||||
#include "../mapping/mem_map.hpp"
|
||||
#include "soctherm.hpp"
|
||||
#include "tsensor_common.hpp"
|
||||
|
||||
|
||||
namespace tsensor {
|
||||
|
||||
namespace {
|
||||
|
||||
#define CAR_CLK_SOURCE_TSENSOR 0x3B8
|
||||
#define CAR_CLK_OUT_ENB_V 0x360
|
||||
#define CAR_CLK_SOURCE_TSENSOR 0x3B8
|
||||
#define CAR_CLK_OUT_ENB_V 0x360
|
||||
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES 0xC
|
||||
#define SWR_SOC_THERM_RST 1 << 14
|
||||
#define CLK_RST_CONTROLLER_RST_DEVICES 0xC
|
||||
#define SWR_SOC_THERM_RST 1 << 14
|
||||
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB 0x18
|
||||
#define CLK_ENB_SOC_THERM 1 << 14
|
||||
#define CLK_RST_CONTROLLER_CLK_OUT_ENB 0x18
|
||||
#define CLK_ENB_SOC_THERM 1 << 14
|
||||
|
||||
#define CAR_CLK_SOURCE_TSENSOR_VAL 0x8000005E
|
||||
#define CAR_CLK_SOURCE_TSENSOR_VAL 0x8000005E
|
||||
|
||||
#define THERMCTL_LEVEL0_GROUP_CPU 0x0
|
||||
#define THERMCTL_LEVEL0_GROUP_GPU 0x4
|
||||
#define THERMCTL_LEVEL0_GROUP_MEM 0x8
|
||||
#define THERMCTL_LEVEL0_GROUP_TSENSE 0xc
|
||||
#define THERMCTL_LEVEL0_GROUP_CPU 0x0
|
||||
#define THERMCTL_LEVEL0_GROUP_GPU 0x4
|
||||
#define THERMCTL_LEVEL0_GROUP_MEM 0x8
|
||||
#define THERMCTL_LEVEL0_GROUP_TSENSE 0xc
|
||||
|
||||
#define TEGRA124_SOCTHERM_SENSOR_CPU 0
|
||||
#define TEGRA124_SOCTHERM_SENSOR_MEM 1
|
||||
#define TEGRA124_SOCTHERM_SENSOR_GPU 2
|
||||
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
|
||||
#define TEGRA124_SOCTHERM_SENSOR_NUM 4
|
||||
#define TEGRA124_SOCTHERM_SENSOR_CPU 0
|
||||
#define TEGRA124_SOCTHERM_SENSOR_MEM 1
|
||||
#define TEGRA124_SOCTHERM_SENSOR_GPU 2
|
||||
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
|
||||
#define TEGRA124_SOCTHERM_SENSOR_NUM 4
|
||||
|
||||
#define TEGRA_SOCTHERM_THROT_LEVEL_NONE 0
|
||||
#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 1
|
||||
#define TEGRA_SOCTHERM_THROT_LEVEL_MED 2
|
||||
#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 3
|
||||
#define TEGRA_SOCTHERM_THROT_LEVEL_NONE 0
|
||||
#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 1
|
||||
#define TEGRA_SOCTHERM_THROT_LEVEL_MED 2
|
||||
#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 3
|
||||
|
||||
#define SENSOR_CONFIG2 8
|
||||
#define SENSOR_CONFIG2_THERMA_MASK (0xffffu << 16)
|
||||
#define SENSOR_CONFIG2_THERMB_MASK 0xffff
|
||||
#define SENSOR_CONFIG2 8
|
||||
#define SENSOR_CONFIG2_THERMA_MASK (0xffffu << 16)
|
||||
#define SENSOR_CONFIG2_THERMB_MASK 0xffff
|
||||
|
||||
#define THERMCTL_THERMTRIP_CTL 0x80
|
||||
#define THERMCTL_THERMTRIP_CTL 0x80
|
||||
|
||||
#define SENSOR_PDIV 0x1c0
|
||||
#define SENSOR_PDIV_CPU_MASK (0xf << 12)
|
||||
#define SENSOR_PDIV_GPU_MASK (0xf << 8)
|
||||
#define SENSOR_PDIV_MEM_MASK (0xf << 4)
|
||||
#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
|
||||
#define SENSOR_PDIV 0x1c0
|
||||
#define SENSOR_PDIV_CPU_MASK (0xf << 12)
|
||||
#define SENSOR_PDIV_GPU_MASK (0xf << 8)
|
||||
#define SENSOR_PDIV_MEM_MASK (0xf << 4)
|
||||
#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
|
||||
|
||||
#define SENSOR_HOTSPOT_OFF 0x1c4
|
||||
#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
|
||||
#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
|
||||
#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
|
||||
#define SENSOR_HOTSPOT_OFF 0x1c4
|
||||
#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
|
||||
#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
|
||||
#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
|
||||
|
||||
#define SENSOR_HW_PLLX_OFFSET_EN 0x1e4
|
||||
#define SENSOR_HW_PLLX_OFFSET_MEM_EN_MASK BIT(2)
|
||||
#define SENSOR_HW_PLLX_OFFSET_CPU_EN_MASK BIT(1)
|
||||
#define SENSOR_HW_PLLX_OFFSET_GPU_EN_MASK BIT(0)
|
||||
#define SENSOR_HW_PLLX_OFFSET_EN 0x1e4
|
||||
#define SENSOR_HW_PLLX_OFFSET_MEM_EN_MASK BIT(2)
|
||||
#define SENSOR_HW_PLLX_OFFSET_CPU_EN_MASK BIT(1)
|
||||
#define SENSOR_HW_PLLX_OFFSET_GPU_EN_MASK BIT(0)
|
||||
|
||||
#define SENSOR_HW_PLLX_OFFSET_MIN 0x1e8
|
||||
#define SENSOR_HW_PLLX_OFFSET_MAX 0x1ec
|
||||
#define SENSOR_HW_PLLX_OFFSET_MEM_MASK (0xff << 16)
|
||||
#define SENSOR_HW_PLLX_OFFSET_GPU_MASK (0xff << 8)
|
||||
#define SENSOR_HW_PLLX_OFFSET_CPU_MASK (0xff << 0)
|
||||
#define SENSOR_HW_PLLX_OFFSET_MIN 0x1e8
|
||||
#define SENSOR_HW_PLLX_OFFSET_MAX 0x1ec
|
||||
#define SENSOR_HW_PLLX_OFFSET_MEM_MASK (0xff << 16)
|
||||
#define SENSOR_HW_PLLX_OFFSET_GPU_MASK (0xff << 8)
|
||||
#define SENSOR_HW_PLLX_OFFSET_CPU_MASK (0xff << 0)
|
||||
|
||||
#define SENSOR_TEMP1 0x1c8
|
||||
#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffffu << 16)
|
||||
#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
|
||||
#define SENSOR_TEMP2 0x1cc
|
||||
#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffffu << 16)
|
||||
#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
|
||||
#define SENSOR_TEMP1 0x1c8
|
||||
#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffffu << 16)
|
||||
#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
|
||||
#define SENSOR_TEMP2 0x1cc
|
||||
#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffffu << 16)
|
||||
#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
|
||||
|
||||
#define SENSOR_VALID 0x1e0
|
||||
#define SENSOR_GPU_VALID_MASK BIT(9)
|
||||
#define SENSOR_CPU_VALID_MASK 0xf
|
||||
#define SENSOR_MEM_VALID_MASK (0x3 << 10)
|
||||
#define SENSOR_VALID 0x1e0
|
||||
#define SENSOR_GPU_VALID_MASK BIT(9)
|
||||
#define SENSOR_CPU_VALID_MASK 0xf
|
||||
#define SENSOR_MEM_VALID_MASK (0x3 << 10)
|
||||
|
||||
#define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1u << 31)
|
||||
#define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
|
||||
#define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
|
||||
#define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
|
||||
#define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
|
||||
#define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
|
||||
#define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
|
||||
#define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
|
||||
#define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1u << 31)
|
||||
#define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
|
||||
#define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
|
||||
#define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
|
||||
#define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
|
||||
#define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
|
||||
#define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
|
||||
#define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
|
||||
|
||||
#define TEGRA210_THERM_IRQ_MEM_MASK (0x3 << 24)
|
||||
#define TEGRA210_THERM_IRQ_GPU_MASK (0x3 << 16)
|
||||
#define TEGRA210_THERM_IRQ_CPU_MASK (0x3 << 8)
|
||||
#define TEGRA210_THERM_IRQ_TSENSE_MASK (0x3 << 0)
|
||||
#define TEGRA210_THERM_IRQ_MEM_MASK (0x3 << 24)
|
||||
#define TEGRA210_THERM_IRQ_GPU_MASK (0x3 << 16)
|
||||
#define TEGRA210_THERM_IRQ_CPU_MASK (0x3 << 8)
|
||||
#define TEGRA210_THERM_IRQ_TSENSE_MASK (0x3 << 0)
|
||||
|
||||
#define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
|
||||
#define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
|
||||
#define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
|
||||
#define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
|
||||
|
||||
#define TEGRA210_THRESH_GRAIN 500
|
||||
#define TEGRA210_BPTT 9
|
||||
#define TEGRA210_THRESH_GRAIN 500
|
||||
#define TEGRA210_BPTT 9
|
||||
|
||||
#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
|
||||
#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
|
||||
|
||||
#define SENSOR_CONFIG0 0
|
||||
#define SENSOR_CONFIG0_STOP BIT(0)
|
||||
#define SENSOR_CONFIG0_CPTR_OVER BIT(2)
|
||||
#define SENSOR_CONFIG0_OVER BIT(3)
|
||||
#define SENSOR_CONFIG0_TCALC_OVER BIT(4)
|
||||
#define SENSOR_CONFIG0_TALL_MASK (0xfffff << 8)
|
||||
#define SENSOR_CONFIG0_TALL_SHIFT 8
|
||||
#define SENSOR_CONFIG0 0
|
||||
#define SENSOR_CONFIG0_STOP BIT(0)
|
||||
#define SENSOR_CONFIG0_CPTR_OVER BIT(2)
|
||||
#define SENSOR_CONFIG0_OVER BIT(3)
|
||||
#define SENSOR_CONFIG0_TCALC_OVER BIT(4)
|
||||
#define SENSOR_CONFIG0_TALL_MASK (0xfffff << 8)
|
||||
#define SENSOR_CONFIG0_TALL_SHIFT 8
|
||||
|
||||
#define PDIV_RATE_T210B0 0xCC0C
|
||||
#define PDIV_RATE_T210 0x8888
|
||||
#define HOTSPOT_VAL 0xA0500
|
||||
#define PDIV_RATE_T210B0 0xCC0C
|
||||
#define PDIV_RATE_T210 0x8888
|
||||
#define HOTSPOT_VAL 0xA0500
|
||||
|
||||
#define SENSOR_CONFIG1 4
|
||||
#define SENSOR_CONFIG1_TSAMPLE_MASK 0x3ff
|
||||
#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
|
||||
#define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3f << 15)
|
||||
#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
|
||||
#define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3f << 24)
|
||||
#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
|
||||
#define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
|
||||
#define SENSOR_CONFIG1 4
|
||||
#define SENSOR_CONFIG1_TSAMPLE_MASK 0x3ff
|
||||
#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
|
||||
#define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3f << 15)
|
||||
#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
|
||||
#define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3f << 24)
|
||||
#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
|
||||
#define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
|
||||
|
||||
#define READBACK_VALUE_MASK 0xff00
|
||||
#define READBACK_VALUE_SHIFT 8
|
||||
#define READBACK_ADD_HALF BIT(7)
|
||||
#define READBACK_NEGATE BIT(0)
|
||||
#define READBACK_VALUE_MASK 0xff00
|
||||
#define READBACK_VALUE_SHIFT 8
|
||||
#define READBACK_ADD_HALF BIT(7)
|
||||
#define READBACK_NEGATE BIT(0)
|
||||
|
||||
#define PDIV_MASK_T210B0 0xFFFF00F0
|
||||
#define HOTSPOT_MASK_T210B0 0xFF0000FF
|
||||
#define PDIV_MASK_T210B0 0xFFFF00F0
|
||||
#define HOTSPOT_MASK_T210B0 0xFF0000FF
|
||||
|
||||
#define PDIV_MASK_T210 0xFFFF0000
|
||||
#define HOTSPOT_MASK_T210 0xFF000000
|
||||
#define PDIV_MASK_T210 0xFFFF0000
|
||||
#define HOTSPOT_MASK_T210 0xFF000000
|
||||
|
||||
#define TSENSOR_TSENSOR_CLKEN 0x1DC
|
||||
#define TSENSOR_TSENSOR_ENABLE 225
|
||||
#define TSENSOR_TSENSOR_CLKEN 0x1DC
|
||||
#define TSENSOR_TSENSOR_ENABLE 225
|
||||
|
||||
const TSensorFuse tfuse = {
|
||||
.fuse_base_cp_mask = 0x3ff << 11,
|
||||
.fuse_base_cp_shift = 11,
|
||||
.fuse_base_ft_mask = 0x7ffu << 21,
|
||||
.fuse_base_ft_shift = 21,
|
||||
.fuse_shift_ft_mask = 0x1f << 6,
|
||||
.fuse_shift_ft_shift = 6,
|
||||
.fuse_base_cp_mask = 0x3ff << 11,
|
||||
.fuse_base_cp_shift = 11,
|
||||
.fuse_base_ft_mask = 0x7ffu << 21,
|
||||
.fuse_base_ft_shift = 21,
|
||||
.fuse_shift_ft_mask = 0x1f << 6,
|
||||
.fuse_shift_ft_shift = 6,
|
||||
.fuse_spare_realignment = 0,
|
||||
};
|
||||
|
||||
const TSensorConfig eristaConf = {
|
||||
.tall = 16300,
|
||||
.tiddq_en = 1,
|
||||
.ten_count = 1,
|
||||
.pdiv = 8,
|
||||
.pdiv_ate = 8,
|
||||
.tsample = 120,
|
||||
.tall = 16300,
|
||||
.tiddq_en = 1,
|
||||
.ten_count = 1,
|
||||
.pdiv = 8,
|
||||
.pdiv_ate = 8,
|
||||
.tsample = 120,
|
||||
.tsample_ate = 480,
|
||||
};
|
||||
|
||||
const TSensorConfig marikoConf = {
|
||||
.tall = 16300,
|
||||
.tiddq_en = 1,
|
||||
.ten_count = 1,
|
||||
.pdiv = 12,
|
||||
.pdiv_ate = 6,
|
||||
.tsample = 240,
|
||||
.tall = 16300,
|
||||
.tiddq_en = 1,
|
||||
.ten_count = 1,
|
||||
.pdiv = 12,
|
||||
.pdiv_ate = 6,
|
||||
.tsample = 240,
|
||||
.tsample_ate = 480,
|
||||
};
|
||||
|
||||
@@ -409,10 +411,11 @@ namespace tsensor {
|
||||
u32 calib[SocthermTSensor_EnumMax] = {};
|
||||
u64 socthermVa, carVa, fuseVa;
|
||||
bool isMariko;
|
||||
}
|
||||
} // namespace
|
||||
|
||||
bool IsDisabledThroughSleep() {
|
||||
return (ReadReg(carVa, CLK_RST_CONTROLLER_RST_DEVICES) & SWR_SOC_THERM_RST) || !(ReadReg(carVa, CLK_RST_CONTROLLER_CLK_OUT_ENB) & CLK_ENB_SOC_THERM);
|
||||
return (ReadReg(carVa, CLK_RST_CONTROLLER_RST_DEVICES) & SWR_SOC_THERM_RST) ||
|
||||
!(ReadReg(carVa, CLK_RST_CONTROLLER_CLK_OUT_ENB) & CLK_ENB_SOC_THERM);
|
||||
}
|
||||
|
||||
bool IsSensorEnabled() {
|
||||
@@ -454,14 +457,14 @@ namespace tsensor {
|
||||
EnableSensor(&marikoTSensors[i], i);
|
||||
}
|
||||
|
||||
pdiv = (ReadReg(socthermVa, SENSOR_PDIV) & PDIV_MASK_T210B0) | PDIV_RATE_T210B0;
|
||||
pdiv = (ReadReg(socthermVa, SENSOR_PDIV) & PDIV_MASK_T210B0) | PDIV_RATE_T210B0;
|
||||
hotspot = (ReadReg(socthermVa, SENSOR_HOTSPOT_OFF) & HOTSPOT_MASK_T210B0) | HOTSPOT_VAL;
|
||||
} else {
|
||||
for (u32 i = 0; i < std::size(eristaTSensors); ++i) {
|
||||
EnableSensor(&eristaTSensors[i], i);
|
||||
}
|
||||
|
||||
pdiv = (ReadReg(socthermVa, SENSOR_PDIV) & PDIV_MASK_T210) | PDIV_RATE_T210;
|
||||
pdiv = (ReadReg(socthermVa, SENSOR_PDIV) & PDIV_MASK_T210) | PDIV_RATE_T210;
|
||||
hotspot = (ReadReg(socthermVa, SENSOR_HOTSPOT_OFF) & HOTSPOT_MASK_T210) | HOTSPOT_VAL;
|
||||
}
|
||||
|
||||
@@ -479,8 +482,8 @@ namespace tsensor {
|
||||
StartSensors();
|
||||
}
|
||||
|
||||
temps.cpu = TranslateTemp(ReadReg(socthermVa, SENSOR_TEMP1) >> 16);
|
||||
temps.gpu = TranslateTemp(ReadReg(socthermVa, SENSOR_TEMP1) & SENSOR_TEMP1_GPU_TEMP_MASK);
|
||||
temps.cpu = TranslateTemp(ReadReg(socthermVa, SENSOR_TEMP1) >> 16);
|
||||
temps.gpu = TranslateTemp(ReadReg(socthermVa, SENSOR_TEMP1) & SENSOR_TEMP1_GPU_TEMP_MASK);
|
||||
temps.pllx = TranslateTemp(ReadReg(socthermVa, SENSOR_TEMP2) & SENSOR_TEMP2_PLLX_TEMP_MASK);
|
||||
|
||||
if (board::GetSocType() == HocClkSocType_Erista) {
|
||||
@@ -495,8 +498,8 @@ namespace tsensor {
|
||||
|
||||
constexpr u64 SocthermPa = 0x700E2000, FusePa = 0x7000F000, CarPa = 0x60006000;
|
||||
R_UNLESS(MapAddress(socthermVa, SocthermPa, "soctherm"));
|
||||
R_UNLESS(MapAddress( fuseVa, FusePa, "fuse"));
|
||||
R_UNLESS(MapAddress( carVa, CarPa, "car"));
|
||||
R_UNLESS(MapAddress(fuseVa, FusePa, "fuse"));
|
||||
R_UNLESS(MapAddress(carVa, CarPa, "car"));
|
||||
|
||||
WriteReg(carVa, CAR_CLK_SOURCE_TSENSOR, CAR_CLK_SOURCE_TSENSOR_VAL);
|
||||
SetBits(carVa, CAR_CLK_OUT_ENB_V, 0x10);
|
||||
@@ -507,11 +510,13 @@ namespace tsensor {
|
||||
|
||||
if (isMariko) {
|
||||
for (u32 i = 0; i < std::size(marikoTSensors); ++i) {
|
||||
CalcTSensorCalib(marikoTSensors[i].config, &sharedCal, &marikoTSensors[i].fuse_corr, &calib[i], marikoTSensors[i].calib_fuse_offset, fuseVa);
|
||||
CalcTSensorCalib(marikoTSensors[i].config, &sharedCal, &marikoTSensors[i].fuse_corr, &calib[i], marikoTSensors[i].calib_fuse_offset,
|
||||
fuseVa);
|
||||
}
|
||||
} else {
|
||||
for (u32 i = 0; i < std::size(eristaTSensors); ++i) {
|
||||
CalcTSensorCalib(eristaTSensors[i].config, &sharedCal, &eristaTSensors[i].fuse_corr, &calib[i], eristaTSensors[i].calib_fuse_offset, fuseVa);
|
||||
CalcTSensorCalib(eristaTSensors[i].config, &sharedCal, &eristaTSensors[i].fuse_corr, &calib[i], eristaTSensors[i].calib_fuse_offset,
|
||||
fuseVa);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -520,4 +525,4 @@ namespace tsensor {
|
||||
fileUtils::LogLine("[Soctherm] Finished init.");
|
||||
}
|
||||
|
||||
}
|
||||
} // namespace tsensor
|
||||
@@ -22,20 +22,21 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <switch.h>
|
||||
#include <hocclk.h>
|
||||
#include <switch.h>
|
||||
|
||||
|
||||
namespace tsensor {
|
||||
|
||||
enum SocthermTSensor : u32 {
|
||||
SocthermTSensor_CPU0 = 0,
|
||||
SocthermTSensor_CPU1 = 1,
|
||||
SocthermTSensor_CPU2 = 2,
|
||||
SocthermTSensor_CPU3 = 3,
|
||||
SocthermTSensor_GPU = 4,
|
||||
SocthermTSensor_PLLX = 5,
|
||||
SocthermTSensor_MEM0 = 6,
|
||||
SocthermTSensor_MEM1 = 7,
|
||||
SocthermTSensor_CPU0 = 0,
|
||||
SocthermTSensor_CPU1 = 1,
|
||||
SocthermTSensor_CPU2 = 2,
|
||||
SocthermTSensor_CPU3 = 3,
|
||||
SocthermTSensor_GPU = 4,
|
||||
SocthermTSensor_PLLX = 5,
|
||||
SocthermTSensor_MEM0 = 6,
|
||||
SocthermTSensor_MEM1 = 7,
|
||||
SocthermTSensor_EnumMax = 8,
|
||||
};
|
||||
|
||||
@@ -49,4 +50,4 @@ namespace tsensor {
|
||||
void InitializeSoctherm();
|
||||
void ReadTSensors(TSensorTemps &temps);
|
||||
|
||||
}
|
||||
} // namespace tsensor
|
||||
@@ -23,8 +23,10 @@
|
||||
*/
|
||||
|
||||
#include <switch.h>
|
||||
|
||||
#include "tsensor_common.hpp"
|
||||
|
||||
|
||||
namespace tsensor {
|
||||
|
||||
static s64 div64_s64(s64 dividend, s64 divisor) {
|
||||
@@ -42,7 +44,7 @@ namespace tsensor {
|
||||
|
||||
static s32 sign_extend32(u32 value, int index) {
|
||||
u8 shift = 31 - index;
|
||||
return (s32) (value << shift) >> shift;
|
||||
return (s32)(value << shift) >> shift;
|
||||
}
|
||||
|
||||
void CalcSharedCal(const TSensorFuse *tfuse, TSensorSharedCalib *shared, u64 fuseVa) {
|
||||
@@ -70,11 +72,11 @@ namespace tsensor {
|
||||
}
|
||||
|
||||
void CalcTSensorCalib(const TSensorConfig *cfg, TSensorSharedCalib *shared, const FuseCorrCoeff *corr, u32 *calibration, u32 offset, u64 fuseVa) {
|
||||
#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
|
||||
#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
|
||||
#define CALIB_COEFFICIENT 1000000LL
|
||||
#define SENSOR_CONFIG2_THERMA_SHIFT 16
|
||||
#define SENSOR_CONFIG2_THERMB_SHIFT 0
|
||||
#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
|
||||
#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
|
||||
#define CALIB_COEFFICIENT 1000000LL
|
||||
#define SENSOR_CONFIG2_THERMA_SHIFT 16
|
||||
#define SENSOR_CONFIG2_THERMB_SHIFT 0
|
||||
|
||||
u32 val, calib;
|
||||
s32 actual_tsensor_ft, actual_tsensor_cp;
|
||||
@@ -112,4 +114,4 @@ namespace tsensor {
|
||||
*calibration = calib;
|
||||
}
|
||||
|
||||
}
|
||||
} // namespace tsensor
|
||||
@@ -26,8 +26,8 @@
|
||||
|
||||
namespace tsensor {
|
||||
|
||||
#define FUSE_TSENSOR_COMMON 0xA80
|
||||
#define FUSE_OFFSET 0x800
|
||||
#define FUSE_TSENSOR_COMMON 0xA80
|
||||
#define FUSE_OFFSET 0x800
|
||||
|
||||
struct TSensorConfig {
|
||||
u32 tall;
|
||||
@@ -96,27 +96,23 @@ namespace tsensor {
|
||||
u32 actual_temp_ft;
|
||||
};
|
||||
|
||||
template<typename T = u32>
|
||||
static inline T ReadReg(u64 base, u32 offset) {
|
||||
return *reinterpret_cast<volatile T*>(base + offset);
|
||||
template <typename T = u32> static inline T ReadReg(u64 base, u32 offset) {
|
||||
return *reinterpret_cast<volatile T *>(base + offset);
|
||||
}
|
||||
|
||||
template<typename T = u32>
|
||||
static inline void WriteReg(u64 base, u32 offset, T value) {
|
||||
*reinterpret_cast<volatile T*>(base + offset) = value;
|
||||
template <typename T = u32> static inline void WriteReg(u64 base, u32 offset, T value) {
|
||||
*reinterpret_cast<volatile T *>(base + offset) = value;
|
||||
}
|
||||
|
||||
template<typename T = u32>
|
||||
static inline void SetBits(u64 base, u32 offset, T mask) {
|
||||
template <typename T = u32> static inline void SetBits(u64 base, u32 offset, T mask) {
|
||||
WriteReg(base, offset, ReadReg<T>(base, offset) | mask);
|
||||
}
|
||||
|
||||
template<typename T = u32>
|
||||
static inline void ClearBits(u64 base, u32 offset, T mask) {
|
||||
template <typename T = u32> static inline void ClearBits(u64 base, u32 offset, T mask) {
|
||||
WriteReg(base, offset, ReadReg<T>(base, offset) & ~mask);
|
||||
}
|
||||
|
||||
void CalcSharedCal(const TSensorFuse *tfuse, TSensorSharedCalib *shared, u64 fuseVa);
|
||||
void CalcTSensorCalib(const TSensorConfig *cfg, TSensorSharedCalib *shared, const FuseCorrCoeff *corr, u32 *calibration, u32 offset, u64 fuseVa);
|
||||
|
||||
}
|
||||
} // namespace tsensor
|
||||
Reference in new issue
Block a user