OmniNX/Horizon-OC-pro
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hocclk: format code

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use clang format file provided for optimal formatting
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souldbminersmwc committed 2026-06-04 19:52:11 -04:00
1 parent c6a8884c14
commit 88bfa9a4ec
118 files changed
+7111 -9615
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Source/hoc-clk/sysmodule/src/soc/gm20b.cpp
+47 -55
View File
@@ -14,56 +14,56 @@
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*
*/
#include "gm20b.hpp"
#include "../mapping/mem_map.hpp"
#include "gm20b.hpp"
namespace gm20b {
u64 gpu_base = 0;
#define GPU_PA 0x57000000
#define GPU_SIZE 0x1000000
#define GPU_TRIM_SYS_GPCPLL_CFG 0x00
#define GPU_TRIM_SYS_GPCPLL_COEFF 0x04
#define GPU_TRIM_SYS_GPCPLL_CFG2 0x08
#define GPU_TRIM_SYS_GPCPLL_CFG3 0x0C
#define GPU_TRIM_SYS_GPCPLL_DVFS0 0x10
#define GPU_TRIM_SYS_GPCPLL_DVFS1 0x14
#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x1C
#define GPU_TRIM_SYS_SEL_VCO 0x2C
#define GPU_TRIM_SYS_GPC2CLK_OUT 0x250
#define GPU_PA 0x57000000
#define GPU_SIZE 0x1000000
#define GPU_TRIM_SYS_GPCPLL_CFG 0x00
#define GPU_TRIM_SYS_GPCPLL_COEFF 0x04
#define GPU_TRIM_SYS_GPCPLL_CFG2 0x08
#define GPU_TRIM_SYS_GPCPLL_CFG3 0x0C
#define GPU_TRIM_SYS_GPCPLL_DVFS0 0x10
#define GPU_TRIM_SYS_GPCPLL_DVFS1 0x14
#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x1C
#define GPU_TRIM_SYS_SEL_VCO 0x2C
#define GPU_TRIM_SYS_GPC2CLK_OUT 0x250
#define GPC_BCAST(x) (*(volatile u32 *)(gpu_base + 0x132800ul + (x)))
#define GPU_TRIM_SYS_GPCPLL(x) (*(volatile u32 *)(gpu_base + 0x137000ul + (x)))
#define GPC_BCAST(x) (*(volatile u32 *)(gpu_base + 0x132800ul + (x)))
#define GPU_TRIM_SYS_GPCPLL(x) (*(volatile u32 *)(gpu_base + 0x137000ul + (x)))
#define GPC_BCAST_GPCPLL_DVFS2 0x20
#define GPC_BCAST_NDIV_SLOWDOWN_DBG 0xa0
#define GPC_BCAST_GPCPLL_DVFS2 0x20
#define GPC_BCAST_NDIV_SLOWDOWN_DBG 0xa0
#define GPCPLL_CFG_ENABLE BIT(0)
#define GPCPLL_CFG_IDDQ BIT(1)
#define GPCPLL_CFG_SYNC_MODE BIT(2)
#define GPCPLL_CFG_LOCK BIT(17)
#define GPCPLL_CFG_ENABLE BIT(0)
#define GPCPLL_CFG_IDDQ BIT(1)
#define GPCPLL_CFG_SYNC_MODE BIT(2)
#define GPCPLL_CFG_LOCK BIT(17)
#define GPCPLL_CFG2_SDM_DIN_MASK 0x000000FFu
#define GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x007FFF00u
#define GPCPLL_CFG2_STEPA_SHIFT 24
#define GPCPLL_CFG2_STEPA_MASK 0xFF000000u
#define GPCPLL_CFG2_SDM_DIN_MASK 0x000000FFu
#define GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x007FFF00u
#define GPCPLL_CFG2_STEPA_SHIFT 24
#define GPCPLL_CFG2_STEPA_MASK 0xFF000000u
#define GPCPLL_CFG3_STEPB_SHIFT 16
#define GPCPLL_CFG3_STEPB_MASK 0x00FF0000u
#define GPCPLL_CFG3_STEPB_SHIFT 16
#define GPCPLL_CFG3_STEPB_MASK 0x00FF0000u
#define GPCPLL_DVFS0_DFS_COEFF_MASK 0x0000007Fu
#define GPCPLL_DVFS0_DFS_COEFF_MASK 0x0000007Fu
#define NDIV_SLOWDOWN_SLOWDOWN_USING_PLL BIT(22)
#define NDIV_SLOWDOWN_EN_DYNRAMP BIT(23)
#define NDIV_SLOWDOWN_SLOWDOWN_USING_PLL BIT(22)
#define NDIV_SLOWDOWN_EN_DYNRAMP BIT(23)
#define DYNRAMP_DONE_SYNCED BIT(24)
#define DYNRAMP_DONE_SYNCED BIT(24)
#define GPCPLL_DVFS2_DFS_EXT_STROBE BIT(16)
#define GPCPLL_DVFS2_DFS_EXT_STROBE BIT(16)
#define RAMP_TIMEOUT_US 500
#define RAMP_TIMEOUT_US 500
static inline void _gpu_mask(u32 reg, u32 mask, u32 val) {
u32 tmp = GPU_TRIM_SYS_GPCPLL(reg);
@@ -78,12 +78,8 @@ namespace gm20b {
}
static void _clk_setup_slide() {
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2,
GPCPLL_CFG2_STEPA_MASK,
0x04u << GPCPLL_CFG2_STEPA_SHIFT);
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG3,
GPCPLL_CFG3_STEPB_MASK,
0x05u << GPCPLL_CFG3_STEPB_SHIFT);
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2, GPCPLL_CFG2_STEPA_MASK, 0x04u << GPCPLL_CFG2_STEPA_SHIFT);
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG3, GPCPLL_CFG3_STEPB_MASK, 0x05u << GPCPLL_CFG3_STEPB_SHIFT);
}
static bool _gpu_pllg_slide(u32 new_divn) {
@@ -95,9 +91,7 @@ namespace gm20b {
_clk_setup_slide();
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN,
NDIV_SLOWDOWN_SLOWDOWN_USING_PLL,
NDIV_SLOWDOWN_SLOWDOWN_USING_PLL);
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN, NDIV_SLOWDOWN_SLOWDOWN_USING_PLL, NDIV_SLOWDOWN_SLOWDOWN_USING_PLL);
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_NEW_MASK, 0);
@@ -106,9 +100,7 @@ namespace gm20b {
GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF) = coeff;
usleep(1);
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN,
NDIV_SLOWDOWN_EN_DYNRAMP,
NDIV_SLOWDOWN_EN_DYNRAMP);
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN, NDIV_SLOWDOWN_EN_DYNRAMP, NDIV_SLOWDOWN_EN_DYNRAMP);
int ramp_timeout = RAMP_TIMEOUT_US;
bool success = false;
@@ -125,9 +117,7 @@ namespace gm20b {
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_MASK, 0);
}
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN,
NDIV_SLOWDOWN_SLOWDOWN_USING_PLL | NDIV_SLOWDOWN_EN_DYNRAMP,
0);
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN, NDIV_SLOWDOWN_SLOWDOWN_USING_PLL | NDIV_SLOWDOWN_EN_DYNRAMP, 0);
(void)GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN);
return success;
@@ -137,11 +127,11 @@ namespace gm20b {
if (!gpu_base)
QueryMemoryMapping(&gpu_base, GPU_PA, GPU_SIZE);
const u32 osc_khz = 38400; // PLL Hz
const u32 osc_khz = 38400; // PLL Hz
u32 coeff = GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF);
u32 divm = coeff & 0xFF;
u32 divp = (coeff >> 16) & 0x3F;
u32 divm = coeff & 0xFF;
u32 divp = (coeff >> 16) & 0x3F;
if (divm == 0 || divp == 0)
return false;
@@ -149,9 +139,11 @@ namespace gm20b {
u32 new_divn = (u64)khz * divm * divp * 2 / osc_khz;
// L4T clamps the registers here for some reason, do that
if (new_divn < 8) new_divn = 8;
if (new_divn > 255) new_divn = 255;
if (new_divn < 8)
new_divn = 8;
if (new_divn > 255)
new_divn = 255;
return _gpu_pllg_slide(new_divn);
}
}
} // namespace gm20b