hocclk: format code
use clang format file provided for optimal formatting
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@@ -4,7 +4,7 @@
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* Copyright (c) 2018 balika011
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* Copyright (c) 2019-2025 CTCaer
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* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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@@ -22,293 +22,283 @@
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#define _FUSE_H_
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#ifndef BIT
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#define BIT(n) (1U<<(n))
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#define BIT(n) (1U << (n))
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#endif
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/*! Fuse registers. */
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#define FUSE_CTRL 0x0
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#define FUSE_ADDR 0x4
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#define FUSE_RDATA 0x8
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#define FUSE_WDATA 0xC
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#define FUSE_TIME_RD1 0x10
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#define FUSE_TIME_RD2 0x14
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#define FUSE_TIME_PGM1 0x18
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#define FUSE_TIME_PGM2 0x1C
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#define FUSE_PRIV2INTFC 0x20
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#define FUSE_PRIV2INTFC_START_DATA BIT(0)
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#define FUSE_PRIV2INTFC_SKIP_RECORDS BIT(1)
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#define FUSE_FUSEBYPASS 0x24
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#define FUSE_PRIVATEKEYDISABLE 0x28
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#define FUSE_PRIVKEY_DISABLE BIT(0)
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#define FUSE_PRIVKEY_TZ_STICKY_BIT BIT(4)
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#define FUSE_DISABLEREGPROGRAM 0x2C
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#define FUSE_WRITE_ACCESS_SW 0x30
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#define FUSE_PWR_GOOD_SW 0x34
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#define FUSE_PRIV2RESHIFT 0x3C
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#define FUSE_FUSETIME_RD0 0x40
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#define FUSE_FUSETIME_RD1 0x44
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#define FUSE_FUSETIME_RD2 0x48
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#define FUSE_FUSETIME_RD3 0x4C
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#define FUSE_PRIVATE_KEY0_NONZERO 0x80
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#define FUSE_PRIVATE_KEY1_NONZERO 0x84
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#define FUSE_PRIVATE_KEY2_NONZERO 0x88
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#define FUSE_PRIVATE_KEY3_NONZERO 0x8C
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#define FUSE_PRIVATE_KEY4_NONZERO 0x90
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#define FUSE_CTRL 0x0
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#define FUSE_ADDR 0x4
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#define FUSE_RDATA 0x8
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#define FUSE_WDATA 0xC
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#define FUSE_TIME_RD1 0x10
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#define FUSE_TIME_RD2 0x14
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#define FUSE_TIME_PGM1 0x18
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#define FUSE_TIME_PGM2 0x1C
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#define FUSE_PRIV2INTFC 0x20
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#define FUSE_PRIV2INTFC_START_DATA BIT(0)
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#define FUSE_PRIV2INTFC_SKIP_RECORDS BIT(1)
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#define FUSE_FUSEBYPASS 0x24
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#define FUSE_PRIVATEKEYDISABLE 0x28
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#define FUSE_PRIVKEY_DISABLE BIT(0)
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#define FUSE_PRIVKEY_TZ_STICKY_BIT BIT(4)
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#define FUSE_DISABLEREGPROGRAM 0x2C
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#define FUSE_WRITE_ACCESS_SW 0x30
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#define FUSE_PWR_GOOD_SW 0x34
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#define FUSE_PRIV2RESHIFT 0x3C
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#define FUSE_FUSETIME_RD0 0x40
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#define FUSE_FUSETIME_RD1 0x44
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#define FUSE_FUSETIME_RD2 0x48
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#define FUSE_FUSETIME_RD3 0x4C
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#define FUSE_PRIVATE_KEY0_NONZERO 0x80
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#define FUSE_PRIVATE_KEY1_NONZERO 0x84
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#define FUSE_PRIVATE_KEY2_NONZERO 0x88
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#define FUSE_PRIVATE_KEY3_NONZERO 0x8C
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#define FUSE_PRIVATE_KEY4_NONZERO 0x90
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/*! Fuse Cached registers */
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#define FUSE_RESERVED_ODM8_B01 0x98 // FUSE_READ_TZ Group 0.
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#define FUSE_RESERVED_ODM9_B01 0x9C // FUSE_READ_TZ Group 0.
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#define FUSE_RESERVED_ODM10_B01 0xA0 // FUSE_READ_TZ Group 0.
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#define FUSE_RESERVED_ODM11_B01 0xA4 // FUSE_READ_TZ Group 0.
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#define FUSE_RESERVED_ODM12_B01 0xA8 // FUSE_READ_TZ Group 1? Is value -1?
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#define FUSE_RESERVED_ODM13_B01 0xAC // FUSE_READ_TZ Group 1? Is value -1?
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#define FUSE_RESERVED_ODM14_B01 0xB0 // FUSE_READ_TZ Group 1? Is value -1?
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#define FUSE_RESERVED_ODM15_B01 0xB4 // FUSE_READ_TZ Group 1? Is value -1?
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#define FUSE_RESERVED_ODM16_B01 0xB8 // FUSE_READ_TZ Group 2? Is value -1?
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#define FUSE_RESERVED_ODM17_B01 0xBC // FUSE_READ_TZ Group 2? Is value -1?
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#define FUSE_RESERVED_ODM18_B01 0xC0 // FUSE_READ_TZ Group 2.
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#define FUSE_RESERVED_ODM19_B01 0xC4 // FUSE_READ_TZ Group 2.
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#define FUSE_RESERVED_ODM20_B01 0xC8 // FUSE_READ_TZ Group 3.
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#define FUSE_RESERVED_ODM21_B01 0xCC // FUSE_READ_TZ Group 3.
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#define FUSE_KEK00_B01 0xD0
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#define FUSE_KEK01_B01 0xD4
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#define FUSE_KEK02_B01 0xD8
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#define FUSE_KEK03_B01 0xDC
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#define FUSE_BEK00_B01 0xE0
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#define FUSE_BEK01_B01 0xE4
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#define FUSE_BEK02_B01 0xE8
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#define FUSE_BEK03_B01 0xEC
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#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4SVT_B01 0xF0
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#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4SVT_B01 0xF4
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#define FUSE_RESERVED_ODM8_B01 0x98 // FUSE_READ_TZ Group 0.
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#define FUSE_RESERVED_ODM9_B01 0x9C // FUSE_READ_TZ Group 0.
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#define FUSE_RESERVED_ODM10_B01 0xA0 // FUSE_READ_TZ Group 0.
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#define FUSE_RESERVED_ODM11_B01 0xA4 // FUSE_READ_TZ Group 0.
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#define FUSE_RESERVED_ODM12_B01 0xA8 // FUSE_READ_TZ Group 1? Is value -1?
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#define FUSE_RESERVED_ODM13_B01 0xAC // FUSE_READ_TZ Group 1? Is value -1?
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#define FUSE_RESERVED_ODM14_B01 0xB0 // FUSE_READ_TZ Group 1? Is value -1?
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#define FUSE_RESERVED_ODM15_B01 0xB4 // FUSE_READ_TZ Group 1? Is value -1?
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#define FUSE_RESERVED_ODM16_B01 0xB8 // FUSE_READ_TZ Group 2? Is value -1?
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#define FUSE_RESERVED_ODM17_B01 0xBC // FUSE_READ_TZ Group 2? Is value -1?
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#define FUSE_RESERVED_ODM18_B01 0xC0 // FUSE_READ_TZ Group 2.
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#define FUSE_RESERVED_ODM19_B01 0xC4 // FUSE_READ_TZ Group 2.
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#define FUSE_RESERVED_ODM20_B01 0xC8 // FUSE_READ_TZ Group 3.
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#define FUSE_RESERVED_ODM21_B01 0xCC // FUSE_READ_TZ Group 3.
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#define FUSE_KEK00_B01 0xD0
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#define FUSE_KEK01_B01 0xD4
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#define FUSE_KEK02_B01 0xD8
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#define FUSE_KEK03_B01 0xDC
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#define FUSE_BEK00_B01 0xE0
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#define FUSE_BEK01_B01 0xE4
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#define FUSE_BEK02_B01 0xE8
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#define FUSE_BEK03_B01 0xEC
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#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4SVT_B01 0xF0
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#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4SVT_B01 0xF4
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#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4SVT_B01 0xF8
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#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4SVT_B01 0xFC
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#define FUSE_PRODUCTION_MODE 0x100
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#define FUSE_JTAG_SECUREID_VALID 0x104
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#define FUSE_ODM_LOCK 0x108
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#define FUSE_OPT_OPENGL_EN 0x10C
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#define FUSE_SKU_INFO 0x110
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#define FUSE_CPU_SPEEDO_0_CALIB 0x114
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#define FUSE_CPU_IDDQ_CALIB 0x118
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#define FUSE_PRODUCTION_MODE 0x100
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#define FUSE_JTAG_SECUREID_VALID 0x104
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#define FUSE_ODM_LOCK 0x108
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#define FUSE_OPT_OPENGL_EN 0x10C
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#define FUSE_SKU_INFO 0x110
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#define FUSE_CPU_SPEEDO_0_CALIB 0x114
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#define FUSE_CPU_IDDQ_CALIB 0x118
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#define FUSE_RESERVED_ODM22_B01 0x11C // FUSE_READ_TZ Group 3.
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#define FUSE_RESERVED_ODM23_B01 0x120 // FUSE_READ_TZ Group 3.
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#define FUSE_RESERVED_ODM24_B01 0x124 // FUSE_READ_TZ Group 4.
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#define FUSE_RESERVED_ODM22_B01 0x11C // FUSE_READ_TZ Group 3.
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#define FUSE_RESERVED_ODM23_B01 0x120 // FUSE_READ_TZ Group 3.
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#define FUSE_RESERVED_ODM24_B01 0x124 // FUSE_READ_TZ Group 4.
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#define FUSE_OPT_FT_REV 0x128
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#define FUSE_CPU_SPEEDO_1_CALIB 0x12C
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#define FUSE_CPU_SPEEDO_2_CALIB 0x130
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#define FUSE_SOC_SPEEDO_0_CALIB 0x134
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#define FUSE_SOC_SPEEDO_1_CALIB 0x138
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#define FUSE_SOC_SPEEDO_2_CALIB 0x13C
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#define FUSE_SOC_IDDQ_CALIB 0x140
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#define FUSE_OPT_FT_REV 0x128
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#define FUSE_CPU_SPEEDO_1_CALIB 0x12C
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#define FUSE_CPU_SPEEDO_2_CALIB 0x130
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#define FUSE_SOC_SPEEDO_0_CALIB 0x134
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#define FUSE_SOC_SPEEDO_1_CALIB 0x138
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#define FUSE_SOC_SPEEDO_2_CALIB 0x13C
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#define FUSE_SOC_IDDQ_CALIB 0x140
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#define FUSE_RESERVED_ODM25_B01 0x144 // FUSE_READ_TZ Group 4.
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#define FUSE_RESERVED_ODM25_B01 0x144 // FUSE_READ_TZ Group 4.
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#define FUSE_FA 0x148
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#define FUSE_RESERVED_PRODUCTION 0x14C
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#define FUSE_HDMI_LANE0_CALIB 0x150
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#define FUSE_HDMI_LANE1_CALIB 0x154
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#define FUSE_HDMI_LANE2_CALIB 0x158
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#define FUSE_HDMI_LANE3_CALIB 0x15C
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#define FUSE_ENCRYPTION_RATE 0x160
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#define FUSE_PUBLIC_KEY0 0x164
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#define FUSE_PUBLIC_KEY1 0x168
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#define FUSE_PUBLIC_KEY2 0x16C
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#define FUSE_PUBLIC_KEY3 0x170
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#define FUSE_PUBLIC_KEY4 0x174
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#define FUSE_PUBLIC_KEY5 0x178
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#define FUSE_PUBLIC_KEY6 0x17C
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#define FUSE_PUBLIC_KEY7 0x180
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#define FUSE_TSENSOR1_CALIB 0x184 // CPU1.
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#define FUSE_TSENSOR2_CALIB 0x188 // CPU2.
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#define FUSE_FA 0x148
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#define FUSE_RESERVED_PRODUCTION 0x14C
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#define FUSE_HDMI_LANE0_CALIB 0x150
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#define FUSE_HDMI_LANE1_CALIB 0x154
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#define FUSE_HDMI_LANE2_CALIB 0x158
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#define FUSE_HDMI_LANE3_CALIB 0x15C
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#define FUSE_ENCRYPTION_RATE 0x160
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#define FUSE_PUBLIC_KEY0 0x164
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#define FUSE_PUBLIC_KEY1 0x168
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#define FUSE_PUBLIC_KEY2 0x16C
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#define FUSE_PUBLIC_KEY3 0x170
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#define FUSE_PUBLIC_KEY4 0x174
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#define FUSE_PUBLIC_KEY5 0x178
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#define FUSE_PUBLIC_KEY6 0x17C
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#define FUSE_PUBLIC_KEY7 0x180
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#define FUSE_TSENSOR1_CALIB 0x184 // CPU1.
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#define FUSE_TSENSOR2_CALIB 0x188 // CPU2.
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#define FUSE_OPT_SECURE_SCC_DIS_B01 0x18C
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#define FUSE_OPT_SECURE_SCC_DIS_B01 0x18C
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#define FUSE_OPT_CP_REV 0x190 // FUSE style revision - ATE. 0x101 0x100
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#define FUSE_OPT_PFG 0x194
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#define FUSE_TSENSOR0_CALIB 0x198 // CPU0.
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#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19C
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#define FUSE_SECURITY_MODE 0x1A0
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#define FUSE_PRIVATE_KEY0 0x1A4
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#define FUSE_PRIVATE_KEY1 0x1A8
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#define FUSE_PRIVATE_KEY2 0x1AC
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#define FUSE_PRIVATE_KEY3 0x1B0
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#define FUSE_PRIVATE_KEY4 0x1B4
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#define FUSE_ARM_JTAG_DIS 0x1B8
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#define FUSE_BOOT_DEVICE_INFO 0x1BC
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#define FUSE_RESERVED_SW 0x1C0
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#define FUSE_OPT_VP9_DISABLE 0x1C4
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#define FUSE_OPT_CP_REV 0x190 // FUSE style revision - ATE. 0x101 0x100
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#define FUSE_OPT_PFG 0x194
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#define FUSE_TSENSOR0_CALIB 0x198 // CPU0.
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#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19C
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#define FUSE_SECURITY_MODE 0x1A0
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#define FUSE_PRIVATE_KEY0 0x1A4
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#define FUSE_PRIVATE_KEY1 0x1A8
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#define FUSE_PRIVATE_KEY2 0x1AC
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#define FUSE_PRIVATE_KEY3 0x1B0
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#define FUSE_PRIVATE_KEY4 0x1B4
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#define FUSE_ARM_JTAG_DIS 0x1B8
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#define FUSE_BOOT_DEVICE_INFO 0x1BC
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#define FUSE_RESERVED_SW 0x1C0
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#define FUSE_OPT_VP9_DISABLE 0x1C4
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#define FUSE_RESERVED_ODM0 0x1C8
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#define FUSE_RESERVED_ODM1 0x1CC
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#define FUSE_RESERVED_ODM2 0x1D0
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#define FUSE_RESERVED_ODM3 0x1D4
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#define FUSE_RESERVED_ODM4 0x1D8
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#define FUSE_RESERVED_ODM5 0x1DC
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#define FUSE_RESERVED_ODM6 0x1E0
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#define FUSE_RESERVED_ODM7 0x1E4
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#define FUSE_RESERVED_ODM0 0x1C8
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#define FUSE_RESERVED_ODM1 0x1CC
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#define FUSE_RESERVED_ODM2 0x1D0
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#define FUSE_RESERVED_ODM3 0x1D4
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#define FUSE_RESERVED_ODM4 0x1D8
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#define FUSE_RESERVED_ODM5 0x1DC
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#define FUSE_RESERVED_ODM6 0x1E0
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#define FUSE_RESERVED_ODM7 0x1E4
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#define FUSE_OBS_DIS 0x1E8
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#define FUSE_OBS_DIS 0x1E8
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#define FUSE_OPT_NVJTAG_PROTECTION_ENABLE_B01 0x1EC
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#define FUSE_USB_CALIB 0x1F0
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#define FUSE_SKU_DIRECT_CONFIG 0x1F4
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#define FUSE_KFUSE_PRIVKEY_CTRL 0x1F8
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#define FUSE_PACKAGE_INFO 0x1FC // 1: MID, 2: DSC.
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#define FUSE_OPT_VENDOR_CODE 0x200
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#define FUSE_OPT_FAB_CODE 0x204
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#define FUSE_OPT_LOT_CODE_0 0x208
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#define FUSE_OPT_LOT_CODE_1 0x20C
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#define FUSE_OPT_WAFER_ID 0x210
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#define FUSE_OPT_X_COORDINATE 0x214
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#define FUSE_OPT_Y_COORDINATE 0x218
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#define FUSE_OPT_SEC_DEBUG_EN 0x21C
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#define FUSE_OPT_OPS_RESERVED 0x220
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#define FUSE_SATA_CALIB 0x224
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#define FUSE_USB_CALIB 0x1F0
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#define FUSE_SKU_DIRECT_CONFIG 0x1F4
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#define FUSE_KFUSE_PRIVKEY_CTRL 0x1F8
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#define FUSE_PACKAGE_INFO 0x1FC // 1: MID, 2: DSC.
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#define FUSE_OPT_VENDOR_CODE 0x200
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#define FUSE_OPT_FAB_CODE 0x204
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#define FUSE_OPT_LOT_CODE_0 0x208
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#define FUSE_OPT_LOT_CODE_1 0x20C
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#define FUSE_OPT_WAFER_ID 0x210
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#define FUSE_OPT_X_COORDINATE 0x214
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#define FUSE_OPT_Y_COORDINATE 0x218
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#define FUSE_OPT_SEC_DEBUG_EN 0x21C
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#define FUSE_OPT_OPS_RESERVED 0x220
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#define FUSE_SATA_CALIB 0x224
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#define FUSE_SPARE_REGISTER_ODM_B01 0x224
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#define FUSE_SPARE_REGISTER_ODM_B01 0x224
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#define FUSE_GPU_IDDQ_CALIB 0x228
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#define FUSE_TSENSOR3_CALIB 0x22C // CPU3.
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#define FUSE_CLOCK_BONDOUT0 0x230
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#define FUSE_CLOCK_BONDOUT1 0x234
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#define FUSE_GPU_IDDQ_CALIB 0x228
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#define FUSE_TSENSOR3_CALIB 0x22C // CPU3.
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#define FUSE_CLOCK_BONDOUT0 0x230
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#define FUSE_CLOCK_BONDOUT1 0x234
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#define FUSE_RESERVED_ODM26_B01 0x238 // FUSE_READ_TZ Group 4.
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#define FUSE_RESERVED_ODM27_B01 0x23C // FUSE_READ_TZ Group 4.
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#define FUSE_RESERVED_ODM28_B01 0x240 // MAX77812 phase configuration. FUSE_READ_TZ Group 5.
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#define FUSE_RESERVED_ODM26_B01 0x238 // FUSE_READ_TZ Group 4.
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#define FUSE_RESERVED_ODM27_B01 0x23C // FUSE_READ_TZ Group 4.
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#define FUSE_RESERVED_ODM28_B01 0x240 // MAX77812 phase configuration. FUSE_READ_TZ Group 5.
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#define FUSE_OPT_SAMPLE_TYPE 0x244
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#define FUSE_OPT_SUBREVISION 0x248 // "", "p", "q", "r". e.g: A01p.
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#define FUSE_OPT_SW_RESERVED_0 0x24C
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#define FUSE_OPT_SW_RESERVED_1 0x250
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#define FUSE_TSENSOR4_CALIB 0x254 // GPU.
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#define FUSE_TSENSOR5_CALIB 0x258 // MEM0.
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#define FUSE_TSENSOR6_CALIB 0x25C // MEM1.
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#define FUSE_TSENSOR7_CALIB 0x260 // PLLX.
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#define FUSE_OPT_PRIV_SEC_DIS 0x264
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#define FUSE_PKC_DISABLE 0x268
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#define FUSE_OPT_SAMPLE_TYPE 0x244
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#define FUSE_OPT_SUBREVISION 0x248 // "", "p", "q", "r". e.g: A01p.
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#define FUSE_OPT_SW_RESERVED_0 0x24C
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#define FUSE_OPT_SW_RESERVED_1 0x250
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#define FUSE_TSENSOR4_CALIB 0x254 // GPU.
|
||||
#define FUSE_TSENSOR5_CALIB 0x258 // MEM0.
|
||||
#define FUSE_TSENSOR6_CALIB 0x25C // MEM1.
|
||||
#define FUSE_TSENSOR7_CALIB 0x260 // PLLX.
|
||||
#define FUSE_OPT_PRIV_SEC_DIS 0x264
|
||||
#define FUSE_PKC_DISABLE 0x268
|
||||
|
||||
#define FUSE_BOOT_SECURITY_INFO_B01 0x268
|
||||
#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4HVT_B01 0x26C
|
||||
#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4HVT_B01 0x270
|
||||
#define FUSE_BOOT_SECURITY_INFO_B01 0x268
|
||||
#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4HVT_B01 0x26C
|
||||
#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4HVT_B01 0x270
|
||||
#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4HVT_B01 0x274
|
||||
#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4HVT_B01 0x278
|
||||
|
||||
#define FUSE_FUSE2TSEC_DEBUG_DISABLE 0x27C
|
||||
#define FUSE_TSENSOR_COMMON 0x280
|
||||
#define FUSE_OPT_CP_BIN 0x284
|
||||
#define FUSE_OPT_GPU_DISABLE 0x288
|
||||
#define FUSE_OPT_FT_BIN 0x28C
|
||||
#define FUSE_OPT_DONE_MAP 0x290
|
||||
#define FUSE_FUSE2TSEC_DEBUG_DISABLE 0x27C
|
||||
#define FUSE_TSENSOR_COMMON 0x280
|
||||
#define FUSE_OPT_CP_BIN 0x284
|
||||
#define FUSE_OPT_GPU_DISABLE 0x288
|
||||
#define FUSE_OPT_FT_BIN 0x28C
|
||||
#define FUSE_OPT_DONE_MAP 0x290
|
||||
|
||||
#define FUSE_RESERVED_ODM29_B01 0x294 // FUSE_READ_TZ Group 5? Is value -1?
|
||||
#define FUSE_RESERVED_ODM29_B01 0x294 // FUSE_READ_TZ Group 5? Is value -1?
|
||||
|
||||
#define FUSE_APB2JTAG_DISABLE 0x298
|
||||
#define FUSE_ODM_INFO 0x29C // Debug features disable.
|
||||
#define FUSE_ARM_CRYPT_DE_FEATURE 0x2A8
|
||||
#define FUSE_APB2JTAG_DISABLE 0x298
|
||||
#define FUSE_ODM_INFO 0x29C // Debug features disable.
|
||||
#define FUSE_ARM_CRYPT_DE_FEATURE 0x2A8
|
||||
|
||||
#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4SVT_B01 0x2B0
|
||||
#define FUSE_OPT_RAM_RCT_TSMCDP_PO4SVT_B01 0x2B4
|
||||
#define FUSE_OPT_RAM_WCT_TSMCDP_PO4SVT_B01 0x2B8
|
||||
#define FUSE_OPT_RAM_KP_TSMCDP_PO4SVT_B01 0x2BC
|
||||
#define FUSE_OPT_RAM_RCT_TSMCDP_PO4SVT_B01 0x2B4
|
||||
#define FUSE_OPT_RAM_WCT_TSMCDP_PO4SVT_B01 0x2B8
|
||||
#define FUSE_OPT_RAM_KP_TSMCDP_PO4SVT_B01 0x2BC
|
||||
|
||||
#define FUSE_WOA_SKU_FLAG 0x2C0
|
||||
#define FUSE_ECO_RESERVE_1 0x2C4
|
||||
#define FUSE_GCPLEX_CONFIG_FUSE 0x2C8
|
||||
#define FUSE_GPU_VPR_AUTO_FETCH_DIS BIT(0)
|
||||
#define FUSE_GPU_VPR_ENABLED BIT(1)
|
||||
#define FUSE_GPU_WPR_ENABLED BIT(2)
|
||||
#define FUSE_PRODUCTION_MONTH 0x2CC
|
||||
#define FUSE_RAM_REPAIR_INDICATOR 0x2D0
|
||||
#define FUSE_TSENSOR9_CALIB 0x2D4 // AOTAG.
|
||||
#define FUSE_VMIN_CALIBRATION 0x2DC
|
||||
#define FUSE_AGING_SENSOR_CALIBRATION 0x2E0
|
||||
#define FUSE_DEBUG_AUTHENTICATION 0x2E4
|
||||
#define FUSE_SECURE_PROVISION_INDEX 0x2E8
|
||||
#define FUSE_SECURE_PROVISION_INFO 0x2EC
|
||||
#define FUSE_OPT_GPU_DISABLE_CP1 0x2F0
|
||||
#define FUSE_SPARE_ENDIS 0x2F4
|
||||
#define FUSE_ECO_RESERVE_0 0x2F8 // AID.
|
||||
#define FUSE_RESERVED_CALIB0 0x304 // GPCPLL ADC Calibration.
|
||||
#define FUSE_RESERVED_CALIB1 0x308
|
||||
#define FUSE_OPT_GPU_TPC0_DISABLE 0x30C
|
||||
#define FUSE_OPT_GPU_TPC0_DISABLE_CP1 0x310
|
||||
#define FUSE_OPT_CPU_DISABLE 0x314
|
||||
#define FUSE_OPT_CPU_DISABLE_CP1 0x318
|
||||
#define FUSE_TSENSOR10_CALIB 0x31C
|
||||
#define FUSE_TSENSOR10_CALIB_AUX 0x320
|
||||
#define FUSE_OPT_RAM_SVOP_DP 0x324
|
||||
#define FUSE_OPT_RAM_SVOP_PDP 0x328
|
||||
#define FUSE_OPT_RAM_SVOP_REG 0x32C
|
||||
#define FUSE_OPT_RAM_SVOP_SP 0x330
|
||||
#define FUSE_OPT_RAM_SVOP_SMPDP 0x334
|
||||
#define FUSE_WOA_SKU_FLAG 0x2C0
|
||||
#define FUSE_ECO_RESERVE_1 0x2C4
|
||||
#define FUSE_GCPLEX_CONFIG_FUSE 0x2C8
|
||||
#define FUSE_GPU_VPR_AUTO_FETCH_DIS BIT(0)
|
||||
#define FUSE_GPU_VPR_ENABLED BIT(1)
|
||||
#define FUSE_GPU_WPR_ENABLED BIT(2)
|
||||
#define FUSE_PRODUCTION_MONTH 0x2CC
|
||||
#define FUSE_RAM_REPAIR_INDICATOR 0x2D0
|
||||
#define FUSE_TSENSOR9_CALIB 0x2D4 // AOTAG.
|
||||
#define FUSE_VMIN_CALIBRATION 0x2DC
|
||||
#define FUSE_AGING_SENSOR_CALIBRATION 0x2E0
|
||||
#define FUSE_DEBUG_AUTHENTICATION 0x2E4
|
||||
#define FUSE_SECURE_PROVISION_INDEX 0x2E8
|
||||
#define FUSE_SECURE_PROVISION_INFO 0x2EC
|
||||
#define FUSE_OPT_GPU_DISABLE_CP1 0x2F0
|
||||
#define FUSE_SPARE_ENDIS 0x2F4
|
||||
#define FUSE_ECO_RESERVE_0 0x2F8 // AID.
|
||||
#define FUSE_RESERVED_CALIB0 0x304 // GPCPLL ADC Calibration.
|
||||
#define FUSE_RESERVED_CALIB1 0x308
|
||||
#define FUSE_OPT_GPU_TPC0_DISABLE 0x30C
|
||||
#define FUSE_OPT_GPU_TPC0_DISABLE_CP1 0x310
|
||||
#define FUSE_OPT_CPU_DISABLE 0x314
|
||||
#define FUSE_OPT_CPU_DISABLE_CP1 0x318
|
||||
#define FUSE_TSENSOR10_CALIB 0x31C
|
||||
#define FUSE_TSENSOR10_CALIB_AUX 0x320
|
||||
#define FUSE_OPT_RAM_SVOP_DP 0x324
|
||||
#define FUSE_OPT_RAM_SVOP_PDP 0x328
|
||||
#define FUSE_OPT_RAM_SVOP_REG 0x32C
|
||||
#define FUSE_OPT_RAM_SVOP_SP 0x330
|
||||
#define FUSE_OPT_RAM_SVOP_SMPDP 0x334
|
||||
|
||||
#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4HVT_B01 0x324
|
||||
#define FUSE_OPT_RAM_RCT_TSMCDP_PO4HVT_B01 0x328
|
||||
#define FUSE_OPT_RAM_WCT_TSMCDP_PO4HVT_B01 0x32c
|
||||
#define FUSE_OPT_RAM_KP_TSMCDP_PO4HVT_B01 0x330
|
||||
#define FUSE_OPT_RAM_SVOP_SP_B01 0x334
|
||||
#define FUSE_OPT_RAM_RCT_TSMCDP_PO4HVT_B01 0x328
|
||||
#define FUSE_OPT_RAM_WCT_TSMCDP_PO4HVT_B01 0x32c
|
||||
#define FUSE_OPT_RAM_KP_TSMCDP_PO4HVT_B01 0x330
|
||||
#define FUSE_OPT_RAM_SVOP_SP_B01 0x334
|
||||
|
||||
#define FUSE_OPT_GPU_TPC0_DISABLE_CP2 0x338
|
||||
#define FUSE_OPT_GPU_TPC1_DISABLE 0x33C
|
||||
#define FUSE_OPT_GPU_TPC1_DISABLE_CP1 0x340
|
||||
#define FUSE_OPT_GPU_TPC1_DISABLE_CP2 0x344
|
||||
#define FUSE_OPT_CPU_DISABLE_CP2 0x348
|
||||
#define FUSE_OPT_GPU_DISABLE_CP2 0x34C
|
||||
#define FUSE_USB_CALIB_EXT 0x350
|
||||
#define FUSE_RESERVED_FIELD 0x354 // RMA.
|
||||
#define FUSE_SPARE_REALIGNMENT_REG 0x37C
|
||||
#define FUSE_SPARE_BIT_0 0x380
|
||||
#define FUSE_OPT_GPU_TPC0_DISABLE_CP2 0x338
|
||||
#define FUSE_OPT_GPU_TPC1_DISABLE 0x33C
|
||||
#define FUSE_OPT_GPU_TPC1_DISABLE_CP1 0x340
|
||||
#define FUSE_OPT_GPU_TPC1_DISABLE_CP2 0x344
|
||||
#define FUSE_OPT_CPU_DISABLE_CP2 0x348
|
||||
#define FUSE_OPT_GPU_DISABLE_CP2 0x34C
|
||||
#define FUSE_USB_CALIB_EXT 0x350
|
||||
#define FUSE_RESERVED_FIELD 0x354 // RMA.
|
||||
#define FUSE_SPARE_REALIGNMENT_REG 0x37C
|
||||
#define FUSE_SPARE_BIT_0 0x380
|
||||
//...
|
||||
#define FUSE_SPARE_BIT_31 0x3FC
|
||||
#define FUSE_SPARE_BIT_31 0x3FC
|
||||
|
||||
/*! Fuse commands. */
|
||||
#define FUSE_IDLE 0x0
|
||||
#define FUSE_READ 0x1
|
||||
#define FUSE_WRITE 0x2
|
||||
#define FUSE_SENSE 0x3
|
||||
#define FUSE_IDLE 0x0
|
||||
#define FUSE_READ 0x1
|
||||
#define FUSE_WRITE 0x2
|
||||
#define FUSE_SENSE 0x3
|
||||
#define FUSE_CMD_MASK 0x3
|
||||
|
||||
/*! Fuse status. */
|
||||
#define FUSE_STATUS_RESET 0
|
||||
#define FUSE_STATUS_POST_RESET 1
|
||||
#define FUSE_STATUS_LOAD_ROW0 2
|
||||
#define FUSE_STATUS_LOAD_ROW1 3
|
||||
#define FUSE_STATUS_IDLE 4
|
||||
#define FUSE_STATUS_READ_SETUP 5
|
||||
#define FUSE_STATUS_READ_STROBE 6
|
||||
#define FUSE_STATUS_SAMPLE_FUSES 7
|
||||
#define FUSE_STATUS_READ_HOLD 8
|
||||
#define FUSE_STATUS_FUSE_SRC_SETUP 9
|
||||
#define FUSE_STATUS_WRITE_SETUP 10
|
||||
#define FUSE_STATUS_WRITE_ADDR_SETUP 11
|
||||
#define FUSE_STATUS_WRITE_PROGRAM 12
|
||||
#define FUSE_STATUS_WRITE_ADDR_HOLD 13
|
||||
#define FUSE_STATUS_FUSE_SRC_HOLD 14
|
||||
#define FUSE_STATUS_LOAD_RIR 15
|
||||
#define FUSE_STATUS_RESET 0
|
||||
#define FUSE_STATUS_POST_RESET 1
|
||||
#define FUSE_STATUS_LOAD_ROW0 2
|
||||
#define FUSE_STATUS_LOAD_ROW1 3
|
||||
#define FUSE_STATUS_IDLE 4
|
||||
#define FUSE_STATUS_READ_SETUP 5
|
||||
#define FUSE_STATUS_READ_STROBE 6
|
||||
#define FUSE_STATUS_SAMPLE_FUSES 7
|
||||
#define FUSE_STATUS_READ_HOLD 8
|
||||
#define FUSE_STATUS_FUSE_SRC_SETUP 9
|
||||
#define FUSE_STATUS_WRITE_SETUP 10
|
||||
#define FUSE_STATUS_WRITE_ADDR_SETUP 11
|
||||
#define FUSE_STATUS_WRITE_PROGRAM 12
|
||||
#define FUSE_STATUS_WRITE_ADDR_HOLD 13
|
||||
#define FUSE_STATUS_FUSE_SRC_HOLD 14
|
||||
#define FUSE_STATUS_LOAD_RIR 15
|
||||
#define FUSE_STATUS_READ_BEFORE_WRITE_SETUP 16
|
||||
#define FUSE_STATUS_READ_DEASSERT_PD 17
|
||||
#define FUSE_STATUS_READ_DEASSERT_PD 17
|
||||
|
||||
/*! Fuse cache registers. */
|
||||
#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))
|
||||
|
||||
#define FUSE_ARRAY_WORDS_NUM 192
|
||||
#define FUSE_ARRAY_WORDS_NUM 192
|
||||
#define FUSE_ARRAY_WORDS_NUM_B01 256
|
||||
|
||||
enum
|
||||
{
|
||||
FUSE_NX_HW_TYPE_ICOSA,
|
||||
FUSE_NX_HW_TYPE_IOWA,
|
||||
FUSE_NX_HW_TYPE_HOAG,
|
||||
FUSE_NX_HW_TYPE_AULA
|
||||
};
|
||||
enum { FUSE_NX_HW_TYPE_ICOSA, FUSE_NX_HW_TYPE_IOWA, FUSE_NX_HW_TYPE_HOAG, FUSE_NX_HW_TYPE_AULA };
|
||||
|
||||
enum
|
||||
{
|
||||
FUSE_NX_HW_STATE_PROD,
|
||||
FUSE_NX_HW_STATE_DEV
|
||||
};
|
||||
enum { FUSE_NX_HW_STATE_PROD, FUSE_NX_HW_STATE_DEV };
|
||||
|
||||
#endif
|
||||
@@ -14,56 +14,56 @@
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#include "gm20b.hpp"
|
||||
#include "../mapping/mem_map.hpp"
|
||||
#include "gm20b.hpp"
|
||||
|
||||
|
||||
namespace gm20b {
|
||||
u64 gpu_base = 0;
|
||||
#define GPU_PA 0x57000000
|
||||
#define GPU_SIZE 0x1000000
|
||||
#define GPU_TRIM_SYS_GPCPLL_CFG 0x00
|
||||
#define GPU_TRIM_SYS_GPCPLL_COEFF 0x04
|
||||
#define GPU_TRIM_SYS_GPCPLL_CFG2 0x08
|
||||
#define GPU_TRIM_SYS_GPCPLL_CFG3 0x0C
|
||||
#define GPU_TRIM_SYS_GPCPLL_DVFS0 0x10
|
||||
#define GPU_TRIM_SYS_GPCPLL_DVFS1 0x14
|
||||
#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x1C
|
||||
#define GPU_TRIM_SYS_SEL_VCO 0x2C
|
||||
#define GPU_TRIM_SYS_GPC2CLK_OUT 0x250
|
||||
#define GPU_PA 0x57000000
|
||||
#define GPU_SIZE 0x1000000
|
||||
#define GPU_TRIM_SYS_GPCPLL_CFG 0x00
|
||||
#define GPU_TRIM_SYS_GPCPLL_COEFF 0x04
|
||||
#define GPU_TRIM_SYS_GPCPLL_CFG2 0x08
|
||||
#define GPU_TRIM_SYS_GPCPLL_CFG3 0x0C
|
||||
#define GPU_TRIM_SYS_GPCPLL_DVFS0 0x10
|
||||
#define GPU_TRIM_SYS_GPCPLL_DVFS1 0x14
|
||||
#define GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN 0x1C
|
||||
#define GPU_TRIM_SYS_SEL_VCO 0x2C
|
||||
#define GPU_TRIM_SYS_GPC2CLK_OUT 0x250
|
||||
|
||||
#define GPC_BCAST(x) (*(volatile u32 *)(gpu_base + 0x132800ul + (x)))
|
||||
#define GPU_TRIM_SYS_GPCPLL(x) (*(volatile u32 *)(gpu_base + 0x137000ul + (x)))
|
||||
#define GPC_BCAST(x) (*(volatile u32 *)(gpu_base + 0x132800ul + (x)))
|
||||
#define GPU_TRIM_SYS_GPCPLL(x) (*(volatile u32 *)(gpu_base + 0x137000ul + (x)))
|
||||
|
||||
#define GPC_BCAST_GPCPLL_DVFS2 0x20
|
||||
#define GPC_BCAST_NDIV_SLOWDOWN_DBG 0xa0
|
||||
#define GPC_BCAST_GPCPLL_DVFS2 0x20
|
||||
#define GPC_BCAST_NDIV_SLOWDOWN_DBG 0xa0
|
||||
|
||||
#define GPCPLL_CFG_ENABLE BIT(0)
|
||||
#define GPCPLL_CFG_IDDQ BIT(1)
|
||||
#define GPCPLL_CFG_SYNC_MODE BIT(2)
|
||||
#define GPCPLL_CFG_LOCK BIT(17)
|
||||
#define GPCPLL_CFG_ENABLE BIT(0)
|
||||
#define GPCPLL_CFG_IDDQ BIT(1)
|
||||
#define GPCPLL_CFG_SYNC_MODE BIT(2)
|
||||
#define GPCPLL_CFG_LOCK BIT(17)
|
||||
|
||||
#define GPCPLL_CFG2_SDM_DIN_MASK 0x000000FFu
|
||||
#define GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x007FFF00u
|
||||
#define GPCPLL_CFG2_STEPA_SHIFT 24
|
||||
#define GPCPLL_CFG2_STEPA_MASK 0xFF000000u
|
||||
#define GPCPLL_CFG2_SDM_DIN_MASK 0x000000FFu
|
||||
#define GPCPLL_CFG2_SDM_DIN_NEW_MASK 0x007FFF00u
|
||||
#define GPCPLL_CFG2_STEPA_SHIFT 24
|
||||
#define GPCPLL_CFG2_STEPA_MASK 0xFF000000u
|
||||
|
||||
#define GPCPLL_CFG3_STEPB_SHIFT 16
|
||||
#define GPCPLL_CFG3_STEPB_MASK 0x00FF0000u
|
||||
#define GPCPLL_CFG3_STEPB_SHIFT 16
|
||||
#define GPCPLL_CFG3_STEPB_MASK 0x00FF0000u
|
||||
|
||||
#define GPCPLL_DVFS0_DFS_COEFF_MASK 0x0000007Fu
|
||||
#define GPCPLL_DVFS0_DFS_COEFF_MASK 0x0000007Fu
|
||||
|
||||
#define NDIV_SLOWDOWN_SLOWDOWN_USING_PLL BIT(22)
|
||||
#define NDIV_SLOWDOWN_EN_DYNRAMP BIT(23)
|
||||
#define NDIV_SLOWDOWN_SLOWDOWN_USING_PLL BIT(22)
|
||||
#define NDIV_SLOWDOWN_EN_DYNRAMP BIT(23)
|
||||
|
||||
#define DYNRAMP_DONE_SYNCED BIT(24)
|
||||
#define DYNRAMP_DONE_SYNCED BIT(24)
|
||||
|
||||
#define GPCPLL_DVFS2_DFS_EXT_STROBE BIT(16)
|
||||
#define GPCPLL_DVFS2_DFS_EXT_STROBE BIT(16)
|
||||
|
||||
#define RAMP_TIMEOUT_US 500
|
||||
#define RAMP_TIMEOUT_US 500
|
||||
|
||||
static inline void _gpu_mask(u32 reg, u32 mask, u32 val) {
|
||||
u32 tmp = GPU_TRIM_SYS_GPCPLL(reg);
|
||||
@@ -78,12 +78,8 @@ namespace gm20b {
|
||||
}
|
||||
|
||||
static void _clk_setup_slide() {
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2,
|
||||
GPCPLL_CFG2_STEPA_MASK,
|
||||
0x04u << GPCPLL_CFG2_STEPA_SHIFT);
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG3,
|
||||
GPCPLL_CFG3_STEPB_MASK,
|
||||
0x05u << GPCPLL_CFG3_STEPB_SHIFT);
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2, GPCPLL_CFG2_STEPA_MASK, 0x04u << GPCPLL_CFG2_STEPA_SHIFT);
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG3, GPCPLL_CFG3_STEPB_MASK, 0x05u << GPCPLL_CFG3_STEPB_SHIFT);
|
||||
}
|
||||
|
||||
static bool _gpu_pllg_slide(u32 new_divn) {
|
||||
@@ -95,9 +91,7 @@ namespace gm20b {
|
||||
|
||||
_clk_setup_slide();
|
||||
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN,
|
||||
NDIV_SLOWDOWN_SLOWDOWN_USING_PLL,
|
||||
NDIV_SLOWDOWN_SLOWDOWN_USING_PLL);
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN, NDIV_SLOWDOWN_SLOWDOWN_USING_PLL, NDIV_SLOWDOWN_SLOWDOWN_USING_PLL);
|
||||
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_NEW_MASK, 0);
|
||||
|
||||
@@ -106,9 +100,7 @@ namespace gm20b {
|
||||
GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF) = coeff;
|
||||
|
||||
usleep(1);
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN,
|
||||
NDIV_SLOWDOWN_EN_DYNRAMP,
|
||||
NDIV_SLOWDOWN_EN_DYNRAMP);
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN, NDIV_SLOWDOWN_EN_DYNRAMP, NDIV_SLOWDOWN_EN_DYNRAMP);
|
||||
|
||||
int ramp_timeout = RAMP_TIMEOUT_US;
|
||||
bool success = false;
|
||||
@@ -125,9 +117,7 @@ namespace gm20b {
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_CFG2, GPCPLL_CFG2_SDM_DIN_MASK, 0);
|
||||
}
|
||||
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN,
|
||||
NDIV_SLOWDOWN_SLOWDOWN_USING_PLL | NDIV_SLOWDOWN_EN_DYNRAMP,
|
||||
0);
|
||||
_gpu_mask(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN, NDIV_SLOWDOWN_SLOWDOWN_USING_PLL | NDIV_SLOWDOWN_EN_DYNRAMP, 0);
|
||||
(void)GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_NDIV_SLOWDOWN);
|
||||
|
||||
return success;
|
||||
@@ -137,11 +127,11 @@ namespace gm20b {
|
||||
if (!gpu_base)
|
||||
QueryMemoryMapping(&gpu_base, GPU_PA, GPU_SIZE);
|
||||
|
||||
const u32 osc_khz = 38400; // PLL Hz
|
||||
const u32 osc_khz = 38400; // PLL Hz
|
||||
|
||||
u32 coeff = GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF);
|
||||
u32 divm = coeff & 0xFF;
|
||||
u32 divp = (coeff >> 16) & 0x3F;
|
||||
u32 divm = coeff & 0xFF;
|
||||
u32 divp = (coeff >> 16) & 0x3F;
|
||||
|
||||
if (divm == 0 || divp == 0)
|
||||
return false;
|
||||
@@ -149,9 +139,11 @@ namespace gm20b {
|
||||
u32 new_divn = (u64)khz * divm * divp * 2 / osc_khz;
|
||||
|
||||
// L4T clamps the registers here for some reason, do that
|
||||
if (new_divn < 8) new_divn = 8;
|
||||
if (new_divn > 255) new_divn = 255;
|
||||
if (new_divn < 8)
|
||||
new_divn = 8;
|
||||
if (new_divn > 255)
|
||||
new_divn = 255;
|
||||
|
||||
return _gpu_pllg_slide(new_divn);
|
||||
}
|
||||
}
|
||||
} // namespace gm20b
|
||||
@@ -14,7 +14,7 @@
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*
|
||||
*/
|
||||
#pragma once
|
||||
#include <../board/board.hpp>
|
||||
|
||||
@@ -14,35 +14,35 @@
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#include "pllmb.hpp"
|
||||
|
||||
namespace pllmb {
|
||||
#define GET_BITS(VAL, HIGH, LOW) ((VAL & ((1UL << (HIGH + 1UL)) - 1UL)) >> LOW)
|
||||
#define GET_BIT(VAL, BIT) GET_BITS(VAL, BIT, BIT)
|
||||
#define GET_BITS(VAL, HIGH, LOW) ((VAL & ((1UL << (HIGH + 1UL)) - 1UL)) >> LOW)
|
||||
#define GET_BIT(VAL, BIT) GET_BITS(VAL, BIT, BIT)
|
||||
|
||||
static inline volatile u32& REG(uintptr_t addr) {
|
||||
return *reinterpret_cast<volatile u32*>(addr);
|
||||
static inline volatile u32 ®(uintptr_t addr) {
|
||||
return *reinterpret_cast<volatile u32 *>(addr);
|
||||
}
|
||||
|
||||
// From jetson nano kernel
|
||||
typedef enum {
|
||||
/* divider = 2 */
|
||||
CLK_PLLX = 5,
|
||||
CLK_PLLM = 2,
|
||||
CLK_PLLX = 5,
|
||||
CLK_PLLM = 2,
|
||||
CLK_PLLMB = 37,
|
||||
/* PLLX & PLLG are backup PLLs for CPU & GPU */
|
||||
/* divider = 1 */
|
||||
CLK_CCLK_G = 18, // A57 CPU cluster
|
||||
CLK_EMC = 36,
|
||||
} PTO_ID; // PLL Test Output Register ID
|
||||
CLK_CCLK_G = 18, // A57 CPU cluster
|
||||
CLK_EMC = 36,
|
||||
} PTO_ID; // PLL Test Output Register ID
|
||||
|
||||
/* See if GM20B clock GPC PLL regs are accessible. */
|
||||
|
||||
#define PLLX_MISC0 0xE4
|
||||
#define PLLM_MISC2 0x9C
|
||||
#define PLLX_MISC0 0xE4
|
||||
#define PLLM_MISC2 0x9C
|
||||
|
||||
double ptoGetMHz(PTO_ID pto_id, u32 divider = 1, u32 presel_reg = 0, u32 presel_mask = 0) {
|
||||
u32 pre_val, val, presel_val;
|
||||
@@ -71,7 +71,7 @@ namespace pllmb {
|
||||
REG(board::clkVirtAddr + 0x60) = val | BIT(9);
|
||||
usleep(500);
|
||||
|
||||
while(REG(board::clkVirtAddr + 0x64) & BIT(31))
|
||||
while (REG(board::clkVirtAddr + 0x64) & BIT(31))
|
||||
;
|
||||
|
||||
val = REG(board::clkVirtAddr + 0x64);
|
||||
@@ -111,6 +111,6 @@ namespace pllmb {
|
||||
|
||||
u32 pllmb = ptoGetMHz(CLK_PLLMB, 2, PLLM_MISC2, BIT(9));
|
||||
u32 pllm = ptoGetMHz(CLK_PLLM, 2, PLLM_MISC2, BIT(8));
|
||||
return pllmb == 0 ? pllm : pllmb; // pllmb is zeroed out at times, fallback to pllm
|
||||
return pllmb == 0 ? pllm : pllmb; // pllmb is zeroed out at times, fallback to pllm
|
||||
}
|
||||
}
|
||||
} // namespace pllmb
|
||||
@@ -14,15 +14,17 @@
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
#include <cstdint>
|
||||
#include <switch.h>
|
||||
#include <hocclk.h>
|
||||
#include "../board/board.hpp"
|
||||
#include <registers.h>
|
||||
#include <switch.h>
|
||||
|
||||
#include "../board/board.hpp"
|
||||
|
||||
namespace pllmb {
|
||||
|
||||
u64 getRamClockRatePLLMB();
|
||||
|
||||
@@ -526,23 +526,23 @@
|
||||
#define CL_DVFS_INTR_STS_0 0x5C
|
||||
#define CL_DVFS_I2C_CLK_DIVISOR_REGISTER_0 0x16C
|
||||
|
||||
#define CLK_SOURCE_EMC 0x19c
|
||||
#define CLK_SOURCE_EMC 0x19c
|
||||
|
||||
#define PLLC_BASE 0x080
|
||||
#define PLLM_BASE 0x090
|
||||
#define PLLP_BASE 0x0a0
|
||||
#define PLLA_BASE 0x0b0
|
||||
#define PLLU_BASE 0x0c0
|
||||
#define _PLLD_BASE 0x0d0
|
||||
#define PLLX_BASE 0x0e0
|
||||
#define PLLE_BASE 0x0e8
|
||||
#define PLLC2_BASE 0x4e8
|
||||
#define PLLC3_BASE 0x4fc
|
||||
#define PLLD2_BASE 0x4b8
|
||||
#define PLLRE_BASE 0x4c4
|
||||
#define PLLC4_BASE 0x5a4
|
||||
#define PLLMB_BASE 0x5e8
|
||||
#define PLLA1_BASE 0x6a4
|
||||
#define PLLDP_BASE 0x590
|
||||
#define PLLC_BASE 0x080
|
||||
#define PLLM_BASE 0x090
|
||||
#define PLLP_BASE 0x0a0
|
||||
#define PLLA_BASE 0x0b0
|
||||
#define PLLU_BASE 0x0c0
|
||||
#define _PLLD_BASE 0x0d0
|
||||
#define PLLX_BASE 0x0e0
|
||||
#define PLLE_BASE 0x0e8
|
||||
#define PLLC2_BASE 0x4e8
|
||||
#define PLLC3_BASE 0x4fc
|
||||
#define PLLD2_BASE 0x4b8
|
||||
#define PLLRE_BASE 0x4c4
|
||||
#define PLLC4_BASE 0x5a4
|
||||
#define PLLMB_BASE 0x5e8
|
||||
#define PLLA1_BASE 0x6a4
|
||||
#define PLLDP_BASE 0x590
|
||||
|
||||
#define OSC_HZ 38400000ULL
|
||||
@@ -33,55 +33,54 @@
|
||||
|
||||
/*! PTO_CLK_CNT */
|
||||
#define PTO_REF_CLK_WIN_CFG_MASK 0xF
|
||||
#define PTO_REF_CLK_WIN_CFG_16P 0xF
|
||||
#define PTO_CNT_EN BIT(9)
|
||||
#define PTO_CNT_RST BIT(10)
|
||||
#define PTO_CLK_ENABLE BIT(13)
|
||||
#define PTO_SRC_SEL_SHIFT 14
|
||||
#define PTO_SRC_SEL_MASK 0x1FF
|
||||
#define PTO_DIV_SEL_MASK (3 << 23)
|
||||
#define PTO_DIV_SEL_GATED (0 << 23)
|
||||
#define PTO_DIV_SEL_DIV1 (1 << 23)
|
||||
#define PTO_DIV_SEL_DIV2_RISING (2 << 23)
|
||||
#define PTO_REF_CLK_WIN_CFG_16P 0xF
|
||||
#define PTO_CNT_EN BIT(9)
|
||||
#define PTO_CNT_RST BIT(10)
|
||||
#define PTO_CLK_ENABLE BIT(13)
|
||||
#define PTO_SRC_SEL_SHIFT 14
|
||||
#define PTO_SRC_SEL_MASK 0x1FF
|
||||
#define PTO_DIV_SEL_MASK (3 << 23)
|
||||
#define PTO_DIV_SEL_GATED (0 << 23)
|
||||
#define PTO_DIV_SEL_DIV1 (1 << 23)
|
||||
#define PTO_DIV_SEL_DIV2_RISING (2 << 23)
|
||||
#define PTO_DIV_SEL_DIV2_FALLING (3 << 23)
|
||||
#define PTO_DIV_SEL_CPU_EARLY (0 << 23)
|
||||
#define PTO_DIV_SEL_CPU_LATE (1 << 23)
|
||||
#define PTO_DIV_SEL_CPU_EARLY (0 << 23)
|
||||
#define PTO_DIV_SEL_CPU_LATE (1 << 23)
|
||||
|
||||
#define PTO_CLK_CNT_BUSY BIT(31)
|
||||
#define PTO_CLK_CNT 0xFFFFFF
|
||||
#define CLK_PTO_CCLK_G_DIV2 0x13
|
||||
#define CLK_PTO_EMC 0x24
|
||||
#define PTO_CLK_CNT_BUSY BIT(31)
|
||||
#define PTO_CLK_CNT 0xFFFFFF
|
||||
#define CLK_PTO_CCLK_G_DIV2 0x13
|
||||
#define CLK_PTO_EMC 0x24
|
||||
|
||||
#define CLOCK(x) (*(volatile u32 *)(g_clk_base + (x)))
|
||||
|
||||
/* Actmon Global registers */
|
||||
#define ACTMON_GLB_STATUS 0x0
|
||||
#define ACTMON_MCCPU_MON_ACT BIT(8)
|
||||
#define ACTMON_MCALL_MON_ACT BIT(9)
|
||||
#define ACTMON_CPU_FREQ_MON_ACT BIT(10)
|
||||
#define ACTMON_BPMP_MON_ACT BIT(14)
|
||||
#define ACTMON_CPU_MON_ACT BIT(15)
|
||||
#define ACTMON_GLB_STATUS 0x0
|
||||
#define ACTMON_MCCPU_MON_ACT BIT(8)
|
||||
#define ACTMON_MCALL_MON_ACT BIT(9)
|
||||
#define ACTMON_CPU_FREQ_MON_ACT BIT(10)
|
||||
#define ACTMON_BPMP_MON_ACT BIT(14)
|
||||
#define ACTMON_CPU_MON_ACT BIT(15)
|
||||
|
||||
#define ACTMON_GLB_PERIOD_CTRL 0x4
|
||||
#define ACTMON_GLB_PERIOD_USEC BIT(8)
|
||||
#define ACTMON_GLB_PERIOD_CTRL 0x4
|
||||
#define ACTMON_GLB_PERIOD_USEC BIT(8)
|
||||
#define ACTMON_GLB_PERIOD_SAMPLE(n) (((n) - 1) & 0xFF)
|
||||
|
||||
/* Actmon Device Registers */
|
||||
#define ACTMON_DEV_SIZE 0x40
|
||||
#define ACTMON_DEV_SIZE 0x40
|
||||
/* Actmon CTRL */
|
||||
#define ACTMON_DEV_CTRL_K_VAL(k) (((k) & 7) << 10)
|
||||
#define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18)
|
||||
#define ACTMON_DEV_CTRL_ENB BIT(31)
|
||||
#define ACTMON_DEV_CTRL_K_VAL(k) (((k) & 7) << 10)
|
||||
#define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18)
|
||||
#define ACTMON_DEV_CTRL_ENB BIT(31)
|
||||
|
||||
#define ACTMON_PERIOD_MS 20
|
||||
#define DEV_COUNT_WEIGHT 1024
|
||||
|
||||
#define ACTMON_BASE (g_act_base + 0x800)
|
||||
#define ACTMON_BASE (g_act_base + 0x800)
|
||||
#define ACTMON_DEV_BASE (ACTMON_BASE + 0x80)
|
||||
#define ACTMON(x) (*(volatile u32 *)(ACTMON_BASE + (x)))
|
||||
|
||||
typedef enum _actmon_dev_t
|
||||
{
|
||||
typedef enum _actmon_dev_t {
|
||||
ACTMON_DEV_CPU,
|
||||
ACTMON_DEV_BPMP,
|
||||
ACTMON_DEV_AHB,
|
||||
@@ -93,8 +92,7 @@ typedef enum _actmon_dev_t
|
||||
ACTMON_DEV_NUM,
|
||||
} actmon_dev_t;
|
||||
|
||||
typedef struct _actmon_dev_reg_t
|
||||
{
|
||||
typedef struct _actmon_dev_reg_t {
|
||||
vu32 ctrl;
|
||||
vu32 upper_wnark;
|
||||
vu32 lower_wmark;
|
||||
@@ -122,8 +120,7 @@ static u32 g_emc_bw_all = 0;
|
||||
static u32 g_emc_bw_cpu = 0;
|
||||
static u32 g_emc_bw_gpu = 0;
|
||||
|
||||
static u32 _clock_get_dev_freq(u32 id, u32 multiplier)
|
||||
{
|
||||
static u32 _clock_get_dev_freq(u32 id, u32 multiplier) {
|
||||
const u32 pto_win = 16;
|
||||
const u32 pto_osc = 32768;
|
||||
|
||||
@@ -142,7 +139,7 @@ static u32 _clock_get_dev_freq(u32 id, u32 multiplier)
|
||||
|
||||
CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL) = val | PTO_CNT_EN;
|
||||
(void)CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL);
|
||||
usleep((1000000ULL * pto_win / pto_osc) + 12 + 2); // 502 us.
|
||||
usleep((1000000ULL * pto_win / pto_osc) + 12 + 2); // 502 us.
|
||||
|
||||
while (CLOCK(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS) & PTO_CLK_CNT_BUSY)
|
||||
;
|
||||
@@ -158,97 +155,81 @@ static u32 _clock_get_dev_freq(u32 id, u32 multiplier)
|
||||
return freq_khz;
|
||||
}
|
||||
|
||||
static void _actmon_dev_enable(actmon_dev_t dev, u32 freq, u32 weight)
|
||||
{
|
||||
static void _actmon_dev_enable(actmon_dev_t dev, u32 freq, u32 weight) {
|
||||
actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
|
||||
|
||||
regs->init_avg = (u32)freq * ACTMON_PERIOD_MS / 2;
|
||||
regs->count_weight = weight;
|
||||
|
||||
regs->ctrl = ACTMON_DEV_CTRL_ENB | ACTMON_DEV_CTRL_ENB_PERIODIC | ACTMON_DEV_CTRL_K_VAL(3); // 8 samples average.
|
||||
regs->ctrl = ACTMON_DEV_CTRL_ENB | ACTMON_DEV_CTRL_ENB_PERIODIC | ACTMON_DEV_CTRL_K_VAL(3); // 8 samples average.
|
||||
}
|
||||
|
||||
static u32 _actmon_dev_get_count_avg(actmon_dev_t dev)
|
||||
{
|
||||
static u32 _actmon_dev_get_count_avg(actmon_dev_t dev) {
|
||||
actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE));
|
||||
|
||||
return regs->avg_count;
|
||||
}
|
||||
|
||||
static inline Result _svcQueryMemoryMappingFallback(u64* virtaddr, u64 physaddr, u64 size)
|
||||
{
|
||||
if(hosversionAtLeast(10,0,0))
|
||||
{
|
||||
static inline Result _svcQueryMemoryMappingFallback(u64 *virtaddr, u64 physaddr, u64 size) {
|
||||
if (hosversionAtLeast(10, 0, 0)) {
|
||||
u64 out_size;
|
||||
return svcQueryMemoryMapping(virtaddr, &out_size, physaddr, size);
|
||||
}
|
||||
else
|
||||
{
|
||||
} else {
|
||||
return svcLegacyQueryIoMapping(virtaddr, physaddr, size);
|
||||
}
|
||||
}
|
||||
|
||||
static void _clock_update_freqs(void)
|
||||
{
|
||||
static void _clock_update_freqs(void) {
|
||||
u64 ticks = armGetSystemTick();
|
||||
if(armTicksToNs(ticks - g_update_ticks) <= WAIT_NS)
|
||||
{
|
||||
if (armTicksToNs(ticks - g_update_ticks) <= WAIT_NS) {
|
||||
return;
|
||||
}
|
||||
|
||||
g_update_ticks = ticks;
|
||||
|
||||
if (!g_clk_base)
|
||||
{
|
||||
if (!g_clk_base) {
|
||||
_svcQueryMemoryMappingFallback(&g_clk_base, 0x60006000ul, 0x1000);
|
||||
}
|
||||
|
||||
if(!g_clk_base)
|
||||
{
|
||||
if (!g_clk_base) {
|
||||
return;
|
||||
}
|
||||
|
||||
g_mem_freq = _clock_get_dev_freq(CLK_PTO_EMC, 1);
|
||||
g_cpu_freq = _clock_get_dev_freq(CLK_PTO_CCLK_G_DIV2, 2);
|
||||
|
||||
if (!g_gpu_base)
|
||||
{
|
||||
if (!g_gpu_base) {
|
||||
_svcQueryMemoryMappingFallback(&g_gpu_base, 0x57000000ul, 0x1000000);
|
||||
}
|
||||
|
||||
if (!g_gpu_base)
|
||||
{
|
||||
if (!g_gpu_base) {
|
||||
return;
|
||||
}
|
||||
|
||||
bool gpu_enabled = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) & BIT(24)) && !(CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_X) & BIT(24));
|
||||
if(!gpu_enabled)
|
||||
{
|
||||
if (!gpu_enabled) {
|
||||
return;
|
||||
}
|
||||
|
||||
if (!g_act_base)
|
||||
{
|
||||
if (!g_act_base) {
|
||||
_svcQueryMemoryMappingFallback(&g_act_base, 0x6000C000ul, 0x1000);
|
||||
}
|
||||
|
||||
if(!g_act_base)
|
||||
{
|
||||
if (!g_act_base) {
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
const u32 osc = 38400000;
|
||||
u32 coeff = GPU_TRIM_SYS_GPCPLL(GPU_TRIM_SYS_GPCPLL_COEFF);
|
||||
u32 divm = coeff & 0xFF;
|
||||
u32 divn = (coeff >> 8) & 0xFF;
|
||||
u32 divn = (coeff >> 8) & 0xFF;
|
||||
u32 divp = (coeff >> 16) & 0x3F;
|
||||
g_gpu_freq = osc * divn / (divm * divp) / 2;
|
||||
|
||||
u32 emc_freq = g_mem_freq / 1000;
|
||||
|
||||
// Check if actmon is disabled
|
||||
if (!(ACTMON(ACTMON_GLB_STATUS) & ACTMON_MCALL_MON_ACT))
|
||||
{
|
||||
if (!(ACTMON(ACTMON_GLB_STATUS) & ACTMON_MCALL_MON_ACT)) {
|
||||
ACTMON(ACTMON_GLB_PERIOD_CTRL) = ACTMON_GLB_PERIOD_SAMPLE(ACTMON_PERIOD_MS);
|
||||
_actmon_dev_enable(ACTMON_DEV_MC_ALL, emc_freq, 256 * 4);
|
||||
}
|
||||
@@ -270,57 +251,47 @@ static void _clock_update_freqs(void)
|
||||
g_emc_bw_gpu = g_emc_bw_all - g_emc_bw_cpu;
|
||||
}
|
||||
|
||||
|
||||
u32 t210ClkCpuFreq(void)
|
||||
{
|
||||
u32 t210ClkCpuFreq(void) {
|
||||
_clock_update_freqs();
|
||||
return g_cpu_freq;
|
||||
}
|
||||
|
||||
u32 t210ClkMemFreq(void)
|
||||
{
|
||||
u32 t210ClkMemFreq(void) {
|
||||
_clock_update_freqs();
|
||||
return g_mem_freq;
|
||||
}
|
||||
|
||||
u32 t210ClkGpuFreq(void)
|
||||
{
|
||||
u32 t210ClkGpuFreq(void) {
|
||||
_clock_update_freqs();
|
||||
return g_gpu_freq;
|
||||
}
|
||||
|
||||
u32 t210EmcLoadAll()
|
||||
{
|
||||
u32 t210EmcLoadAll() {
|
||||
_clock_update_freqs();
|
||||
return g_emc_lall;
|
||||
}
|
||||
|
||||
u32 t210EmcLoadCpu()
|
||||
{
|
||||
u32 t210EmcLoadCpu() {
|
||||
_clock_update_freqs();
|
||||
return g_emc_lcpu;
|
||||
}
|
||||
|
||||
u32 t210EmcBwAll()
|
||||
{
|
||||
u32 t210EmcBwAll() {
|
||||
_clock_update_freqs();
|
||||
return g_emc_bw_all;
|
||||
}
|
||||
|
||||
u32 t210EmcBwCpu()
|
||||
{
|
||||
u32 t210EmcBwCpu() {
|
||||
_clock_update_freqs();
|
||||
return g_emc_bw_cpu;
|
||||
}
|
||||
|
||||
u32 t210EmcBwGpu()
|
||||
{
|
||||
u32 t210EmcBwGpu() {
|
||||
_clock_update_freqs();
|
||||
return g_emc_bw_gpu;
|
||||
}
|
||||
|
||||
u32 t210EmcBwPeak()
|
||||
{
|
||||
u32 t210EmcBwPeak() {
|
||||
_clock_update_freqs();
|
||||
return ((u64)g_mem_freq * 16) / 1000000;
|
||||
}
|
||||
@@ -12,9 +12,9 @@
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/* --------------------------------------------------------------------------
|
||||
* "THE BEER-WARE LICENSE" (Revision 42):
|
||||
* <p-sam@d3vs.net>, <natinusala@gmail.com>, <m4x@m4xw.net>
|
||||
@@ -24,12 +24,10 @@
|
||||
* --------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <switch.h>
|
||||
|
||||
Reference in new issue
Block a user