DRAM MR4 tsensor reading

Source/hoc-clk/sysmodule/src/soc/dram_mrr.cpp

@@ -251,6 +251,21 @@ namespace soc::mrr {
         return data;
     }
 
+    bool ReadRamMr4(u8 *mr4) {
+        EmcTopology topo = {};
+        if (!QueryTopology(&topo))
+            return false;
+
+        ClearMrrLeftovers();
+
+        emc_mr_data_t data = {};
+        if (!ReadMrxRank(MR4_TEMP, topo.ranks > 1, topo.channels > 1, &data))
+            return false;
+
+        *mr4 = data.chip0.rank0_ch0;
+        return true;
+    }
+
     /* MR8 density field (bits 5:2) to MB */
     static bool DecodeDensityMb(u8 mr8, u32 *mb) {
         switch ((mr8 & 0x3C) >> 2)

Source/hoc-clk/sysmodule/src/soc/dram_mrr.hpp

@@ -99,9 +99,7 @@ namespace soc::mrr {
     emc_mr_data_t sdram_read_mrx(emc_mr_t mrx);
     bool IsMrrAvailable();
 
-    /* Fuse-style DRAM ID (hekate numbering, as in board::GetDramID):
-       derived from MRR when the patched exosphere grants EMC access,
-       otherwise falls back to the fuse ODM4 ID. MRR-detected 8GB WT:B/NEE
-       (no dedicated fuse numbering) alias to Aula AA-MGCL 8GB (28). */
+    bool ReadRamMr4(u8 *mr4);
+
     u8 IdentifyDramId();
 }