OmniNX/Horizon-OC-pro
2
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Refactor tsensor

Browse Source
This commit is contained in:
Lightos1
2026-05-05 20:43:43 +02:00
parent 9cf901d487
commit 2e39421074
14 changed files with 488 additions and 584 deletions
Download Patch File Download Diff File Expand all files Collapse all files

241
Source/hoc-clk/sysmodule/src/tsensor/aotag.cpp Normal file
View File

@@ -0,0 +1,241 @@
/*
* drivers/thermal/tegra_aotag.c
*
* TEGRA AOTAG (Always-On Thermal Alert Generator) driver.
*
* Copyright (c) 2014 - 2017, NVIDIA CORPORATION. All rights reserved.
*
* Copyright (c) 1994, Linus Torvalds
*
* Copyright (c) 2026, Souldbminer
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <notification.h>
#include "../mem_map.hpp"
#include "../file_utils.hpp"
#include "tsensor_common.hpp"
#include "aotag.hpp"
namespace tsensor {
#define PMC_BASE 0x7000E400
#define TEGRA_FUSE_CP_REV_0_3 (3)
#define FUSE_CP_REV 0x190
namespace {
u64 fuseVa = 0;
bool wasInit = false;
}
#define REG_SET(r, mask, value) \
((r & ~(mask##_MASK)) | ((value<<(mask##_POS_START)) & mask##_MASK))
#define REG_GET(r, mask) \
((r & mask##_MASK) >> mask##_POS_START)
#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
static const TSensorFuse tegra_aotag_fuse = {
.fuse_base_cp_mask = 0x3ff << 11,
.fuse_base_cp_shift = 11,
.fuse_base_ft_mask = (u32)0x7ff << 21,
.fuse_base_ft_shift = 21,
.fuse_shift_ft_mask = 0x1f << 6,
.fuse_shift_ft_shift = 6,
.fuse_spare_realignment = 0,
};
static TSensorConfig tegra_aotag_config = {
.tall = 76,
.tiddq_en = 1,
.ten_count = 16,
.pdiv = 8,
.pdiv_ate = 8,
.tsample = 9,
.tsample_ate = 39,
};
static TSensorConfig tegra210b01_aotag_config = {
.tall = 76,
.tiddq_en = 1,
.ten_count = 16,
.pdiv = 12,
.pdiv_ate = 6,
.tsample = 19,
.tsample_ate = 39,
};
static const FuseCorrCoeff tegra_aotag_coeff = {
.alpha = 1063200,
.beta = -6749000,
};
static const FuseCorrCoeff tegra210b01_aotag_coeff = {
.alpha = 991100,
.beta = 1096200,
};
struct aotag_sensor_info_t {
struct TSensorConfig *config;
const struct TSensorFuse *fuse;
const struct FuseCorrCoeff *coeff;
s32 therm_a;
s32 therm_b;
};
struct aotag_platform_data {
struct TSensorConfig *config;
const struct FuseCorrCoeff *coeff;
};
static aotag_platform_data tegra210_plat_data = {
.config = &tegra_aotag_config,
.coeff = &tegra_aotag_coeff,
};
static aotag_platform_data tegra210b01_plat_data = {
.config = &tegra210b01_aotag_config,
.coeff = &tegra210b01_aotag_coeff,
};
aotag_sensor_info_t aotag_sensor_info = {
.config = NULL,
.fuse = NULL,
.coeff = NULL,
.therm_a = 0,
.therm_b = 0,
};
aotag_sensor_info_t *info = &aotag_sensor_info;
aotag_platform_data *pdata = NULL;
u32 ReadPmcReg(unsigned long offset) {
SecmonArgs args = {};
args.X[0] = 0xF0000002;
args.X[1] = PMC_BASE + offset;
svcCallSecureMonitor(&args);
if (args.X[1] == (PMC_BASE + offset)) { // if param 1 is identical read failed
return 0;
}
return args.X[1];
}
void WritePmcReg(u32 value, unsigned long offset) {
SecmonArgs args = {};
args.X[0] = 0xF0000002;
args.X[1] = PMC_BASE + offset;
args.X[2] = 0xFFFFFFFF;
args.X[3] = (value);
svcCallSecureMonitor(&args);
}
static inline void SetBit(unsigned long nr, volatile void *addr) {
int *m = ((int *) addr) + (nr >> 5);
*m |= 1 << (nr & 31);
}
static inline void ClearBit(unsigned long nr, volatile void *addr) {
int *m = ((int *) addr) + (nr >> 5);
*m &= ~(1 << (nr & 31));
}
void InitializeAotag(bool isMariko) {
constexpr u64 FusePa = 0x7000F000;
R_UNLESS(MapAddress(fuseVa, FusePa, "fuse"));
if (isMariko) {
// u32 major, minor, rev;
pdata = &tegra210b01_plat_data;
info->config = &tegra210b01_aotag_config;
// tegra_fuse_readl(FUSE_CP_REV, &rev);
// minor = rev & 0x1f;
// major = (rev >> 5) & 0x3f;
// if (major == 0 && minor < TEGRA_FUSE_CP_REV_0_3) {
// info->config->tsample_ate -= 1;
// }
} else {
info->config = &tegra_aotag_config;
pdata = &tegra210_plat_data;
}
info->fuse = &tegra_aotag_fuse;
info->coeff = pdata->coeff;
aotag_sensor_info_t *ps_info = &aotag_sensor_info;
TSensorSharedCalib shared_fuses;
u32 therm_ab;
CalcSharedCal(ps_info->fuse, &shared_fuses, fuseVa);
CalcTSensorCalib(ps_info->config, &shared_fuses, ps_info->coeff, &therm_ab, AOTAG_FUSE_ADDR, fuseVa);
ps_info->therm_a = REG_GET(therm_ab, CONFIG2_THERM_A);
ps_info->therm_b = REG_GET(therm_ab, CONFIG2_THERM_B);
WritePmcReg(therm_ab, PMC_TSENSOR_CONFIG2);
aotag_sensor_info_t *i = info;
unsigned long r = 0;
r = REG_SET(r, CONFIG0_TALL, i->config->tall);
WritePmcReg(r, PMC_TSENSOR_CONFIG0);
r = 0;
r = REG_SET(r, CONFIG1_TEN_COUNT, i->config->ten_count);
r = REG_SET(r, CONFIG1_TIDDQ_EN, i->config->tiddq_en);
r = REG_SET(r, CONFIG1_TSAMPLE, (i->config->tsample - 1));
SetBit(CONFIG1_TEMP_ENABLE_POS, &r);
WritePmcReg(r, PMC_TSENSOR_CONFIG1);
r = 0;
r = REG_SET(r, TSENSOR_PDIV, i->config->pdiv);
WritePmcReg(r, PMC_TSENSOR_PDIV0);
r = ReadPmcReg(PMC_AOTAG_CFG);
SetBit(CFG_TAG_EN_POS, &r);
ClearBit(CFG_DISABLE_CLK_POS, &r);
WritePmcReg(r, PMC_AOTAG_CFG);
fileUtils::LogLine("[aotag] Init complete!");
wasInit = true;
}
s32 ReadAotag() {
if (!wasInit) {
return -125;
}
u32 regval = 0, abs = 0, fraction = 0, valid = 0, sign = 0;
s32 temp = 0;
regval = ReadPmcReg(PMC_TSENSOR_STATUS1);
valid = REG_GET(regval, STATUS1_TEMP_VALID);
if (!valid) {
return -125;
}
abs = REG_GET(regval, STATUS1_TEMP_ABS);
fraction = REG_GET(regval, STATUS1_TEMP_FRAC);
sign = REG_GET(regval, STATUS1_TEMP_SIGN);
temp = (abs * 1000) + (fraction * 500);
if (sign) {
temp = (-1) * (temp);
}
return temp;
}
bool IsInitialized() {
return wasInit;
}
}

156
Source/hoc-clk/sysmodule/src/tsensor/aotag.hpp Normal file
View File

@@ -0,0 +1,156 @@
/*
*
* TEGRA AOTAG (Always-On Thermal Alert Generator) driver.
*
* Copyright (c) 2014 - 2017, NVIDIA CORPORATION. All rights reserved.
*
* Copyright (c) 2026, Souldbminer
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#pragma once
namespace tsensor {
#define MASK(start, end) \
(((0xFFFFFFFF)<<start) & (u32)(((u64)1<<(end+1))-1))
#define MAX_THRESHOLD_TEMP (127000)
#define MIN_THRESHOLD_TEMP (-127000)
/*
* Register definitions
*/
#define TSENSOR_COMMON_FUSE_ADDR (0x280)
// NVIDIA driver uses 1D4 here but its incorrect.
// I guess that's what happens when you vibecode your AOTAG driver (jk)
#define AOTAG_FUSE_ADDR (0x2D4)
#define PMC_R_OBS_AOTAG (0x017)
#define PMC_R_OBS_AOTAG_CAPTURE (0x017)
#define PMC_RST_STATUS (0x1B4)
#define PMC_DIRECT_THERMTRIP_CFG (0x474)
#define PMC_AOTAG_CFG (0x484)
#define CFG_DISABLE_CLK_POS (0)
#define CFG_SW_TRIGGER_POS (2)
#define CFG_USE_EXT_TRIGGER_POS (3)
#define CFG_ENABLE_SW_DEBUG_POS (4)
#define CFG_TAG_EN_POS (5)
#define CFG_THERMTRIP_EN_POS (6)
#define PMC_AOTAG_THRESH1_CFG (0x488)
#define PMC_AOTAG_THRESH2_CFG (0x48C)
#define PMC_AOTAG_THRESH3_CFG (0x490)
#define THRESH3_CFG_POS_START (0)
#define THRESH3_CFG_POS_END (14)
#define THRESH3_CFG_MASK (MASK(THRESH3_CFG_POS_START,\
THRESH3_CFG_POS_END))
#define PMC_AOTAG_STATUS (0x494)
#define PMC_AOTAG_SECURITY (0x498)
#define PMC_TSENSOR_CONFIG0 (0x49C)
#define CONFIG0_STOP_POS (0)
#define CONFIG0_RO_SEL_POS (1)
#define CONFIG0_STATUS_CLR_POS (5)
#define CONFIG0_TALL_POS_START (8)
#define CONFIG0_TALL_POS_END (27)
#define CONFIG0_TALL_SIZE (CONFIG0_TALL_POS_END - \
CONFIG0_TALL_POS + 1)
#define CONFIG0_TALL_MASK (MASK(CONFIG0_TALL_POS_START, \
CONFIG0_TALL_POS_END))
#define PMC_TSENSOR_CONFIG1 (0x4A0)
#define CONFIG1_TEMP_ENABLE_POS (31)
#define CONFIG1_TEN_COUNT_POS_START (24)
#define CONFIG1_TEN_COUNT_POS_END (29)
#define CONFIG1_TEN_COUNT_MASK (MASK(CONFIG1_TEN_COUNT_POS_START, \
CONFIG1_TEN_COUNT_POS_END))
#define CONFIG1_TIDDQ_EN_POS_START (15)
#define CONFIG1_TIDDQ_EN_POS_END (20)
#define CONFIG1_TIDDQ_EN_MASK (MASK(CONFIG1_TIDDQ_EN_POS_START, \
CONFIG1_TIDDQ_EN_POS_END))
#define CONFIG1_TSAMPLE_POS_START (0)
#define CONFIG1_TSAMPLE_POS_END (9)
#define CONFIG1_TSAMPLE_MASK (MASK(CONFIG1_TSAMPLE_POS_START, \
CONFIG1_TSAMPLE_POS_END))
#define PMC_TSENSOR_CONFIG2 (0x4A4)
#define CONFIG2_THERM_A_POS_START (16)
#define CONFIG2_THERM_A_POS_END (31)
#define CONFIG2_THERM_A_MASK (MASK(CONFIG2_THERM_A_POS_START, \
CONFIG2_THERM_A_POS_END))
#define CONFIG2_THERM_B_POS_START (0)
#define CONFIG2_THERM_B_POS_END (15)
#define CONFIG2_THERM_B_MASK (MASK(CONFIG2_THERM_B_POS_START, \
CONFIG2_THERM_B_POS_END))
#define PMC_TSENSOR_STATUS0 (0x4A8)
#define STATUS0_CAPTURE_VALID_POS (31)
#define STATUS0_CAPTURE_POS_START (0)
#define STATUS0_CAPTURE_POS_END (15)
#define STATUS0_CAPTURE_MASK (MASK(STATUS0_CAPTURE_POS_START, \
STATUS0_CAPTURE_POS_END))
#define PMC_TSENSOR_STATUS1 (0x4AC)
#define STATUS1_TEMP_POS (31)
#define STATUS1_TEMP_POS_START (0)
#define STATUS1_TEMP_POS_END (15)
#define STATUS1_TEMP_MASK (MASK(STATUS1_TEMP_POS_START, \
STATUS1_TEMP_POS_END))
#define STATUS1_TEMP_VALID_POS_START (31)
#define STATUS1_TEMP_VALID_POS_END (31)
#define STATUS1_TEMP_VALID_MASK (MASK(STATUS1_TEMP_VALID_POS_START, \
STATUS1_TEMP_VALID_POS_END))
#define STATUS1_TEMP_ABS_POS_START (8)
#define STATUS1_TEMP_ABS_POS_END (15)
#define STATUS1_TEMP_ABS_MASK (MASK(STATUS1_TEMP_ABS_POS_START, \
STATUS1_TEMP_ABS_POS_END))
#define STATUS1_TEMP_FRAC_POS_START (7)
#define STATUS1_TEMP_FRAC_POS_END (7)
#define STATUS1_TEMP_FRAC_MASK (MASK(STATUS1_TEMP_FRAC_POS_START, \
STATUS1_TEMP_FRAC_POS_END))
#define STATUS1_TEMP_SIGN_POS_START (0)
#define STATUS1_TEMP_SIGN_POS_END (0)
#define STATUS1_TEMP_SIGN_MASK (MASK(STATUS1_TEMP_SIGN_POS_START, \
STATUS1_TEMP_SIGN_POS_END))
#define PMC_TSENSOR_STATUS2 (0x4B0)
#define PMC_TSENSOR_PDIV0 (0x4B4)
#define TSENSOR_PDIV_POS_START (12)
#define TSENSOR_PDIV_POS_END (15)
#define TSENSOR_PDIV_MASK (MASK(TSENSOR_PDIV_POS_START, \
TSENSOR_PDIV_POS_END))
#define PMC_AOTAG_INTR_EN (0x4B8)
#define PMC_AOTAG_INTR_DIS (0x4BC)
#define AOTAG_FUSE_CALIB_CP_POS_START (0)
#define AOTAG_FUSE_CALIB_CP_POS_END (12)
#define AOTAG_FUSE_CALIB_CP_MASK (MASK(AOTAG_FUSE_CALIB_CP_POS_START, \
AOTAG_FUSE_CALIB_CP_POS_END))
#define AOTAG_FUSE_CALIB_FT_POS_START (13)
#define AOTAG_FUSE_CALIB_FT_POS_END (25)
#define AOTAG_FUSE_CALIB_FT_MASK (MASK(AOTAG_FUSE_CALIB_FT_POS_START, \
AOTAG_FUSE_CALIB_FT_POS_END))
void InitializeAotag(bool isMariko);
s32 ReadAotag();
bool IsInitialized();
}

526
Source/hoc-clk/sysmodule/src/tsensor/soctherm.cpp Normal file
View File

@@ -0,0 +1,526 @@
/*
* Copyright (c) 2014 - 2019, NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Mikko Perttunen <mperttunen@nvidia.com>
*
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include <switch.h>
#include <hocclk.h>
#include "../board/board.hpp"
#include "../file_utils.hpp"
#include "../mem_map.hpp"
#include "soctherm.hpp"
#include "tsensor_common.hpp"
namespace tsensor {
namespace {
#define CAR_CLK_SOURCE_TSENSOR 0x3B8
#define CAR_CLK_OUT_ENB_V 0x360
#define CLK_RST_CONTROLLER_RST_DEVICES 0xC
#define SWR_SOC_THERM_RST 1 << 14
#define CLK_RST_CONTROLLER_CLK_OUT_ENB 0x18
#define CLK_ENB_SOC_THERM 1 << 14
#define CAR_CLK_SOURCE_TSENSOR_VAL 0x8000005E
#define THERMCTL_LEVEL0_GROUP_CPU 0x0
#define THERMCTL_LEVEL0_GROUP_GPU 0x4
#define THERMCTL_LEVEL0_GROUP_MEM 0x8
#define THERMCTL_LEVEL0_GROUP_TSENSE 0xc
#define TEGRA124_SOCTHERM_SENSOR_CPU 0
#define TEGRA124_SOCTHERM_SENSOR_MEM 1
#define TEGRA124_SOCTHERM_SENSOR_GPU 2
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
#define TEGRA124_SOCTHERM_SENSOR_NUM 4
#define TEGRA_SOCTHERM_THROT_LEVEL_NONE 0
#define TEGRA_SOCTHERM_THROT_LEVEL_LOW 1
#define TEGRA_SOCTHERM_THROT_LEVEL_MED 2
#define TEGRA_SOCTHERM_THROT_LEVEL_HIGH 3
#define SENSOR_CONFIG2 8
#define SENSOR_CONFIG2_THERMA_MASK (0xffffu << 16)
#define SENSOR_CONFIG2_THERMB_MASK 0xffff
#define THERMCTL_THERMTRIP_CTL 0x80
#define SENSOR_PDIV 0x1c0
#define SENSOR_PDIV_CPU_MASK (0xf << 12)
#define SENSOR_PDIV_GPU_MASK (0xf << 8)
#define SENSOR_PDIV_MEM_MASK (0xf << 4)
#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
#define SENSOR_HOTSPOT_OFF 0x1c4
#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
#define SENSOR_HW_PLLX_OFFSET_EN 0x1e4
#define SENSOR_HW_PLLX_OFFSET_MEM_EN_MASK BIT(2)
#define SENSOR_HW_PLLX_OFFSET_CPU_EN_MASK BIT(1)
#define SENSOR_HW_PLLX_OFFSET_GPU_EN_MASK BIT(0)
#define SENSOR_HW_PLLX_OFFSET_MIN 0x1e8
#define SENSOR_HW_PLLX_OFFSET_MAX 0x1ec
#define SENSOR_HW_PLLX_OFFSET_MEM_MASK (0xff << 16)
#define SENSOR_HW_PLLX_OFFSET_GPU_MASK (0xff << 8)
#define SENSOR_HW_PLLX_OFFSET_CPU_MASK (0xff << 0)
#define SENSOR_TEMP1 0x1c8
#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffffu << 16)
#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
#define SENSOR_TEMP2 0x1cc
#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffffu << 16)
#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
#define SENSOR_VALID 0x1e0
#define SENSOR_GPU_VALID_MASK BIT(9)
#define SENSOR_CPU_VALID_MASK 0xf
#define SENSOR_MEM_VALID_MASK (0x3 << 10)
#define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1u << 31)
#define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30)
#define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29)
#define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28)
#define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27)
#define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18)
#define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9)
#define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff
#define TEGRA210_THERM_IRQ_MEM_MASK (0x3 << 24)
#define TEGRA210_THERM_IRQ_GPU_MASK (0x3 << 16)
#define TEGRA210_THERM_IRQ_CPU_MASK (0x3 << 8)
#define TEGRA210_THERM_IRQ_TSENSE_MASK (0x3 << 0)
#define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18)
#define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9)
#define TEGRA210_THRESH_GRAIN 500
#define TEGRA210_BPTT 9
#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
#define SENSOR_CONFIG0 0
#define SENSOR_CONFIG0_STOP BIT(0)
#define SENSOR_CONFIG0_CPTR_OVER BIT(2)
#define SENSOR_CONFIG0_OVER BIT(3)
#define SENSOR_CONFIG0_TCALC_OVER BIT(4)
#define SENSOR_CONFIG0_TALL_MASK (0xfffff << 8)
#define SENSOR_CONFIG0_TALL_SHIFT 8
#define PDIV_RATE_T210B0 0xCC0C
#define PDIV_RATE_T210 0x8888
#define HOTSPOT_VAL 0xA0500
#define SENSOR_CONFIG1 4
#define SENSOR_CONFIG1_TSAMPLE_MASK 0x3ff
#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
#define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3f << 15)
#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
#define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3f << 24)
#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
#define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
#define READBACK_VALUE_MASK 0xff00
#define READBACK_VALUE_SHIFT 8
#define READBACK_ADD_HALF BIT(7)
#define READBACK_NEGATE BIT(0)
#define PDIV_MASK_T210B0 0xFFFF00F0
#define HOTSPOT_MASK_T210B0 0xFF0000FF
#define PDIV_MASK_T210 0xFFFF0000
#define HOTSPOT_MASK_T210 0xFF000000
#define TSENSOR_TSENSOR_CLKEN 0x1DC
#define TSENSOR_TSENSOR_ENABLE 225
const TSensorFuse tfuse = {
.fuse_base_cp_mask = 0x3ff << 11,
.fuse_base_cp_shift = 11,
.fuse_base_ft_mask = 0x7ffu << 21,
.fuse_base_ft_shift = 21,
.fuse_shift_ft_mask = 0x1f << 6,
.fuse_shift_ft_shift = 6,
.fuse_spare_realignment = 0,
};
const TSensorConfig eristaConf = {
.tall = 16300,
.tiddq_en = 1,
.ten_count = 1,
.pdiv = 8,
.pdiv_ate = 8,
.tsample = 120,
.tsample_ate = 480,
};
const TSensorConfig marikoConf = {
.tall = 16300,
.tiddq_en = 1,
.ten_count = 1,
.pdiv = 12,
.pdiv_ate = 6,
.tsample = 240,
.tsample_ate = 480,
};
const struct TSensorGroup tSensorGroupCpu = {
.name = "cpu",
.id = TEGRA124_SOCTHERM_SENSOR_CPU,
.sensor_temp_offset = SENSOR_TEMP1,
.sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
.pdiv_mask = SENSOR_PDIV_CPU_MASK,
.pllx_hotspot_diff = 10,
.pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
.hw_pllx_offset_mask = SENSOR_HW_PLLX_OFFSET_CPU_MASK,
.hw_pllx_offset_en_mask = SENSOR_HW_PLLX_OFFSET_CPU_EN_MASK,
.thermtrip_enable_mask = TEGRA210_THERMTRIP_CPU_EN_MASK,
.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
.thermtrip_threshold_mask = TEGRA210_THERMTRIP_CPU_THRESH_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU,
.thermctl_isr_mask = TEGRA210_THERM_IRQ_CPU_MASK,
.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
};
const struct TSensorGroup tSensorGroupGpu = {
.name = "gpu",
.id = TEGRA124_SOCTHERM_SENSOR_GPU,
.sensor_temp_offset = SENSOR_TEMP1,
.sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
.pdiv_mask = SENSOR_PDIV_GPU_MASK,
.pllx_hotspot_diff = 5,
.pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
.hw_pllx_offset_mask = SENSOR_HW_PLLX_OFFSET_GPU_MASK,
.hw_pllx_offset_en_mask = SENSOR_HW_PLLX_OFFSET_GPU_EN_MASK,
.thermtrip_enable_mask = TEGRA210_THERMTRIP_GPU_EN_MASK,
.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
.thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU,
.thermctl_isr_mask = TEGRA210_THERM_IRQ_GPU_MASK,
.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
};
const struct TSensorGroup tSensorGroupPll = {
.name = "pll",
.id = TEGRA124_SOCTHERM_SENSOR_PLLX,
.sensor_temp_offset = SENSOR_TEMP2,
.sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
.pdiv_mask = SENSOR_PDIV_PLLX_MASK,
.thermtrip_enable_mask = TEGRA210_THERMTRIP_TSENSE_EN_MASK,
.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
.thermtrip_threshold_mask = TEGRA210_THERMTRIP_TSENSE_THRESH_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE,
.thermctl_isr_mask = TEGRA210_THERM_IRQ_TSENSE_MASK,
.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
};
const struct TSensorGroup eristaTSensorGroupMem = {
.name = "mem",
.id = TEGRA124_SOCTHERM_SENSOR_MEM,
.sensor_temp_offset = SENSOR_TEMP2,
.sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
.pdiv_mask = SENSOR_PDIV_MEM_MASK,
.pllx_hotspot_diff = 0,
.pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
.hw_pllx_offset_mask = SENSOR_HW_PLLX_OFFSET_MEM_MASK,
.hw_pllx_offset_en_mask = SENSOR_HW_PLLX_OFFSET_MEM_EN_MASK,
.thermtrip_enable_mask = TEGRA210_THERMTRIP_MEM_EN_MASK,
.thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK,
.thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK,
.thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM,
.thermctl_isr_mask = TEGRA210_THERM_IRQ_MEM_MASK,
.thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK,
.thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK,
};
const TSensor eristaTSensors[] = {
{
.name = "cpu0",
.base = 0xc0,
.config = &eristaConf,
.calib_fuse_offset = 0x198,
.fuse_corr = {
.alpha = 1085000,
.beta = 3244200,
},
.group = &tSensorGroupCpu,
}, {
.name = "cpu1",
.base = 0xe0,
.config = &eristaConf,
.calib_fuse_offset = 0x184,
.fuse_corr = {
.alpha = 1126200,
.beta = -67500,
},
.group = &tSensorGroupCpu,
}, {
.name = "cpu2",
.base = 0x100,
.config = &eristaConf,
.calib_fuse_offset = 0x188,
.fuse_corr = {
.alpha = 1098400,
.beta = 2251100,
},
.group = &tSensorGroupCpu,
}, {
.name = "cpu3",
.base = 0x120,
.config = &eristaConf,
.calib_fuse_offset = 0x22c,
.fuse_corr = {
.alpha = 1108000,
.beta = 602700,
},
.group = &tSensorGroupCpu,
}, {
.name = "gpu",
.base = 0x180,
.config = &eristaConf,
.calib_fuse_offset = 0x254,
.fuse_corr = {
.alpha = 1074300,
.beta = 2734900,
},
.group = &tSensorGroupGpu,
}, {
.name = "pllx",
.base = 0x1a0,
.config = &eristaConf,
.calib_fuse_offset = 0x260,
.fuse_corr = {
.alpha = 1039700,
.beta = 6829100,
},
.group = &tSensorGroupPll,
}, {
.name = "mem0",
.base = 0x140,
.config = &eristaConf,
.calib_fuse_offset = 0x258,
.fuse_corr = {
.alpha = 1069200,
.beta = 3549900,
},
.group = &eristaTSensorGroupMem,
}, {
.name = "mem1",
.base = 0x160,
.config = &eristaConf,
.calib_fuse_offset = 0x25c,
.fuse_corr = {
.alpha = 1173700,
.beta = -6263600,
},
.group = &eristaTSensorGroupMem,
},
};
const TSensor marikoTSensors[] = {
{
.name = "cpu0",
.base = 0xc0,
.config = &marikoConf,
.calib_fuse_offset = 0x198,
.fuse_corr = {
.alpha = 1085000,
.beta = 3244200,
},
.group = &tSensorGroupCpu,
}, {
.name = "cpu1",
.base = 0xe0,
.config = &marikoConf,
.calib_fuse_offset = 0x184,
.fuse_corr = {
.alpha = 1126200,
.beta = -67500,
},
.group = &tSensorGroupCpu,
}, {
.name = "cpu2",
.base = 0x100,
.config = &marikoConf,
.calib_fuse_offset = 0x188,
.fuse_corr = {
.alpha = 1098400,
.beta = 2251100,
},
.group = &tSensorGroupCpu,
}, {
.name = "cpu3",
.base = 0x120,
.config = &marikoConf,
.calib_fuse_offset = 0x22c,
.fuse_corr = {
.alpha = 1108000,
.beta = 602700,
},
.group = &tSensorGroupCpu,
}, {
.name = "gpu",
.base = 0x180,
.config = &marikoConf,
.calib_fuse_offset = 0x254,
.fuse_corr = {
.alpha = 1074300,
.beta = 2734900,
},
.group = &tSensorGroupGpu,
}, {
.name = "pllx",
.base = 0x1a0,
.config = &marikoConf,
.calib_fuse_offset = 0x260,
.fuse_corr = {
.alpha = 1039700,
.beta = 6829100,
},
.group = &tSensorGroupPll,
},
};
u32 calib[SocthermTSensor_EnumMax] = {};
u64 socthermVa, carVa, fuseVa;
bool isMariko;
}
bool IsDisabledThroughSleep() {
return (ReadReg(carVa, CLK_RST_CONTROLLER_RST_DEVICES) & SWR_SOC_THERM_RST) || !(ReadReg(carVa, CLK_RST_CONTROLLER_CLK_OUT_ENB) & CLK_ENB_SOC_THERM);
}
bool IsSensorEnabled() {
return ReadReg(socthermVa, TSENSOR_TSENSOR_CLKEN);
}
void EnableSensor(const TSensor *sensor, u32 sensorIdx) {
u32 val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
WriteReg(socthermVa, sensor->base + SENSOR_CONFIG0, val);
val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
val |= SENSOR_CONFIG1_TEMP_ENABLE;
WriteReg(socthermVa, sensor->base + SENSOR_CONFIG1, val);
WriteReg(socthermVa, sensor->base + SENSOR_CONFIG2, calib[sensorIdx]);
}
s32 TranslateTemp(u16 val) {
s32 t;
t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
if (val & READBACK_ADD_HALF) {
t += 500;
}
if (val & READBACK_NEGATE) {
t *= -1;
}
return t;
}
void StartSensors() {
u32 pdiv, hotspot;
if (isMariko) {
for (u32 i = 0; i < std::size(marikoTSensors); ++i) {
EnableSensor(&marikoTSensors[i], i);
}
pdiv = (ReadReg(socthermVa, SENSOR_PDIV) & PDIV_MASK_T210B0) | PDIV_RATE_T210B0;
hotspot = (ReadReg(socthermVa, SENSOR_HOTSPOT_OFF) & HOTSPOT_MASK_T210B0) | HOTSPOT_VAL;
} else {
for (u32 i = 0; i < std::size(eristaTSensors); ++i) {
EnableSensor(&eristaTSensors[i], i);
}
pdiv = (ReadReg(socthermVa, SENSOR_PDIV) & PDIV_MASK_T210) | PDIV_RATE_T210;
hotspot = (ReadReg(socthermVa, SENSOR_HOTSPOT_OFF) & HOTSPOT_MASK_T210) | HOTSPOT_VAL;
EnableSensor(&eristaTSensors[SocthermTSensor_MEM0], SocthermTSensor_MEM0);
EnableSensor(&eristaTSensors[SocthermTSensor_MEM1], SocthermTSensor_MEM1);
}
WriteReg(socthermVa, SENSOR_PDIV, pdiv);
WriteReg(socthermVa, SENSOR_HOTSPOT_OFF, hotspot);
WriteReg(socthermVa, TSENSOR_TSENSOR_CLKEN, TSENSOR_TSENSOR_ENABLE);
}
void ReadTSensors(TSensorTemps &temps) {
if (IsDisabledThroughSleep()) {
return;
}
if (!IsSensorEnabled()) {
StartSensors();
}
temps.cpu = TranslateTemp(ReadReg(socthermVa, SENSOR_TEMP1) >> 16);
temps.gpu = TranslateTemp(ReadReg(socthermVa, SENSOR_TEMP1) & SENSOR_TEMP1_GPU_TEMP_MASK);
temps.pllx = TranslateTemp(ReadReg(socthermVa, SENSOR_TEMP2) & SENSOR_TEMP2_PLLX_TEMP_MASK);
if (board::GetSocType() == HocClkSocType_Erista) {
temps.mem = TranslateTemp(ReadReg(socthermVa, SENSOR_TEMP2) >> 16);
} else {
temps.mem = -1;
}
}
void InitializeSoctherm() {
isMariko = board::GetSocType() == HocClkSocType_Mariko;
constexpr u64 SocthermPa = 0x700E2000, FusePa = 0x7000F000, CarPa = 0x60006000;
R_UNLESS(MapAddress(socthermVa, SocthermPa, "soctherm"));
R_UNLESS(MapAddress( fuseVa, FusePa, "fuse"));
R_UNLESS(MapAddress( carVa, CarPa, "car"));
WriteReg(carVa, CAR_CLK_SOURCE_TSENSOR, CAR_CLK_SOURCE_TSENSOR_VAL);
SetBits(carVa, CAR_CLK_OUT_ENB_V, 0x10);
svcSleepThread(2000);
TSensorSharedCalib sharedCal = {};
CalcSharedCal(&tfuse, &sharedCal, fuseVa);
if (isMariko) {
for (u32 i = 0; i < std::size(marikoTSensors); ++i) {
CalcTSensorCalib(marikoTSensors[i].config, &sharedCal, &marikoTSensors[i].fuse_corr, &calib[i], marikoTSensors[i].calib_fuse_offset, fuseVa);
}
} else {
for (u32 i = 0; i < std::size(eristaTSensors); ++i) {
CalcTSensorCalib(eristaTSensors[i].config, &sharedCal, &eristaTSensors[i].fuse_corr, &calib[i], eristaTSensors[i].calib_fuse_offset, fuseVa);
}
}
StartSensors();
fileUtils::LogLine("[Soctherm] Finished init.");
}
}

52
Source/hoc-clk/sysmodule/src/tsensor/soctherm.hpp Normal file
View File

@@ -0,0 +1,52 @@
/*
* Copyright (c) 2014 - 2019, NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Mikko Perttunen <mperttunen@nvidia.com>
*
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#pragma once
#include <switch.h>
#include <hocclk.h>
namespace tsensor {
enum SocthermTSensor : u32 {
SocthermTSensor_CPU0 = 0,
SocthermTSensor_CPU1 = 1,
SocthermTSensor_CPU2 = 2,
SocthermTSensor_CPU3 = 3,
SocthermTSensor_GPU = 4,
SocthermTSensor_PLLX = 5,
SocthermTSensor_MEM0 = 6,
SocthermTSensor_MEM1 = 7,
SocthermTSensor_EnumMax = 8,
};
struct TSensorTemps {
s32 cpu;
s32 gpu;
s32 mem;
s32 pllx;
};
void InitializeSoctherm();
void ReadTSensors(TSensorTemps &temps);
}

115
Source/hoc-clk/sysmodule/src/tsensor/tsensor_common.cpp Normal file
View File

@@ -0,0 +1,115 @@
/*
* Copyright (c) 2014 - 2019, NVIDIA CORPORATION. All rights reserved.
*
* Copyright (c) 1994, Linus Torvalds
*
* Author:
* Mikko Perttunen <mperttunen@nvidia.com>
*
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include <switch.h>
#include "tsensor_common.hpp"
namespace tsensor {
static s64 div64_s64(s64 dividend, s64 divisor) {
return dividend / divisor;
}
static s64 div64_s64_precise(s64 a, s32 b) {
s64 r, al;
al = a << 16;
r = div64_s64(al * 2 + 1, 2 * b);
return r >> 16;
}
static s32 sign_extend32(u32 value, int index) {
u8 shift = 31 - index;
return (s32) (value << shift) >> shift;
}
void CalcSharedCal(const TSensorFuse *tfuse, TSensorSharedCalib *shared, u64 fuseVa) {
constexpr u32 NominalCalibFt = 105;
constexpr u32 NominalCalibCp = 25;
s32 shifted_cp, shifted_ft;
u32 val = ReadReg(fuseVa, FUSE_TSENSOR_COMMON);
shared->base_cp = (val & tfuse->fuse_base_cp_mask) >> tfuse->fuse_base_cp_shift;
shared->base_ft = (val & tfuse->fuse_base_ft_mask) >> tfuse->fuse_base_ft_shift;
shifted_ft = (val & tfuse->fuse_shift_ft_mask) >> tfuse->fuse_shift_ft_shift;
shifted_ft = sign_extend32(shifted_ft, 4);
if (tfuse->fuse_spare_realignment) {
val = ReadReg(fuseVa, tfuse->fuse_spare_realignment + FUSE_CACHE_OFFSET);
}
shifted_cp = sign_extend32(val, 5);
shared->actual_temp_cp = 2 * NominalCalibCp + shifted_cp;
shared->actual_temp_ft = 2 * NominalCalibFt + shifted_ft;
}
void CalcTSensorCalib(const TSensorConfig *cfg, TSensorSharedCalib *shared, const FuseCorrCoeff *corr, u32 *calibration, u32 offset, u64 fuseVa) {
#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
#define CALIB_COEFFICIENT 1000000LL
#define SENSOR_CONFIG2_THERMA_SHIFT 16
#define SENSOR_CONFIG2_THERMB_SHIFT 0
u32 val, calib;
s32 actual_tsensor_ft, actual_tsensor_cp;
s32 delta_sens, delta_temp;
s32 mult, div;
s16 therma, thermb;
s64 temp;
val = ReadReg(fuseVa, offset + FUSE_CACHE_OFFSET);
actual_tsensor_cp = (shared->base_cp * 64) + sign_extend32(val, 12);
val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK) >> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
actual_tsensor_ft = (shared->base_ft * 32) + sign_extend32(val, 12);
delta_sens = actual_tsensor_ft - actual_tsensor_cp;
delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
mult = cfg->pdiv * cfg->tsample_ate;
div = cfg->tsample * cfg->pdiv_ate;
temp = (s64)delta_temp * (1LL << 13) * mult;
therma = div64_s64_precise(temp, (s64)delta_sens * div);
temp = ((s64)actual_tsensor_ft * shared->actual_temp_cp) - ((s64)actual_tsensor_cp * shared->actual_temp_ft);
thermb = div64_s64_precise(temp, delta_sens);
temp = (s64)therma * corr->alpha;
therma = div64_s64_precise(temp, CALIB_COEFFICIENT);
temp = (s64)thermb * corr->alpha + corr->beta;
thermb = div64_s64_precise(temp, CALIB_COEFFICIENT);
calib = ((u16)therma << SENSOR_CONFIG2_THERMA_SHIFT) | ((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
*calibration = calib;
}
}

122
Source/hoc-clk/sysmodule/src/tsensor/tsensor_common.hpp Normal file
View File

@@ -0,0 +1,122 @@
/*
* Copyright (c) 2014 - 2019, NVIDIA CORPORATION. All rights reserved.
*
* Copyright (c) 1994, Linus Torvalds
*
* Author:
* Mikko Perttunen <mperttunen@nvidia.com>
*
* Copyright (c) Souldbminer, Lightos_ and Horizon OC Contributors
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
#pragma once
namespace tsensor {
#define FUSE_TSENSOR_COMMON 0xA80
#define FUSE_CACHE_OFFSET 0x800
struct TSensorConfig {
u32 tall;
u32 tiddq_en;
u32 ten_count;
u32 pdiv;
u32 pdiv_ate;
u32 tsample;
u32 tsample_ate;
};
struct FuseCorrCoeff {
s32 alpha;
s32 beta;
};
struct TSensorGroup {
const char *name;
u8 id;
u16 sensor_temp_offset;
u32 sensor_temp_mask;
u32 pdiv_mask;
u32 pllx_hotspot_diff;
u32 pllx_hotspot_mask;
u32 hw_pllx_offset_mask;
u32 hw_pllx_offset_en_mask;
u32 thermtrip_enable_mask;
u32 thermtrip_any_en_mask;
u32 thermtrip_threshold_mask;
u16 thermctl_lvl0_offset;
u32 thermctl_isr_mask;
u32 thermctl_lvl0_up_thresh_mask;
u32 thermctl_lvl0_dn_thresh_mask;
};
struct TSensorGroupOffsets {
u32 max;
u32 min;
u32 hw_offsetting_en;
const TSensorGroup *ttg;
};
struct TSensor {
const char *name;
const u32 base;
const TSensorConfig *config;
const u32 calib_fuse_offset;
const FuseCorrCoeff fuse_corr;
const TSensorGroup *group;
};
struct TSensorFuse {
u32 fuse_base_cp_mask;
u32 fuse_base_cp_shift;
u32 fuse_base_ft_mask;
u32 fuse_base_ft_shift;
u32 fuse_shift_ft_mask;
u32 fuse_shift_ft_shift;
u32 fuse_spare_realignment;
};
struct TSensorSharedCalib {
u32 base_cp;
u32 base_ft;
u32 actual_temp_cp;
u32 actual_temp_ft;
};
template<typename T = u32>
static inline T ReadReg(u64 base, u32 offset) {
return *reinterpret_cast<volatile T*>(base + offset);
}
template<typename T = u32>
static inline void WriteReg(u64 base, u32 offset, T value) {
*reinterpret_cast<volatile T*>(base + offset) = value;
}
template<typename T = u32>
static inline void SetBits(u64 base, u32 offset, T mask) {
WriteReg(base, offset, ReadReg<T>(base, offset) | mask);
}
template<typename T = u32>
static inline void ClearBits(u64 base, u32 offset, T mask) {
WriteReg(base, offset, ReadReg<T>(base, offset) & ~mask);
}
void CalcSharedCal(const TSensorFuse *tfuse, TSensorSharedCalib *shared, u64 fuseVa);
void CalcTSensorCalib(const TSensorConfig *cfg, TSensorSharedCalib *shared, const FuseCorrCoeff *corr, u32 *calibration, u32 offset, u64 fuseVa);
}