add all low timings
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@@ -36,7 +36,7 @@ volatile CustomizeTable C = {
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.hpMode = DISABLED,
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.commonEmcMemVolt = 1175000, /* LPDDR4(X) JEDEC Specification */
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.eristaEmcMaxClock = 1600000, /* Maximum HB-MGCH ram rating */
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.eristaEmcMaxClock = 1633000, /* Maximum HB-MGCH ram rating */
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/* Available: 66MHz step rate, 100MHz step rate, 133MHz step rate and jedec. */
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/* Jedec freqs are 1333MHz, 1600MHz, 1866MHz, 2133MHz, 2400MHz, 2666MHz, 2933MHz, 3200MHz. */
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@@ -65,8 +65,14 @@ volatile CustomizeTable C = {
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/* Frequency where non low timings gets used. */
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.timingEmcTbreak = DISABLED,
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.low_t6_tRTW = 0,
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.low_t7_tWTR = 0,
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.low_t1_tRCD = 0,
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.low_t2_tRP = 0,
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.low_t3_tRAS = 0,
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.low_t4_tRRD = 0,
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.low_t5_tRFC = 0,
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.low_t6_tRTW = 0,
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.low_t7_tWTR = 0,
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.low_t8_tREFI = 0,
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.readLatency = {
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/* 1333 */ 0,
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@@ -20,8 +20,8 @@
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#pragma once
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#define CUST_REV 4
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#define KIP_VERSION 241
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#define CUST_REV 5
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#define KIP_VERSION 242
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#include "oc_common.hpp"
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#include "pcv/pcv_common.hpp"
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@@ -89,8 +89,14 @@ struct CustomizeTable {
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u32 t2_tRP_cap;
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u32 timingEmcTbreak;
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u32 low_t1_tRCD;
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u32 low_t2_tRP;
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u32 low_t3_tRAS;
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u32 low_t4_tRRD;
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u32 low_t5_tRFC;
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u32 low_t6_tRTW;
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u32 low_t7_tWTR;
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u32 low_t8_tREFI;
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u32 readLatency[4];
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u32 writeLatency[4];
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@@ -134,27 +134,32 @@ namespace ams::ldr::hoc::pcv::mariko {
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/* At 1333WL, for some reason (incorrect ram timing config in mtc table?), tRP causes crashes at high reductions - 2 seems to be the most common limit. */
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/* This is a lazy workaround until I find the issue... */
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u32 tRPpbIndex = C.t2_tRP;
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const bool lowFreq = freq < C.timingEmcTbreak;
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volatile u32 tRPpbIndex = lowFreq ? C.low_t2_tRP : C.t2_tRP;
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if (WL == WL_1331) {
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tRPpbIndex = MIN(C.t2_tRP_cap, C.t2_tRP);
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tRPpbIndex = MIN(C.t2_tRP_cap, tRPpbIndex);
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}
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tRCD = tRCD_values[C.t1_tRCD];
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tRPpb = tRP_values[tRPpbIndex];
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tRAS = tRAS_values[C.t3_tRAS];
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tRRD = tRRD_values[C.t4_tRRD];
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tRFCpb = tRFC_values[C.t5_tRFC];
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u32 tRTW = C.t6_tRTW;
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u32 tWTR = 10 - tWTR_values[C.t7_tWTR];
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tRCD = tRCD_values[lowFreq ? C.low_t1_tRCD : C.t1_tRCD];
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tRPpb = tRP_values[tRPpbIndex];
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tRAS = tRAS_values[lowFreq ? C.low_t3_tRAS : C.t3_tRAS];
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tRRD = tRRD_values[lowFreq ? C.low_t4_tRRD : C.t4_tRRD];
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tRFCpb = tRFC_values[lowFreq ? C.low_t5_tRFC : C.t5_tRFC];
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if (freq < C.timingEmcTbreak) {
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tRTW = C.low_t6_tRTW;
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tWTR = 10 - tWTR_values[C.low_t7_tWTR];
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}
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u32 tRTW = lowFreq ? C.low_t6_tRTW : C.t6_tRTW;
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u32 tWTR = 10 - tWTR_values[lowFreq ? C.low_t7_tWTR : C.t7_tWTR];
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s32 finetRTW = C.fineTune_t6_tRTW;
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s32 finetWTR = C.fineTune_t7_tWTR;
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u32 tREFI = lowFreq ? C.low_t8_tREFI : C.t8_tREFI;
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refresh_raw = 0xFFFF;
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if (tREFI != 6) {
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refresh_raw = CEIL(tREFpb_values[tREFI] / tCK_avg) - 0x40;
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refresh_raw = MIN(refresh_raw, static_cast<u32>(0xFFFF));
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}
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tRC = tRAS + tRPpb;
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tRFCab = tRFCpb * 2;
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tXSR = static_cast<double>(tRFCab + 7.5);
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@@ -130,6 +130,8 @@ namespace ams::ldr::hoc {
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inline u32 tFAW;
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inline double tRPab;
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inline u32 refresh_raw;
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inline u32 RL;
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inline u32 WL;
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@@ -375,12 +375,6 @@ namespace ams::ldr::hoc::pcv::mariko {
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WRITE_PARAM_ALL_REG(table, emc_cfg, 0xF3200000);
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}
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u32 refresh_raw = 0xFFFF;
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if (C.t8_tREFI != 6) {
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refresh_raw = CEIL(tREFpb_values[C.t8_tREFI] / tCK_avg) - 0x40;
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refresh_raw = MIN(refresh_raw, static_cast<u32>(0xFFFF));
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}
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u32 trefbw = refresh_raw + 0x40;
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trefbw = MIN(trefbw, static_cast<u32>(0x3FFF));
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