#!/bin/bash

# ============================================================
# Copyright (c) Lightos_
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License
# along with this program.  If not, see <http://www.gnu.org/licenses/>.
#
# ============================================================

BASE=0x70019000

REGISTERS="
MC_ERR_ADR_0 0xc
MC_SMMU_CONFIG_0 0x10
MC_SMMU_TLB_CONFIG_0 0x14
MC_SMMU_PTC_CONFIG_0 0x18
MC_SMMU_PTB_ASID_0 0x1c
MC_SMMU_PTB_DATA_0 0x20
MC_SMMU_TLB_FLUSH_0 0x30
MC_SMMU_PTC_FLUSH_0 0x34
MC_EMEM_CFG_0 0x50
MC_EMEM_ROW_WIDTH 0x54
MC_EMEM_ADR_CFG_DEV0_0 0x58
MC_EMEM_ADR_CFG_DEV1_0 0x5c
MC_EMEM_ADR_CFG_CHANNEL_MASK_0 0x60
MC_EMEM_ADR_CFG_BANK_MASK_0_0 0x64
MC_EMEM_ADR_CFG_BANK_MASK_1_0 0x68
MC_EMEM_ADR_CFG_BANK_MASK_2_0 0x6c
MC_SECURITY_CFG0_0 0x70
MC_SECURITY_CFG1_0 0x74
MC_EMEM_ARB_CFG_0 0x90
MC_EMEM_ARB_OUTSTANDING_REQ_0 0x94
MC_EMEM_ARB_TIMING_RCD_0 0x98
MC_EMEM_ARB_TIMING_RP_0 0x9c
MC_EMEM_ARB_TIMING_RC_0 0xa0
MC_EMEM_ARB_TIMING_RAS_0 0xa4
MC_EMEM_ARB_TIMING_FAW_0 0xa8
MC_EMEM_ARB_TIMING_RRD_0 0xac
MC_EMEM_ARB_TIMING_RAP2PRE_0 0xb0
MC_EMEM_ARB_TIMING_WAP2PRE_0 0xb4
MC_EMEM_ARB_TIMING_R2R_0 0xb8
MC_EMEM_ARB_TIMING_W2W_0 0xbc
MC_EMEM_ARB_TIMING_R2W_0 0xc0
MC_EMEM_ARB_TIMING_W2R_0 0xc4
MC_EMEM_ARB_DA_TURNS_0 0xd0
MC_EMEM_ARB_DA_COVERS_0 0xd4
MC_EMEM_ARB_MISC0_0 0xd8
C_EMEM_ARB_MISC1_0 0xdc
MC_EMEM_ARB_MISC2_0 0xc8
MC_EMEM_ARB_RING1_THROTTLE_0 0xe0
MC_EMEM_ARB_RING3_THROTTLE_0 0xe4
MC_EMEM_ARB_OVERRIDE_0 0xe8
MC_EMEM_ARB_RSV_0 0xec
MC_CLKEN_OVERRIDE_0 0xf4
MC_TIMING_CONTROL_0 0xfc
MC_STAT_CONTROL_0 0x100
MC_CLIENT_HOTRESET_CTRL_0 0x200
MC_CLIENT_HOTRESET_STATUS_0 0x204
MC_EMEM_ARB_ISOCHRONOUS_0_0 0x208
MC_EMEM_ARB_ISOCHRONOUS_1_0 0x20c
MC_EMEM_ARB_ISOCHRONOUS_2_0 0x210
MC_EMEM_ARB_ISOCHRONOUS_3_0 0x214
MC_EMEM_ARB_HYSTERESIS_0_0 0x218
MC_EMEM_ARB_HYSTERESIS_1_0 0x21c
MC_EMEM_ARB_HYSTERESIS_2_0 0x220
MC_EMEM_ARB_HYSTERESIS_3_0 0x224
MC_SMMU_AFI_ASID_0 0x238
MC_SMMU_AVPC_ASID_0 0x23c
MC_SMMU_DC_ASID_0 0x240
MC_SMMU_DCB_ASID_0 0x244
MC_SMMU_HC_ASID_0 0x250
MC_SMMU_HDA_ASID_0 0x254
MC_SMMU_ISP2_ASID_0 0x258
MC_SMMU_NVENC_ASID_0 0x264
MC_SMMU_NV_ASID_0 0x268
MC_SMMU_NV2_ASID_0 0x26c
MC_SMMU_PPCS_ASID_0 0x270
MC_SMMU_SATA_ASID_0 0x274
MC_SMMU_VI_ASID_0 0x280
MC_SMMU_VIC_ASID_0 0x284
MC_SMMU_XUSB_HOST_ASID_0 0x288
MC_SMMU_XUSB_DEV_ASID_0 0x28c
MC_SMMU_TSEC_ASID_0 0x294
MC_SMMU_PPCS1_ASID_0 0x298
MC_VIDEO_PROTECT_VPR_OVERRIDE_0 0x418
MC_VIDEO_PROTECT_VPR_OVERRIDE1_0 0x590
MC_SMMU_TLB_SET_SELECTION_MASK_0_0 0x600
MC_DISPLAY_SNAP_RING_0 0x608
MC_ERR_VPR_STATUS_0 0x654
MC_ERR_VPR_ADR_0 0x658
MC_IRAM_REG_CTRL_0 0x964
MC_EMEM_CFG_ACCESS_CTRL_0 0x664
MC_TZ_SECURITY_CTRL_0 0x668
MC_EMEM_ARB_OUTSTANDING_REQ_RING3_0 0x66c
MC_SEC_CARVEOUT_BOM_0 0x670
MC_SEC_CARVEOUT_SIZE_MB_0 0x674
MC_SEC_CARVEOUT_REG_CTRL_0 0x678
MC_ERR_SEC_STATUS_0 0x67c
MC_ERR_SEC_ADR_0 0x680
MC_PC_IDLE_CLOCK_GATE_CONFIG_0 0x684
MC_STUTTER_CONTROL_0 0x688
MC_EMEM_ARB_NISO_THROTTLE_0 0x6b0
MC_EMEM_ARB_NISO_THROTTLE_MASK_0 0x6b8
MC_EMEM_ARB_RING0_THROTTLE_MASK_0 0x6bc
MC_EMEM_ARB_TIMING_RFCPB_0 0x6c0
MC_EMEM_ARB_TIMING_CCDMW_0 0x6c4
MC_EMEM_ARB_REFPB_HP_CTRL_0 0x6f0
MC_EMEM_ARB_REFPB_BANK_CTRL_0 0x6f4
MC_EMEM_ARB_OVERRIDE_1_0 0x968
MC_CLIENT_HOTRESET_CTRL_1_0 0x970
MC_CLIENT_HOTRESET_STATUS_1_0 0x974
MC_VIDEO_PROTECT_GPU_OVERRIDE_0_0 0x984
MC_VIDEO_PROTECT_GPU_OVERRIDE_1_0 0x988
MC_MTS_CARVEOUT_BOM_0 0x9a0
MC_MTS_CARVEOUT_SIZE_MB_0 0x9a4
MC_MTS_CARVEOUT_ADR_HI_0 0x9a8
MC_MTS_CARVEOUT_REG_CTRL_0 0x9ac
MC_SMMU_PTC_FLUSH_1_0 0x9b8
MC_SECURITY_CFG3_0 0x9bc
MC_EMEM_BANK_SWIZZLE_CFG0_0 0x9c0
MC_EMEM_BANK_SWIZZLE_CFG1_0 0x9c4
MC_EMEM_BANK_SWIZZLE_CFG2_0 0x9c8
MC_EMEM_BANK_SWIZZLE_CFG3_0 0x9cc
MC_SEC_CARVEOUT_ADR_HI_0 0x9d4
MC_SMMU_DC1_ASID_0 0xa88
MC_SMMU_SDMMC1A_ASID_0 0xa94
MC_SMMU_SDMMC2A_ASID_0 0xa98
MC_SMMU_SDMMC3A_ASID_0 0xa9c
MC_SMMU_SDMMC4A_ASID_0 0xaa0
MC_SMMU_ISP2B_ASID_0 0xaa4
MC_SMMU_GPU_ASID_0 0xaa8
MC_SMMU_GPUB_ASID_0 0xaac
MC_SMMU_PPCS2_ASID_0 0xab0
MC_SMMU_NVDEC_ASID_0 0xab4
MC_SMMU_APE_ASID_0 0xab8
MC_SMMU_SE_ASID_0 0xabc
MC_SMMU_NVJPG_ASID_0 0xac0
MC_SMMU_HC1_ASID_0 0xac4
MC_SMMU_SE1_ASID_0 0xac8
MC_SMMU_AXIAP_ASID_0 0xacc
MC_SMMU_ETR_ASID_0 0xad0
MC_SMMU_TSECB_ASID_0 0xad4
MC_SMMU_TSEC1_ASID_0 0xad8
MC_SMMU_TSECB1_ASID_0 0xadc
MC_SMMU_NVDEC1_ASID_0 0xae0
MC_EMEM_ARB_NISO_THROTTLE_MASK_1_0 0xb80
MC_EMEM_ARB_HYSTERESIS_4_0 0xb84
MC_EMEM_ARB_ISOCHRONOUS_4_0 0xb94
MC_EMEM_ARB_DHYSTERESIS_0_0 0xbb0
MC_EMEM_ARB_DHYSTERESIS_1_0 0xbb4
MC_EMEM_ARB_DHYSTERESIS_2_0 0xbb8
MC_EMEM_ARB_DHYSTERESIS_3_0 0xbbc
MC_EMEM_ARB_DHYSTERESIS_4_0 0xbc0
MC_EMEM_ARB_DHYST_CTRL_0 0xbcc
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0_0 0xbd0
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1_0 0xbd4
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2_0 0xbd8
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3_0 0xbdc
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4_0 0xbe0
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5_0 0xbe4
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6_0 0xbe8
MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7_0 0xbec
MC_DA_CONFIG0_0 0x9dc
MC_AHB_PTSA_MIN_0 0x4e0
MC_AUD_PTSA_MIN_0 0x54c
MC_MLL_MPCORER_PTSA_RATE_0 0x44c
MC_RING2_PTSA_RATE_0 0x440
MC_USBD_PTSA_RATE_0 0x530
MC_USBX_PTSA_MIN_0 0x528
MC_USBD_PTSA_MIN_0 0x534
MC_APB_PTSA_MAX_0 0x4f0
MC_JPG_PTSA_RATE_0 0x584
MC_DIS_PTSA_MIN_0 0x420
MC_AVP_PTSA_MAX_0 0x4fc
MC_AVP_PTSA_RATE_0 0x4f4
MC_RING1_PTSA_MIN_0 0x480
MC_DIS_PTSA_MAX_0 0x424
MC_SD_PTSA_MAX_0 0x4d8
MC_MSE_PTSA_RATE_0 0x4c4
MC_VICPC_PTSA_MIN_0 0x558
MC_PCX_PTSA_MAX_0 0x4b4
MC_ISP_PTSA_RATE_0 0x4a0
MC_A9AVPPC_PTSA_MIN_0 0x48c
MC_RING2_PTSA_MAX_0 0x448
MC_AUD_PTSA_RATE_0 0x548
MC_HOST_PTSA_MIN_0 0x51c
MC_MLL_MPCORER_PTSA_MAX_0 0x454
MC_SD_PTSA_MIN_0 0x4d4
MC_RING1_PTSA_RATE_0 0x47c
MC_JPG_PTSA_MIN_0 0x588
MC_HDAPC_PTSA_MIN_0 0x62c
MC_AVP_PTSA_MIN_0 0x4f8
MC_JPG_PTSA_MAX_0 0x58c
MC_VE_PTSA_MAX_0 0x43c
MC_DFD_PTSA_MAX_0 0x63c
MC_VICPC_PTSA_RATE_0 0x554
MC_GK_PTSA_MAX_0 0x544
MC_VICPC_PTSA_MAX_0 0x55c
MC_SDM_PTSA_MAX_0 0x624
MC_SAX_PTSA_RATE_0 0x4b8
MC_PCX_PTSA_MIN_0 0x4b0
MC_APB_PTSA_MIN_0 0x4ec
MC_GK2_PTSA_MIN_0 0x614
MC_PCX_PTSA_RATE_0 0x4ac
MC_RING1_PTSA_MAX_0 0x484
MC_HDAPC_PTSA_RATE_0 0x628
MC_MLL_MPCORER_PTSA_MIN_0 0x450
MC_GK2_PTSA_MAX_0 0x618
MC_AUD_PTSA_MAX_0 0x550
MC_GK2_PTSA_RATE_0 0x610
MC_ISP_PTSA_MAX_0 0x4a8
MC_DISB_PTSA_RATE_0 0x428
MC_VE2_PTSA_MAX_0 0x49c
MC_DFD_PTSA_MIN_0 0x638
MC_FTOP_PTSA_RATE_0 0x50c
MC_A9AVPPC_PTSA_RATE_0 0x488
MC_VE2_PTSA_MIN_0 0x498
MC_USBX_PTSA_MAX_0 0x52c
MC_DIS_PTSA_RATE_0 0x41c
MC_USBD_PTSA_MAX_0 0x538
MC_A9AVPPC_PTSA_MAX_0 0x490
MC_USBX_PTSA_RATE_0 0x524
MC_FTOP_PTSA_MAX_0 0x514
MC_HDAPC_PTSA_MAX_0 0x630
MC_SD_PTSA_RATE_0 0x4d0
MC_DFD_PTSA_RATE_0 0x634
MC_FTOP_PTSA_MIN_0 0x510
MC_SDM_PTSA_RATE_0 0x61c
MC_AHB_PTSA_RATE_0 0x4dc
MC_SMMU_SMMU_PTSA_MAX_0 0x460
MC_RING2_PTSA_MIN_0 0x444
MC_SDM_PTSA_MIN_0 0x620
MC_APB_PTSA_RATE_0 0x4e8
MC_MSE_PTSA_MIN_0 0x4c8
MC_HOST_PTSA_RATE_0 0x518
MC_VE_PTSA_RATE_0 0x434
MC_AHB_PTSA_MAX_0 0x4e4
MC_SAX_PTSA_MIN_0 0x4bc
MC_SMMU_SMMU_PTSA_MIN_0 0x45c
MC_ISP_PTSA_MIN_0 0x4a4
MC_HOST_PTSA_MAX_0 0x520
MC_SAX_PTSA_MAX_0 0x4c0
MC_VE_PTSA_MIN_0 0x438
MC_GK_PTSA_MIN_0 0x540
MC_MSE_PTSA_MAX_0 0x4cc
MC_DISB_PTSA_MAX_0 0x430
MC_DISB_PTSA_MIN_0 0x42c
MC_SMMU_SMMU_PTSA_RATE_0 0x458
MC_VE2_PTSA_RATE_0 0x494
MC_GK_PTSA_RATE_0 0x53c
MC_PTSA_GRANT_DECREMENT_0 0x960
MC_LATENCY_ALLOWANCE_AVPC_0_0 0x2e4
MC_LATENCY_ALLOWANCE_AXIAP_0_0 0x3a0
MC_LATENCY_ALLOWANCE_XUSB_1_0 0x380
MC_LATENCY_ALLOWANCE_ISP2B_0_0 0x384
MC_LATENCY_ALLOWANCE_SDMMCAA_0_0 0x3bc
MC_LATENCY_ALLOWANCE_SDMMCA_0_0 0x3b8
MC_LATENCY_ALLOWANCE_ISP2_0_0 0x370
MC_LATENCY_ALLOWANCE_SE_0_0 0x3e0
MC_LATENCY_ALLOWANCE_ISP2_1_0 0x374
MC_LATENCY_ALLOWANCE_DC_0_0 0x2e8
MC_LATENCY_ALLOWANCE_VIC_0_0 0x394
MC_LATENCY_ALLOWANCE_DCB_1_0 0x2f8
MC_LATENCY_ALLOWANCE_NVDEC_0_0 0x3d8
MC_LATENCY_ALLOWANCE_DCB_2_0 0x2fc
MC_LATENCY_ALLOWANCE_TSEC_0_0 0x390
MC_LATENCY_ALLOWANCE_DC_2_0 0x2f0
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0AB_0 0x694
MC_LATENCY_ALLOWANCE_PPCS_1_0 0x348
MC_LATENCY_ALLOWANCE_XUSB_0_0 0x37c
MC_LATENCY_ALLOWANCE_PPCS_0_0 0x344
MC_LATENCY_ALLOWANCE_TSECB_0_0 0x3f0
MC_LATENCY_ALLOWANCE_AFI_0_0 0x2e0
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0B_0 0x698
MC_LATENCY_ALLOWANCE_DC_1_0 0x2ec
MC_LATENCY_ALLOWANCE_APE_0_0 0x3dc
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0C_0 0x6a0
MC_LATENCY_ALLOWANCE_A9AVP_0_0 0x3a4
MC_LATENCY_ALLOWANCE_GPU2_0_0 0x3e8
MC_LATENCY_ALLOWANCE_DCB_0_0 0x2f4
MC_LATENCY_ALLOWANCE_HC_1_0 0x314
MC_LATENCY_ALLOWANCE_SDMMC_0_0 0x3c0
MC_LATENCY_ALLOWANCE_NVJPG_0_0 0x3e4
MC_LATENCY_ALLOWANCE_PTC_0_0 0x34c
MC_LATENCY_ALLOWANCE_ETR_0_0 0x3ec
MC_LATENCY_ALLOWANCE_MPCORE_0_0 0x320
MC_LATENCY_ALLOWANCE_VI2_0_0 0x398
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0BB_0 0x69c
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0CB_0 0x6a4
MC_LATENCY_ALLOWANCE_SATA_0_0 0x350
MC_SCALED_LATENCY_ALLOWANCE_DISPLAY0A_0 0x690
MC_LATENCY_ALLOWANCE_HC_0_0 0x310
MC_LATENCY_ALLOWANCE_DC_3_0 0x3c8
MC_LATENCY_ALLOWANCE_GPU_0_0 0x3ac
MC_LATENCY_ALLOWANCE_SDMMCAB_0_0 0x3c4
MC_LATENCY_ALLOWANCE_ISP2B_1_0 0x388
MC_LATENCY_ALLOWANCE_NVENC_0_0 0x328
MC_LATENCY_ALLOWANCE_HDA_0_0 0x318
"

echo "Dumping MC registers from BASE=$BASE"
echo "-----------------------------------"

set -- $REGISTERS
while [ $# -gt 0 ]; do
    name=$1
    offset=$2
    addr=$(printf "0x%X" $((BASE + offset)))
    val=$(busybox devmem "$addr")
    echo "$name = $val"
    shift 2
done
