143 lines
4.0 KiB
C
143 lines
4.0 KiB
C
/*
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* Copyright (c) 2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "uart.h"
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#include "../../irq.h"
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// Adapted from TF asm code
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// AMBA PL101 driver
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/*
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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//115200
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static inline volatile PL011UartRegisters *uartGetRegisters(UartDevice dev)
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{
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switch (dev) {
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case UART_A:
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return (volatile PL011UartRegisters *)0x09000000;
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default:
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return NULL;
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}
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}
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void uartInit(UartDevice dev, u32 baudRate, u32 flags)
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{
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/* The TRM (DDI0183) reads:
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Program the control registers as follows:
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1. Disable the UART.
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2. Wait for the end of transmission or reception of the current character.
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3. Flush the transmit FIFO by disabling bit 4 (FEN) in the line control register
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(UARTCLR_H).
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4. Reprogram the control register.
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5. Enable the UART.
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*/
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(void)flags;
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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// First, disable the UART. Flush the receive FIFO, wait for tx to complete, and disable both FIFOs.
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uart->cr &= ~PL011_UARTCR_UARTEN;
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while (!(uart->fr & PL011_UARTFR_RXFE)) {
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uart->dr;
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}
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while (uart->fr & PL011_UARTFR_BUSY);
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// This flushes the transmit FIFO:
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uart->lcr_h &= ~PL011_UARTLCR_H_FEN;
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// Set baudrate, Divisor = (Uart clock * 4) / baudrate; stored in IBRD|FBRD
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u32 divisor = (4 * UART_CLK_IN_HZ) / baudRate;
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uart->ibrd = divisor >> 6;
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uart->fbrd = divisor & 0x3F;
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// Select FIFO fill levels for interrupts
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uart->ifls = PL011_IFLS_RX4_8 | PL011_IFLS_TX4_8;
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// FIFO Enabled / No Parity / 8 Data bit / One Stop Bit
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uart->lcr_h = PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8;
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// Select the interrupts we want to have
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// RX timeout and TX/RX fill interrupts
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uart->imsc = PL011_RTI | PL011_RXI | PL011_RXI;
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// Clear any pending errors
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uart->ecr = 0;
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// Clear all interrupts
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uart->icr = PL011_ALL_INTERRUPTS;
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// Register the interrupt ID
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//configureInterrupt(uartGetIrqId(dev), IRQ_PRIORITY_HOST, true);
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// Enable tx, rx, and uart overall
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uart->cr = PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN;
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uart->imsc = PL011_RTI | PL011_RXI | PL011_RXI;
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}
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void uartWriteData(UartDevice dev, const void *buffer, size_t size)
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{
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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const u8 *buf8 = (const u8 *)buffer;
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for (size_t i = 0; i < size; i++) {
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while (uart->fr & PL011_UARTFR_TXFF); // while TX FIFO full
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uart->dr = buf8[i];
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}
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}
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void uartReadData(UartDevice dev, void *buffer, size_t size)
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{
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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u8 *buf8 = (u8 *)buffer;
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size_t i;
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for (i = 0; i < size; i++) {
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while (uart->fr & PL011_UARTFR_RXFE);
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buf8[i] = uart->dr;
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}
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}
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size_t uartReadDataMax(UartDevice dev, void *buffer, size_t maxSize)
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{
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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u8 *buf8 = (u8 *)buffer;
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size_t i;
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for (i = 0; i < maxSize && !(uart->fr & PL011_UARTFR_RXFE); i++) {
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buf8[i] = uart->dr;
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}
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return 1 + i;
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}
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void uartSetInterruptStatus(UartDevice dev, bool read, bool enable)
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{
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volatile PL011UartRegisters *uart = uartGetRegisters(dev);
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u32 mask = read ? PL011_RTI | PL011_RXI : PL011_RTI;
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if (enable) {
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uart->imsc |= mask;
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} else {
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uart->icr = mask;
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uart->imsc &= ~mask;
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}
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} |