75 lines
3.0 KiB
C
75 lines
3.0 KiB
C
/*
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* Copyright (c) 2019 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "../utils.h"
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#include "../sysreg.h"
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#include "../arm.h"
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#include "../mmu.h"
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#include "../debug_log.h"
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#include "memory_map_mmu_cfg.h"
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void configureMemoryMapEnableMmu(void)
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{
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u32 addrSpaceSize;
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uintptr_t ttbr0 = configureMemoryMap(&addrSpaceSize);
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u32 ps = GET_SYSREG(id_aa64mmfr0_el1) & 0xF;
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/*
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- PA size: from ID_AA64MMFR0_EL1
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- Granule size: 4KB
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- Shareability attribute for memory associated with translation table walks using TTBR0_EL2: Inner Shareable
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- Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2: Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable
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- Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2: Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable
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- T0SZ = from configureMemoryMap
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*/
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u64 tcr = TCR_EL2_RSVD | TCR_PS(ps) | TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA | TCR_T0SZ(addrSpaceSize);
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/*
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- Attribute 0: Normal memory, Inner and Outer Write-Back Read-Allocate Write-Allocate Non-transient
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- Attribute 1: Device-nGnRE memory
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- Other attributes: Device-nGnRnE memory
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*/
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u64 mair = 0x4FFull;
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flush_dcache_all();
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invalidate_icache_all();
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set_memory_registers_enable_mmu(ttbr0, tcr, mair);
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}
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void configureMemoryMapEnableStage2(void)
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{
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u32 addrSpaceSize;
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uintptr_t vttbr = configureStage2MemoryMap(&addrSpaceSize);
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u32 ps = GET_SYSREG(id_aa64mmfr0_el1) & 0xF;
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/*
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- PA size: from ID_AA64MMFR0_EL1
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- Granule size: 4KB
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- Shareability attribute for memory associated with translation table walks using VTTBR_EL2: Inner Shareable
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- Outer cacheability attribute for memory associated with translation table walks using VTTBR_EL2: Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable
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- Inner cacheability attribute for memory associated with translation table walks using VTTBR_EL2: Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable
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- SL0 = start at level 1
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- T0SZ = from configureMemoryMap
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*/
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u64 vtcr = VTCR_EL2_RSVD | TCR_PS(ps) | TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA | VTCR_SL0(1) | TCR_T0SZ(addrSpaceSize);
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flush_dcache_all();
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invalidate_icache_all();
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set_memory_registers_enable_stage2(vttbr, vtcr);
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}
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