145 lines
4.8 KiB
C++
145 lines
4.8 KiB
C++
/*
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* Copyright (c) 2019-2020 Atmosphère-NX
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include "cpu/hvisor_cpu_exception_sysregs.hpp"
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namespace ams::hvisor {
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struct alignas(16) ExceptionStackFrame {
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u64 x[31]; // x0 .. x30
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union {
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u64 sp_el1;
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u64 sp_el2;
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};
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u64 sp_el0;
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u64 elr_el2;
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u64 spsr_el2;
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cpu::ExceptionSyndromeRegister esr_el2;
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u64 far_el2;
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u64 cntpct_el0;
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u64 cntp_ctl_el0;
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u64 cntv_ctl_el0;
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constexpr bool IsA32() const { return (spsr_el2 & cpu::PSR_MODE32) != 0; }
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constexpr bool IsThumb() const { return IsA32() && (spsr_el2 & cpu::PSR_AA32_THUMB) != 0; }
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constexpr u32 GetT32ItFlags() const
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{
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u64 it10 = (spsr_el2 >> cpu::PSR_AA32_IT10_MASK) & cpu::PSR_AA32_IT10_MASK;
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u64 it72 = (spsr_el2 >> cpu::PSR_AA32_IT72_MASK) & cpu::PSR_AA32_IT72_MASK;
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return it72 << 2 | it10;
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}
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constexpr void SetT32ItFlags(u32 flags)
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{
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spsr_el2 &= ~(cpu::PSR_AA32_IT72_MASK << cpu::PSR_AA32_IT72_SHIFT);
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spsr_el2 &= ~(cpu::PSR_AA32_IT10_MASK << cpu::PSR_AA32_IT10_SHIFT);
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u64 it10 = flags & cpu::PSR_AA32_IT10_MASK;
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u64 it72 = (flags >> 2) & cpu::PSR_AA32_IT72_MASK;
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spsr_el2 |= it72 << cpu::PSR_AA32_IT72_SHIFT;
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spsr_el2 |= it10 << cpu::PSR_AA32_IT10_SHIFT;
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}
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constexpr bool EvaluateConditionCode(u32 conditionCode) const
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{
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u64 spsr = spsr_el2;
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if (conditionCode == 14) {
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// AL
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return true;
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} else if (conditionCode == 15) {
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// Invalid encoding
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return false;
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}
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// NZCV
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bool n = (spsr & BIT(31)) != 0;
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bool z = (spsr & BIT(30)) != 0;
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bool c = (spsr & BIT(29)) != 0;
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bool v = (spsr & BIT(28)) != 0;
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bool tableHalf[] = {
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// EQ, CS, MI, VS, HI, GE, GT
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z, c, n, v, c && !z, n == v, !z && n == v,
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};
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return (conditionCode & 1) == 0 ? tableHalf[conditionCode / 2] : !tableHalf[conditionCode / 2];
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}
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constexpr void AdvanceItState()
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{
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u32 it = GetT32ItFlags();
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// Just in case EL0 is executing A32 (& not sure if fully supported)
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if (!IsThumb() || it == 0) {
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return;
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}
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// Last instruction of the block => wipe, otherwise advance
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SetT32ItFlags((it & 7) == 0 ? 0 : (it & 0xE0) | ((it << 1) & 0x1F));
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}
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constexpr void SkipInstruction(size_t size)
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{
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AdvanceItState();
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elr_el2 += size;
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}
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template<typename T = u64>
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constexpr T ReadRegister(u32 id) const
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{
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static_assert(std::is_integral_v<T> && std::is_unsigned_v<T>);
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return id == 31 ? static_cast<T>(0u) /* xzr */ : static_cast<T>(x[id]);
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}
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constexpr void WriteRegister(u32 id, u64 val)
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{
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if (id != 31) {
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// If not xzr
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x[id] = val;
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}
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}
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constexpr u64 &GetSpRef()
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{
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// Note: the return value is more or less meaningless if we took an exception from A32...
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// We try our best to reflect which privilege level the exception was took from, nonetheless
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bool spEl0 = false;
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u64 m = spsr_el2 & 0xF;
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if (IsA32()) {
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spEl0 = m == 0;
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} else {
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u64 el = m >> 2;
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spEl0 = el == 0 || (m & 1) == 0; // note: frame->sp_el2 is aliased to frame->sp_el1
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}
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return spEl0 ? sp_el0 : sp_el1;
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}
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};
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static_assert(offsetof(ExceptionStackFrame, far_el2) == 0x120, "Wrong definition for ExceptionStackFrame");
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static_assert(sizeof(ExceptionStackFrame) == 0x140, "Wrong size for ExceptionStackFrame");
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static_assert(std::is_standard_layout_v<ExceptionStackFrame>);
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static_assert(std::is_trivial_v<ExceptionStackFrame>);
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}
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/*void dumpStackFrame(const ExceptionStackFrame *frame, bool sameEl);
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void exceptionEnterInterruptibleHypervisorCode(void);*/
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